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Reduced complexity of spill logic by ensuring the irom outputs offset instrutions on a spill.
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@ -36,15 +36,20 @@ module irom(
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localparam OFFSET = $clog2(`XLEN/8);
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logic [`XLEN-1:0] IROMInstrFFull;
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logic [31:0] RawIROMInstrF;
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logic [1:0] AdrD;
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flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
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rom1p1r #(ADDR_WDITH, `XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
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if (`XLEN == 32) assign IROMInstrF = IROMInstrFFull;
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if (`XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
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else begin
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// IROM is aligned to XLEN words, but instructions are 32 bits. Select between the two
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// haves. Adr is the Next PCF not PCF so we delay 1 cycle.
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logic AdrD;
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flopen #(1) AdrReg(clk, ce, Adr[OFFSET-1], AdrD);
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assign IROMInstrF = AdrD ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
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assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
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end
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// If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
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// The spill logic will handle merging the two together.
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assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
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endmodule
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@ -51,7 +51,7 @@ module spillsupport #(parameter CACHE_ENABLED)
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logic TakeSpillF;
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logic SpillF;
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logic SelSpillF, SpillSaveF;
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logic [15:0] SpillDataLine0, SavedInstr;
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logic [15:0] SpillDataLine0;
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typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
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(* mark_debug = "true" *) statetype CurrState, NextState;
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@ -83,12 +83,11 @@ module spillsupport #(parameter CACHE_ENABLED)
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assign SelNextSpillF = (CurrState == STATE_READY & TakeSpillF) |
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(CurrState == STATE_SPILL & IFUCacheBusStallD);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF;
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assign SavedInstr = CACHE_ENABLED ? InstrRawF[15:0] : InstrRawF[31:16];
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(SpillSaveF & ~Flush),
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.reset(reset),
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.d(SavedInstr),
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.d(InstrRawF[15:0]),
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.q(SpillDataLine0));
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mux2 #(32) postspillmux(.d0(InstrRawF), .d1({InstrRawF[15:0], SpillDataLine0}), .s(SpillF),
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