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https://github.com/openhwgroup/cvw
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show instruction assembly in waveform
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@ -40,6 +40,7 @@ view wave
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add wave /testbench_busybear/clk
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add wave /testbench_busybear/reset
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add wave -divider
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add wave -hex /testbench_busybear/PCtext
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add wave -hex /testbench_busybear/pcExpected
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add wave -hex /testbench_busybear/dut/dp/PCF
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add wave -hex /testbench_busybear/dut/dp/InstrF
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@ -129,6 +130,6 @@ add wave /testbench_busybear/InstrWName
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#set DefaultRadix hexadecimal
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#
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#-- Run the Simulation
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run 800
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run 900
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#run -all
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##quit
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@ -126,6 +126,7 @@ module testbench_busybear();
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end
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logic [63:0] lastInstrF, lastPC, lastPC2;
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string PCtext, PCtext2;
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integer instrs;
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initial begin
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instrs = 0;
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@ -140,6 +141,8 @@ module testbench_busybear();
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else begin
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//if (~speculative) begin
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%s %s\n", PCtext, PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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