mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
More cleanup of IFU.
This commit is contained in:
Ross Thompson
parent
554df2377e
commit
910d16b642
@ -35,10 +35,11 @@
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module bpred
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(input logic clk, reset,
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input logic StallF, StallD, StallE,
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input logic FlushF, FlushD, FlushE,
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input logic StallF, StallD, StallE, StallM,
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input logic FlushF, FlushD, FlushE, FlushM,
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// Fetch stage
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// the prediction
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
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output logic [`XLEN-1:0] BPPredPCF,
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output logic SelBPPredF,
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@ -53,13 +54,14 @@ module bpred
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input logic [`XLEN-1:0] IEUAdrE, // The branch destination if the branch is taken.
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input logic [`XLEN-1:0] PCD, // The address the branch predictor took.
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input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
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input logic [4:0] InstrClassE,
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output logic [4:0] InstrClassM,
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// Report branch prediction status
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output logic BPPredWrongE,
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output logic BPPredDirWrongE,
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output logic BTBPredPCWrongE,
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output logic RASPredPCWrongE,
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output logic BPPredClassNonCFIWrongE
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output logic BPPredWrongM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM
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);
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logic BTBValidF;
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@ -71,14 +73,14 @@ module bpred
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logic FallThroughWrongE;
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logic PredictionPCWrongE;
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logic PredictionInstrClassWrongE;
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logic [4:0] InstrClassD, InstrClassE;
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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// Part 1 branch direction prediction
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if (`BPTYPE == "BPTWOBIT") begin:Predictor
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twoBitPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.StallF(StallF),
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twoBitPredictor DirPredictor(.clk, .reset, .StallF,
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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@ -87,58 +89,27 @@ module bpred
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.UpdatePrediction(UpdateBPPredE));
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end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
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globalHistoryPredictor DirPredictor(.clk, .reset, .StallF, .StallE,
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.PCNextF, .BPPredF,
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.InstrClassE, .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .BPPredDirWrongE,
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.PCE, .PCSrcE, .UpdateBPPredE);
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globalHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.PCNextF(PCNextF),
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.BPPredF(BPPredF),
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// update
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.InstrClassE(InstrClassE),
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.BPInstrClassE(BPInstrClassE),
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.BPPredDirWrongE(BPPredDirWrongE),
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.PCE(PCE),
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.PCSrcE(PCSrcE),
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.UpdateBPPredE(UpdateBPPredE));
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end else if (`BPTYPE == "BPGSHARE") begin:Predictor
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gsharePredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.PCNextF(PCNextF),
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.BPPredF(BPPredF),
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// update
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.InstrClassE(InstrClassE),
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.BPInstrClassE(BPInstrClassE),
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.BPPredDirWrongE(BPPredDirWrongE),
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.PCE(PCE),
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.PCSrcE(PCSrcE),
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.UpdateBPPredE(UpdateBPPredE));
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gsharePredictor DirPredictor(.clk, .reset, .StallF, .StallE,
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.PCNextF, .BPPredF,
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.InstrClassE, .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .BPPredDirWrongE,
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.PCE, .PCSrcE, .UpdateBPPredE);
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end
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else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
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localHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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localHistoryPredictor DirPredictor(.clk,
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.reset, .StallF, .StallE, .FlushF,
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0] & ~StallE),
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.PCSrcE(PCSrcE),
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.UpdatePrediction(UpdateBPPredE));
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end
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else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
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localHistoryPredictor DirPredictor(.clk(clk),
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.reset(reset),
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.*, // Stalls and flushes
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.LookUpPC(PCNextF),
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.Prediction(BPPredF),
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// update
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.UpdatePC(PCE),
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.UpdateEN(InstrClassE[0] & ~StallE),
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.PCSrcE(PCSrcE),
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.PCSrcE,
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.UpdatePrediction(UpdateBPPredE));
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end
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@ -201,15 +172,35 @@ module bpred
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.d(BPPredD),
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.q(BPPredE));
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// the branch predictor needs a compact decoding of the instruction class.
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// *** consider adding in the alternate return address x5 for returns.
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assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
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assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
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assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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flopenrc #(5) InstrClassRegE(.clk, .reset, .en(~StallE), .clear(FlushE), .d(InstrClassD), .q(InstrClassE));
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flopenrc #(5) InstrClassRegM(.clk, .reset, .en(~StallM), .clear(FlushM), .d(InstrClassE), .q(InstrClassM));
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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// branch predictor
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flopenrc #(4) BPPredWrongRegM(.clk, .reset, .en(~StallM), .clear(FlushM),
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.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
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.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
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// pipeline the class
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flopenrc #(5) InstrClassRegD(.clk(clk),
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flopenrc #(5) BPInstrClassRegD(.clk(clk),
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.reset(reset),
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.en(~StallD),
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.clear(FlushD),
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.d(BPInstrClassF),
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.q(BPInstrClassD));
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flopenrc #(5) InstrClassRegE(.clk(clk),
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flopenrc #(5) BPInstrClassRegE(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.clear(FlushE),
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@ -100,8 +100,6 @@ module ifu (
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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logic BPPredWrongM;
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(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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logic [`XLEN+1:0] PCFExt;
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@ -159,8 +157,7 @@ module ifu (
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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assign {ITLBMissF, InstrAccessFaultF} = '0;
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assign InstrPageFaultF = '0;
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assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0;
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assign PCPF = PCF;
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assign CacheableF = '1;
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end
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@ -182,22 +179,11 @@ module ifu (
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end else begin : bus
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localparam integer WORDSPERLINE = `MEM_ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LOGWPL = `MEM_ICACHE ? $clog2(WORDSPERLINE) : 1;
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localparam integer LINELEN = `MEM_ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
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localparam integer WordCountThreshold = `MEM_ICACHE ? WORDSPERLINE - 1 : 0;
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localparam integer LINEBYTELEN = LINELEN/8;
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localparam integer OFFSETLEN = $clog2(LINEBYTELEN);
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logic [LOGWPL-1:0] WordCount;
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logic SelUncachedAdr;
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logic [LINELEN-1:0] ICacheMemWriteData;
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logic [`PA_BITS-1:0] LocalIFUBusAdr;
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logic [`PA_BITS-1:0] ICacheBusAdr;
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logic ICacheBusAck;
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genvar index;
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busdp #(WORDSPERLINE, LINELEN)
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busdp(.clk, .reset,
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@ -226,7 +212,7 @@ module ifu (
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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.FinalWriteData('0),
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.RW(IFURWF),
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.Atomic(2'b00), .FlushCache(1'b0),
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.Atomic('0), .FlushCache('0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(), .InvalidateCacheM(InvalidateICacheM));
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@ -237,13 +223,8 @@ module ifu (
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end
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end
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// branch predictor signal
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF, PCNext0F, PCNext1F, PCNext2F;
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logic [4:0] InstrClassD, InstrClassE;
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logic [`XLEN-1:0] PCNext1F, PCNext2F;
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
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@ -253,14 +234,9 @@ module ifu (
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assign PrivilegedChangePCM = RetM | TrapM;
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// *** move unnecessary muxes into BPRED_ENABLED
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
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// The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
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mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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@ -268,38 +244,28 @@ module ifu (
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// branch and jump predictor
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if (`BPRED_ENABLED) begin : bpred
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// *** move the rest of this hardware into branch predictor including instruction class registers
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logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
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flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), .d(BPPredWrongE), .q(BPPredWrongM));
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF, PCNext0F;
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logic BPPredWrongM;
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE,
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.FlushF, .FlushD, .FlushE,
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.PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
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.PCD, .PCLinkE, .InstrClassE, .BPPredWrongE, .BPPredDirWrongE,
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.BTBPredPCWrongE, .RASPredPCWrongE, .BPPredClassNonCFIWrongE);
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.StallF, .StallD, .StallE, .StallM,
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.FlushF, .FlushD, .FlushE, .FlushM,
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.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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// the branch predictor needs a compact decoding of the instruction class.
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// *** consider adding in the alternate return address x5 for returns.
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assign InstrClassD[4] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or r5
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assign InstrClassD[3] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
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assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01; // jump register, but not return
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assign InstrClassD[1] = InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01; // jump, RD != x1 or x5
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assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
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// branch predictor
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flopenrc #(5) InstrClassRegE(.clk, .reset, .en(~StallE), .clear(FlushE), .d(InstrClassD), .q(InstrClassE));
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flopenrc #(5) InstrClassRegM(.clk, .reset, .en(~StallM), .clear(FlushM), .d(InstrClassE), .q(InstrClassM));
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flopenrc #(4) BPPredWrongRegM(.clk, .reset, .en(~StallM), .clear(FlushM),
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.d({BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE}),
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.q({BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM}));
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
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.s(BPPredWrongM), .y(PCBPWrongInvalidate));
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end else begin : bpred
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assign BPPredPCF = '0;
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assign BPPredWrongE = PCSrcE;
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assign BPPredWrongM = '0;
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assign {SelBPPredF, BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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assign PCNext1F = PCPlus2or4F;
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assign PCBPWrongInvalidate = PCE;
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end
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// pcadder
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@ -313,16 +279,12 @@ module ifu (
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else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
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// Decode stage pipeline register and logic
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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// *** combine these with others in better way, including M, F
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// Misaligned PC logic
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// Instruction address misalignement only from br/jal(r) instructions.
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@ -336,7 +298,6 @@ module ifu (
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// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
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flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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// *** Ross Thompson. Check InstrMisalignedAdrM as I believe it is the same as PCF. Should be able to remove.
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flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
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// Instruction and PC/PCLink pipeline registers
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@ -347,4 +308,3 @@ module ifu (
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flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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endmodule
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