From 90ef371abc97b01ab73bf6f31bf17eb40132585f Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Sat, 5 Nov 2022 13:34:24 -0700 Subject: [PATCH] fixed fifo timout handling. error now in data ready interrupt --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 454d05be5..ca197876c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1072,9 +1072,9 @@ uart_data_wait: li t3, 0x10000002 // IIR li a4, 0x61 uart_read_LSR_IIR: - lb t4, 0(t3) // save IIR before reading LSR mgith clear it + lbu t4, 0(t3) // save IIR before reading LSR might clear it // check if IIR is the rxfifotimeout interrupt. if it is, then read the fifo then go back and repeat this. - li t5, 6 + li t5, 0xCC // Value in IIR for Fifo Enabled, with timeout interrupt pending beq t4, t5, uart_rxfifo_timout lb t5, 0(t2) // read LSR andi t6, t5, 0x61 // wait until all transmissions are done and data is ready @@ -1083,7 +1083,6 @@ uart_read_LSR_IIR: uart_rxfifo_timout: li t4, 0x10000000 // read from the fifo lb t5, 0(t4) - lb t5, 0(t4) //read the fifo until empty j uart_read_LSR_IIR