From 90e89ced1db83c769e9bbdd7db3462e36d6e7725 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 26 Feb 2024 04:20:08 -0800 Subject: [PATCH] Fixes for synthesis. HPTW change will break x detection --- bin/wally-tool-chain-install.sh | 12 ++++++------ src/cache/cacheLRU.sv | 10 +++++----- src/mmu/hptw.sv | 4 +++- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 6e7e4c8e9..74157bffa 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -69,9 +69,6 @@ fi cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain -# Temporarily use the following commands until gcc-13 is part of riscv-gnu-toolchain (issue #1249) -#git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13 -#./configure --prefix=/opt/riscv --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13 ./configure --prefix=${RISCV} --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" make -j ${NUM_THREADS} @@ -111,14 +108,15 @@ cd riscv-isa-sim/build make -j ${NUM_THREADS} make install cd ../arch_test_target/spike/device -sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include +# dh 2/5/24: these should be obsolete +#sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include +#sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Wally needs Verilator 5.021 or later. # Verilator needs to be built from scratch to get the latest version # apt-get install verilator installs version 4.028 as of 6/8/23 sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g -sudo apt-get install -y libfl2 libfl-dev # Ubuntu only (ignore if gives error) +sudo apt-get install -y perl g++ ccache help2man libgoogle-perftools-dev numactl perl-doc zlib1g cd $RISCV git clone https://github.com/verilator/verilator # Only first time # unsetenv VERILATOR_ROOT # For csh; ignore error if on bash @@ -173,6 +171,8 @@ sudo make install cd $RISCV opam init -y --disable-sandboxing +opam update +opam upgrade opam switch create 5.1.0 opam install sail -y diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index e795dd765..1b803f5d3 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -143,16 +143,16 @@ module cacheLRU // This is a two port memory. // Every cycle must read from CacheSetData and each load/store must write the new LRU. always_ff @(posedge clk) begin - if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize + if (reset | (InvalidateCache & ~FlushStage)) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; if(CacheEn) begin if(ClearValid & ~FlushStage) - LRUMemory[PAdr] <= '0; + LRUMemory[PAdr] = '0; else if(LRUWriteEn) - LRUMemory[PAdr] <= NextLRU; + LRUMemory[PAdr] = NextLRU; if(LRUWriteEn & (PAdr == CacheSetTag)) - CurrLRU <= #1 NextLRU; + CurrLRU = NextLRU; else - CurrLRU <= #1 LRUMemory[CacheSetTag]; + CurrLRU = LRUMemory[CacheSetTag]; end end diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index 0823dc7e0..4e292ba3d 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -148,6 +148,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrUpdateDAM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) assign PRegEn = HPTWRW[1] & ~DCacheBusStallM | UpdatePTE; flopenr #(P.XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache + assert property(@(posedge clk) ~PRegEn | reset | NextPTE[0] !== 1'bx); // report writing an x PTE from an uninitialized page table // Assign PTE descriptors common across all XLEN values // For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table @@ -173,7 +174,8 @@ module hptw import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] AccessedPTE; assign AccessedPTE = {PTE[P.XLEN-1:8], (SetDirty | PTE[7]), 1'b1, PTE[5:0]}; // set accessed bit, conditionally set dirty bit - assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + //assign ReadDataNoXM = (ReadDataM[0] === 'x) ? '0 : ReadDataM; // If the PTE.V bit is x because it was read from uninitialized memory set to 0 to avoid x propagation and hanging the simulation. + assign ReadDataNoXM = ReadDataM; // *** temporary fix for synthesis; === and x in line above are not synthesizable. mux2 #(P.XLEN) NextPTEMux(ReadDataNoXM, AccessedPTE, UpdatePTE, NextPTE); // NextPTE = ReadDataNoXM when ADUE = 0 because UpdatePTE = 0 flopenr #(P.PA_BITS) HPTWAdrWriteReg(clk, reset, SaveHPTWAdr, HPTWReadAdr, HPTWWriteAdr);