diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index cb6658b1c..a940bebb0 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -49,7 +49,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 76b587924..9e0de57cc 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 352554006..0f5ed3f0c 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -50,7 +50,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 47991e014..0e9f74654 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -49,7 +49,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh
index 78b85286a..d0c1d7e52 100644
--- a/pipelined/config/rv32i/wally-config.vh
+++ b/pipelined/config/rv32i/wally-config.vh
@@ -50,7 +50,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index 2f08e2f28..db40ed3b5 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -49,7 +49,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
-`define DMEM 1
+`define DTIM 1
 `define IROM 1
 `define BUS 0
 `define DCACHE 0
diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh
index 8af61d884..99c525ea9 100644
--- a/pipelined/config/rv64BP/wally-config.vh
+++ b/pipelined/config/rv64BP/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh
index 653dd864e..815e99e98 100644
--- a/pipelined/config/rv64fp/wally-config.vh
+++ b/pipelined/config/rv64fp/wally-config.vh
@@ -52,7 +52,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh
index 6a40a6885..0792ab6a8 100644
--- a/pipelined/config/rv64fpquad/wally-config.vh
+++ b/pipelined/config/rv64fpquad/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index eef5448b4..9796d0c29 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh
index c0477fc62..f14a0529b 100644
--- a/pipelined/config/rv64i/wally-config.vh
+++ b/pipelined/config/rv64i/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 0
+`define DTIM 0
 `define IROM 0
 `define BUS 1
 `define DCACHE 1
diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh
index ddd68f9dc..9e0191ff4 100644
--- a/pipelined/config/rv64ic/wally-config.vh
+++ b/pipelined/config/rv64ic/wally-config.vh
@@ -51,7 +51,7 @@
 `define UARCH_SINGLECYCLE 0
 
 // LSU microarchitectural Features
-`define DMEM 1
+`define DTIM 1
 `define IROM 1
 `define BUS 0
 `define DCACHE 0
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 46b2b534a..941909fe2 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -198,7 +198,8 @@ module lsu (
   // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore.
   // *** becomes DTIM_RAM_BASE
 
-  if (`DMEM) begin : dtim
+  if (`DTIM) begin : dtim
+    // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
     dtim dtim(.clk, .reset, .LSURWM,
               .IEUAdrE(CPUBusy | LSURWM[0] | reset ? IEUAdrM : IEUAdrE),
               .TrapM, .WriteDataM(LSUWriteDataM), 
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 38eba244b..66901df27 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -234,7 +234,7 @@ logic [3:0] dummy;
       end else begin
         if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
         else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-        if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+        if (`DTIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
       end
 
       if (riscofTest) begin
@@ -328,12 +328,12 @@ logic [3:0] dummy;
           /* verilator lint_off INFINITELOOP */
           while (signature[i] !== 'bx) begin
             logic [`XLEN-1:0] sig;
-            if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
+            if (`DTIM) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
             else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
             //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
             if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
               errors = errors+1;
-              $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h", 
+              $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM) = %h, signature = %h", 
                     tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
               $stop;//***debug
              end
@@ -363,7 +363,7 @@ logic [3:0] dummy;
             //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
             if (`IROM)               $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
             else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-            if (`DMEM)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+            if (`DTIM)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
 
             if (riscofTest) begin
               ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
@@ -456,11 +456,10 @@ module riscvassertions;
 	  assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
     assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
     assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
-    //    assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
+    assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM == 0 & `IROM == 0)) else $error("Can't simultaneously have virtual memory and DTIM/IROM because local memories don't translate addresses");
     assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
     assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    //assert (`DCACHE == 1 & `BUS ==0) else $error("Dcache requires DBUS.");
-    //assert (`ICACHE == 1 & `BUS ==0) else $error("Icache requires IBUS.");    
+    assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
   end