Removed delayed AHB signals from top level

pipelined/src/ebu/ahblite.sv

@@ -72,16 +72,14 @@ module ahblite (
   (* mark_debug = "true" *) output logic [2:0] HBURST,
   (* mark_debug = "true" *) output logic [3:0] HPROT,
   (* mark_debug = "true" *) output logic [1:0] HTRANS,
-  (* mark_debug = "true" *) output logic HMASTLOCK,
+  (* mark_debug = "true" *) output logic HMASTLOCK
-  // Delayed signals for writes
-  (* mark_debug = "true" *) output logic [3:0] HSIZED,
-  (* mark_debug = "true" *) output logic HWRITED
 );
 
   typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
   statetype BusState, NextBusState;
   logic LSUGrant;
   logic [2:0] HADDRD;
+  logic [3:0] HSIZED;
  
   assign HCLK = clk;
   assign HRESETn = ~reset;
@@ -120,15 +118,14 @@ module ahblite (
   assign HPROT = 4'b0011; // not used; see Section 3.7
   assign HMASTLOCK = 0; // no locking supported
   assign HWRITE = (NextBusState == MEMWRITE);
-  // Byte mask for HWSTRB
-  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD), .ByteMask(HWSTRB));
 
   // delay write data by one cycle for
   flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
-  // delay signals for subword writes
+
+  // Byte mask for HWSTRB based on delayed signals
   flop #(3)   adrreg(HCLK, HADDR[2:0], HADDRD);
   flop #(4)   sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
-  flop #(1)   writereg(HCLK, HWRITE, HWRITED);
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD), .ByteMask(HWSTRB));
 
   // Send control back to IFU and LSU
   assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD);

pipelined/src/lsu/busfsm.sv

@@ -103,7 +103,7 @@ module busfsm #(parameter integer   WordCountThreshold,
 
   assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE);
   assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access.
-  assign CntEn = (PreCntEn & BusAck | (BusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up.
+  assign CntEn = (PreCntEn & BusAck | BusInit) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up.
 
   assign UnCachedAccess = ~CACHE_ENABLED | ~Cacheable;
 

pipelined/src/uncore/uncore.sv

@@ -51,9 +51,6 @@ module uncore (
   output logic [`AHBW-1:0] HRDATA,
   output logic             HREADY, HRESP,
   output logic             HSELEXT,
-  // delayed signals
-  input  logic [2:0]       HADDRD,
-  input  logic             HWRITED,
   // peripheral pins
   output logic             MTimerInt, MSwInt, MExtInt, SExtInt,
   input  logic [31:0]      GPIOPinsIn,

pipelined/src/wally/wallypipelinedcore.sv

@@ -48,11 +48,7 @@ module wallypipelinedcore (
    output logic [2:0]         HBURST,
    output logic [3:0]         HPROT,
    output logic [1:0]         HTRANS,
-   output logic         HMASTLOCK,
+   output logic         HMASTLOCK
-   // Delayed signals for subword write
-   output logic [2:0]         HADDRD,
-   output logic [3:0]         HSIZED,
-   output logic         HWRITED
    );
 
   //  logic [1:0]  ForwardAE, ForwardBE;
@@ -311,7 +307,7 @@ module wallypipelinedcore (
  
      .HREADY, .HRESP, .HCLK, .HRESETn,
      .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
-     .HPROT, .HTRANS, .HMASTLOCK, .HSIZED, .HWRITED);
+     .HPROT, .HTRANS, .HMASTLOCK);
   end
 
   

pipelined/src/wally/wallypipelinedsoc.sv

@@ -76,10 +76,6 @@ module wallypipelinedsoc (
   logic             MTimerInt, MSwInt; // from CLINT
   logic [63:0]      MTIME_CLINT; // from CLINT to CSRs
   logic             MExtInt,SExtInt; // from PLIC
-  logic [2:0]       HADDRD;
-  logic [3:0]       HSIZED;
-  logic             HWRITED;
-
 
   // synchronize reset to SOC clock domain
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
@@ -89,13 +85,12 @@ module wallypipelinedsoc (
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt, 
     .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
+    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
-    .HADDRD, .HSIZED, .HWRITED
    );
 
   uncore uncore(.HCLK, .HRESETn, .TIMECLK,
     .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
-    .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED,
+    .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP,
     .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, 
 		.HSELEXT,
 		.SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK