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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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This commit is contained in:
Ross Thompson 2022-04-21 09:52:42 -05:00
commit 8fcd4d47b7
41 changed files with 5521 additions and 954 deletions
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12
linux/buildroot-config-src/wally/rootfs_overlay/.profile
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@ -2,8 +2,8 @@ echo "Hello this ~/.profile is meant to demonstrate running some basic commands
echo "I am $(whoami)" echo "I am $(whoami)"
echo "And I am on $(hostname)" echo "And I am on $(hostname)"
touch myFile.txt touch myFile.txt
echo "This is a line of text." > myFile.txt echo "Hello World!" > myFile.txt
echo "A second line of text." >> myFile.txt echo "And farewell!" >> myFile.txt
mkdir myDir mkdir myDir
mv myFile.txt myDir mv myFile.txt myDir
echo "Created myFile.txt and moved it to myDir. It contains:" echo "Created myFile.txt and moved it to myDir. It contains:"
@ -17,9 +17,6 @@ cd myDir
ln -s ../myScript.sh symLinkToMyScript.sh ln -s ../myScript.sh symLinkToMyScript.sh
echo "Created symLinkToMyScript.sh. Running it yields:" echo "Created symLinkToMyScript.sh. Running it yields:"
./symLinkToMyScript.sh ./symLinkToMyScript.sh
ln ../myScript.sh hardLinkToMyScript.sh
echo "Created hardLinkToMyScript.sh. Running it yields:"
./hardLinkToMyScript.sh
echo "Now let\'s remove all these example files and scripts" echo "Now let\'s remove all these example files and scripts"
cd / cd /
rm -r myDir rm -r myDir
@ -28,10 +25,5 @@ echo "Here is disk usage:"
df -h df -h
echo "And here are the current processes:" echo "And here are the current processes:"
ps ps
echo "We can create a user."
cd /
mkdir home
echo "password\npassword\n" | adduser myUser
su -c "cd ~; echo \"I am $(whoami) (a new user) and my home directory is $(pwd)\""
echo "And finally a login prompt." echo "And finally a login prompt."
login login

4
pipelined/config/rv32ia/wally-config.vh
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@ -95,10 +95,10 @@
`define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_SUPPORTED 1'b0
`define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_BASE 34'h80000000
`define EXT_MEM_RANGE 34'h07FFFFFF `define EXT_MEM_RANGE 34'h07FFFFFF
`define CLINT_SUPPORTED 1'b0 `define CLINT_SUPPORTED 1'b1
`define CLINT_BASE 34'h02000000 `define CLINT_BASE 34'h02000000
`define CLINT_RANGE 34'h0000FFFF `define CLINT_RANGE 34'h0000FFFF
`define GPIO_SUPPORTED 1'b0 `define GPIO_SUPPORTED 1'b1
`define GPIO_BASE 34'h10060000 `define GPIO_BASE 34'h10060000
`define GPIO_RANGE 34'h000000FF `define GPIO_RANGE 34'h000000FF
`define UART_SUPPORTED 1'b1 `define UART_SUPPORTED 1'b1

3
pipelined/src/uncore/uartPC16550D.sv
View File

@ -316,6 +316,9 @@ module uartPC16550D(
end else begin end else begin
if (rxstate == UART_DONE) begin if (rxstate == UART_DONE) begin
RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register
if (rxoverrunerr) $warning("UART RX Overrun Error\n");
if (rxparityerr) $warning("UART RX Parity Error\n");
if (rxframingerr) $warning("UART RX Framing Error\n");
if (fifoenabled) begin if (fifoenabled) begin
rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata};
rxfifohead <= #1 rxfifohead + 1; rxfifohead <= #1 rxfifohead + 1;

28
pipelined/testbench/tests.vh
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@ -1472,6 +1472,8 @@ string imperas32f[] = '{
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
"rv64i_m/privilege/WALLY-trap-01", "0050a0", "rv64i_m/privilege/WALLY-trap-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-s-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-u-01", "0050a0",
"rv64i_m/privilege/WALLY-MIE-01", "0050a0", "rv64i_m/privilege/WALLY-MIE-01", "0050a0",
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0", "rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
"rv64i_m/privilege/WALLY-stvec-01", "0050a0", "rv64i_m/privilege/WALLY-stvec-01", "0050a0",
@ -1540,15 +1542,23 @@ string wally32i[] = '{
string wally32priv[] = '{ string wally32priv[] = '{
`WALLYTEST, `WALLYTEST,
"rv32i_m/privilege/WALLY-CSR-permission-s-01", "004060", "rv32i_m/privilege/WALLY-CSR-permission-s-01", "006080",
"rv32i_m/privilege/WALLY-CSR-permission-u-01", "004060", "rv32i_m/privilege/WALLY-CSR-permission-u-01", "006080",
"rv32i_m/privilege/WALLY-minfo-01", "004060", "rv32i_m/privilege/WALLY-minfo-01", "005080",
"rv32i_m/privilege/WALLY-misa-01", "004060", "rv32i_m/privilege/WALLY-misa-01", "005080",
"rv32i_m/privilege/WALLY-MMU-SV32", "004060", "rv32i_m/privilege/WALLY-MMU-SV32", "005080",
"rv32i_m/privilege/WALLY-PMA", "004060", "rv32i_m/privilege/WALLY-PMA", "005080",
"rv32i_m/privilege/WALLY-PMP", "004060", "rv32i_m/privilege/WALLY-PMP", "005080",
"rv32i_m/privilege/WALLY-scratch-01", "004060", "rv32i_m/privilege/WALLY-trap-01", "005080",
"rv32i_m/privilege/WALLY-sscratch-s-01", "004060" "rv32i_m/privilege/WALLY-trap-s-01", "005080",
"rv32i_m/privilege/WALLY-trap-u-01", "005080",
"rv32i_m/privilege/WALLY-MIE-01", "005080",
"rv32i_m/privilege/WALLY-mtvec-01", "005080",
"rv32i_m/privilege/WALLY-stvec-01", "005080",
"rv32i_m/privilege/WALLY-PIE-stack-01", "005080",
"rv32i_m/privilege/WALLY-PIE-stack-s-01", "005080",
"rv32i_m/privilege/WALLY-trap-sret-01", "005080"
}; };
string wally32periph[] = '{ string wally32periph[] = '{

18
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag
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@ -34,12 +34,22 @@ rv32i_sc_tests = \
WALLY-CSR-permission-u-01 \ WALLY-CSR-permission-u-01 \
WALLY-minfo-01 \ WALLY-minfo-01 \
WALLY-misa-01 \ WALLY-misa-01 \
WALLY-scratch-01 \
WALLY-sscratch-s-01 \
WALLY-AMO \ WALLY-AMO \
WALLY-LRSC WALLY-LRSC \
# WALLY-scratch-01 \
# WALLY-sscratch-s-01 \
target_tests_nosim = WALLY-PMA \ target_tests_nosim = \
WALLY-PMA \
WALLY-mtvec-01 \
WALLY-stvec-01 \
WALLY-MIE-01 \
WALLY-PIE-stack-01 \
WALLY-PIE-stack-s-01 \
WALLY-trap-sret-01 \
WALLY-trap-01 \
WALLY-trap-s-01 \
WALLY-trap-u-01 \
rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests))

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-MIE-01.reference_output Normal file
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1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-01.reference_output Normal file
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File diff suppressed because it is too large Load Diff

1012
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output Normal file
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File diff suppressed because it is too large Load Diff

8
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-PMA.reference_output
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@ -1,10 +1,6 @@
beef00b5 beef00b5
00000007 # write access fault with 16 bit write to CLINT 000000b6
00000005 # read access fault with 16 bit write to CLINT ffffffb7
00000bad
00000007 # write access fault with 8 bit write to CLINT
00000005 # read access fault with 8 bit write to CLINT
00000bad
00000001 00000001
00000bad 00000bad
00000002 00000002

15
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
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@ -1,11 +1,10 @@
000000 00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
deadbeef 80000007 # mcause from m time interrupt
deadbeef 00000000 # mtval for mtime interrupt (0x0)
deadbeef 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
deadbeef 0000000b # mcause from M mode ecall from test termination
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

4
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-scratch-01.reference_output
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@ -1,7 +1,7 @@
00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch 00000111 # Test 5.3.2.3: successful read the 0x111 written to mscratch
00000000
0000000b # ecall from ending tests in machine mode 0000000b # ecall from ending tests in machine mode
deadbeef 00000000
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

8
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-sscratch-s-01.reference_output
View File

@ -1,11 +1,11 @@
00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch 00000111 # Test 5.3.2.3: successful read of the 0x111 written to sscratch
00000000
0000000b # ecall from going to s mode from m mode 0000000b # ecall from going to s mode from m mode
00000000
00000aaa # successful read of 0xAAA written to sscratch 00000aaa # successful read of 0xAAA written to sscratch
00000000
00000009 # ecall from ending tests in supervisor mode 00000009 # ecall from ending tests in supervisor mode
deadbeef 00000000
deadbeef
deadbeef
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

40
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
View File

@ -1,23 +1,23 @@
deadbeef 00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
deadbeef 00000222 # readback value of mideleg after attempting to delegate all interrupts.
deadbeef 0000000b # mcause from ecall for going from M mode to S mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 80000001 # mcause from s soft interrupt
deadbeef 00000000 # mtval for ssoft interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # mcause from ecall for going from S mode to M mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0000000b # mcause from ecall for going from M mode to U mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 80000001 # mcause from s soft interrupt from user mode this time
deadbeef 00000000 # mtval for mtime interrupt (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # mcause from U mode ecall from test termination
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

76
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1,4 +1,7 @@
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000001 # mcause from an instruction access fault 00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
@ -6,16 +9,16 @@
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
800003ec # mtval of breakpoint instruction adress (0x800003ec) 8000016c # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
800003f5 # mtval of misaligned address (0x800003f5) 80000175 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000411 # mtval of address with misaligned store instr (0x80000410) 80000191 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)
@ -29,37 +32,52 @@
00000009 # mcause from S mode ecall 00000009 # mcause from S mode ecall
00000000 # mtval of ecall (*** defined to be zero for now) 00000000 # mtval of ecall (*** defined to be zero for now)
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec01 # value to indicate successful vectoring on s soft interrupt
80000001 # mcause value from s soft interrupt
00000000 # mtval for ssoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec03 # value to indicate successful vectoring on m soft interrupt
80000003 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec05 # value to indicate successful vectoring on s time interrupt
80000005 # mcause value from s time interrupt
00000000 # mtval for stime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec07 # value to indicate successful vectoring on m time interrupt
80000007 # mcause value from m time interrupt 80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0) 00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec09 # value to indicate successful vectoring on s ext interrupt
80000001 # mcause value from m soft interrupt 80000009 # mcause value from s ext interrupt
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for sext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec0b # value to indicate successful vectoring on m ext interrupt
8000000b # mcause value from m ext interrupt 8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0) 00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable) fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
00000001 # Test 5.3.1.4: mcause from an instruction access fault 00000000 # mcause from instruction addr misaligned fault
8000013a # mtval of faulting instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000001 # mcause from an instruction access fault
00000000 # mtval of faulting instruction address (0x0) 00000000 # mtval of faulting instruction address (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000002 # mcause from an Illegal instruction 00000002 # mcause from an Illegal instruction
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
800003ec # mtval of breakpoint instruction adress (0x800003ec) 8000016c # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
800003f5 # mtval of misaligned address (0x800003f5) 80000175 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000411 # mtval of address with misaligned store instr (0x80000410) 80000191 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)
@ -67,16 +85,16 @@
0000000b # mcause from M mode ecall 0000000b # mcause from M mode ecall
00000000 # mtval of ecall (*** defined to be zero for now) 00000000 # mtval of ecall (*** defined to be zero for now)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec03 # value to indicate successful vectoring on m soft interrupt
80000007 # mcause value from time interrupt 80000003 # mcause value from m soft interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts
80000001 # mcause value from m soft interrupt
00000000 # mtval for msoft interrupt (0x0) 00000000 # mtval for msoft interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
000007ec # value to indicate a vectored interrupts 0007ec07 # value to indicate successful vectoring on m time interrupt
0000000b # mcause value from m ext interrupt 80000007 # mcause value from m time interrupt
00000000 # mtval for mtime interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0007ec0b # value to indicate successful vectoring on m ext interrupt
8000000b # mcause value from m ext interrupt
00000000 # mtval for mext interrupt (0x0) 00000000 # mtval for mext interrupt (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
0000000b # mcause from M mode ecall from test termination 0000000b # mcause from M mode ecall from test termination
@ -988,3 +1006,19 @@ deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

206
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -1,106 +1,106 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 80000001 # scause value from s soft interrupt
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 80000003 # scause value from m soft interrupt
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 80000007 # scause value from m time interrupt
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 8000000b # scause value from m ext interrupt
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 80000001 # scause value from s soft interrupt
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000009 # scause from S mode ecall from test termination
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

1024
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-sret-01.reference_output Normal file
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@ -1,92 +1,92 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 80000003 # scause value from m soft interrupt
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 80000007 # scause value from m time interrupt
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 8000000b # scause value from m ext interrupt
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 8000013a # stval of faulting instruction adress
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000003 # scause from Breakpoint
deadbeef 8000016c # stval of breakpoint instruction adress
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000004 # scause from load address misaligned
deadbeef 80000175 # stval of misaligned address
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000005 # scause from load access
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000006 # scause from store misaligned
deadbeef 80000191 # stval of address with misaligned store instr
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000007 # scause from store access
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 80000009 # scause value from s ext interrupt
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000008 # scause from U mode ecall from test termination
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

44
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MIE-01.S Normal file
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@ -0,0 +1,44 @@
///////////////////////////////////////////
//
// WALLY-MIE
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1.
WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
// test 5.3.1.6 Interrupt enabling and priority tests
// note that none of these interrupts should be caught or handled.
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

49
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-01.S Normal file
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@ -0,0 +1,49 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1
li x28, 0x8
csrs mstatus, x28 // set mstatus.MIE bit to 1
WRITE_READ_CSR mie, 0xFFF
// test 5.3.1.6 Interrupt enabling and priority tests
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x8
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_m_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

53
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PIE-stack-s-01.S Normal file
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@ -0,0 +1,53 @@
///////////////////////////////////////////
//
// WALLY-privilege-interrupt-enable-stack
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts.
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
// test 5.3.1.6 Interrupt enabling and priority tests
GOTO_S_MODE
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x2
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
// attempt to cause interrupt, it should not go through
jal cause_s_soft_interrupt
END_TESTS
TEST_STACK_AND_DATA

10
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
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@ -83,12 +83,12 @@ test_cases:
# Use timecmp register as readable and writable section of the CLINT # Use timecmp register as readable and writable section of the CLINT
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, write32_test # 32-bit write: success
.4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success .4byte CLINT_BASE + 0x4000, 0xBEEF00B5, read32_test # 32-bit read: success
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test# 16-bit write: failure *** Due to non-native access length in CLINT .4byte CLINT_BASE + 0x4000, 0xBEEF00B6, write16_test # 16-bit write: success
.4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test# 16-bit read: failure .4byte CLINT_BASE + 0x4000, 0xBEEF00B6, read16_test # 16-bit read: success
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test# 08-bit write: failure .4byte CLINT_BASE + 0x4000, 0xBEEF00B7, write08_test # 08-bit write: success
.4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test# 08-bit read: failure .4byte CLINT_BASE + 0x4000, 0xBEEF00B7, read08_test # 08-bit read: success
.4byte CLINT_BASE, 0xbad, executable_test# execute: instruction access fault .4byte CLINT_BASE, 0xbad, executable_test # execute: instruction access fault
# ----------------- PLIC --------------------- # ----------------- PLIC ---------------------

344
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
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@ -39,8 +39,7 @@ RVTEST_CODE_BEGIN
// //
// Initialize x6 as a virtual pointer to the test results // Initialize x6 as a virtual pointer to the test results
// Initialize x16 as a physical pointer to the test results // Initialize x16 as a physical pointer to the test results
// Set up stack pointer (sp = x2) // Set up stack pointer, mscratch, sscratch
// Set up the exception Handler, keeping the original handler in x4.
// //
// --------------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------------
@ -49,8 +48,12 @@ RVTEST_CODE_BEGIN
la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers la x16, test_1_res // x16 reserved for the physical address equivalent of x6 to be used in trap handlers
// any time either is used, both must be updated. // any time either is used, both must be updated.
// address for stack // address for normal user stack, mscratch stack, and sscratch stack
la sp, top_of_stack la sp, mscratch_top
csrw mscratch, sp
la sp, sscratch_top
csrw sscratch, sp
la sp, stack_top
.endm .endm
@ -61,11 +64,13 @@ j end_trap_triggers
// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
// This effectively includes everything that isn't to do with page faults (virtual memory) // This effectively includes everything that isn't to do with page faults (virtual memory)
//
// INPUTS: a3 (x13): the number of times one of the infinitely looping interrupt causes should loop before giving up and continuing without the interrupt firing.
//
cause_instr_addr_misaligned: cause_instr_addr_misaligned:
// cause a misaligned address trap // cause a misaligned address trap
auipc x28, 0 // get current PC, which is aligned auipc x28, 0 // get current PC, which is aligned
addi x28, x28, 0x3 // add 1 to pc to create misaligned address addi x28, x28, 0x2 // add 2 to pc to create misaligned address (Assumes compressed instructions are disabled)
jr x28 // cause instruction address midaligned trap jr x28 // cause instruction address midaligned trap
ret ret
@ -79,10 +84,10 @@ cause_instr_access:
ret ret
cause_illegal_instr: cause_illegal_instr:
.word 0x00000000 // a 32 bit zros is an illegal instruction .word 0x00000000 // 32 bit zero is an illegal instruction
ret ret
cause_breakpnt: // **** cause_breakpnt:
ebreak ebreak
ret ret
@ -113,10 +118,11 @@ cause_ecall:
ecall ecall
ret ret
cause_time_interrupt: cause_m_time_interrupt:
// The following code works for both RV32 and RV64. // The following code works for both RV32 and RV64.
// RV64 alone would be easier using double-word adds and stores // RV64 alone would be easier using double-word adds and stores
li x28, 0x30 // Desired offset from the present time li x28, 0x30 // Desired offset from the present time
mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles
la x29, 0x02004000 // MTIMECMP register in CLINT la x29, 0x02004000 // MTIMECMP register in CLINT
la x30, 0x0200BFF8 // MTIME register in CLINT la x30, 0x0200BFF8 // MTIME register in CLINT
lw x7, 0(x30) // low word of MTIME lw x7, 0(x30) // low word of MTIME
@ -127,21 +133,99 @@ cause_time_interrupt:
sw x31,4(x29) // store into most significant word of MTIMECMP sw x31,4(x29) // store into most significant word of MTIMECMP
nowrap: nowrap:
sw x28, 0(x29) // store into least significant word of MTIMECMP sw x28, 0(x29) // store into least significant word of MTIMECMP
loop: j loop // wait until interrupt occurs time_loop:
//wfi // *** this may now spin us forever in the loop???
addi a3, a3, -1
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
cause_soft_interrupt: cause_s_time_interrupt:
li x28, 0x20
csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
nop // added extra nops in so the csrs can get through the pipeline before returning.
ret
cause_m_soft_interrupt:
la x28, 0x02000000 // MSIP register in CLINT la x28, 0x02000000 // MSIP register in CLINT
li x29, 1 // 1 in the lsb li x29, 1 // 1 in the lsb
sw x29, 0(x28) // Write MSIP bit sw x29, 0(x28) // Write MSIP bit
ret ret
cause_ext_interrupt: cause_s_soft_interrupt:
li x28, 0x2
csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
ret
cause_m_ext_interrupt:
# ========== Configure PLIC ==========
# m priority threshold = 0
li x28, 0xC200000
li x29, 0
sw x29, 0(x28)
# s priority threshold = 7
li x28, 0xC201000
li x29, 7
sw x29, 0(x28)
# source 3 (GPIO) priority = 1
li x28, 0xC000000
li x29, 1
sw x29, 0x0C(x28)
# enable source 3 in M Mode
li x28, 0x0C002000
li x29, 0b1000
sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1 li x29, 0x1
sw x29, 8(x28) // enable the first pin as an output sw x29, 0x08(x28) // enable the first pin as an output
sw x29, 28(x28) // set first pin to high interrupt enable
sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt) sw x0, 0x1C(x28) // clear rise_ip
sw x0, 0x24(x28) // clear fall_ip
sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
m_ext_loop:
//wfi
addi a3, a3, -1
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_s_ext_interrupt_GPIO:
# ========== Configure PLIC ==========
# s priority threshold = 0
li x28, 0xC201000
li x29, 0
sw x29, 0(x28)
# m priority threshold = 7
li x28, 0xC200000
li x29, 7
sw x29, 0(x28)
# source 3 (GPIO) priority = 1
li x28, 0xC000000
li x29, 1
sw x29, 0x0C(x28)
# enable source 3 in S mode
li x28, 0x0C002080
li x29, 0b1000
sw x29, 0(x28)
li x28, 0x10060000 // load base GPIO memory location
li x29, 0x1
sw x29, 0x08(x28) // enable the first pin as an output
sw x0, 0x1C(x28) // clear rise_ip
sw x0, 0x24(x28) // clear fall_ip
sw x0, 0x2C(x28) // clear high_ip
sw x0, 0x34(x28) // clear low_ip
sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
s_ext_loop:
//wfi
addi a3, a3, -1
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
end_trap_triggers: end_trap_triggers:
@ -149,7 +233,7 @@ end_trap_triggers:
.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0 .macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
// MODE decides which mode this trap handler will be taken in (M or S mode) // MODE decides which mode this trap handler will be taken in (M or S mode)
// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1) // Vectored decides whether interrupts are handled with the vector table at trap_handler_MODE (1)
// vs Using the non-vector approach the rest of the trap handler takes (0) // vs Using the non-vector approach the rest of the trap handler takes (0)
// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1) // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
// vs not saving that info to the signature (0) // vs not saving that info to the signature (0)
@ -214,24 +298,28 @@ trap_handler_\MODE\():
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
j segfault_\MODE\() // 2: reserved j segfault_\MODE\() // 2: reserved
j soft_interrupt_\MODE\() // 3: breakpoint j m_soft_vector_\MODE\() // 3: breakpoint
j segfault_\MODE\() // 4: reserved j segfault_\MODE\() // 4: reserved
j time_interrupt_\MODE\() // 5: load access fault j s_time_vector_\MODE\() // 5: load access fault
j segfault_\MODE\() // 6: reserved j segfault_\MODE\() // 6: reserved
j time_interrupt_\MODE\() // 7: store access fault j m_time_vector_\MODE\() // 7: store access fault
j segfault_\MODE\() // 8: reserved j segfault_\MODE\() // 8: reserved
j ext_interrupt_\MODE\() // 9: ecall from S-mode j s_ext_vector_\MODE\() // 9: ecall from S-mode
j segfault_\MODE\() // 10: reserved j segfault_\MODE\() // 10: reserved
j ext_interrupt_\MODE\() // 11: ecall from M-mode j m_ext_vector_\MODE\() // 11: ecall from M-mode
// 12 through >=16 are reserved or designated for platform use // 12 through >=16 are reserved or designated for platform use
trap_unvectored_\MODE\(): trap_unvectored_\MODE\():
// The processor is always in machine mode when a trap takes us here csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
// *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
// save registers on stack before using // save registers on stack before using
sw x1, -4(sp) sw x1, -4(sp)
sw x5, -8(sp) sw x5, -8(sp)
sw x7, -12(sp)
// Record trap // Record trap
csrr x1, \MODE\()cause // record the mcause csrr x1, \MODE\()cause // record the mcause
@ -261,49 +349,36 @@ trap_unvectored_\MODE\():
// Respond to trap based on cause // Respond to trap based on cause
// All interrupts should return after being logged // All interrupts should return after being logged
csrr x1, \MODE\()cause csrr x1, \MODE\()cause
li x5, 0x8000000000000000 // if msb is set, it is an interrupt li x5, 0x80000000 // if msb is set, it is an interrupt
and x5, x5, x1 and x5, x5, x1
bnez x5, trapreturn_\MODE\() // return from interrupt bnez x5, interrupt_handler_\MODE\()
// Other trap handling is specified in the vector Table // Other trap handling is specified in the vector Table
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
la x5, exception_vector_table_\MODE\() la x5, exception_vector_table_\MODE\()
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
add x5, x5, x1 // compute address of vector in Table
lw x5, 0(x5) // fectch address of handler from vector Table
jr x5 // and jump to the handler
interrupt_handler_\MODE\():
la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
add x5, x5, x1 // compute address of vector in Table add x5, x5, x1 // compute address of vector in Table
lw x5, 0(x5) // fectch address of handler from vector Table lw x5, 0(x5) // fectch address of handler from vector Table
jr x5 // and jump to the handler jr x5 // and jump to the handler
segfault_\MODE\(): segfault_\MODE\():
lw x5, -8(sp) // restore registers from stack before faulting lw x7, -12(sp) // restore registers from stack before faulting
lw x5, -8(sp)
lw x1, -4(sp) lw x1, -4(sp)
j terminate_test // halt program. j terminate_test // halt program.
trapreturn_\MODE\(): trapreturn_\MODE\():
// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
csrr x1, \MODE\()epc // get the mepc csrr x1, \MODE\()epc // get the mepc
addi x1, x1, 4 // *** should be 2 for compressed instructions, see note. addi x1, x1, 4
// ****** KMG: the following is no longer as easy to determine. mepc gets the virtual address of the trapped instruction,
// ******** but in the handler, we work in M mode with physical addresses
// This means the address in mepc is suddenly pointing somewhere else.
// to get this to work, We could either retranslate the vaddr back into a paddr (probably on the scale of difficult to intractible)
// or we could come up with some other ingenious way to stay in M mode and see if the instruction was compressed.
// lw x5, 0(x1) // read the faulting instruction
// li x1, 3 // check bottom 2 bits of instruction to see if compressed
// and x5, x5, x1 // mask the other bits
// beq x5, x1, trapreturn_uncompressed // if 11, the instruction is return_uncompressed
// trapreturn_compressed:
// csrr x1, mepc // get the mepc again
// addi x1, x1, 2 // add 2 to find the next instruction
// j trapreturn_specified // and return
// trapreturn_uncompressed:
// csrr x1, mepc // get the mepc again
// addi x1, x1, 4 // add 4 to find the next instruction
trapreturn_specified_\MODE\(): trapreturn_specified_\MODE\():
// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc) // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
// note that we don't need to change x7 since it was a temporary register with no important address in it.
// so that when we return to a new virtual address, they're all in the right spot as well. // so that when we return to a new virtual address, they're all in the right spot as well.
beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address. beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
@ -333,7 +408,7 @@ trapreturn_specified_\MODE\():
and x7, x5, x6 // x7 = offset for x6 and x7, x5, x6 // x7 = offset for x6
add x6, x7, a1 // x6 = new address for the result pointer add x6, x7, a1 // x6 = new address for the result pointer
// set return address, stored temporarily in x1, to the next instruction, but in the new virtual page. // reset x1, which temporarily holds the return address that will be written to mepc.
and x1, x5, x1 // x1 = offset for the return address and x1, x5, x1 // x1 = offset for the return address
add x1, x1, a1 // x1 = new return address. add x1, x1, a1 // x1 = new return address.
@ -342,13 +417,16 @@ trapreturn_specified_\MODE\():
trapreturn_finished_\MODE\(): trapreturn_finished_\MODE\():
csrw \MODE\()epc, x1 // update the mepc with address of next instruction csrw \MODE\()epc, x1 // update the mepc with address of next instruction
lw x5, -8(sp) // restore registers from stack before returning lw x7, -12(sp) // restore registers from stack before returning
lw x5, -8(sp)
lw x1, -4(sp) lw x1, -4(sp)
csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
\MODE\()ret // return from trap \MODE\()ret // return from trap
// specific exception handlers
ecallhandler_\MODE\(): ecallhandler_\MODE\():
// Check input parameter a0. encoding above. // Check input parameter a0. encoding above.
// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
li x5, 2 // case 2: change to machine mode li x5, 2 // case 2: change to machine mode
beq a0, x5, ecallhandler_changetomachinemode_\MODE\() beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
li x5, 3 // case 3: change to supervisor mode li x5, 3 // case 3: change to supervisor mode
@ -359,22 +437,23 @@ ecallhandler_\MODE\():
j segfault_\MODE\() j segfault_\MODE\()
ecallhandler_changetomachinemode_\MODE\(): ecallhandler_changetomachinemode_\MODE\():
// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret // Force status.MPP (bits 12:11) to 11 to enter machine mode after mret
// note that it is impossible to return to M mode after a trap delegated to S mode
li x1, 0b1100000000000 li x1, 0b1100000000000
csrs \MODE\()status, x1 csrs \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
ecallhandler_changetosupervisormode_\MODE\(): ecallhandler_changetosupervisormode_\MODE\():
// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret
li x1, 0b1100000000000 li x1, 0b1000000000000
csrc \MODE\()status, x1 csrc \MODE\()status, x1
li x1, 0b0100000000000 li x1, 0b0100100000000
csrs \MODE\()status, x1 csrs \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
ecallhandler_changetousermode_\MODE\(): ecallhandler_changetousermode_\MODE\():
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 00 to enter user mode after (m/s)ret
li x1, 0b1100000000000 li x1, 0b1100100000000
csrc \MODE\()status, x1 csrc \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
@ -390,7 +469,6 @@ illegalinstr_\MODE\():
j trapreturn_\MODE\() // return to the code after recording the mcause j trapreturn_\MODE\() // return to the code after recording the mcause
accessfault_\MODE\(): accessfault_\MODE\():
// *** What do I have to do here?
j trapreturn_\MODE\() j trapreturn_\MODE\()
addr_misaligned_\MODE\(): addr_misaligned_\MODE\():
@ -399,34 +477,107 @@ addr_misaligned_\MODE\():
breakpt_\MODE\(): breakpt_\MODE\():
j trapreturn_\MODE\() j trapreturn_\MODE\()
soft_interrupt_\MODE\(): // Vectored interrupt handlers: record the fact that the handler went to the correct vector and then continue to handling
li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. // note: does not mess up any registers, saves and restores them to the stack instead.
sw x5, 0(x16)
s_soft_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
j vectored_int_end_\MODE\()
m_soft_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
j vectored_int_end_\MODE\()
s_time_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
j vectored_int_end_\MODE\()
m_time_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
j vectored_int_end_\MODE\()
s_ext_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
j vectored_int_end_\MODE\()
m_ext_vector_\MODE\():
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
sw x5, -4(sp) // put x5 on the scratch stack before messing with it
li x5, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
j vectored_int_end_\MODE\()
vectored_int_end_\MODE\():
sw x5, 0(x16) // store to signature to show vectored interrupts succeeded.
addi x6, x6, 4 addi x6, x6, 4
addi x16, x16, 4 addi x16, x16, 4
la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT lw x5, -4(sp) // restore x5 before continuing to handle trap in case its needed.
sw x0, 0(x28) j trap_stack_saved_\MODE\()
j trap_unvectored_\MODE\()
// specific interrupt handlers
soft_interrupt_\MODE\():
la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
sw x0, 0(x5)
csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit
lw x1, -4(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
// Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
// This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
time_interrupt_\MODE\(): time_interrupt_\MODE\():
li x5, 0x7EC la x5, 0x02004000 // MTIMECMP register in CLINT
sw x5, 0(x16) li x7, 0xFFFFFFFF
addi x6, x6, 4 sw x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
addi x16, x16, 4
la x29, 0x02004000 // MTIMECMP register in CLINT li x5, 0x20
li x30, 0xFFFFFFFF csrc \MODE\()ip, x5
sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trap_unvectored_\MODE\() j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
ext_interrupt_\MODE\(): ext_interrupt_\MODE\():
li x5, 0x7EC
sw x5, 0(x16)
addi x6, x6, 4
addi x16, x16, 4
li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
sw x0, 8(x28) // disable the first pin as an output sw x0, 8(x28) // disable the first pin as an output
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
j trap_unvectored_\MODE\()
# reset PLIC to turn off external interrupts
# m priority threshold = 7
li x28, 0xC200000
li x5, 0x7
sw x5, 0(x28)
# s priority threshold = 7
li x28, 0xC201000
li x5, 0x7
sw x5, 0(x28)
# source 3 (GPIO) priority = 0
li x28, 0xC000000
li x5, 0
sw x5, 0x0C(x28)
# disable source 3 in M mode
li x28, 0x0C002000
li x5, 0b0000
sw x5, 0(x28)
# enable source 3 in S mode
li x28, 0x0C002080
li x29, 0b0000
sw x29, 0(x28)
li x5, 0x200
csrc \MODE\()ip, x5
lw x1, -4(sp) // load return address from stack into ra (the address to return to after the loop is complete)
j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
// Table of trap behavior // Table of trap behavior
// lists what to do on each exception (not interrupts) // lists what to do on each exception (not interrupts)
@ -452,6 +603,22 @@ exception_vector_table_\MODE\():
.4byte segfault_\MODE\() // 14: reserved .4byte segfault_\MODE\() // 14: reserved
.4byte trapreturn_\MODE\() // 15: store page fault .4byte trapreturn_\MODE\() // 15: store page fault
.align 2 // aligns this data table to an 4 byte boundary
interrupt_vector_table_\MODE\():
.4byte segfault_\MODE\() // 0: reserved
.4byte soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
.4byte segfault_\MODE\() // 2: reserved
.4byte soft_interrupt_\MODE\() // 3: breakpoint
.4byte segfault_\MODE\() // 4: reserved
.4byte time_interrupt_\MODE\() // 5: load access fault
.4byte segfault_\MODE\() // 6: reserved
.4byte time_interrupt_\MODE\() // 7: store access fault
.4byte segfault_\MODE\() // 8: reserved
.4byte ext_interrupt_\MODE\() // 9: ecall from S-mode
.4byte segfault_\MODE\() // 10: reserved
.4byte ext_interrupt_\MODE\() // 11: ecall from M-mode
.align 2 .align 2
trap_return_pagetype_table_\MODE\(): trap_return_pagetype_table_\MODE\():
.4byte 0xC // 0: kilopage has 12 offset bits .4byte 0xC // 0: kilopage has 12 offset bits
@ -589,7 +756,8 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
// Turn translation off // Turn translation off
li x7, 0 // satp.MODE value for bare metal (0) li x7, 0 // satp.MODE value for bare metal (0)
slli x7, x7, 31 slli x7, x7, 31
sfence.vma x0, x0 // *** flushes global pte's as well csrw satp, x7
//sfence.vma x0, x0 // *** flushes global pte's as well
.endm .endm
.macro GOTO_SV32 ASID BASE_PPN .macro GOTO_SV32 ASID BASE_PPN
@ -602,7 +770,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field. li x28, \BASE_PPN // Base Pagetable physical page number, satp.PPN field.
add x7, x7, x28 add x7, x7, x28
csrw satp, x7 csrw satp, x7
sfence.vma x0, x0 // *** flushes global pte's as well //sfence.vma x0, x0 // *** flushes global pte's as well
.endm .endm
.macro WRITE_READ_CSR CSR VAL .macro WRITE_READ_CSR CSR VAL
@ -996,9 +1164,19 @@ rvtest_data:
RVTEST_DATA_END RVTEST_DATA_END
.align 2 // align stack to 4 byte boundary .align 2 // align stack to 4 byte boundary
bottom_of_stack: stack_bottom:
.fill 1024, 4, 0xdeadbeef .fill 1024, 4, 0xdeadbeef
top_of_stack: stack_top:
.align 2
mscratch_bottom:
.fill 512, 4, 0xdeadbeef
mscratch_top:
.align 2
sscratch_bottom:
.fill 512, 4, 0xdeadbeef
sscratch_top:
RVMODEL_DATA_BEGIN RVMODEL_DATA_BEGIN

13
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
View File

@ -21,24 +21,23 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests // test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
li x28, 0x8 li x28, 0x8
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts WRITE_READ_CSR mie, 0xFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler // cause traps, ensuring that we DONT go through the vectored part of the trap handler
// *** this assumes that interrupt code 0 remains reserved
CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

1
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S
View File

@ -26,7 +26,6 @@
INIT_TESTS INIT_TESTS
TRAP_HANDLER m TRAP_HANDLER m
// Test 5.3.2.3: Scratch registers test // Test 5.3.2.3: Scratch registers test
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode

27
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
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@ -21,34 +21,33 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.5 Unvectored interrupt tests // test 5.3.1.5 Unvectored interrupt tests
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits. TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
// li x28, 0x8 li x28, 0x2
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode csrs sstatus, x28 // set sstatus.SIE bit to 1
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts WRITE_READ_CSR mie, 0xFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
GOTO_S_MODE GOTO_S_MODE
// cause traps, ensuring that we DONT go through the vectored part of the trap handler jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
// *** this assumes that interrupt code 0 remains reserved
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. GOTO_M_MODE
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
GOTO_U_MODE jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. GOTO_U_MODE // Should cause software interrupt to fire off.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

30
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
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@ -21,7 +21,7 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -47,16 +47,21 @@ GOTO_U_MODE // Causes M mode ecall
GOTO_S_MODE // Causes U mode ecall GOTO_S_MODE // Causes U mode ecall
GOTO_M_MODE // Causes S mode ecall GOTO_M_MODE // Causes S mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_s_soft_interrupt
jal cause_ext_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt
jal cause_m_time_interrupt
jal cause_s_ext_interrupt_GPIO
jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
jal cause_instr_access jal cause_instr_access
jal cause_illegal_instr jal cause_illegal_instr
jal cause_breakpnt jal cause_breakpnt
@ -66,9 +71,16 @@ jal cause_store_addr_misaligned
jal cause_store_acc jal cause_store_acc
jal cause_ecall // M mode ecall jal cause_ecall // M mode ecall
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken jal cause_m_soft_interrupt
jal cause_ext_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
END_TESTS END_TESTS

78
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
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@ -21,38 +21,46 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
GOTO_S_MODE GOTO_S_MODE
li x28, 0x8 jal cause_instr_addr_misaligned
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
jal cause_load_acc
jal cause_store_addr_misaligned
jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_s_soft_interrupt
CAUSE_INSTR_ACCESS jal cause_m_soft_interrupt
CAUSE_ILLEGAL_INSTR //jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
CAUSE_BREAKPNT jal cause_m_time_interrupt
CAUSE_LOAD_ADDR_MISALIGNED li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
CAUSE_LOAD_ACC // since interrupts are not always enabled,
CAUSE_STORE_ADDR_MISALIGNED jal cause_s_ext_interrupt_GPIO
CAUSE_STORE_ACC li a3, 0x40
CAUSE_ECALL jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -63,21 +71,27 @@ GOTO_M_MODE // so we can write the delegate registers
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

42
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S Normal file
View File

@ -0,0 +1,42 @@
///////////////////////////////////////////
//
// WALLY-trap-sret
//
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
//
// Created 2022-04-10
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
#include "WALLY-TEST-LIB-32.h"
INIT_TESTS
TRAP_HANDLER m, DEBUG=1
// test 5.3.1.6 Interrupt enabling and priority tests
li x28, 0x400000
csrs mstatus, x28 // Set mstatus.tsr to 1.
GOTO_S_MODE
sret // attempt to run sret instruction.
// should cause illegal instruction exception despite being in s mode
END_TESTS
TEST_STACK_AND_DATA

74
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
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@ -21,10 +21,12 @@
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////// ///////////////////////////////////////////
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-32.h"
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
@ -32,27 +34,31 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE GOTO_U_MODE
// li x28, 0x8 jal cause_instr_addr_misaligned
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_load_acc
CAUSE_INSTR_ACCESS jal cause_store_addr_misaligned
CAUSE_ILLEGAL_INSTR jal cause_store_acc
CAUSE_BREAKPNT jal cause_ecall
CAUSE_LOAD_ADDR_MISALIGNED
CAUSE_LOAD_ACC
CAUSE_STORE_ADDR_MISALIGNED
CAUSE_STORE_ACC
CAUSE_ECALL
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -65,19 +71,25 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE GOTO_U_MODE
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -66,6 +66,8 @@ target_tests_nosim = \
WALLY-PIE-stack-s-01 \ WALLY-PIE-stack-s-01 \
WALLY-trap-sret-01 \ WALLY-trap-sret-01 \
WALLY-trap-01 \ WALLY-trap-01 \
WALLY-trap-s-01 \
WALLY-trap-u-01 \
# Have all 0's in references! # Have all 0's in references!
#WALLY-MEPC \ #WALLY-MEPC \
#WALLY-SEPC \ #WALLY-SEPC \

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -1014,3 +1014,11 @@ deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

422
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -1,219 +1,209 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 00000000
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
deadbeef 00000000
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 00000000
deadbeef 00000001 # scause value from s soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 00000000
deadbeef 00000003 # scause value from m soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 00000000
deadbeef 00000007 # scause value from m time interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 00000000
deadbeef 0000000b # scause value from m ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef ffffffff
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000000
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 00000000
deadbeef 00000001 # scause value from s soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall from test termination
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

356
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -1,181 +1,181 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 00000000
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
deadbeef 00000000
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 00000000
deadbeef 00000003 # scause value from m soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 00000000
deadbeef 00000007 # scause value from m time interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 00000000
deadbeef 0000000b # scause value from m ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef ffffffff
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000000
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall from test termination
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S
View File

@ -36,7 +36,7 @@ WRITE_READ_CSR mie, 0xFFF
// test 5.3.1.6 Interrupt enabling and priority tests // test 5.3.1.6 Interrupt enabling and priority tests
// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling // Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
jal cause_m_soft_interrupt jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x8 li x28, 0x8
csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S
View File

@ -40,7 +40,7 @@ WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
GOTO_S_MODE GOTO_S_MODE
// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling // Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling
jal cause_s_soft_interrupt jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
li x28, 0x2 li x28, 0x2
csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen

52
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -66,7 +66,9 @@ j end_trap_triggers
// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
// This effectively includes everything that isn't to do with page faults (virtual memory) // This effectively includes everything that isn't to do with page faults (virtual memory)
//
// INPUTS: a3 (x13): the number of times one of the infinitely looping interrupt causes should loop before giving up and continuing without the interrupt firing.
//
cause_instr_addr_misaligned: cause_instr_addr_misaligned:
// cause a misaligned address trap // cause a misaligned address trap
auipc x28, 0 // get current PC, which is aligned auipc x28, 0 // get current PC, which is aligned
@ -122,6 +124,7 @@ cause_m_time_interrupt:
// The following code works for both RV32 and RV64. // The following code works for both RV32 and RV64.
// RV64 alone would be easier using double-word adds and stores // RV64 alone would be easier using double-word adds and stores
li x28, 0x30 // Desired offset from the present time li x28, 0x30 // Desired offset from the present time
mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles
la x29, 0x02004000 // MTIMECMP register in CLINT la x29, 0x02004000 // MTIMECMP register in CLINT
la x30, 0x0200BFF8 // MTIME register in CLINT la x30, 0x0200BFF8 // MTIME register in CLINT
lw x7, 0(x30) // low word of MTIME lw x7, 0(x30) // low word of MTIME
@ -133,8 +136,9 @@ cause_m_time_interrupt:
nowrap: nowrap:
sw x28, 0(x29) // store into least significant word of MTIMECMP sw x28, 0(x29) // store into least significant word of MTIMECMP
time_loop: time_loop:
wfi //wfi // *** this may now spin us forever in the loop???
j time_loop // wait until interrupt occurs addi a3, a3, -1
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
cause_s_time_interrupt: cause_s_time_interrupt:
@ -160,6 +164,10 @@ cause_m_ext_interrupt:
li x28, 0xC200000 li x28, 0xC200000
li x29, 0 li x29, 0
sw x29, 0(x28) sw x29, 0(x28)
# s priority threshold = 7
li x28, 0xC201000
li x29, 7
sw x29, 0(x28)
# source 3 (GPIO) priority = 1 # source 3 (GPIO) priority = 1
li x28, 0xC000000 li x28, 0xC000000
li x29, 1 li x29, 1
@ -181,9 +189,9 @@ cause_m_ext_interrupt:
sw x29, 0x28(x28) // set first pin to interrupt on a rising value sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
m_ext_loop: m_ext_loop:
wfi //wfi
lw x29, 0x8(x28) addi a3, a3, -1
bnez x28, m_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins. bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
cause_s_ext_interrupt_GPIO: cause_s_ext_interrupt_GPIO:
@ -217,14 +225,9 @@ cause_s_ext_interrupt_GPIO:
sw x29, 0x28(x28) // set first pin to interrupt on a rising value sw x29, 0x28(x28) // set first pin to interrupt on a rising value
sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt) sw x29, 0x0C(x28) // write a 1 to the first output pin (cause interrupt)
s_ext_loop: s_ext_loop:
wfi //wfi
lw x29, 0x8(x28) addi a3, a3, -1
bnez x28, s_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins. bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret
cause_s_ext_interrupt_IP:
li x28, 0x200
csrs mip, x28 // set supervisor external interrupt pending.
ret ret
end_trap_triggers: end_trap_triggers:
@ -436,21 +439,22 @@ ecallhandler_\MODE\():
ecallhandler_changetomachinemode_\MODE\(): ecallhandler_changetomachinemode_\MODE\():
// Force status.MPP (bits 12:11) to 11 to enter machine mode after mret // Force status.MPP (bits 12:11) to 11 to enter machine mode after mret
// note that it is impossible to return to M mode after a trap delegated to S mode
li x1, 0b1100000000000 li x1, 0b1100000000000
csrs \MODE\()status, x1 csrs \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
ecallhandler_changetosupervisormode_\MODE\(): ecallhandler_changetosupervisormode_\MODE\():
// Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 01 to enter supervisor mode after (m/s)ret
li x1, 0b1000000000000 li x1, 0b1000000000000
csrc \MODE\()status, x1 csrc \MODE\()status, x1
li x1, 0b0100000000000 li x1, 0b0100100000000
csrs \MODE\()status, x1 csrs \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
ecallhandler_changetousermode_\MODE\(): ecallhandler_changetousermode_\MODE\():
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret // Force status.MPP (bits 12:11) and status.SPP (bit 8) to 00 to enter user mode after (m/s)ret
li x1, 0b1100000000000 li x1, 0b1100100000000
csrc \MODE\()status, x1 csrc \MODE\()status, x1
j trapreturn_\MODE\() j trapreturn_\MODE\()
@ -543,18 +547,26 @@ ext_interrupt_\MODE\():
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt) sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
# reset PLIC to turn off external interrupts # reset PLIC to turn off external interrupts
# priority threshold = 7 # m priority threshold = 7
li x28, 0xC200000 li x28, 0xC200000
li x5, 0x7 li x5, 0x7
sw x5, 0(x28) sw x5, 0(x28)
# s priority threshold = 7
li x28, 0xC201000
li x5, 0x7
sw x5, 0(x28)
# source 3 (GPIO) priority = 0 # source 3 (GPIO) priority = 0
li x28, 0xC000000 li x28, 0xC000000
li x5, 0 li x5, 0
sw x5, 0x0C(x28) sw x5, 0x0C(x28)
# disable source 3 # disable source 3 in M mode
li x28, 0x0C002000 li x28, 0x0C002000
li x5, 0b0000 li x5, 0b0000
sw x5, 0(x28) sw x5, 0(x28)
# enable source 3 in S mode
li x28, 0x0C002080
li x29, 0b0000
sw x29, 0(x28)
li x5, 0x200 li x5, 0x200
csrc \MODE\()ip, x5 csrc \MODE\()ip, x5

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
View File

@ -37,7 +37,7 @@ WRITE_READ_CSR mie, 0xFFF
// cause traps, ensuring that we DONT go through the vectored part of the trap handler // cause traps, ensuring that we DONT go through the vectored part of the trap handler
jal cause_m_time_interrupt jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
END_TESTS END_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
View File

@ -41,7 +41,7 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE GOTO_S_MODE
jal cause_s_soft_interrupt jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
GOTO_M_MODE GOTO_M_MODE

10
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -52,12 +52,10 @@ jal cause_s_soft_interrupt
jal cause_m_soft_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
@ -77,8 +75,10 @@ jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire si
jal cause_m_soft_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt jal cause_m_ext_interrupt

76
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -25,34 +25,42 @@
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
GOTO_S_MODE GOTO_S_MODE
li x28, 0x8 jal cause_instr_addr_misaligned
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
jal cause_load_acc
jal cause_store_addr_misaligned
jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_s_soft_interrupt
CAUSE_INSTR_ACCESS jal cause_m_soft_interrupt
CAUSE_ILLEGAL_INSTR //jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
CAUSE_BREAKPNT jal cause_m_time_interrupt
CAUSE_LOAD_ADDR_MISALIGNED li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
CAUSE_LOAD_ACC // since interrupts are not always enabled,
CAUSE_STORE_ADDR_MISALIGNED jal cause_s_ext_interrupt_GPIO
CAUSE_STORE_ACC li a3, 0x40
CAUSE_ECALL jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -63,21 +71,27 @@ GOTO_M_MODE // so we can write the delegate registers
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

72
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -25,6 +25,8 @@
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
@ -32,27 +34,31 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE GOTO_U_MODE
// li x28, 0x8 jal cause_instr_addr_misaligned
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_load_acc
CAUSE_INSTR_ACCESS jal cause_store_addr_misaligned
CAUSE_ILLEGAL_INSTR jal cause_store_acc
CAUSE_BREAKPNT jal cause_ecall
CAUSE_LOAD_ADDR_MISALIGNED
CAUSE_LOAD_ACC
CAUSE_STORE_ADDR_MISALIGNED
CAUSE_STORE_ACC
CAUSE_ECALL
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -65,19 +71,25 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE GOTO_U_MODE
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS