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clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals

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This commit is contained in:
Kip Macsai-Goren 2022-05-04 23:01:23 +00:00
parent 88173b8bb3
commit 8f748c4014
9 changed files with 51 additions and 51 deletions
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12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
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@ -6,16 +6,16 @@
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
8000016c # mtval of breakpoint instruction adress 80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
80000175 # mtval of misaligned address 80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000191 # mtval of address with misaligned store instr 80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)
@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # mtval of faulting instruction (0x0) 00000000 # mtval of faulting instruction (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
8000016c # mtval of breakpoint instruction adress 80000168 # mtval of breakpoint instruction adress
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
80000175 # mtval of misaligned address 80000171 # mtval of misaligned address
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000005 # mcause from load access 00000005 # mcause from load access
00000000 # mtval of accessed adress (0x0) 00000000 # mtval of accessed adress (0x0)
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
80000191 # mtval of address with misaligned store instr 80000189 # mtval of address with misaligned store instr
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000007 # mcause from store access 00000007 # mcause from store access
00000000 # mtval of accessed address (0x0) 00000000 # mtval of accessed address (0x0)

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -9,16 +9,16 @@
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
8000016c # stval of breakpoint instruction adress 80000168 # stval of breakpoint instruction adress
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000175 # stval of misaligned address 80000171 # stval of misaligned address
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000191 # stval of address with misaligned store instr 80000189 # stval of address with misaligned store instr
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)
@ -64,16 +64,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
8000016c # stval of breakpoint instruction adress 80000168 # stval of breakpoint instruction adress
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000175 # stval of misaligned address 80000171 # stval of misaligned address
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000191 # stval of address with misaligned store instr 80000189 # stval of address with misaligned store instr
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output
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@ -9,16 +9,16 @@
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
8000016c # stval of breakpoint instruction adress 80000168 # stval of breakpoint instruction adress
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000175 # stval of misaligned address 80000171 # stval of misaligned address
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000191 # stval of address with misaligned store instr 80000189 # stval of address with misaligned store instr
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)
@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl
00000000 # stval of faulting instruction (0x0) 00000000 # stval of faulting instruction (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
8000016c # stval of breakpoint instruction adress 80000168 # stval of breakpoint instruction adress
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
80000175 # stval of misaligned address 80000171 # stval of misaligned address
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000005 # scause from load access 00000005 # scause from load access
00000000 # stval of accessed adress (0x0) 00000000 # stval of accessed adress (0x0)
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000006 # scause from store misaligned 00000006 # scause from store misaligned
80000191 # stval of address with misaligned store instr 80000189 # stval of address with misaligned store instr
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000007 # scause from store access 00000007 # scause from store access
00000000 # stval of accessed address (0x0) 00000000 # stval of accessed address (0x0)

9
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-wfi-01.reference_output
View File

@ -1013,3 +1013,12 @@ deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

12
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
View File

@ -75,10 +75,9 @@ cause_instr_addr_misaligned:
ret ret
cause_instr_access: cause_instr_access:
la t3, 0x0 // address zero is an address with no memory
sw ra, -4(sp) // push the return adress ontot the stack sw ra, -4(sp) // push the return adress ontot the stack
addi sp, sp, -4 addi sp, sp, -4
jalr t3 // cause instruction access trap jalr zero // cause instruction access trap (address zero is an address with no memory)
lw ra, 0(sp) // pop return adress back from the stack lw ra, 0(sp) // pop return adress back from the stack
addi sp, sp, 4 addi sp, sp, 4
ret ret
@ -98,8 +97,7 @@ cause_load_addr_misaligned:
ret ret
cause_load_acc: cause_load_acc:
la t3, 0 // 0 is an address with no memory lw t4, 0(zero) // load from unimplemented address (zero)
lw t4, 0(t3) // load from unimplemented address
ret ret
cause_store_addr_misaligned: cause_store_addr_misaligned:
@ -109,8 +107,7 @@ cause_store_addr_misaligned:
ret ret
cause_store_acc: cause_store_acc:
la t3, 0 // 0 is an address with no memory sw t4, 0(zero) // store to unimplemented address (zero)
sw t4, 0(t3) // store to unimplemented address
ret ret
cause_ecall: cause_ecall:
@ -134,7 +131,6 @@ cause_m_time_interrupt:
nowrap: nowrap:
sw t3, 0(t4) // store into least significant word of MTIMECMP sw t3, 0(t4) // store into least significant word of MTIMECMP
time_loop: time_loop:
//wfi // *** this may now spin us forever in the loop???
addi a3, a3, -1 addi a3, a3, -1
bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt bnez a3, time_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
@ -188,7 +184,6 @@ cause_m_ext_interrupt:
sw t4, 0x28(t3) // set first pin to interrupt on a rising value sw t4, 0x28(t3) // set first pin to interrupt on a rising value
sw t4, 0x0C(t3) // write a 1 to the first output pin (cause interrupt) sw t4, 0x0C(t3) // write a 1 to the first output pin (cause interrupt)
m_ext_loop: m_ext_loop:
//wfi
addi a3, a3, -1 addi a3, a3, -1
bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt bnez a3, m_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret
@ -225,7 +220,6 @@ cause_s_ext_interrupt_GPIO:
sw t4, 0x28(t3) // set first pin to interrupt on a rising value sw t4, 0x28(t3) // set first pin to interrupt on a rising value
sw t4, 0x0C(t3) // write a 1 to the first output pin (cause interrupt) sw t4, 0x0C(t3) // write a 1 to the first output pin (cause interrupt)
s_ext_loop: s_ext_loop:
//wfi
addi a3, a3, -1 addi a3, a3, -1
bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt bnez a3, s_ext_loop // go through this loop for [a3 value] iterations before returning without performing interrupt
ret ret

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
View File

@ -14,13 +14,13 @@
00000000 00000000
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
00000000 00000000
80000404 # mtval of breakpoint instruction adress (0x80000404) 80000400 # mtval of breakpoint instruction adress (0x80000400)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
00000000 00000000
8000040d # mtval of misaligned address (0x8000040d) 80000409 # mtval of misaligned address (0x80000409)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -32,7 +32,7 @@
00000000 00000000
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
00000000 00000000
80000429 # mtval of address with misaligned store instr (0x80000429) 80000421 # mtval of address with misaligned store instr (0x80000421)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -126,13 +126,13 @@ ffffffff
00000000 00000000
00000003 # mcause from Breakpoint 00000003 # mcause from Breakpoint
00000000 00000000
80000404 # mtval of breakpoint instruction adress (0x80000404) 80000400 # mtval of breakpoint instruction adress (0x80000400)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
00000004 # mcause from load address misaligned 00000004 # mcause from load address misaligned
00000000 00000000
8000040d # mtval of misaligned address (0x8000040d) 80000409 # mtval of misaligned address (0x80000409)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000
@ -144,7 +144,7 @@ ffffffff
00000000 00000000
00000006 # mcause from store misaligned 00000006 # mcause from store misaligned
00000000 00000000
80000429 # mtval of address with misaligned store instr (0x80000429) 80000421 # mtval of address with misaligned store instr (0x80000421)
00000000 00000000
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
00000000 00000000

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
View File

@ -20,13 +20,13 @@
00000000 00000000
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
00000000 00000000
80000404 # stval of breakpoint instruction adress (0x80000404) 80000400 # stval of breakpoint instruction adress (0x80000400)
00000000 00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
00000000 00000000
8000040d # stval of misaligned address (0x8000040d) 80000409 # stval of misaligned address (0x80000409)
00000000 00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
@ -38,7 +38,7 @@
00000000 00000000
00000006 # scause from store misaligned 00000006 # scause from store misaligned
00000000 00000000
80000429 # stval of address with misaligned store instr (0x80000429) 80000421 # stval of address with misaligned store instr (0x80000421)
00000000 00000000
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
@ -130,13 +130,13 @@ ffffffff
00000000 00000000
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
00000000 00000000
80000404 # stval of breakpoint instruction adress (0x80000404) 80000400 # stval of breakpoint instruction adress (0x80000400)
00000000 00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
00000000 00000000
8000040d # stval of misaligned address (0x8000040d) 80000409 # stval of misaligned address (0x80000409)
00000000 00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000
@ -148,7 +148,7 @@ ffffffff
00000000 00000000
00000006 # scause from store misaligned 00000006 # scause from store misaligned
00000000 00000000
80000429 # stval of address with misaligned store instr (0x80000429) 80000421 # stval of address with misaligned store instr (0x80000421)
00000000 00000000
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
View File

@ -20,13 +20,13 @@
00000000 00000000
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
00000000 00000000
80000404 # stval of breakpoint instruction adress (0x80000404) 80000400 # stval of breakpoint instruction adress (0x80000400)
00000000 00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
00000000 00000000
8000040d # stval of misaligned address (0x8000040d) 80000409 # stval of misaligned address (0x80000409)
00000000 00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
@ -38,7 +38,7 @@
00000000 00000000
00000006 # scause from store misaligned 00000006 # scause from store misaligned
00000000 00000000
80000429 # stval of address with misaligned store instr (0x80000429) 80000421 # stval of address with misaligned store instr (0x80000421)
00000000 00000000
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
00000000 00000000
@ -116,13 +116,13 @@ ffffffff
00000000 00000000
00000003 # scause from Breakpoint 00000003 # scause from Breakpoint
00000000 00000000
80000404 # stval of breakpoint instruction adress (0x80000404) 80000400 # stval of breakpoint instruction adress (0x80000400)
00000000 00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000
00000004 # scause from load address misaligned 00000004 # scause from load address misaligned
00000000 00000000
8000040d # stval of misaligned address (0x8000040d) 80000409 # stval of misaligned address (0x80000409)
00000000 00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000
@ -134,7 +134,7 @@ ffffffff
00000000 00000000
00000006 # scause from store misaligned 00000006 # scause from store misaligned
00000000 00000000
80000429 # stval of address with misaligned store instr (0x80000429) 80000421 # stval of address with misaligned store instr (0x80000421)
00000000 00000000
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
00000000 00000000

9
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
View File

@ -77,10 +77,9 @@ cause_instr_addr_misaligned:
ret ret
cause_instr_access: cause_instr_access:
la t3, 0x0 // address zero is an address with no memory
sd ra, -8(sp) // push the return adress onto the stack sd ra, -8(sp) // push the return adress onto the stack
addi sp, sp, -8 addi sp, sp, -8
jalr t3 // cause instruction access trap jalr zero // cause instruction access trap (address zero is an address with no memory)
ld ra, 0(sp) // pop return adress back from the stack ld ra, 0(sp) // pop return adress back from the stack
addi sp, sp, 8 addi sp, sp, 8
ret ret
@ -100,8 +99,7 @@ cause_load_addr_misaligned:
ret ret
cause_load_acc: cause_load_acc:
la t3, 0 // 0 is an address with no memory lw t4, 0(zero) // load from unimplemented address ( zero)
lw t4, 0(t3) // load from unimplemented address
ret ret
cause_store_addr_misaligned: cause_store_addr_misaligned:
@ -111,8 +109,7 @@ cause_store_addr_misaligned:
ret ret
cause_store_acc: cause_store_acc:
la t3, 0 // 0 is an address with no memory sw t4, 0(zero) // store to unimplemented address (zero)
sw t4, 0(t3) // store to unimplemented address
ret ret
cause_ecall: cause_ecall: