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Added commenets and formating to abhcachefsm and abhcacheinterface.

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This commit is contained in:
Ross Thompson 2023-01-17 22:22:23 -06:00
parent f146a01344
commit 8f4f17a4c8
2 changed files with 28 additions and 24 deletions
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21
pipelined/src/ebu/ahbcacheinterface.sv
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@ -32,13 +32,14 @@
module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHBW) (
input logic HCLK, HRESETn,
// bus interface
// bus interface controls
input logic HREADY, // AHB peripheral ready
input logic [`AHBW-1:0] HRDATA, // AHB read data
output logic [2:0] HSIZE, // AHB transaction width
output logic [2:0] HBURST, // AHB burst length
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation
output logic [2:0] HSIZE, // AHB transaction width
output logic [2:0] HBURST, // AHB burst length
// bus interface buses
input logic [`AHBW-1:0] HRDATA, // AHB read data
output logic [`PA_BITS-1:0] HADDR, // AHB address
output logic [`AHBW-1:0] HWDATA, // AHB write data
output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask
@ -51,7 +52,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHB
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus
output logic [LOGWPL-1:0] BeatCount, // Beat position within the cache line
output logic [LOGWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// uncached interface
@ -67,11 +68,11 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, LLENPOVERAHB
output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
localparam integer BeatCountThreshold = BEATSPERLINE - 1; //
logic [`PA_BITS-1:0] LocalHADDR;
logic [LOGWPL-1:0] BeatCountDelayed;
logic CaptureEn;
logic [`AHBW-1:0] PreHWDATA;
localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
logic [LOGWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
genvar index;

31
pipelined/src/ebu/buscachefsm.sv
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@ -33,26 +33,29 @@ module buscachefsm #(parameter integer BeatCountThreshold, LOGWPL) (
input logic HRESETn,
// IEU interface
input logic Flush,
input logic [1:0] BusRW,
input logic Stall,
output logic BusCommitted,
output logic BusStall,
output logic CaptureEn,
input logic Stall, // Core pipeline is stalled
input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write
output logic BusStall, // Bus is busy with an in flight memory operation
output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
// ahb cache interface locals.
output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
// cache interface
input logic [1:0] CacheBusRW,
output logic CacheBusAck,
input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch
output logic CacheBusAck, // Handshack to $ indicating bus transaction completed
// lsu interface
output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed,
output logic SelBusBeat,
output logic [LOGWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase
output logic [LOGWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage
output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
// BUS interface
input logic HREADY,
output logic [1:0] HTRANS,
output logic HWRITE,
output logic [2:0] HBURST
input logic HREADY, // AHB peripheral ready
output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
output logic HWRITE, // AHB 0: Read operation 1: Write operation
output logic [2:0] HBURST // AHB burst length
);
typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;