From 8f3acedec8223bbdd419ca358ed200dfe26b31ed Mon Sep 17 00:00:00 2001
From: Kevin Kim <kevindkim723@gmail.com>
Date: Mon, 6 Mar 2023 05:52:08 -0800
Subject: [PATCH] formatted files

---
 src/ieu/bmu/bitreverse.sv |  1 -
 src/ieu/bmu/bmuctrl.sv    |  6 ++----
 src/ieu/bmu/ext.sv        |  2 --
 src/ieu/bmu/popcnt.sv     |  2 --
 src/ieu/bmu/zbb.sv        | 21 ++++-----------------
 src/ieu/bmu/zbc.sv        |  5 ++---
 src/ieu/shifter.sv        |  1 -
 7 files changed, 8 insertions(+), 30 deletions(-)

diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv
index 559bb0c09..644783e57 100644
--- a/src/ieu/bmu/bitreverse.sv
+++ b/src/ieu/bmu/bitreverse.sv
@@ -37,7 +37,6 @@ module bitreverse #(parameter WIDTH=32) (
   for (i=0; i<WIDTH;i++) begin:loop
     assign b[WIDTH-i-1] = a[i];
   end
-
 endmodule
 
 
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 3675a7114..ef9d2bb89 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -63,11 +63,11 @@ module bmuctrl(
   logic       MaskD;                           // Indicates if zbs instruction in Decode Stage
   logic       PreShiftD;                       // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
   logic [2:0] BALUControlD;                    // ALU Control signals for B instructions
+
   `define BMUCTRLW 16
 
   logic [`BMUCTRLW-1:0] BMUControlsD;                 // Main B Instructions Decoder control signals
 
-
   // Extract fields
   assign OpD = InstrD[6:0];
   assign Funct3D = InstrD[14:12];
@@ -158,7 +158,7 @@ module bmuctrl(
       17'b0110011_0000101_111:   BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0;  // maxu
       17'b0110011_0000101_100:   BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0;  // min
       17'b0110011_0000101_101:   BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0;  // minu
-      default:                   BMUControlsD = {Funct3D, {12'b0}, {1'b1}};        // not B instruction or shift
+      default:                   BMUControlsD = {Funct3D, {12'b0}, {1'b1}};             // not B instruction or shift
     endcase
 
   // Unpack Control Signals
@@ -170,8 +170,6 @@ module bmuctrl(
   // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches
   assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6];
 
-   
-
   // BMU Execute stage pipieline control register
   flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD,  BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE});
 endmodule
\ No newline at end of file
diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv
index 3a832de65..250616b58 100644
--- a/src/ieu/bmu/ext.sv
+++ b/src/ieu/bmu/ext.sv
@@ -42,6 +42,4 @@ module ext #(parameter WIDTH = 32) (
   assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
 
   mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult);
-
- 
 endmodule
\ No newline at end of file
diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv
index 544c1344f..36de67432 100644
--- a/src/ieu/bmu/popcnt.sv
+++ b/src/ieu/bmu/popcnt.sv
@@ -39,6 +39,4 @@ module popcnt #(parameter WIDTH = 32) (
   end
 
   assign PopCnt = sum[$clog2(WIDTH):0];
-
-  
 endmodule
diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv
index 54459db82..70b984ead 100644
--- a/src/ieu/bmu/zbb.sv
+++ b/src/ieu/bmu/zbb.sv
@@ -37,32 +37,19 @@ module zbb #(parameter WIDTH=32) (
   input  logic             lt,           // lt flag
   input  logic [2:0]       ZBBSelect,    // Indicates word operation
   output logic [WIDTH-1:0] ZBBResult);   // ZBB result
-
   
-  // count result
-  logic [WIDTH-1:0] CntResult;           
-  
-  // min,max result
-  logic [WIDTH-1:0] MaxResult;           
-  logic [WIDTH-1:0] MinResult;           
-
-  // byte results
-  logic [WIDTH-1:0] ByteResult;
-
-  // sign/zero extend results
-  logic [WIDTH-1:0] ExtResult;           // sign/zero extend result
-
+  logic [WIDTH-1:0] CntResult;           // count result
+  logic [WIDTH-1:0] MinResult,MaxResult; // min,max result
+  logic [WIDTH-1:0] ByteResult;          // byte results
+  logic [WIDTH-1:0] ExtResult;           // sign/zero extend results
 
   cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult));
   byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult));
   ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult));
 
-
   assign MaxResult = (lt) ? B : A;
   assign MinResult = (lt) ? A : B;
 
   // ZBB Result select mux
   mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult);
-
-
 endmodule
\ No newline at end of file
diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv
index c1ed706ba..d53dd75e6 100644
--- a/src/ieu/bmu/zbc.sv
+++ b/src/ieu/bmu/zbc.sv
@@ -42,14 +42,13 @@ module zbc #(parameter WIDTH=32) (
   assign select = ~Funct3[1:0];
 
   bitreverse #(WIDTH) brB(.a(B), .b(RevB));
-   
 
   mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, select, x);
   mux3 #(WIDTH) ymux({{1'b0},RevB[WIDTH-2:0]}, RevB, B,  select, y);
+
   clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult));
+  
   bitreverse  #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult));
 
   mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
-
-
 endmodule
\ No newline at end of file
diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv
index b784414b9..dbed7655c 100644
--- a/src/ieu/shifter.sv
+++ b/src/ieu/shifter.sv
@@ -39,7 +39,6 @@ module shifter (
   logic [2*`XLEN-2:0]      z, zshift;                       // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
   logic [`LOG_XLEN-1:0]    amttrunc, offset;                // Shift amount adjusted for RV64, right-shift amount
 
-
   if (`ZBB_SUPPORTED) begin: rotfunnel
     if (`XLEN==32) begin // rv32 with rotates
       always_comb  // funnel mux