From 8ee80c5d5432ad936c4f87397c459960450d7d1d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 12 Jan 2023 12:07:07 -0600
Subject: [PATCH] Created separate imperas testbench. Resolved logger issue
 with the duplicated instructions after commit.

---
 .../regression/wally-pipelined-imperas.do     | 45 +++++++++++++++++++
 pipelined/testbench/testbench_imperas.sv      |  6 +--
 2 files changed, 47 insertions(+), 4 deletions(-)
 create mode 100644 pipelined/regression/wally-pipelined-imperas.do

diff --git a/pipelined/regression/wally-pipelined-imperas.do b/pipelined/regression/wally-pipelined-imperas.do
new file mode 100644
index 000000000..e0d5070a3
--- /dev/null
+++ b/pipelined/regression/wally-pipelined-imperas.do
@@ -0,0 +1,45 @@
+# wally-pipelined.do 
+#
+# Modification by Oklahoma State University & Harvey Mudd College
+# Use with Testbench 
+# James Stine, 2008; David Harris 2021
+# Go Cowboys!!!!!!
+#
+# Takes 1:10 to run RV64IC tests using gui
+
+# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
+
+# Use this wally-pipelined.do file to run this example.
+# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
+#     do wally-pipelined.do
+# or, to run from a shell, type the following at the shell prompt:
+#     vsim -do wally-pipelined.do -c
+# (omit the "-c" to see the GUI while running from the shell)
+
+onbreak {resume}
+
+# create library
+if [file exists work] {
+    vdel -all
+}
+vlib work
+
+# compile source files
+# suppress spurious warnngs about 
+# "Extra checking for conflicts with always_comb done at vopt time"
+# because vsim will run vopt
+
+# start and run simulation
+# remove +acc flag for faster sim during regressions if there is no need to access internal signals
+        # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN.  For now just live with the warnings.
+vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench_imperas.sv ../testbench/common/*.sv   ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 
+vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt 
+vsim workopt +nowarn3829  -fatal 7
+view wave
+#-- display input and output signals as hexidecimal values
+add log -recursive /*
+do wave.do
+
+run -all
+noview ../testbench/testbench_imperas.sv
+view wave
diff --git a/pipelined/testbench/testbench_imperas.sv b/pipelined/testbench/testbench_imperas.sv
index 372257c5c..929f16b22 100644
--- a/pipelined/testbench/testbench_imperas.sv
+++ b/pipelined/testbench/testbench_imperas.sv
@@ -32,10 +32,8 @@
 `include "wally-config.vh"
 `include "tests.vh"
 
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
 
-module testbench_imperas;
+module testbench;
   parameter DEBUG=0;
   parameter TEST="none";
  
@@ -694,7 +692,7 @@ module rvviTrace();
   flopenrc #(`XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
   flopenrc #(1)     InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
 
-  assign valid = InstrValidW;
+  assign valid = InstrValidW & ~StallW & ~FlushW;
   assign insn = InstrRawW;
   assign pc_rdata = PCW;