mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved UnalignedPCNextF mux into IFU
This commit is contained in:
David Harris
parent
0ff049db86
commit
8eace30f49
@ -56,8 +56,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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output logic BPWrongM, // Prediction is wrong
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// Mem
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output logic CommittedF, // I$ or bus memory operation started, delay interrupts
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input logic [P.XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
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output logic [P.XLEN-1:0] PC2NextF, // Selected PC between branch prediction and next valid PC if CSRWriteFence
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input logic [P.XLEN-1:0] EPCM, // Exception Program counter from privileged unit
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input logic [P.XLEN-1:0] TrapVectorM, // Trap vector, from privileged unit
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input logic RetM, TrapM, // return instruction, or trap
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output logic [31:0] InstrD, // The decoded instruction in Decode stage
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output logic [31:0] InstrM, // The decoded instruction in Memory stage
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output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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@ -100,6 +101,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic [P.XLEN-1:0] PCNextF; // Next PCF, selected from Branch predictor, Privilege, or PC+2/4
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logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
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logic [P.XLEN-1:0] PC2NextF; // Selected PC between branch prediction and next valid PC if CSRWriteFence
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logic [P.XLEN-1:0] UnalignedPCNextF; // The next PCF, but not aligned to 2 bytes.
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logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
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logic [P.XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
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logic [P.XLEN-1:0] PCSpillNextF; // Next PCF after possible + 2 to handle spill
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@ -128,7 +132,6 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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logic IFUCacheBusStallF; // EIther I$ or bus busy with multicycle operation
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logic GatedStallD; // StallD gated by selected next spill
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// branch predictor signal
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logic [P.XLEN-1:0] PC1NextF; // Branch predictor next PCF
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logic BusCommittedF; // Bus memory operation in flight, delay interrupts
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logic CacheCommittedF; // I$ memory operation started, delay interrupts
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logic SelIROM; // PMA indicates instruction address is in the IROM
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@ -300,20 +303,23 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.XLEN) pcmux2(.d0(PC1NextF), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PC2NextF));
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else assign PC2NextF = PC1NextF;
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mux3 #(P.XLEN) pcmux3(PC2NextF, EPCM, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
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mux2 #(P.XLEN) pcresetmux({UnalignedPCNextF[P.XLEN-1:1], 1'b0}, P.RESET_VECTOR[P.XLEN-1:0], reset, PCNextF);
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flopen #(P.XLEN) pcreg(clk, ~StallF | reset, PCNextF, PCF);
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
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// choose PC+2 or PC+4 based on CompressedF, which arrives later.
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// Speeds up critical path as compared to selecting adder input based on CompressedF
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always_comb
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if (CompressedF) // add 2
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if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
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else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
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if (P.COMPRESSED_SUPPORTED)
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// choose PC+2 or PC+4 based on CompressedF, which arrives later.
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// Speeds up critical path as compared to selecting adder input based on CompressedF
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always_comb
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if (CompressedF) // add 2
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if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00};
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else PCPlus2or4F = {PCF[P.XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4
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else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // always add 4 if compressed instructions are not supported
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Branch and Jump Predictor
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@ -34,7 +34,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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input logic StallE, StallM, StallW,
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input logic [31:0] InstrM, // current instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return logic
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input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic
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input logic [P.XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic TrapM, // trap is occurring
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@ -86,9 +86,11 @@ module csr import cvw::*; #(parameter cvw_t P) (
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output logic [3:0] ENVCFG_CBE,
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output logic ENVCFG_PBMTE, // Page-based memory type enable
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output logic ENVCFG_ADUE, // HPTW A/D Update enable
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// PC logic output from privileged unit to IFU
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output logic [P.XLEN-1:0] EPCM, // Exception Program counter to IFU PC logic
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output logic [P.XLEN-1:0] TrapVectorM, // Trap vector, to IFU PC logic
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//
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output logic [P.XLEN-1:0] CSRReadValW, // value read from CSR
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output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC, accounting for traps and returns
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output logic IllegalCSRAccessM, // Illegal CSR access: CSR doesn't exist or is inaccessible at this privilege level
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output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
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);
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@ -117,10 +119,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
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logic IllegalCSRMWriteReadonlyM;
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logic [P.XLEN-1:0] CSRReadVal2M;
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logic [11:0] MIP_REGW_writeable;
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logic [P.XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM;
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logic [P.XLEN-1:0] TVecM,NextFaultMtvalM;
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logic MTrapM, STrapM;
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logic [P.XLEN-1:0] EPC;
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logic RetM;
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logic SelMtvecM;
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logic [P.XLEN-1:0] TVecAlignedM;
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logic InstrValidNotFlushedM;
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@ -168,9 +168,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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// Trap Returns
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// A trap sets the PC to TrapVector
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// A return sets the PC to MEPC or SEPC
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assign RetM = mretM | sretM;
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mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
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mux3 #(P.XLEN) pcmux3(PC2NextF, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF);
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mux2 #(P.XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPCM);
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///////////////////////////////////////////
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// CSRWriteValM
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@ -38,7 +38,7 @@ module privdec import cvw::*; #(parameter cvw_t P) (
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input logic STATUS_TSR, STATUS_TVM, STATUS_TW, // status bits
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output logic IllegalInstrFaultM, // Illegal instruction
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output logic EcallFaultM, BreakpointFaultM, // Ecall or breakpoint; must retire, so don't flush it when the trap occurs
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output logic sretM, mretM, // return instructions
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output logic sretM, mretM, RetM, // return instructions
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output logic wfiM, wfiW, sfencevmaM // wfi / sfence.vma / sinval.vma instructions
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);
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@ -66,6 +66,7 @@ module privdec import cvw::*; #(parameter cvw_t P) (
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assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & rs1zeroM & P.S_SUPPORTED &
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(PrivilegeModeW == P.M_MODE | PrivilegeModeW == P.S_MODE & ~STATUS_TSR);
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assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & rs1zeroM & (PrivilegeModeW == P.M_MODE);
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assign RetM = sretM | mretM;
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assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000) & rs1zeroM;
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assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001) & rs1zeroM;
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assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101) & rs1zeroM;
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@ -37,7 +37,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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input logic [31:0] InstrM, // Instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] IEUAdrM, // address from IEU
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input logic [P.XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return PC logic
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input logic [P.XLEN-1:0] PCM, // program counter
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// control signals
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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@ -85,8 +85,9 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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output logic [3:0] ENVCFG_CBE, // Cache block operation enables
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output logic ENVCFG_PBMTE, // Page-based memory type enable
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output logic ENVCFG_ADUE, // HPTW A/D Update enable
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// PC logic output in privileged unit
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output logic [P.XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic
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// PC logic output from privileged unit to IFU
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output logic [P.XLEN-1:0] EPCM, // Exception Program counter to IFU PC logic
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output logic [P.XLEN-1:0] TrapVectorM, // Trap vector, to IFU PC logic
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// control outputs
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output logic RetM, TrapM, // return instruction, or trap
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output logic sfencevmaM, // sfence.vma instruction
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@ -125,11 +126,11 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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privdec #(P) pmd(.clk, .reset, .StallW, .FlushW, .InstrM(InstrM[31:15]),
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.PrivilegedM, .IllegalIEUFPUInstrM, .IllegalCSRAccessM,
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.PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .IllegalInstrFaultM,
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.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .wfiM, .wfiW, .sfencevmaM);
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.EcallFaultM, .BreakpointFaultM, .sretM, .mretM, .RetM, .wfiM, .wfiW, .sfencevmaM);
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// Control and Status Registers
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csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF,
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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@ -142,7 +143,8 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.MEDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
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.SATP_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.SetFflagsM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE,
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.CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM);
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.EPCM, .TrapVectorM,
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.CSRReadValW, .IllegalCSRAccessM, .BigEndianM);
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// pipeline early-arriving trap sources
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privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
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@ -154,9 +156,8 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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.InstrMisalignedFaultM, .InstrAccessFaultM, .HPTWInstrAccessFaultM, .IllegalInstrFaultM,
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.BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
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.LoadPageFaultM, .StoreAmoPageFaultM,
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.mretM, .sretM, .PrivilegeModeW,
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.LoadPageFaultM, .StoreAmoPageFaultM, .PrivilegeModeW,
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.MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE,
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.InstrValidM, .CommittedM, .CommittedF,
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.TrapM, .RetM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
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.TrapM, .wfiM, .wfiW, .InterruptM, .ExceptionM, .IntPendingM, .DelegateM, .CauseM);
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endmodule
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@ -32,7 +32,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
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input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
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input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources
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input logic mretM, sretM, // return instructions
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input logic wfiM, wfiW, // wait for interrupt instruction
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input logic [1:0] PrivilegeModeW, // current privilege mode
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input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs
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@ -41,7 +40,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
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input logic InstrValidM, // current instruction is valid, not flushed
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input logic CommittedM, CommittedF, // LSU/IFU has committed to a bus operation that can't be interrupted
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output logic TrapM, // Trap is occurring
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output logic RetM, // Return instruction being executed
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output logic InterruptM, // Interrupt is occurring
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output logic ExceptionM, // exception is occurring
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output logic IntPendingM, // Interrupt is pending, might occur if enabled
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@ -74,7 +72,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
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(PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
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///////////////////////////////////////////
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// Trigger Traps and RET
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// Trigger Traps
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// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
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// Traps are the union of exceptions and interrupts.
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///////////////////////////////////////////
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@ -89,7 +87,6 @@ module trap import cvw::*; #(parameter cvw_t P) (
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LoadAccessFaultM | StoreAmoAccessFaultM;
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// coverage on
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assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter.
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assign RetM = mretM | sretM;
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///////////////////////////////////////////
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// Cause priority defined in privileged spec
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@ -48,8 +48,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic RetM;
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logic TrapM;
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logic TrapM, RetM;
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// signals that must connect through DP
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logic IntDivE, W64E;
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@ -63,7 +62,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] PCSpillF, PCE, PCLinkE;
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logic [P.XLEN-1:0] PCM;
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logic [P.XLEN-1:0] CSRReadValW, MDUResultW;
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logic [P.XLEN-1:0] UnalignedPCNextF, PC2NextF;
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logic [P.XLEN-1:0] EPCM, TrapVectorM;
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logic [1:0] MemRWE;
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logic [1:0] MemRWM;
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logic InstrValidD, InstrValidE, InstrValidM;
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@ -173,13 +172,13 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.InstrValidE, .InstrValidD,
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.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
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// Fetch
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.HRDATA, .PCSpillF, .IFUHADDR, .PC2NextF,
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.HRDATA, .PCSpillF, .IFUHADDR,
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.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
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.ICacheAccess, .ICacheMiss,
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// Execute
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.PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM,
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// Mem
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.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
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.CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
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.InstrD, .InstrM, .InstrOrigM, .PCM, .InstrClassM, .BPDirPredWrongM,
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.BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
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// Faults out
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@ -281,8 +280,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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privileged #(P) priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF,
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.InstrM, .InstrOrigM, .CSRReadValW, .UnalignedPCNextF,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
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.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
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.InstrValidM, .CommittedM, .CommittedF,
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.FRegWriteM, .LoadStallD, .StoreStallD,
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@ -301,7 +300,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM);
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end else begin
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assign CSRReadValW = 0;
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assign UnalignedPCNextF = PC2NextF;
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assign EPCM = 0;
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assign TrapVectorM = 0;
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assign RetM = 0;
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assign TrapM = 0;
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assign wfiM = 0;
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