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https://github.com/openhwgroup/cvw
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New radix-2 algorithm implemented and working
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@ -75,7 +75,7 @@ module srt (
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// Quotient Selection logic
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// Quotient Selection logic
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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// Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm)
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qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN-1], WC[`DIVLEN+3:`DIVLEN-1], Sqrt, qp, qz, qn);
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qsel2 qsel2(WS[`DIVLEN+3:`DIVLEN], WC[`DIVLEN+3:`DIVLEN], Sqrt, qp, qz, qn);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(`NE) expflop(clk, Start, calcExp, rExp);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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flopen #(1) signflop(clk, Start, calcSign, rsign);
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@ -154,7 +154,7 @@ module srtpreproc (
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// Selecting correct divider inputs
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// Selecting correct divider inputs
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assign DivX = Int ? PreprocA : PreprocX;
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assign DivX = Int ? PreprocA : PreprocX;
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assign SqrtX = XExp[0] ? {4'b0000, SrcXFrac, 1'b0} : {5'b11111, SrcXFrac};
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assign SqrtX = XExp[0] ? {5'b11101, SrcXFrac} : {4'b1111, SrcXFrac, 1'b0};
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assign X = Sqrt ? {SqrtX, {(`EXTRAFRACBITS-1){1'b0}}} : {4'b0001, DivX};
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assign X = Sqrt ? {SqrtX, {(`EXTRAFRACBITS-1){1'b0}}} : {4'b0001, DivX};
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assign D = {4'b0001, Int ? PreprocB : PreprocY};
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assign D = {4'b0001, Int ? PreprocB : PreprocY};
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@ -169,13 +169,13 @@ endmodule
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/////////////////////////////////
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/////////////////////////////////
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// Quotient Selection, Radix 2 //
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// Quotient Selection, Radix 2 //
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/////////////////////////////////
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/////////////////////////////////
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module qsel2 ( // *** eventually just change to 4 bits
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module qsel2 (
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input logic [`DIVLEN+3:`DIVLEN-1] ps, pc,
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input logic [`DIVLEN+3:`DIVLEN] ps, pc,
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input logic Sqrt,
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input logic Sqrt,
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output logic qp, qz, qn
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output logic qp, qz, qn
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);
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);
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logic [`DIVLEN+3:`DIVLEN-1] p, g;
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logic [`DIVLEN+3:`DIVLEN] p, g;
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logic magnitude, sign, cout;
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logic magnitude, sign, cout;
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// The quotient selection logic is presented for simplicity, not
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// The quotient selection logic is presented for simplicity, not
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@ -186,8 +186,8 @@ module qsel2 ( // *** eventually just change to 4 bits
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assign p = ps ^ pc;
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assign p = ps ^ pc;
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assign g = ps & pc;
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assign g = ps & pc;
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assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN-1]);
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assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]);
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assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & (g[`DIVLEN] | (Sqrt & (p[`DIVLEN] & g[`DIVLEN-1])))));
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assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & (g[`DIVLEN])));
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assign #1 sign = p[`DIVLEN+3] ^ cout;
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assign #1 sign = p[`DIVLEN+3] ^ cout;
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) &
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(ps[52]^pc[52]));
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(ps[52]^pc[52]));
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@ -283,7 +283,7 @@ module sotfc2(
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logic [`DIVLEN+3:0] SNext, SMNext, SMux;
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logic [`DIVLEN+3:0] SNext, SMNext, SMux;
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flopr #(`DIVLEN+4) SMreg(clk, Start, SMNext, SM);
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flopr #(`DIVLEN+4) SMreg(clk, Start, SMNext, SM);
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mux2 #(`DIVLEN+4) Smux(SNext, {3'b000, Sqrt, {(`DIVLEN){1'b0}}}, Start, SMux);
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mux2 #(`DIVLEN+4) Smux(SNext, {2'b00, Sqrt, {(`DIVLEN+1){1'b0}}}, Start, SMux);
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flop #(`DIVLEN+4) Sreg(clk, SMux, S);
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flop #(`DIVLEN+4) Sreg(clk, SMux, S);
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always_comb begin
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always_comb begin
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@ -298,7 +298,7 @@ module sotfc2(
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SMNext = SM | ((C << 1) & ~(C << 2));
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SMNext = SM | ((C << 1) & ~(C << 2));
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end
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end
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end
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end
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assign Sq = S[`DIVLEN] ? S[`DIVLEN-1:1] : S[`DIVLEN-2:0];
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assign Sq = S[`DIVLEN+1] ? S[`DIVLEN:2] : S[`DIVLEN-1:1];
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endmodule
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endmodule
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//////////////////////////
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//////////////////////////
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@ -311,7 +311,7 @@ module creg(input logic clk,
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);
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);
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logic [`DIVLEN+3:0] CMux;
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logic [`DIVLEN+3:0] CMux;
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mux2 #(`DIVLEN+4) Cmux({1'b1, C[`DIVLEN+3:1]}, {5'b11111, Sqrt, {(`DIVLEN-2){1'b0}}}, Start, CMux);
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mux2 #(`DIVLEN+4) Cmux({1'b1, C[`DIVLEN+3:1]}, {4'b1111, Sqrt, {(`DIVLEN-1){1'b0}}}, Start, CMux);
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flop #(`DIVLEN+4) cflop(clk, CMux, C);
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flop #(`DIVLEN+4) cflop(clk, CMux, C);
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endmodule
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endmodule
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