Lint cleanup from wallypipeliendhart

wally-pipelined/src/ieu/ieu.sv

@@ -31,7 +31,6 @@ module ieu (
   input logic [31:0] 	   InstrD,
   input logic 		   IllegalIEUInstrFaultD, 
   output logic 		   IllegalBaseInstrFaultD,
-  output logic 		   RegWriteD,
   // Execute Stage interface
   input logic [`XLEN-1:0]  PCE, 
   input logic [`XLEN-1:0]  PCLinkE,
@@ -48,7 +47,6 @@ module ieu (
   // Memory stage interface
   input logic 		   DataMisalignedM, // from LSU
   input logic 		   SquashSCW, // from LSU
-  output logic [1:0] 	   MemRWE, // read/write control goes to LSU	    
   output logic [1:0] 	   MemRWM, // read/write control goes to LSU
   output logic [1:0] 	   AtomicE, // atomic control goes to LSU	    
   output logic [1:0] 	   AtomicM, // atomic control goes to LSU
@@ -87,6 +85,8 @@ module ieu (
   logic        TargetSrcE;
   logic        SCE;
   logic        InstrValidW;
+  logic [1:0]  MemRWE;
+  logic        RegWriteD;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;

wally-pipelined/src/ifu/ifu.sv

@@ -100,6 +100,7 @@ module ifu (
   
   logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
   logic [`XLEN+1:0]    PCFExt;
+  logic                ITLBHitF, ISquashBusAccessF;
 
   generate
     if (`XLEN==32) begin

wally-pipelined/src/lsu/lsu.sv

@@ -89,14 +89,13 @@ module lsu
    output logic 	       WalkerLoadPageFaultM,
    output logic 	       WalkerStorePageFaultM,
 
-   output logic 	       DTLBHitM, // not connected 
-
    input 		       var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
    input 		       var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
    );
 
   logic 		       SquashSCM;
   logic 		       DTLBPageFaultM;
+  logic            DTLBHitM;
 
   
   logic [`PA_BITS-1:0] 	       MemPAdrM;  // from mmu to dcache

wally-pipelined/src/muldiv/muldiv.sv

@@ -27,8 +27,6 @@
 
 module muldiv (
 	       input logic 		clk, reset,
-	       // Decode Stage interface
-	       input logic [31:0] 	InstrD, 
 	       // Execute Stage interface
 	       input logic [`XLEN-1:0] 	SrcAE, SrcBE,
 	       input logic [2:0] 	Funct3E, Funct3M,
@@ -38,7 +36,7 @@ module muldiv (
 	       // Divide Done
 	       output logic 		DivBusyE, 
 	       // hazards
-	       input logic 		StallE, StallM, StallW, FlushM, FlushW 
+	       input logic 		StallM, StallW, FlushM, FlushW 
 	       );
 
    generate

wally-pipelined/src/privileged/privileged.sv

@@ -32,8 +32,8 @@ module privileged (
   input  logic             FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW,
   input  logic             CSRReadM, CSRWriteM,
   input  logic [`XLEN-1:0] SrcAM,
-  input  logic [`XLEN-1:0] PCF,PCD,PCE,PCM,
-  input  logic [31:0]      InstrD, InstrE, InstrM, InstrW,
+  input  logic [`XLEN-1:0] PCM,
+  input  logic [31:0]      InstrM,
   output logic [`XLEN-1:0] CSRReadValW,
   output logic [`XLEN-1:0] PrivilegedNextPCM,
   output logic             RetM, TrapM, 

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -36,7 +36,6 @@ module wallypipelinedhart
    input logic 		    DataAccessFaultM,
    input logic [63:0] 	    MTIME_CLINT, MTIMECMP_CLINT,
    // Bus Interface
-   input logic [15:0] 	    rd2, // bogus, delete when real multicycle fetch works
    input logic [`AHBW-1:0]  HRDATA,
    input logic 		    HREADY, HRESP,
    output logic 	    HCLK, HRESETn,
@@ -48,7 +47,6 @@ module wallypipelinedhart
    output logic [3:0] 	    HPROT,
    output logic [1:0] 	    HTRANS,
    output logic 	    HMASTLOCK,
-   output logic [5:0] 	    HSELRegions,
    // Delayed signals for subword write
    output logic [2:0] 	    HADDRD,
    output logic [3:0] 	    HSIZED,
@@ -70,11 +68,10 @@ module wallypipelinedhart
   logic [2:0] 		    Funct3E;
   //  logic [31:0] InstrF;
   logic [31:0] 		    InstrD, InstrE, InstrM, InstrW;
-  logic [`XLEN-1:0] 	    PCD, PCE, PCM, PCLinkE, PCLinkW;
+  logic [`XLEN-1:0] 	    PCD, PCE, PCM, PCLinkE;
   logic [`XLEN-1:0] 	    PCTargetE;
   logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
-  logic [1:0] 		    MemRWE;  
   logic [1:0] 		    MemRWM;
   logic 		    InstrValidM;
   logic 		    InstrMisalignedFaultM;
@@ -89,9 +86,8 @@ module wallypipelinedhart
   logic 		    PCSrcE;
   logic 		    CSRWritePendingDEM;
   logic 		    DivBusyE;
-  logic 		    RegWriteD;
   logic 		    LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD;
-  logic 		    SquashSCM, SquashSCW;
+  logic 		    SquashSCW;
   // floating point unit signals
   logic [2:0] 		    FRM_REGW;
    logic [4:0]        RdE, RdM, RdW;
@@ -104,13 +100,11 @@ module wallypipelinedhart
   logic 		    FRegWriteM;
   logic 		    FPUStallD;
   logic [4:0] 		    SetFflagsM;
-  logic [`XLEN-1:0] 	    FPUResultW;
 
   // memory management unit signals
   logic 		    ITLBWriteF;
   logic 		    ITLBFlushF, DTLBFlushM;
   logic 		    ITLBMissF;
-  logic 		    DTLBHitM;
   logic [`XLEN-1:0] 	    SATP_REGW;
   logic              STATUS_MXR, STATUS_SUM, STATUS_MPRV;
   logic  [1:0]       STATUS_MPP;

wally-pipelined/src/wally/wallypipelinedsoc.sv

@@ -60,7 +60,6 @@ module wallypipelinedsoc (
   // Uncore signals
   logic [`AHBW-1:0] HRDATA;   // from AHB mux in uncore
   logic             HREADY, HRESP;
-  logic [5:0]       HSELRegions;
   logic             InstrAccessFaultF, DataAccessFaultM;
   logic             TimerIntM, SwIntM; // from CLINT
   logic [63:0]      MTIME_CLINT, MTIMECMP_CLINT; // from CLINT to CSRs
@@ -68,16 +67,15 @@ module wallypipelinedsoc (
   logic [2:0]       HADDRD;
   logic [3:0]       HSIZED;
   logic             HWRITED;
-  logic [15:0]      rd2; // bogus, delete when real multicycle fetch works
   logic [31:0]      InstrF;
    
   // instantiate processor and memories
   wallypipelinedhart hart(.clk, .reset,
     .PCF,  .TimerIntM, .ExtIntM, .SwIntM, .DataAccessFaultM, 
-    .MTIME_CLINT, .MTIMECMP_CLINT, .rd2, 
+    .MTIME_CLINT, .MTIMECMP_CLINT, 
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA,
     .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
-    .HSELRegions, .HADDRD, .HSIZED, .HWRITED
+    .HADDRD, .HSIZED, .HWRITED
    );
 
   // instructions now come from uncore memory. This line can be removed at any time.