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Merge pull request #158 from kipmacsaigoren/bitmanip-alu
Modularize Bit Manipulation Specific ALU Changes
This commit is contained in:
David Harris
GitHub
commit
8e2fb8f926
130
src/ieu/alu.sv
130
src/ieu/alu.sv
@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [2:0] ALUSelect, // ALU mux select signal
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input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
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input logic [1:0] CompFlags, // Comparator flags
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@ -43,43 +43,31 @@ module alu #(parameter WIDTH=32) (
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals
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logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC
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logic [WIDTH-1:0] MaskB; // BitMask of B
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
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logic [WIDTH-1:0] RevA; // Bit-reversed A
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic W64; // RV64 W-type instruction
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logic SubArith; // Performing subtraction or arithmetic right shift
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logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
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logic Asign, Bsign; // Sign bits of A, B
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, ALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic W64; // RV64 W-type instruction
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logic SubArith; // Performing subtraction or arithmetic right shift
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logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
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logic Asign, Bsign; // Sign bits of A, B
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logic shSignA;
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [1:0] shASelect; // select signal for shifter source generation mux
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logic Rotate; // Indicates if it is Rotate instruction
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logic Mask; // Indicates if it is ZBS instruction
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logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
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logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
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logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter
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logic [1:0] shASelect; // select signal for shifter source generation mux
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logic Rotate; // Indicates if it is Rotate instruction
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Extract control signals from bitmanip ALUControl.
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assign {Rotate, Mask, PreShift} = BALUControl;
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// Extract rotate signal from BALUControl.
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assign Rotate = BALUControl[2];
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// Pack control signals into shifter select
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assign shASelect = {W64,SubArith};
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assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
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if (`ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
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mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
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end else assign CondMaskB = B;
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// Pack control signals into shifter select signal.
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assign shASelect = {W64, SubArith};
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// A, A sign bit muxes
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if (WIDTH == 64) begin
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mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA);
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mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA);
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@ -88,16 +76,6 @@ module alu #(parameter WIDTH=32) (
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assign CondExtA = A;
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end
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// shifter rotate source select mux
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if (`ZBB_SUPPORTED & WIDTH == 64) begin
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mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA);
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end else assign rotA = A;
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if (`ZBA_SUPPORTED) begin: zbapreshift
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// Pre-Shift
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assign CondShiftA = CondExtA << (PreShiftAmt);
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end else assign CondShiftA = A;
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// Addition
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assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
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assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
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@ -116,59 +94,33 @@ module alu #(parameter WIDTH=32) (
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assign LTU = ~Carry;
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// Select appropriate ALU Result
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if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin
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always_comb
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect
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3'b000: FullResult = Sum; // add or sub
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3'b001: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
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3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & CondMaskInvB; // and, bclr
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endcase
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always_comb begin
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect
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3'b000: FullResult = Sum; // add or sub
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3'b001: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
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3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift;// bext
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & CondMaskInvB; // and, bclr
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endcase
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end
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else begin
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always_comb
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation)
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else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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end
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if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse
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bitreverse #(WIDTH) brA(.A, .RevA);
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end
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if (`ZBC_SUPPORTED) begin: zbc
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zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult);
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end else assign ZBCResult = 0;
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign ALUResult = FullResult;
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// Final Result B instruction select mux
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder
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always_comb
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case (BSelect)
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// 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC
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2'b00: Result = ALUResult;
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2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: Result = ZBBResult;
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2'b11: Result = ZBCResult;
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endcase
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end else assign Result = ALUResult;
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if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect,
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.Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .rotA, .Result);
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end else begin
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assign Result = ALUResult;
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assign CondMaskB = B;
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assign CondShiftA = A;
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assign rotA = A;
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end
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endmodule
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109
src/ieu/bmu/bitmanipalu.sv
Normal file
109
src/ieu/bmu/bitmanipalu.sv
Normal file
@ -0,0 +1,109 @@
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///////////////////////////////////////////
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// bitmanipalu.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 23 March 2023
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// Modified: 23 March 2023
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//
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// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension
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//
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// Documentation: RISC-V System on Chip Design Chapter 15
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module bitmanipalu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] ALUControl, // With Funct3, indicates operation to perform
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input logic [2:0] ALUSelect, // ALU mux select signal
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect
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input logic [1:0] CompFlags, // Comparator flags
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal
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input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
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output logic [WIDTH-1:0] rotA, // Rotate source signal
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output logic [WIDTH-1:0] Result); // Result
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logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
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logic [WIDTH-1:0] MaskB; // BitMask of B
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logic [WIDTH-1:0] RevA; // Bit-reversed A
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logic W64; // RV64 W-type instruction
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logic SubArith; // Performing subtraction or arithmetic right shift
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logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops
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logic Rotate; // Indicates if it is Rotate instruction
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logic Mask; // Indicates if it is ZBS instruction
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logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
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logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
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// Extract control signals from ALUControl.
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assign {W64, SubArith, ALUOp} = ALUControl;
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// Extract control signals from bitmanip ALUControl.
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assign {Mask, PreShift} = BALUControl[1:0];
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// Mask Generation Mux
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if (`ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB);
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mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
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end else assign CondMaskB = B;
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// shifter rotate source select mux
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if (`ZBB_SUPPORTED & WIDTH == 64) begin
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mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA);
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end else assign rotA = A;
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// Pre-Shift Mux
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if (`ZBA_SUPPORTED) begin: zbapreshift
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assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
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assign CondShiftA = CondExtA << (PreShiftAmt);
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end else begin
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assign PreShiftAmt = 2'b0;
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assign CondShiftA = A;
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end
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// Bit reverse needed for some ZBB, ZBC instructions
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if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse
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bitreverse #(WIDTH) brA(.A, .RevA);
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end
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// ZBC Unit
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if (`ZBC_SUPPORTED) begin: zbc
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zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult);
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end else assign ZBCResult = 0;
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// ZBB Unit
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if (`ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Result Select Mux
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always_comb
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case (BSelect)
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// 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC
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2'b00: Result = ALUResult;
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2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
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2'b10: Result = ZBBResult;
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2'b11: Result = ZBCResult;
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endcase
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endmodule
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