mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
David Harris
commit
8e01007d1c
wally-pipelined
linux-testgen/testvector-generation
regression/wave-dos
src/fpu
testbench
@ -95,7 +95,7 @@ try:
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|||||||
# Next 32 lines are the Register File
|
# Next 32 lines are the Register File
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if lastRead == l.split()[0]:
|
if lastRead == l.split()[0]:
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readData = int(l.split()[1][2:], 16)
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readData = int(l.split()[1][2:], 16)
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readData <<= (8 * (lastReadLoc % 8))
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#readData <<= (8 * (lastReadLoc % 8)) <-- this was used to make byte and half-word instructions match what the bus unit sees in RV64. However, it is no longer needed because the testvectors are now compared against what the hart sees (not what the bus unit sees).
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wMem.write('{:x}\n'.format(readData))
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wMem.write('{:x}\n'.format(readData))
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if readLoc == l.split()[0]:
|
if readLoc == l.split()[0]:
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readLoc = l.split()[1][2:]
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readLoc = l.split()[1][2:]
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File diff suppressed because it is too large
Load Diff
@ -91,6 +91,7 @@ module fpdiv (
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wire load_regrv, load_regs;
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wire load_regrv, load_regs;
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logic exp_cout1, exp_cout2;
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logic exp_cout1, exp_cout2;
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logic exp_odd, open;
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logic exp_odd, open;
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// logic reset;
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|
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// Convert the input operands to their appropriate forms based on
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// Convert the input operands to their appropriate forms based on
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// the orignal operands, the op_type , and their precision P.
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// the orignal operands, the op_type , and their precision P.
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@ -8,7 +8,7 @@ module fsm (done, load_rega, load_regb, load_regc,
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input start;
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input start;
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// input error;
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// input error;
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input op_type;
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input op_type;
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//***can use divbusy insted of holdinputs
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output done;
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output done;
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output load_rega;
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output load_rega;
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output load_regb;
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output load_regb;
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@ -1,4 +1,3 @@
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|
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module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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|
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// bit partitions
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// bit partitions
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@ -7,7 +6,7 @@ module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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logic [3:0] x2;
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logic [3:0] x2;
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logic [2:0] x2_1cmp;
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logic [2:0] x2_1cmp;
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// mem outputs
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// mem outputs
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logic [12:0] y0;
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logic [13:0] y0;
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logic [5:0] y1;
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logic [5:0] y1;
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// input to CPA
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// input to CPA
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logic [14:0] op1;
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logic [14:0] op1;
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@ -19,8 +18,8 @@ module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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assign x1 = a[6:4];
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assign x1 = a[6:4];
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assign x2 = a[3:0];
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assign x2 = a[3:0];
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|
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sbtm_a2 mem1 ({x0[3:0], x1}, y0);
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sbtm_a2 mem1 ({x0, x1}, y0);
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assign op1 = {1'b0, y0, 1'b0};
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assign op1 = {y0, 1'b0};
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|
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// 1s cmp per sbtm/stam
|
// 1s cmp per sbtm/stam
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assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
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assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
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@ -30,10 +29,12 @@ module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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{8'b0, y1, 1'b1};
|
{8'b0, y1, 1'b1};
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|
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// CPA
|
// CPA
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bk15 cp1 (cout, p, op1, op2, 1'b0);
|
//adder #(15) cp1 (op1, op2, 1'b0, p, cout);
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|
assign {cout, p} = op1 + op2;
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assign y = p[14:4];
|
assign y = p[14:4];
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|
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endmodule // sbtm2
|
endmodule // sbtm2
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|
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|
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|
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|
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@ -1,136 +1,200 @@
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module sbtm_a2 (input logic [6:0] a,
|
module sbtm_a2 (input logic [7:0] a,
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output logic [12:0] y);
|
output logic [13:0] y);
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||||||
always_comb
|
always_comb
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case(a)
|
case(a)
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||||||
7'b0000000: y = 13'b1111111110001;
|
8'b01000000: y = 14'b10110100010111;
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7'b0000001: y = 13'b1111111010001;
|
8'b01000001: y = 14'b10110010111111;
|
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7'b0000010: y = 13'b1111110110010;
|
8'b01000010: y = 14'b10110001101000;
|
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7'b0000011: y = 13'b1111110010011;
|
8'b01000011: y = 14'b10110000010011;
|
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7'b0000100: y = 13'b1111101110101;
|
8'b01000100: y = 14'b10101111000001;
|
||||||
7'b0000101: y = 13'b1111101010110;
|
8'b01000101: y = 14'b10101101110000;
|
||||||
7'b0000110: y = 13'b1111100111001;
|
8'b01000110: y = 14'b10101100100001;
|
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7'b0000111: y = 13'b1111100011011;
|
8'b01000111: y = 14'b10101011010011;
|
||||||
7'b0001000: y = 13'b1111011111110;
|
8'b01001000: y = 14'b10101010000111;
|
||||||
7'b0001001: y = 13'b1111011100001;
|
8'b01001001: y = 14'b10101000111101;
|
||||||
7'b0001010: y = 13'b1111011000100;
|
8'b01001010: y = 14'b10100111110100;
|
||||||
7'b0001011: y = 13'b1111010101000;
|
8'b01001011: y = 14'b10100110101101;
|
||||||
7'b0001100: y = 13'b1111010001100;
|
8'b01001100: y = 14'b10100101100111;
|
||||||
7'b0001101: y = 13'b1111001110000;
|
8'b01001101: y = 14'b10100100100010;
|
||||||
7'b0001110: y = 13'b1111001010101;
|
8'b01001110: y = 14'b10100011011111;
|
||||||
7'b0001111: y = 13'b1111000111010;
|
8'b01001111: y = 14'b10100010011101;
|
||||||
7'b0010000: y = 13'b1111000011111;
|
8'b01010000: y = 14'b10100001011100;
|
||||||
7'b0010001: y = 13'b1111000000100;
|
8'b01010001: y = 14'b10100000011100;
|
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7'b0010010: y = 13'b1110111101010;
|
8'b01010010: y = 14'b10011111011110;
|
||||||
7'b0010011: y = 13'b1110111010000;
|
8'b01010011: y = 14'b10011110100001;
|
||||||
7'b0010100: y = 13'b1110110110110;
|
8'b01010100: y = 14'b10011101100100;
|
||||||
7'b0010101: y = 13'b1110110011101;
|
8'b01010101: y = 14'b10011100101001;
|
||||||
7'b0010110: y = 13'b1110110000100;
|
8'b01010110: y = 14'b10011011101111;
|
||||||
7'b0010111: y = 13'b1110101101011;
|
8'b01010111: y = 14'b10011010110110;
|
||||||
7'b0011000: y = 13'b1110101010010;
|
8'b01011000: y = 14'b10011001111110;
|
||||||
7'b0011001: y = 13'b1110100111001;
|
8'b01011001: y = 14'b10011001000110;
|
||||||
7'b0011010: y = 13'b1110100100001;
|
8'b01011010: y = 14'b10011000010000;
|
||||||
7'b0011011: y = 13'b1110100001001;
|
8'b01011011: y = 14'b10010111011011;
|
||||||
7'b0011100: y = 13'b1110011110001;
|
8'b01011100: y = 14'b10010110100110;
|
||||||
7'b0011101: y = 13'b1110011011010;
|
8'b01011101: y = 14'b10010101110011;
|
||||||
7'b0011110: y = 13'b1110011000010;
|
8'b01011110: y = 14'b10010101000000;
|
||||||
7'b0011111: y = 13'b1110010101011;
|
8'b01011111: y = 14'b10010100001110;
|
||||||
7'b0100000: y = 13'b1110010010100;
|
8'b01100000: y = 14'b10010011011100;
|
||||||
7'b0100001: y = 13'b1110001111110;
|
8'b01100001: y = 14'b10010010101100;
|
||||||
7'b0100010: y = 13'b1110001100111;
|
8'b01100010: y = 14'b10010001111100;
|
||||||
7'b0100011: y = 13'b1110001010001;
|
8'b01100011: y = 14'b10010001001101;
|
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7'b0100100: y = 13'b1110000111011;
|
8'b01100100: y = 14'b10010000011111;
|
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7'b0100101: y = 13'b1110000100101;
|
8'b01100101: y = 14'b10001111110001;
|
||||||
7'b0100110: y = 13'b1110000001111;
|
8'b01100110: y = 14'b10001111000100;
|
||||||
7'b0100111: y = 13'b1101111111010;
|
8'b01100111: y = 14'b10001110011000;
|
||||||
7'b0101000: y = 13'b1101111100101;
|
8'b01101000: y = 14'b10001101101100;
|
||||||
7'b0101001: y = 13'b1101111010000;
|
8'b01101001: y = 14'b10001101000001;
|
||||||
7'b0101010: y = 13'b1101110111011;
|
8'b01101010: y = 14'b10001100010110;
|
||||||
7'b0101011: y = 13'b1101110100110;
|
8'b01101011: y = 14'b10001011101100;
|
||||||
7'b0101100: y = 13'b1101110010001;
|
8'b01101100: y = 14'b10001011000011;
|
||||||
7'b0101101: y = 13'b1101101111101;
|
8'b01101101: y = 14'b10001010011010;
|
||||||
7'b0101110: y = 13'b1101101101001;
|
8'b01101110: y = 14'b10001001110010;
|
||||||
7'b0101111: y = 13'b1101101010101;
|
8'b01101111: y = 14'b10001001001010;
|
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7'b0110000: y = 13'b1101101000001;
|
8'b01110000: y = 14'b10001000100011;
|
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7'b0110001: y = 13'b1101100101101;
|
8'b01110001: y = 14'b10000111111101;
|
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7'b0110010: y = 13'b1101100011010;
|
8'b01110010: y = 14'b10000111010111;
|
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7'b0110011: y = 13'b1101100000110;
|
8'b01110011: y = 14'b10000110110001;
|
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7'b0110100: y = 13'b1101011110011;
|
8'b01110100: y = 14'b10000110001100;
|
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7'b0110101: y = 13'b1101011100000;
|
8'b01110101: y = 14'b10000101100111;
|
||||||
7'b0110110: y = 13'b1101011001101;
|
8'b01110110: y = 14'b10000101000011;
|
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7'b0110111: y = 13'b1101010111010;
|
8'b01110111: y = 14'b10000100011111;
|
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7'b0111000: y = 13'b1101010101000;
|
8'b01111000: y = 14'b10000011111100;
|
||||||
7'b0111001: y = 13'b1101010010101;
|
8'b01111001: y = 14'b10000011011001;
|
||||||
7'b0111010: y = 13'b1101010000011;
|
8'b01111010: y = 14'b10000010110111;
|
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7'b0111011: y = 13'b1101001110001;
|
8'b01111011: y = 14'b10000010010101;
|
||||||
7'b0111100: y = 13'b1101001011111;
|
8'b01111100: y = 14'b10000001110011;
|
||||||
7'b0111101: y = 13'b1101001001101;
|
8'b01111101: y = 14'b10000001010010;
|
||||||
7'b0111110: y = 13'b1101000111100;
|
8'b01111110: y = 14'b10000000110001;
|
||||||
7'b0111111: y = 13'b1101000101010;
|
8'b01111111: y = 14'b10000000010001;
|
||||||
7'b1000000: y = 13'b1101000011001;
|
8'b10000000: y = 14'b01111111110001;
|
||||||
7'b1000001: y = 13'b1101000000111;
|
8'b10000001: y = 14'b01111111010001;
|
||||||
7'b1000010: y = 13'b1100111110110;
|
8'b10000010: y = 14'b01111110110010;
|
||||||
7'b1000011: y = 13'b1100111100101;
|
8'b10000011: y = 14'b01111110010011;
|
||||||
7'b1000100: y = 13'b1100111010100;
|
8'b10000100: y = 14'b01111101110101;
|
||||||
7'b1000101: y = 13'b1100111000011;
|
8'b10000101: y = 14'b01111101010110;
|
||||||
7'b1000110: y = 13'b1100110110011;
|
8'b10000110: y = 14'b01111100111001;
|
||||||
7'b1000111: y = 13'b1100110100010;
|
8'b10000111: y = 14'b01111100011011;
|
||||||
7'b1001000: y = 13'b1100110010010;
|
8'b10001000: y = 14'b01111011111110;
|
||||||
7'b1001001: y = 13'b1100110000010;
|
8'b10001001: y = 14'b01111011100001;
|
||||||
7'b1001010: y = 13'b1100101110010;
|
8'b10001010: y = 14'b01111011000100;
|
||||||
7'b1001011: y = 13'b1100101100001;
|
8'b10001011: y = 14'b01111010101000;
|
||||||
7'b1001100: y = 13'b1100101010010;
|
8'b10001100: y = 14'b01111010001100;
|
||||||
7'b1001101: y = 13'b1100101000010;
|
8'b10001101: y = 14'b01111001110000;
|
||||||
7'b1001110: y = 13'b1100100110010;
|
8'b10001110: y = 14'b01111001010101;
|
||||||
7'b1001111: y = 13'b1100100100011;
|
8'b10001111: y = 14'b01111000111010;
|
||||||
7'b1010000: y = 13'b1100100010011;
|
8'b10010000: y = 14'b01111000011111;
|
||||||
7'b1010001: y = 13'b1100100000100;
|
8'b10010001: y = 14'b01111000000100;
|
||||||
7'b1010010: y = 13'b1100011110101;
|
8'b10010010: y = 14'b01110111101010;
|
||||||
7'b1010011: y = 13'b1100011100101;
|
8'b10010011: y = 14'b01110111010000;
|
||||||
7'b1010100: y = 13'b1100011010110;
|
8'b10010100: y = 14'b01110110110110;
|
||||||
7'b1010101: y = 13'b1100011000111;
|
8'b10010101: y = 14'b01110110011101;
|
||||||
7'b1010110: y = 13'b1100010111001;
|
8'b10010110: y = 14'b01110110000100;
|
||||||
7'b1010111: y = 13'b1100010101010;
|
8'b10010111: y = 14'b01110101101011;
|
||||||
7'b1011000: y = 13'b1100010011011;
|
8'b10011000: y = 14'b01110101010010;
|
||||||
7'b1011001: y = 13'b1100010001101;
|
8'b10011001: y = 14'b01110100111001;
|
||||||
7'b1011010: y = 13'b1100001111110;
|
8'b10011010: y = 14'b01110100100001;
|
||||||
7'b1011011: y = 13'b1100001110000;
|
8'b10011011: y = 14'b01110100001001;
|
||||||
7'b1011100: y = 13'b1100001100010;
|
8'b10011100: y = 14'b01110011110001;
|
||||||
7'b1011101: y = 13'b1100001010100;
|
8'b10011101: y = 14'b01110011011010;
|
||||||
7'b1011110: y = 13'b1100001000110;
|
8'b10011110: y = 14'b01110011000010;
|
||||||
7'b1011111: y = 13'b1100000111000;
|
8'b10011111: y = 14'b01110010101011;
|
||||||
7'b1100000: y = 13'b1100000101010;
|
8'b10100000: y = 14'b01110010010100;
|
||||||
7'b1100001: y = 13'b1100000011100;
|
8'b10100001: y = 14'b01110001111110;
|
||||||
7'b1100010: y = 13'b1100000001111;
|
8'b10100010: y = 14'b01110001100111;
|
||||||
7'b1100011: y = 13'b1100000000001;
|
8'b10100011: y = 14'b01110001010001;
|
||||||
7'b1100100: y = 13'b1011111110100;
|
8'b10100100: y = 14'b01110000111011;
|
||||||
7'b1100101: y = 13'b1011111100110;
|
8'b10100101: y = 14'b01110000100101;
|
||||||
7'b1100110: y = 13'b1011111011001;
|
8'b10100110: y = 14'b01110000001111;
|
||||||
7'b1100111: y = 13'b1011111001100;
|
8'b10100111: y = 14'b01101111111010;
|
||||||
7'b1101000: y = 13'b1011110111111;
|
8'b10101000: y = 14'b01101111100101;
|
||||||
7'b1101001: y = 13'b1011110110010;
|
8'b10101001: y = 14'b01101111010000;
|
||||||
7'b1101010: y = 13'b1011110100101;
|
8'b10101010: y = 14'b01101110111011;
|
||||||
7'b1101011: y = 13'b1011110011000;
|
8'b10101011: y = 14'b01101110100110;
|
||||||
7'b1101100: y = 13'b1011110001011;
|
8'b10101100: y = 14'b01101110010001;
|
||||||
7'b1101101: y = 13'b1011101111110;
|
8'b10101101: y = 14'b01101101111101;
|
||||||
7'b1101110: y = 13'b1011101110010;
|
8'b10101110: y = 14'b01101101101001;
|
||||||
7'b1101111: y = 13'b1011101100101;
|
8'b10101111: y = 14'b01101101010101;
|
||||||
7'b1110000: y = 13'b1011101011001;
|
8'b10110000: y = 14'b01101101000001;
|
||||||
7'b1110001: y = 13'b1011101001100;
|
8'b10110001: y = 14'b01101100101101;
|
||||||
7'b1110010: y = 13'b1011101000000;
|
8'b10110010: y = 14'b01101100011010;
|
||||||
7'b1110011: y = 13'b1011100110100;
|
8'b10110011: y = 14'b01101100000110;
|
||||||
7'b1110100: y = 13'b1011100101000;
|
8'b10110100: y = 14'b01101011110011;
|
||||||
7'b1110101: y = 13'b1011100011100;
|
8'b10110101: y = 14'b01101011100000;
|
||||||
7'b1110110: y = 13'b1011100010000;
|
8'b10110110: y = 14'b01101011001101;
|
||||||
7'b1110111: y = 13'b1011100000100;
|
8'b10110111: y = 14'b01101010111010;
|
||||||
7'b1111000: y = 13'b1011011111000;
|
8'b10111000: y = 14'b01101010101000;
|
||||||
7'b1111001: y = 13'b1011011101100;
|
8'b10111001: y = 14'b01101010010101;
|
||||||
7'b1111010: y = 13'b1011011100000;
|
8'b10111010: y = 14'b01101010000011;
|
||||||
7'b1111011: y = 13'b1011011010101;
|
8'b10111011: y = 14'b01101001110001;
|
||||||
7'b1111100: y = 13'b1011011001001;
|
8'b10111100: y = 14'b01101001011111;
|
||||||
7'b1111101: y = 13'b1011010111101;
|
8'b10111101: y = 14'b01101001001101;
|
||||||
7'b1111110: y = 13'b1011010110010;
|
8'b10111110: y = 14'b01101000111100;
|
||||||
7'b1111111: y = 13'b1011010100111;
|
8'b10111111: y = 14'b01101000101010;
|
||||||
default: y = 13'bxxxxxxxxxxxxx;
|
8'b11000000: y = 14'b01101000011001;
|
||||||
|
8'b11000001: y = 14'b01101000000111;
|
||||||
|
8'b11000010: y = 14'b01100111110110;
|
||||||
|
8'b11000011: y = 14'b01100111100101;
|
||||||
|
8'b11000100: y = 14'b01100111010100;
|
||||||
|
8'b11000101: y = 14'b01100111000011;
|
||||||
|
8'b11000110: y = 14'b01100110110011;
|
||||||
|
8'b11000111: y = 14'b01100110100010;
|
||||||
|
8'b11001000: y = 14'b01100110010010;
|
||||||
|
8'b11001001: y = 14'b01100110000010;
|
||||||
|
8'b11001010: y = 14'b01100101110010;
|
||||||
|
8'b11001011: y = 14'b01100101100001;
|
||||||
|
8'b11001100: y = 14'b01100101010010;
|
||||||
|
8'b11001101: y = 14'b01100101000010;
|
||||||
|
8'b11001110: y = 14'b01100100110010;
|
||||||
|
8'b11001111: y = 14'b01100100100011;
|
||||||
|
8'b11010000: y = 14'b01100100010011;
|
||||||
|
8'b11010001: y = 14'b01100100000100;
|
||||||
|
8'b11010010: y = 14'b01100011110101;
|
||||||
|
8'b11010011: y = 14'b01100011100101;
|
||||||
|
8'b11010100: y = 14'b01100011010110;
|
||||||
|
8'b11010101: y = 14'b01100011000111;
|
||||||
|
8'b11010110: y = 14'b01100010111001;
|
||||||
|
8'b11010111: y = 14'b01100010101010;
|
||||||
|
8'b11011000: y = 14'b01100010011011;
|
||||||
|
8'b11011001: y = 14'b01100010001101;
|
||||||
|
8'b11011010: y = 14'b01100001111110;
|
||||||
|
8'b11011011: y = 14'b01100001110000;
|
||||||
|
8'b11011100: y = 14'b01100001100010;
|
||||||
|
8'b11011101: y = 14'b01100001010100;
|
||||||
|
8'b11011110: y = 14'b01100001000110;
|
||||||
|
8'b11011111: y = 14'b01100000111000;
|
||||||
|
8'b11100000: y = 14'b01100000101010;
|
||||||
|
8'b11100001: y = 14'b01100000011100;
|
||||||
|
8'b11100010: y = 14'b01100000001111;
|
||||||
|
8'b11100011: y = 14'b01100000000001;
|
||||||
|
8'b11100100: y = 14'b01011111110100;
|
||||||
|
8'b11100101: y = 14'b01011111100110;
|
||||||
|
8'b11100110: y = 14'b01011111011001;
|
||||||
|
8'b11100111: y = 14'b01011111001100;
|
||||||
|
8'b11101000: y = 14'b01011110111111;
|
||||||
|
8'b11101001: y = 14'b01011110110010;
|
||||||
|
8'b11101010: y = 14'b01011110100101;
|
||||||
|
8'b11101011: y = 14'b01011110011000;
|
||||||
|
8'b11101100: y = 14'b01011110001011;
|
||||||
|
8'b11101101: y = 14'b01011101111110;
|
||||||
|
8'b11101110: y = 14'b01011101110010;
|
||||||
|
8'b11101111: y = 14'b01011101100101;
|
||||||
|
8'b11110000: y = 14'b01011101011001;
|
||||||
|
8'b11110001: y = 14'b01011101001100;
|
||||||
|
8'b11110010: y = 14'b01011101000000;
|
||||||
|
8'b11110011: y = 14'b01011100110100;
|
||||||
|
8'b11110100: y = 14'b01011100101000;
|
||||||
|
8'b11110101: y = 14'b01011100011100;
|
||||||
|
8'b11110110: y = 14'b01011100010000;
|
||||||
|
8'b11110111: y = 14'b01011100000100;
|
||||||
|
8'b11111000: y = 14'b01011011111000;
|
||||||
|
8'b11111001: y = 14'b01011011101100;
|
||||||
|
8'b11111010: y = 14'b01011011100000;
|
||||||
|
8'b11111011: y = 14'b01011011010101;
|
||||||
|
8'b11111100: y = 14'b01011011001001;
|
||||||
|
8'b11111101: y = 14'b01011010111101;
|
||||||
|
8'b11111110: y = 14'b01011010110010;
|
||||||
|
8'b11111111: y = 14'b01011010100111;
|
||||||
|
default: y = 14'bxxxxxxxxxxxxxx;
|
||||||
endcase // case (a)
|
endcase // case (a)
|
||||||
|
|
||||||
endmodule // sbtm_a0
|
endmodule // sbtm_a0
|
||||||
|
|||||||
@ -61,7 +61,7 @@ string tests32f[] = '{
|
|||||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||||
"rv32f/I-FCVT-W-S-01", "2000",
|
"rv32f/I-FCVT-W-S-01", "2000",
|
||||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||||
// "rv32f/I-FDIV-S-01", "2000",
|
"rv32f/I-FDIV-S-01", "2000",
|
||||||
"rv32f/I-FEQ-S-01", "2000",
|
"rv32f/I-FEQ-S-01", "2000",
|
||||||
"rv32f/I-FLE-S-01", "2000",
|
"rv32f/I-FLE-S-01", "2000",
|
||||||
"rv32f/I-FLT-S-01", "2000",
|
"rv32f/I-FLT-S-01", "2000",
|
||||||
@ -77,7 +77,7 @@ string tests32f[] = '{
|
|||||||
"rv32f/I-FSGNJ-S-01", "2000",
|
"rv32f/I-FSGNJ-S-01", "2000",
|
||||||
"rv32f/I-FSGNJN-S-01", "2000",
|
"rv32f/I-FSGNJN-S-01", "2000",
|
||||||
"rv32f/I-FSGNJX-S-01", "2000",
|
"rv32f/I-FSGNJX-S-01", "2000",
|
||||||
// "rv32f/I-FSQRT-S-01", "2000",
|
"rv32f/I-FSQRT-S-01", "2000",
|
||||||
"rv32f/I-FSW-01", "2000",
|
"rv32f/I-FSW-01", "2000",
|
||||||
"rv32f/I-FLW-01", "2110",
|
"rv32f/I-FLW-01", "2110",
|
||||||
"rv32f/I-FSUB-S-01", "2000"
|
"rv32f/I-FSUB-S-01", "2000"
|
||||||
|
|||||||
@ -27,7 +27,7 @@
|
|||||||
|
|
||||||
module testbench();
|
module testbench();
|
||||||
|
|
||||||
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000001; // # of instructions at which to turn on waves in graphical sim
|
parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000000; // # of instructions at which to turn on waves in graphical sim
|
||||||
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////////////////
|
||||||
@ -399,7 +399,7 @@ module testbench();
|
|||||||
if ($time == 0) begin
|
if ($time == 0) begin
|
||||||
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
||||||
if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
|
if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
|
||||||
$display("%0t ps, PCW %x, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, PCW, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
|
$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, PCW, PCtextW, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
end else begin
|
end else begin
|
||||||
@ -410,11 +410,11 @@ module testbench();
|
|||||||
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
|
||||||
end
|
end
|
||||||
if (i != regNumExpected) begin
|
if (i != regNumExpected) begin
|
||||||
$display("%0t ps, PCW %x %s, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, PCW, PCtextW, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
|
$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, PCW, PCtextW, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
if (~(dut.hart.ieu.dp.regf.rf[i] === regExpected)) begin
|
if (~(dut.hart.ieu.dp.regf.rf[i] === regExpected)) begin
|
||||||
$display("%0t ps, PCW %x %s, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, PCW, PCtextW, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
|
$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, PCW, PCtextW, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -422,9 +422,9 @@ module testbench();
|
|||||||
end
|
end
|
||||||
endgenerate
|
endgenerate
|
||||||
|
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////
|
||||||
//////////////////////// Bus Unit Read/Write Checking /////////////////////////
|
//////////////////////// Memory Read/Write Checking /////////////////////////
|
||||||
///////////////////////////////////////////////////////////////////////////////
|
/////////////////////////////////////////////////////////////////////////////
|
||||||
// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
|
// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
|
||||||
// including subwords. Brief explanation on signals:
|
// including subwords. Brief explanation on signals:
|
||||||
//
|
//
|
||||||
@ -452,11 +452,9 @@ module testbench();
|
|||||||
// ------------
|
// ------------
|
||||||
// Read Checker
|
// Read Checker
|
||||||
// ------------
|
// ------------
|
||||||
always @(dut.hart.lsu.dcache.ReadDataM) begin
|
always @(negedge clk) begin
|
||||||
#2;
|
//if (dut.hart.MemRWM[1] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM) begin <-- This doesn't work because ReadDataM can be used for other things (namely page table walking) while the pipeline is stalled, leaving it in a different state when the pipeline unstalls
|
||||||
if (dut.hart.MemRWM[1]
|
if (dut.hart.MemRWM[1] && dut.hart.lsu.dcache.ReadDataWEn) begin // <-- ReadDataWEn is a good indicator that the pipeline is using the current contents of ReadDataM
|
||||||
&& (dut.hart.ebu.CaptureDataM)
|
|
||||||
&& dut.hart.lsu.dcache.ReadDataM !== {64{1'bx}}) begin
|
|
||||||
if($feof(data_file_memR)) begin
|
if($feof(data_file_memR)) begin
|
||||||
$display("no more memR data to read");
|
$display("no more memR data to read");
|
||||||
`ERROR
|
`ERROR
|
||||||
@ -465,18 +463,18 @@ module testbench();
|
|||||||
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
|
scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
|
||||||
assign readAdrTranslated = adrTranslator(readAdrExpected);
|
assign readAdrTranslated = adrTranslator(readAdrExpected);
|
||||||
if (~(dut.hart.lsu.dcache.MemPAdrM === readAdrTranslated)) begin
|
if (~(dut.hart.lsu.dcache.MemPAdrM === readAdrTranslated)) begin
|
||||||
$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.MemPAdrM does not equal readAdrExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
|
$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal readAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
if (readDataExpected !== dut.hart.lsu.dcache.ReadDataM) begin
|
if (readDataExpected !== dut.hart.lsu.dcache.ReadDataM) begin
|
||||||
if (dut.hart.lsu.dcache.MemPAdrM inside `LINUX_FIX_READ) begin
|
if (dut.hart.lsu.dcache.MemPAdrM inside `LINUX_FIX_READ) begin
|
||||||
if (dut.hart.lsu.dcache.MemPAdrM != 'h10000005) // Suppress the warning for UART LSR so we can read UART output
|
if (dut.hart.lsu.dcache.MemPAdrM != 'h10000005) // Suppress the warning for UART LSR so we can read UART output
|
||||||
$display("warning %0t ps, PCM %x %s, instr %0d, adr %0d: forcing readDataExpected to expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, readDataExpected, dut.hart.lsu.dcache.ReadDataM);
|
$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s:: forcing readDataExpected to expected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readDataExpected, dut.hart.lsu.dcache.ReadDataM);
|
||||||
force dut.hart.lsu.dcache.ReadDataM = readDataExpected;
|
force dut.hart.lsu.dcache.ReadDataM = readDataExpected;
|
||||||
#9;
|
#9;
|
||||||
release dut.hart.lsu.dcache.ReadDataM;
|
release dut.hart.lsu.dcache.ReadDataM;
|
||||||
end else begin
|
end else begin
|
||||||
$display("%0t ps, PCM %x %s, instr %0d: ExpectedreadDataExpected does not equal dut.hart.lsu.dcache.ReadDataM: %x, %x from address %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, readDataExpected, dut.hart.lsu.dcache.ReadDataM, dut.hart.lsu.dcache.MemPAdrM);
|
$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: ReadDataM does not equal readDataExpected: %x, %x from address %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.ReadDataM, readDataExpected, dut.hart.lsu.dcache.MemPAdrM);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -486,10 +484,8 @@ module testbench();
|
|||||||
// -------------
|
// -------------
|
||||||
// Write Checker
|
// Write Checker
|
||||||
// -------------
|
// -------------
|
||||||
// this might need to change
|
always @(negedge clk) begin
|
||||||
always @(negedge dut.hart.lsu.dcache.MemRWM) begin
|
if (dut.hart.MemRWM[0] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM && ($time != 0)) begin
|
||||||
//#1;
|
|
||||||
if (($time != 0) && ~dut.hart.hzu.FlushM) begin
|
|
||||||
if($feof(data_file_memW)) begin
|
if($feof(data_file_memW)) begin
|
||||||
$display("no more memW data to read");
|
$display("no more memW data to read");
|
||||||
`ERROR
|
`ERROR
|
||||||
@ -499,11 +495,11 @@ module testbench();
|
|||||||
assign writeAdrTranslated = adrTranslator(writeAdrExpected);
|
assign writeAdrTranslated = adrTranslator(writeAdrExpected);
|
||||||
|
|
||||||
if (writeDataExpected != dut.hart.lsu.dcache.WriteDataM && ~dut.uncore.HSELPLICD) begin
|
if (writeDataExpected != dut.hart.lsu.dcache.WriteDataM && ~dut.uncore.HSELPLICD) begin
|
||||||
$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.WriteDataM does not equal writeDataExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.WriteDataM, writeDataExpected);
|
$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.WriteDataM, writeDataExpected);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
if (~(writeAdrTranslated === dut.hart.lsu.dcache.MemPAdrM) && ~dut.uncore.HSELPLICD) begin
|
if (~(writeAdrTranslated === dut.hart.lsu.dcache.MemPAdrM) && ~dut.uncore.HSELPLICD) begin
|
||||||
$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.MemPAdrM does not equal writeAdrExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
|
$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
|
||||||
`ERROR
|
`ERROR
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user