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renamed rv32/64g to rv32/64gc in configuration

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This commit is contained in:
David Harris 2021-12-14 11:22:00 -08:00
parent 0e9fe6c214
commit 8dcf2c65f2
10 changed files with 5 additions and 5 deletions
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0
wally-pipelined/config/rv32g/BTBPredictor.txt → wally-pipelined/config/rv32gc/BTBPredictor.txt
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0
wally-pipelined/config/rv32g/twoBitPredictor.txt → wally-pipelined/config/rv32gc/twoBitPredictor.txt
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wally-pipelined/config/rv32g/wally-config.vh → wally-pipelined/config/rv32gc/wally-config.vh
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wally-pipelined/config/rv64g/BTBPredictor.txt → wally-pipelined/config/rv64gc/BTBPredictor.txt
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0
wally-pipelined/config/rv64g/twoBitPredictor.txt → wally-pipelined/config/rv64gc/twoBitPredictor.txt
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wally-pipelined/config/rv64g/wally-config.vh → wally-pipelined/config/rv64gc/wally-config.vh
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2
wally-pipelined/regression/lint-wally
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@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
verilator=`which verilator` verilator=`which verilator`
basepath=$(dirname $0)/.. basepath=$(dirname $0)/..
for config in rv64g rv32g; do for config in rv64gc rv32gc; do
echo "$config linting..." echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"

4
wally-pipelined/regression/regression-wally.py
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@ -53,7 +53,7 @@ tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c", "arch64m", "imperas6
for test in tests64: for test in tests64:
tc = TestCase( tc = TestCase(
name=test, name=test,
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!", cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)
#tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"] #tests32 = ["arch32i", "arch32priv", "arch32c", "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a", "imperas32c"]
@ -61,7 +61,7 @@ tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c", "arch32m", "imperas3
for test in tests32: for test in tests32:
tc = TestCase( tc = TestCase(
name=test, name=test,
cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32g "+test+"\n!", cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32gc "+test+"\n!",
grepstr="All tests ran without failures") grepstr="All tests ran without failures")
configs.append(tc) configs.append(tc)

2
wally-pipelined/regression/sim-fp64-batch
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@ -1,3 +1,3 @@
vsim -c <<! vsim -c <<!
do wally-fp64-batch.do rv64g imperas64d do wally-fp64-batch.do rv64gc imperas64d
! !

2
wally-pipelined/regression/wally-fp64.do
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@ -37,7 +37,7 @@ vlib work
#} #}
# start and run simulation # start and run simulation
# remove +acc flag for faster sim during regressions if there is no need to access internal signals # remove +acc flag for faster sim during regressions if there is no need to access internal signals
vlog +incdir+../config/rv64g +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583
vopt +acc work.testbench -G TEST=imperas64d -o workopt vopt +acc work.testbench -G TEST=imperas64d -o workopt
vsim workopt vsim workopt