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Merge pull request #337 from harshinisrinath1001/main

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Fixed the spacing of the uncore and wally modules
This commit is contained in:
David Harris 2023-06-15 11:33:29 -07:00 committed by GitHub
commit 8dbbf9201a
11 changed files with 375 additions and 374 deletions
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1
src/uncore/gpio_apb.sv
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@ -151,4 +151,3 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)};
endmodule

2
src/uncore/plic_apb.sv
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@ -97,6 +97,7 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
// ==================
// Register Interface
// ==================
always @(posedge PCLK) begin
// resetting
if (~PRESETn) begin
@ -245,4 +246,3 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]);
assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]);
endmodule

2
src/uncore/ram_ahb.sv
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@ -74,7 +74,6 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(P.XLEN)) memory(.clk(HCLK), .ce(1'b1),
.addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam));
// use this to add arbitrary latency to ram. Helps test AHB controller correctness
if(`RAM_LATENCY > 0) begin
logic [7:0] NextCycle, Cycle;
@ -110,4 +109,3 @@ module ram_ahb import cvw::*; #(parameter cvw_t P,
end
endmodule

1
src/uncore/rom_ahb.sv
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@ -48,4 +48,3 @@ module rom_ahb import cvw::*; #(parameter cvw_t P,
rom1p1r #(ADDR_WIDTH, P.XLEN, P.FPGA)
memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));
endmodule

8
src/uncore/uartPC16550D.sv
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@ -122,6 +122,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Input synchronization: 2-stage synchronizer
///////////////////////////////////////////
always_ff @(posedge PCLK) begin
{SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
{SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} :
@ -132,6 +133,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Register interface (Table 1, note some are read only and some write only)
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin // Table 3 Reset Configuration
IER <= #1 4'b0;
@ -208,6 +210,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// Ross Thompson: Found a bug. If the baud rate dividers DLM, and DLL are reloaded
// the baudcount is not reset to {DLM, DLL, UART_PRESCALE}
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
baudcount <= #1 1;
@ -233,6 +236,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// receive timing and control
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
rxoversampledcnt <= #1 0;
@ -267,6 +271,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// receive shift register, buffer register, FIFO
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit
else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit
@ -368,6 +373,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// transmit timing and control
///////////////////////////////////////////
always_ff @(posedge PCLK, negedge PRESETn)
if (~PRESETn) begin
txoversampledcnt <= #1 0;
@ -395,6 +401,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// transmit holding register, shift register, FIFO
///////////////////////////////////////////
always_comb begin // compute value for parity and tx holding register
nexttxdata = fifoenabled ? txfifo[txfifotail] : TXHR; // pick from FIFO or holding register
case (LCR[1:0]) // compute parity from appropriate number of bits
@ -495,6 +502,7 @@ module uartPC16550D #(parameter UART_PRESCALE, QEMU) (
///////////////////////////////////////////
// interrupts
///////////////////////////////////////////
assign RXerr = |LSR[4:1]; // LS interrupt if any of the flags are true
assign RXerrIP = RXerr & ~squashRXerrIP; // intr squashed upon reading LSR
assign rxdataavailintr = fifoenabled ? rxfifotriggered : rxdataready;

1
src/uncore/uart_apb.sv
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@ -97,4 +97,3 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
);
endmodule

1
src/uncore/uncore.sv
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@ -189,4 +189,3 @@ module uncore import cvw::*; #(parameter cvw_t P)(
HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);
endmodule

3
src/wally/cvw.sv
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@ -148,7 +148,6 @@ typedef struct packed {
int BPRED_SIZE;
int BTB_SIZE;
// FPU division architecture
int RADIX;
int DIVCOPIES;
@ -256,7 +255,7 @@ typedef struct packed {
// division constants
int DIVN ;
int LOGR;
int LOGR ;
int RK ;
int LOGRK ;
int FPDUR ;

2
src/wally/wallypipelinedcore.sv
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@ -319,7 +319,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.clk, .reset,
.FRM_REGW, // Rounding mode from CSR
.InstrD, // instruction from IFU
.ReadDataW(ReadDataW[P.FLEN-1:0]),// Read data from memory
.ReadDataW(ReadDataW[P.FLEN-1:0]), // Read data from memory
.ForwardedSrcAE, // Integer input being processed (from IEU)
.StallE, .StallM, .StallW, // stall signals from HZU
.FlushE, .FlushM, .FlushW, // flush signals from HZU