diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv
index f22855f3e..f18469d1e 100644
--- a/wally-pipelined/testbench/testbench-busybear.sv
+++ b/wally-pipelined/testbench/testbench-busybear.sv
@@ -416,18 +416,6 @@ module testbench();
   `CHECK_CSR2(STVAL, `CSRS)
   `CHECK_CSR(STVEC)
 
-              //$stop;
-  generate 
-    if (`BUSYBEAR == 1) begin
-      initial begin //this is temporary until the bug can be fixed!!!
-        #11130100;
-      force dut.hart.ieu.dp.regf.rf[5] = 64'h0000000080000004;
-      #100;
-      release dut.hart.ieu.dp.regf.rf[5];
-      end
-    end 
-  endgenerate
-
   logic speculative;
   initial begin
     speculative = 0;