From 8d33bf0b4a51f5d18fe4ae001d3727861edf9cc1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 5 Jan 2022 16:57:22 -0600 Subject: [PATCH] Slower but correct implementation of flush. --- pipelined/src/cache/cache.sv | 69 ++++++++++++++------------------- pipelined/src/cache/cachefsm.sv | 56 +++++++++++++++++--------- pipelined/src/cache/cacheway.sv | 4 +- 3 files changed, 70 insertions(+), 59 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 61a230925..3359e9c92 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,38 +30,37 @@ module cache #(parameter integer LINELEN, parameter integer NUMWAYS, parameter integer DCACHE = 1) (input logic clk, - input logic reset, - input logic CPUBusy, - + input logic reset, + input logic CPUBusy, // cpu side - input logic [1:0] RW, - input logic [1:0] Atomic, - input logic FlushCache, - input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits. + input logic [1:0] RW, + input logic [1:0] Atomic, + input logic FlushCache, + input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] LsuPAdrM, // physical address - input logic [11:0] PreLsuPAdrM, // physical or virtual address - input logic [`XLEN-1:0] FinalWriteData, - output logic [`XLEN-1:0] ReadDataWord, - output logic CacheCommitted, + input logic [11:0] PreLsuPAdrM, // physical or virtual address + input logic [`XLEN-1:0] FinalWriteData, + output logic [`XLEN-1:0] ReadDataWord, + output logic CacheCommitted, // Bus fsm interface - input logic IgnoreRequest, - output logic CacheFetchLine, - output logic CacheWriteLine, + input logic IgnoreRequest, + output logic CacheFetchLine, + output logic CacheWriteLine, - input logic CacheBusAck, + input logic CacheBusAck, output logic [`PA_BITS-1:0] CacheBusAdr, input logic [LINELEN-1:0] CacheMemWriteData, - output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0], + output logic [`XLEN-1:0] ReadDataLineSets [(LINELEN/`XLEN)-1:0], - output logic CacheStall, + output logic CacheStall, // to performance counters - output logic CacheMiss, - output logic CacheAccess, - input logic InvalidateCacheM + output logic CacheMiss, + output logic CacheAccess, + input logic InvalidateCacheM ); @@ -73,7 +72,7 @@ module cache #(parameter integer LINELEN, localparam integer LOGWPL = $clog2(WORDSPERLINE); localparam integer LOGXLENBYTES = $clog2(`XLEN/8); - localparam integer FlushAdrThreshold = NUMLINES; + localparam integer FlushAdrThreshold = NUMLINES - 1; logic [1:0] SelAdr; logic [INDEXLEN-1:0] RAdr; @@ -103,12 +102,10 @@ module cache #(parameter integer LINELEN, logic [INDEXLEN-1:0] FlushAdr; logic [INDEXLEN-1:0] FlushAdrP1; - logic [INDEXLEN-1:0] FlushAdrQ; - logic [INDEXLEN-1:0] FlushAdrMux; - logic SelLastFlushAdr; logic FlushAdrCntEn; logic FlushAdrCntRst; logic FlushAdrFlag; + logic FlushWayFlag; logic [NUMWAYS-1:0] FlushWay; logic [NUMWAYS-1:0] NextFlushWay; @@ -126,14 +123,12 @@ module cache #(parameter integer LINELEN, mux3 #(INDEXLEN) AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), - .d2(FlushAdrMux), + .d2(FlushAdr), .s(SelAdr), .y(RAdr)); - mux2 #(INDEXLEN) - FlushAdrSelMux(.d0(FlushAdr), .d1(FlushAdrQ), .s(SelLastFlushAdr), - .y(FlushAdrMux)); - + + cacheway #(.NUMLINES(NUMLINES), .LINELEN(LINELEN), .TAGLEN(TAGLEN), .OFFSETLEN(OFFSETLEN), .INDEXLEN(INDEXLEN)) MemWay[NUMWAYS-1:0](.clk, .reset, .RAdr, @@ -218,7 +213,7 @@ module cache #(parameter integer LINELEN, mux3 #(`PA_BITS) BaseAdrMux(.d0({LsuPAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d2({VictimTag, FlushAdrQ, {{OFFSETLEN}{1'b0}}}), + .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), .s({SelFlush, SelEvict}), .y(CacheBusAdr)); @@ -228,17 +223,11 @@ module cache #(parameter integer LINELEN, flopenr #(INDEXLEN) FlushAdrReg(.clk, .reset(reset | FlushAdrCntRst), - .en(FlushAdrCntEn & FlushWay[NUMWAYS-2]), + .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; - flopenr #(INDEXLEN) - FlushAdrQReg(.clk, - .reset(reset | FlushAdrCntRst), - .en(FlushAdrCntEn), - .d(FlushAdr), - .q(FlushAdrQ)); flopenl #(NUMWAYS) FlushWayReg(.clk, @@ -252,7 +241,9 @@ module cache #(parameter integer LINELEN, assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; - assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; + //assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0] & FlushWay[NUMWAYS-1]; + assign FlushAdrFlag = FlushAdr == FlushAdrThreshold[INDEXLEN-1:0]; + assign FlushWayFlag = FlushWay[NUMWAYS-1]; // controller // *** fixme @@ -268,7 +259,7 @@ module cache #(parameter integer LINELEN, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, .SRAMLineWriteEnableM, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, - .FlushWayCntRst, .FlushAdrFlag, .FlushCache, .SelLastFlushAdr, + .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .VDWriteEnable, .LRUWriteEn); diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index a76ba3d6f..02606c574 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -43,6 +43,7 @@ module cachefsm input logic CacheHit, input logic VictimDirty, input logic FlushAdrFlag, + input logic FlushWayFlag, // hazard outputs output logic CacheStall, @@ -65,7 +66,6 @@ module cachefsm output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, - output logic SelLastFlushAdr, output logic FlushAdrCntEn, output logic FlushWayCntEn, output logic FlushAdrCntRst, @@ -90,6 +90,8 @@ module cachefsm STATE_CPU_BUSY_FINISH_AMO, STATE_FLUSH, + STATE_FLUSH_CHECK, + STATE_FLUSH_INCR, STATE_FLUSH_WRITE_BACK, STATE_FLUSH_CLEAR_DIRTY} statetype; @@ -126,7 +128,6 @@ module cachefsm NextState = STATE_READY; CacheFetchLine = 1'b0; CacheWriteLine = 1'b0; - SelLastFlushAdr = 1'b0; case (CurrState) STATE_READY: begin @@ -152,10 +153,9 @@ module cachefsm // Flush dcache to next level of memory else if(FlushCache) begin NextState = STATE_FLUSH; - CacheStall = 1'b1; - SelAdr = 2'b10; FlushAdrCntRst = 1'b1; FlushWayCntRst = 1'b1; + CacheStall = 1'b1; end // amo hit @@ -337,34 +337,50 @@ module cachefsm end end - STATE_FLUSH: begin + STATE_FLUSH: begin + // intialize flush counters + SelFlush = 1'b1; + CacheStall = 1'b1; + SelAdr = 2'b10; + NextState = STATE_FLUSH_CHECK; + end + + STATE_FLUSH_CHECK: begin CacheStall = 1'b1; SelAdr = 2'b10; SelFlush = 1'b1; - FlushAdrCntEn = 1'b1; - FlushWayCntEn = 1'b1; - SelLastFlushAdr = 1'b0; if(VictimDirty) begin NextState = STATE_FLUSH_WRITE_BACK; - FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; CacheWriteLine = 1'b1; - SelLastFlushAdr = 1'b1; - end else if (FlushAdrFlag) begin + end else if (FlushAdrFlag & FlushWayFlag) begin NextState = STATE_READY; CacheStall = 1'b0; - FlushAdrCntEn = 1'b0; + SelAdr = 2'b00; FlushWayCntEn = 1'b0; + end else if(FlushWayFlag) begin + NextState = STATE_FLUSH_INCR; + FlushAdrCntEn = 1'b1; + + FlushWayCntEn = 1'b1; end else begin - NextState = STATE_FLUSH; + FlushWayCntEn = 1'b1; + NextState = STATE_FLUSH_CHECK; end end + + STATE_FLUSH_INCR: begin + CacheStall = 1'b1; + SelAdr = 2'b10; + SelFlush = 1'b1; + FlushWayCntRst = 1'b1; + NextState = STATE_FLUSH_CHECK; + end STATE_FLUSH_WRITE_BACK: begin CacheStall = 1'b1; SelAdr = 2'b10; SelFlush = 1'b1; - SelLastFlushAdr = 1'b1; if(CacheBusAck) begin NextState = STATE_FLUSH_CLEAR_DIRTY; end else begin @@ -378,16 +394,18 @@ module cachefsm VDWriteEnable = 1'b1; SelFlush = 1'b1; SelAdr = 2'b10; - FlushAdrCntEn = 1'b0; FlushWayCntEn = 1'b0; - SelLastFlushAdr = 1'b0; - if(FlushAdrFlag) begin + if(FlushAdrFlag & FlushWayFlag) begin NextState = STATE_READY; CacheStall = 1'b0; SelAdr = 2'b00; - end else begin - NextState = STATE_FLUSH; + end else if (FlushWayFlag) begin + NextState = STATE_FLUSH_INCR; FlushAdrCntEn = 1'b1; + + FlushWayCntEn = 1'b1; + end else begin + NextState = STATE_FLUSH_CHECK; FlushWayCntEn = 1'b1; end end diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index f16d7194b..271985e79 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -34,7 +34,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [`PA_BITS-1:0] PAdr, input logic WriteEnable, input logic VDWriteEnable, - input logic [LINELEN/`XLEN-1:0] WriteWordEnable, + input logic [LINELEN/`XLEN-1:0] WriteWordEnable, input logic TagWriteEnable, input logic [LINELEN-1:0] WriteData, input logic SetValid, @@ -135,6 +135,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, end else begin:dirty assign Dirty = 1'b0; end + + endmodule // DCacheMemWay