diff --git a/pipelined/src/cache/AHBBuscachefsm.sv b/pipelined/src/cache/AHBBuscachefsm.sv new file mode 100644 index 000000000..ddd9eed87 --- /dev/null +++ b/pipelined/src/cache/AHBBuscachefsm.sv @@ -0,0 +1,161 @@ +/////////////////////////////////////////// +// busfsm.sv +// +// Written: Ross Thompson ross1728@gmail.com December 29, 2021 +// Modified: +// +// Purpose: Load/Store Unit's interface to BUS for cacheless system +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// HCLK and clk must be the same clock! +module AHBBuscachefsm #(parameter integer WordCountThreshold, + parameter integer LOGWPL, parameter logic CACHE_ENABLED ) + (input logic HCLK, + input logic HRESETn, + + // IEU interface + input logic [1:0] RW, + input logic CPUBusy, + output logic BusCommitted, + output logic BusStall, + output logic CaptureEn, + + // cache interface + input logic [1:0] CacheRW, + output logic CacheBusAck, + + // lsu interface + input logic Cacheable, + output logic SelUncachedAdr, + output logic [LOGWPL-1:0] WordCount, WordCountDelayed, + output logic SelBusWord, + + // BUS interface + input logic HREADY, + output logic [1:0] HTRANS, + output logic HWRITE, + output logic [2:0] HBURST +); + + typedef enum logic [2:0] {STATE_READY, + STATE_CAPTURE, + STATE_DELAY, + STATE_CPU_BUSY, + STATE_CACHE_ACCESS} busstatetype; + + typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + logic WordCntEn; + logic [LOGWPL-1:0] NextWordCount; + logic WordCountFlag; + logic [2:0] LocalBurstType; + logic CntReset; + + + assign CntReset = BusNextState == STATE_READY; + + // Used to send address for address stage of AHB. + flopenr #(LOGWPL) + WordCountReg(.clk(HCLK), + .reset(~HRESETn | CntReset), + .en(WordCntEn), + .d(NextWordCount), + .q(WordCount)); + + // Used to store data from data phase of AHB. + flopenr #(LOGWPL) + WordCountDelayedReg(.clk(HCLK), + .reset(~HRESETn | CntReset), + .en(WordCntEn), + .d(WordCount), + .q(WordCountDelayed)); + assign NextWordCount = WordCount + 1'b1; + + assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access. + assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) | + (BusNextState == STATE_READY & |CacheRW & HREADY); + + + always_ff @(posedge HCLK) + if (~HRESETn) BusCurrState <= #1 STATE_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + case(BusCurrState) + STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE; + else if (HREADY & |CacheRW) BusNextState = STATE_CACHE_ACCESS; + else BusNextState = STATE_READY; + STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY; + else BusNextState = STATE_CAPTURE; + STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CACHE_ACCESS: if(HREADY & WordCountFlag) BusNextState = STATE_READY; + else BusNextState = STATE_CACHE_ACCESS; + default: BusNextState = STATE_READY; + endcase + end + + assign BusStall = (BusCurrState == STATE_READY & (|RW | |CacheRW)) | + (BusCurrState == STATE_CAPTURE) | + (BusCurrState == STATE_CACHE_ACCESS); + + assign BusCommitted = BusCurrState != STATE_READY; // *** might not be correct + + assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) | + (BusCurrState == STATE_CAPTURE & ~HREADY) | + (BusCurrState == STATE_CACHE_ACCESS & ~HREADY & |WordCount) ? AHB_NONSEQ : + (BusCurrState == STATE_CACHE_ACCESS & ~HREADY & ~|WordCount) ? AHB_SEQ : AHB_IDLE; + + assign HWRITE = (BusCurrState == STATE_READY & (RW[0] | CacheRW[0])) | // *** might not be necessary, maybe just RW[0] + (BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]); + assign CaptureEn = BusCurrState == STATE_CAPTURE | (BusCurrState == STATE_CACHE_ACCESS & HREADY); + assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; // Don't want to use burst when doing an Uncached Access. + + always_comb begin + case(WordCountThreshold) + 0: LocalBurstType = 3'b000; + 3: LocalBurstType = 3'b011; // INCR4 + 7: LocalBurstType = 3'b101; // INCR8 + 15: LocalBurstType = 3'b111; // INCR16 + default: LocalBurstType = 3'b001; // INCR without end. + endcase + end + + assign SelUncachedAdr = (BusCurrState == STATE_READY & |RW) | + (BusCurrState == STATE_CAPTURE) | + (BusCurrState == STATE_DELAY); + + assign CacheBusAck = (BusCurrState == STATE_CAPTURE & HREADY & WordCountFlag); + + assign SelBusWord = (BusCurrState == STATE_READY & RW[0]) | + (BusCurrState == STATE_CAPTURE & RW[0]) | + (BusCurrState == STATE_CACHE_ACCESS & CacheRW[0]); + +endmodule diff --git a/pipelined/src/cache/AHBCachedp.sv b/pipelined/src/cache/AHBCachedp.sv new file mode 100644 index 000000000..7ea57c2dd --- /dev/null +++ b/pipelined/src/cache/AHBCachedp.sv @@ -0,0 +1,90 @@ +/////////////////////////////////////////// +// AHBCachedp.sv +// +// Written: Ross Thompson ross1728@gmail.com August 29, 2022 +// Modified: +// +// Purpose: Cache/Bus data path. +// Bus Side logic +// register the fetch data from the next level of memory. +// This register should be necessary for timing. There is no register in the uncore or +// ahblite controller between the memories and this cache. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module AHBCachedp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) + ( + input logic HCLK, HRESETn, + + // bus interface + input logic HREADY, + input logic [`XLEN-1:0] HRDATA, + output logic [2:0] HSIZE, + output logic [2:0] HBURST, + output logic [1:0] HTRANS, + output logic HWRITE, + output logic [`PA_BITS-1:0] HADDR, + output logic [LOGWPL-1:0] WordCount, + + // cache interface + input logic [`PA_BITS-1:0] CacheBusAdr, + input logic [1:0] CacheRW, + output logic CacheBusAck, + output logic [LINELEN-1:0] FetchBuffer, + output logic SelUncachedAdr, + + // lsu/ifu interface + input logic [`PA_BITS-1:0] PAdr, + input logic [1:0] RW, + input logic CPUBusy, + input logic Cacheable, + input logic [2:0] Funct3, + output logic SelBusWord, + output logic BusStall, + output logic BusCommitted); + + localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + logic [`PA_BITS-1:0] LocalHADDR; + logic [LOGWPL-1:0] WordCountDelayed; + logic CaptureEn; + + genvar index; + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + logic [WORDSPERLINE-1:0] CaptureWord; + assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed); + flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); + end + + mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR); + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + + mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE)); + + AHBBuscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( + .HCLK, .HRESETn, .RW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, + .CacheRW, .CacheBusAck, .Cacheable, .SelUncachedAdr, .WordCount, .WordCountDelayed, + .HREADY, .HTRANS, .HWRITE, .HBURST); +endmodule diff --git a/pipelined/src/ebu/ahbmultimanager.sv b/pipelined/src/ebu/ahbmultimanager.sv new file mode 100644 index 000000000..3c3881f65 --- /dev/null +++ b/pipelined/src/ebu/ahbmultimanager.sv @@ -0,0 +1,177 @@ +/////////////////////////////////////////// +// abhmultimanager +// +// Written: Ross Thompson August 29, 2022 +// ross1728@gmail.com +// Modified: +// +// Purpose: AHB multi manager interface to merge LSU and IFU controls. +// See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0 +// Arbitrates requests from instruction and data streams +// Connects core to peripherals and I/O pins on SOC +// Bus width presently matches XLEN +// Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ahbmultimanager + ( + input logic clk, reset, + // Signals from IFU + input logic [`PA_BITS-1:0] IFUHADDR, + input logic [2:0] IFUHBURST, + input logic [1:0] IFUHTRANS, + output logic IFUHREADY, + // Signals from LSU + input logic [`PA_BITS-1:0] LSUHADDR, + input logic [`XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [`XLEN/8-1:0] LSUHWSTRB, + input logic [2:0] LSUHSIZE, + input logic [2:0] LSUHBURST, + input logic [1:0] LSUHTRANS, + input logic LSUHWRITE, + output logic LSUHREADY, + // add LSUHWSTRB *** + + // AHB-Lite external signals + (* mark_debug = "true" *) input logic HREADY, HRESP, + (* mark_debug = "true" *) output logic HCLK, HRESETn, + (* mark_debug = "true" *) output logic [`PA_BITS-1:0] HADDR, // *** one day switch to a different bus that supports the full physical address + (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA, + (* mark_debug = "true" *) output logic [`XLEN/8-1:0] HWSTRB, + (* mark_debug = "true" *) output logic HWRITE, + (* mark_debug = "true" *) output logic [2:0] HSIZE, + (* mark_debug = "true" *) output logic [2:0] HBURST, + (* mark_debug = "true" *) output logic [3:0] HPROT, + (* mark_debug = "true" *) output logic [1:0] HTRANS, + (* mark_debug = "true" *) output logic HMASTLOCK + ); + + localparam ADRBITS = $clog2(`XLEN/8); // address bits for Byte Mask generator + + typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; + statetype BusState, NextBusState; + logic LSUGrant; + logic [ADRBITS-1:0] HADDRD; + logic [1:0] HSIZED; + + logic [1:0] save, restore, dis, sel; + logic both; + logic DoArbitration; + + logic [`PA_BITS-1:0] IFUHADDRSave, IFUHADDRRestore; + logic [1:0] IFUHTRANSSave, IFUHTRANSRestore; + logic [2:0] IFUHBURSTSave, IFUHBURSTRestore; + + logic [`PA_BITS-1:0] LSUHADDRSave, LSUHADDRRestore; + logic [1:0] LSUHTRANSSave, LSUHTRANSRestore; + logic [2:0] LSUHBURSTSave, LSUHBURSTRestore; + logic [2:0] LSUHSIZESave, LSUHSIZERestore; + logic LSUHWRITESave, LSUHWRITERestore; + + logic IFUReq, LSUReq; + logic IFUActive, LSUActive; + + + assign HCLK = clk; + assign HRESETn = ~reset; + + + // if two requests come in at once pick one to select and save the others Address phase + // inputs. + + // input stage IFU + flopenr #(3+2+`PA_BITS) IFUSaveReg(HCLK, ~HRESETn, save[0], + {IFUHBURST, IFUHTRANS, IFUHADDR}, + {IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave}); + mux2 #(3+2+`PA_BITS) IFURestorMux({IFUHBURST, IFUHTRANS, IFUHADDR}, + {IFUHBURSTSave, IFUHTRANSSave, IFUHADDRSave}, + restore[0], + {IFUHBURSTRestore, IFUHTRANSRestore, IFUHADDRRestore}); + assign IFUReq = IFUHTRANSRestore != 2'b00; + + assign IFUHREADY = HREADY & ~dis[0]; + assign IFUActive = IFUReq & IFUHREADY; + + // input stage LSU + flopenr #(1+3+3+2+`PA_BITS) LSUSaveReg(HCLK, ~HRESETn, save[1], + {LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR}, + {LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave}); + mux2 #(1+3+3+2+`PA_BITS) LSURestorMux({LSUHWRITE, LSUHSIZE, LSUHBURST, LSUHTRANS, LSUHADDR}, + {LSUHWRITESave, LSUHSIZESave, LSUHBURSTSave, LSUHTRANSSave, LSUHADDRSave}, + restore[1], + {LSUHWRITERestore, LSUHSIZERestore, LSUHBURSTRestore, LSUHTRANSRestore, LSUHADDRRestore}); + + assign LSUReq = LSUHTRANSRestore != 2'b00; + assign LSUHREADY = HREADY & ~dis[1]; + assign LSUActive = LSUReq & LSUHREADY; + + assign both = LSUActive & IFUActive; + + // output mux //*** rewrite for general number of managers. + assign HADDR = sel[1] ? LSUHADDRRestore : sel[0] ? IFUHADDRRestore : '0; + assign HSIZE = sel[1] ? LSUHSIZERestore : sel[0] ? 3'b010: '0; // Instruction reads are always 32 bits + assign HBURST = sel[1] ? LSUHBURSTRestore : sel[0] ? IFUHBURSTRestore : '0; // If doing memory accesses, use LSUburst, else use Instruction burst. + assign HTRANS = sel[1] ? LSUHTRANSRestore : sel[0] ? IFUHTRANSRestore: '0; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise + assign HPROT = 4'b0011; // not used; see Section 3.7 + assign HMASTLOCK = 0; // no locking supported + assign HWRITE = sel[1] ? LSUHWRITERestore : sel[0] ? 1'b0 : '0; + + // basic arb always selects LSU when both + assign save[0] = BusState == IDLE & both; + assign restore[0] = BusState == ARBITRATE; + assign dis[0] = BusState == ARBITRATE; + assign sel[0] = (NextBusState == ARBITRATE) ? 1'b0 : IFUReq; + + // + assign save[1] = 1'b0; + assign restore[1] = 1'b0; + assign dis[1] = 1'b0; + assign sel[1] = NextBusState == ARBITRATE ? LSUReq : 1'b0; + + + + // Bus State FSM + // Data accesses have priority over instructions. However, if a data access comes + // while an cache line read is occuring, the line read finishes before + // the data access can take place. + + flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); + always_comb + case (BusState) + IDLE: if (both) NextBusState = ARBITRATE; + else NextBusState = IDLE; + ARBITRATE: if (HREADY)NextBusState = IDLE; + else NextBusState = ARBITRATE; + default: NextBusState = IDLE; + endcase // case (BusState) + + assign DoArbitration = BusState == ARBITRATE; + + assign HWDATA = LSUHWDATA; + assign HWSTRB = LSUHWSTRB; + + +endmodule diff --git a/pipelined/src/lsu/AHBBusfsm.sv b/pipelined/src/lsu/AHBBusfsm.sv new file mode 100644 index 000000000..b88d5ed47 --- /dev/null +++ b/pipelined/src/lsu/AHBBusfsm.sv @@ -0,0 +1,86 @@ +/////////////////////////////////////////// +// busfsm.sv +// +// Written: Ross Thompson ross1728@gmail.com December 29, 2021 +// Modified: +// +// Purpose: Load/Store Unit's interface to BUS for cacheless system +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// HCLK and clk must be the same clock! +module AHBBusfsm + (input logic HCLK, + input logic HRESETn, + + // IEU interface + input logic [1:0] RW, + input logic CPUBusy, + output logic BusCommitted, + output logic BusStall, + output logic CaptureEn, + input logic HREADY, + output logic [1:0] HTRANS, + output logic HWRITE +); + + typedef enum logic [2:0] {STATE_READY, + STATE_CAPTURE, + STATE_DELAY, + STATE_CPU_BUSY} busstatetype; + + typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype; + + (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; + + always_ff @(posedge HCLK) + if (~HRESETn) BusCurrState <= #1 STATE_READY; + else BusCurrState <= #1 BusNextState; + + always_comb begin + case(BusCurrState) + STATE_READY: if(HREADY & |RW) BusNextState = STATE_CAPTURE; + else BusNextState = STATE_READY; + STATE_CAPTURE: if(HREADY) BusNextState = STATE_DELAY; + else BusNextState = STATE_CAPTURE; + STATE_DELAY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + STATE_CPU_BUSY: if(CPUBusy) BusNextState = STATE_CPU_BUSY; + else BusNextState = STATE_READY; + default: BusNextState = STATE_READY; + endcase + end + + assign BusStall = (BusCurrState == STATE_READY & |RW) | + (BusCurrState == STATE_CAPTURE); + + assign BusCommitted = BusCurrState != STATE_READY; + + assign HTRANS = (BusCurrState == STATE_READY & HREADY & |RW) | + (BusCurrState == STATE_CAPTURE & ~HREADY) ? AHB_NONSEQ : AHB_IDLE; + assign HWRITE = (BusCurrState == STATE_READY) & RW[0]; // *** might not be necessary, maybe just RW[0] + assign CaptureEn = BusCurrState == STATE_CAPTURE; + +endmodule diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 58013f9d2..8f1053401 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -258,14 +258,14 @@ module lsu ( .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .FetchBuffer, .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - cachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp( - .clk, .reset, - .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), - .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete), + AHBCachedp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) cachedp( + .HCLK(clk), .HRESETn(~reset), + .HRDATA, + .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .WordCount, .SelBusWord, - .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), - .SelUncachedAdr, .IgnoreRequest, .RW(LSURWM), .CPUBusy, .Cacheable(CacheableM), + .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheRW({DCacheFetchLine, DCacheWriteLine} & ~{IgnoreRequest, IgnoreRequest}), + .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(LSUPAdrM), + .SelUncachedAdr, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), .CPUBusy, .Cacheable(CacheableM), .BusStall, .BusCommitted(BusCommittedM)); mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, FetchBuffer[`XLEN-1:0]}),