diff --git a/bin/regression-wally b/bin/regression-wally index 1c3cde58e..512856602 100755 --- a/bin/regression-wally +++ b/bin/regression-wally @@ -517,6 +517,8 @@ def main(): TIMEOUT_DUR = 60*1440 # 1 day elif args.testfloat: TIMEOUT_DUR = 30*60 # seconds + elif args.nightly: + TIMEOUT_DUR = 30*60 # seconds else: TIMEOUT_DUR = 10*60 # seconds diff --git a/bin/wsim b/bin/wsim index 23807526c..cef7eca27 100755 --- a/bin/wsim +++ b/bin/wsim @@ -82,7 +82,7 @@ if (args.rvvi): if(int(args.locksteplog) >= 1): EnableLog = 1 else: EnableLog = 0 if (args.lockstep): - prefix = "IMPERAS_TOOLS=" + WALLY + "/sim/imperas.ic" + prefix = "IMPERAS_TOOLS=" + WALLY + "/config/"+args.config+"/imperas.ic" if(args.locksteplog != 0): ImperasPlusArgs = " +IDV_TRACE2LOG=" + str(EnableLog) + " +IDV_TRACE2LOG_AFTER=" + str(args.locksteplog) else: ImperasPlusArgs = "" if(args.fcov): diff --git a/config/rv32gc/imperas.ic b/config/rv32gc/imperas.ic new file mode 100644 index 000000000..c9b8292f2 --- /dev/null +++ b/config/rv32gc/imperas.ic @@ -0,0 +1,119 @@ +# imperas.ic +# Initialization file for ImperasDV lock step simulation +# David_Harris@hmc.edu 15 August 2024 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +#--mpdconsole +#--gdbconsole +#--showoverrides +#--showcommands + +# Core settings +--variant RV32GC # for RV32GC +--override cpu/priv_version=1.12 +--override cpu/user_version=20191213 +# arch +--override cpu/mimpid=0x100 +--override cpu/mvendorid=0x602 +--override cpu/marchid=0x24 +--override refRoot/cpu/tvec_align=64 +--override refRoot/cpu/envcfg_mask=1 # dh 1/26/24 this should be deleted when ImperasDV is updated to allow envcfg.FIOM to be written + +# bit manipulation +--override cpu/add_Extensions=B +--override cpu/bitmanip_version=1.0.0 +--override cpu/misa_B_Zba_Zbb_Zbs=T + +# More extensions +--override cpu/Zcb=T +--override cpu/Zicond=T +--override cpu/Zfh=T +--override cpu/Zfa=T + +# Cache block operations +--override cpu/Zicbom=T +--override cpu/Zicbop=T +--override cpu/Zicboz=T +--override cmomp_bytes=64 # Zic64b +--override cmoz_bytes=64 # Zic64b +--override lr_sc_grain=8 # Za64rs requires <=64; we use native word size + +# 64 KiB continuous huge pages supported +#--override cpu/Svpbmt=F +#--override cpu/Svnapot_page_mask=65536 + +# SV32 supported +--override cpu/Sv_modes=3 +#--showoverrides + +--override cpu/Svinval=T + + +# clarify +#--override refRoot/cpu/mtvec_sext=F + +--override cpu/tval_ii_code=T + +#--override cpu/time_undefined=T +#--override cpu/cycle_undefined=T +#--override cpu/instret_undefined=T +#--override cpu/hpmcounter_undefined=T + +--override cpu/reset_address=0x80000000 + +--override cpu/unaligned=F # Zicclsm (should be true) +--override cpu/ignore_non_leaf_DAU=1 +--override cpu/wfi_is_nop=T +--override cpu/misa_Extensions_mask=0x0 # MISA not writable +--override cpu/Sstc=T + +# Enable SVADU hardware update of A/D bits when menvcfg.ADUE=1 +--override cpu/Svadu=T +#--override cpu/updatePTEA=F +#--override cpu/updatePTED=F + +--override cpu/PMP_registers=16 +--override cpu/PMP_undefined=T + +# mstatus.FS is set dirty on any write to a FPR, or when a fp operation signals an exception +--override cpu/mstatus_fs_mode=write_1 + +# PMA Settings +# 'r': read access allowed +# 'w': write access allowed +# 'x': execute access allowed +# 'a': aligned access required +# 'A': atomic instructions NOT allowed (actually USER1 privilege needed) +# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed) +# '1': 1-byte accesses allowed +# '2': 2-byte accesses allowed +# '4': 4-byte accesses allowed +# '8': 8-byte accesses allowed +# '-', space: ignored (use for input string formatting). +# +# SVxx Memory 0x0000000000 0x7FFFFFFFFF +# +--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0xFFFFFFFFFFFFFFFFFF -attributes " ---a-- ---- " # All memory inaccessible unless defined otherwise +--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ---a-- ---- " # INITIAL +--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 " # BOOTROM +--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw-aA- --48 " # SDC +--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw-aA- 1248 " # CLINT +--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw-aA- --4- " # PLIC +--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw-aA- 1--- " # UART0 error - 0x10000000 - 0x100000FF +--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw-aA- --4- " # GPIO error - 0x10069000 - 0x100600FF +--callcommand refRoot/cpu/setPMA -lo 0x0010040000 -hi 0x0010040FFF -attributes " rw-aA- --4- " # SPI error - 0x10040000 - 0x10040FFF +--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 " # UNCORE_RAM + +# Enable the Imperas instruction coverage +#-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 +#-override refRoot/cpu/cv/cover=basic +#-override refRoot/cpu/cv/extensions=RV32I + +# Add Imperas simulator application instruction tracing +# uncomment these to provide tracing +--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 +--override cpu/debugflags=6 --override cpu/verbose=1 +--override cpu/show_c_prefix=T + +# Store simulator output to logfile +--output imperas.log diff --git a/sim/imperas.ic b/config/rv64gc/imperas.ic similarity index 95% rename from sim/imperas.ic rename to config/rv64gc/imperas.ic index b3485aff7..fa9b56dfc 100644 --- a/sim/imperas.ic +++ b/config/rv64gc/imperas.ic @@ -109,9 +109,9 @@ # Add Imperas simulator application instruction tracing # uncomment these to provide tracing ---verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 ---override cpu/debugflags=6 --override cpu/verbose=1 ---override cpu/show_c_prefix=T +#--verbose --trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # --traceafter 300000000 +#--override cpu/debugflags=6 --override cpu/verbose=1 +#--override cpu/show_c_prefix=T # Store simulator output to logfile --output imperas.log diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 80f7af651..5676f6c13 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -169,12 +169,17 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; - CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; + CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[P.XLEN-1:0]; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW; CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; + if (P.XLEN == 32) begin + CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrsr.MSTATUSH_REGW; + CSRArray[12'h31A] = testbench.dut.core.priv.priv.csr.csrm.MENVCFGH_REGW; + CSRArray[12'h15D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW[63:32]; + end end else begin // hold the old value if the pipeline is stalled. // PMP CFG 3A0 to 3AF diff --git a/testbench/testbench.sv b/testbench/testbench.sv index d214ef3b6..f91bdcc67 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -762,7 +762,7 @@ end void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VENDOR, "riscv.ovpworld.org")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_NAME, "riscv")); void'(rvviRefConfigSetString(IDV_CONFIG_MODEL_VARIANT, "RV64GCK")); - void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, 56)); + void'(rvviRefConfigSetInt(IDV_CONFIG_MODEL_ADDRESS_BUS_WIDTH, XLEN==64 ? 56 : 34)); void'(rvviRefConfigSetInt(IDV_CONFIG_MAX_NET_LATENCY_RETIREMENTS, 6)); if(elffilename == "buildroot") filename = ""; @@ -824,15 +824,25 @@ end void'(rvviRefCsrSetVolatile(0, 32'hC02)); // INSTRET void'(rvviRefCsrSetVolatile(0, 32'hB02)); // MINSTRET void'(rvviRefCsrSetVolatile(0, 32'hC01)); // TIME - + if (P.XLEN == 32) begin + void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH + void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hB82)); // MINSTRETH + void'(rvviRefCsrSetVolatile(0, 32'hC81)); // TIMEH + end // User HPMCOUNTER3 - HPMCOUNTER31 for (iter='hC03; iter<='hC1F; iter++) begin void'(rvviRefCsrSetVolatile(0, iter)); // HPMCOUNTERx + if (P.XLEN == 32) + void'(rvviRefCsrSetVolatile(0, iter+128)); // HPMCOUNTERxH end // Machine MHPMCOUNTER3 - MHPMCOUNTER31 for (iter='hB03; iter<='hB1F; iter++) begin void'(rvviRefCsrSetVolatile(0, iter)); // MHPMCOUNTERx + if (P.XLEN == 32) + void'(rvviRefCsrSetVolatile(0, iter+128)); // MHPMCOUNTERxH end // cannot predict this register due to latency between diff --git a/tests/custom/spitest/spitest.c b/tests/custom/spitest/spitest.c index fc08f496c..23d408c16 100644 --- a/tests/custom/spitest/spitest.c +++ b/tests/custom/spitest/spitest.c @@ -92,7 +92,7 @@ void main() { do { // Send 8 dummy bytes (fifo should be empty) for (j = 0; j < 8; j++) { - spi_sendbyte(0xaa); + spi_sendbyte(0xaa + j); } // Reset counter. Process bytes AS THEY COME IN. diff --git a/tests/custom/spitest/start.s b/tests/custom/spitest/start.s new file mode 100644 index 000000000..57f66ce79 --- /dev/null +++ b/tests/custom/spitest/start.s @@ -0,0 +1,59 @@ +.section .init +.global _start +.type _start, @function + +_start: + # Initialize global pointer + .option push + .option norelax + 1:auipc gp, %pcrel_hi(__global_pointer$) + addi gp, gp, %pcrel_lo(1b) + .option pop + + li x1, 0 + li x2, 0 + li x4, 0 + li x5, 0 + li x6, 0 + li x7, 0 + li x8, 0 + li x9, 0 + li x10, 0 + li x11, 0 + li x12, 0 + li x13, 0 + li x14, 0 + li x15, 0 + li x16, 0 + li x17, 0 + li x18, 0 + li x19, 0 + li x20, 0 + li x21, 0 + li x22, 0 + li x23, 0 + li x24, 0 + li x25, 0 + li x26, 0 + li x27, 0 + li x28, 0 + li x29, 0 + li x30, 0 + li x31, 0 + + + + # set the stack pointer to the top of memory - 8 bytes (pointer size) + li sp, 0x87FFFFF8 + + jal ra, main + jal ra, _halt + +.section .text +.global _halt +.type _halt, @function +_halt: + li gp, 1 + li a0, 0 + ecall + j _halt