Fixed Zicclsm bug. Misalignment and spill detection were not masked by access type. Therefore a page table walk which always aligned could have had an IEUAdrM misaligned which erroneously caused a shift in the read data.

src/lsu/align.sv

@@ -38,10 +38,11 @@ module align import cvw::*;  #(parameter cvw_t P) (
   input logic [2:0]               Funct3M, // Size of memory operation
   input logic [1:0]               MemRWM, 
   input logic                     CacheableM,
-  input logic [P.LLEN*2-1:0]DCacheReadDataWordM,  // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
+  input logic [P.LLEN*2-1:0]      DCacheReadDataWordM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
   input logic                     CacheBusHPWTStall, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
   input logic                     DTLBMissM, // ITLB miss, ignore memory request
   input logic                     DataUpdateDAM, // ITLB miss, ignore memory request
+  input logic                     SelHPTW,
 
   input logic [(P.LLEN-1)/8:0]    ByteMaskM,
   input logic [(P.LLEN-1)/8:0]    ByteMaskExtendedM,
@@ -83,6 +84,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   logic [$clog2(LLENINBYTES)-1:0]                 ByteOffsetM;
   logic                                HalfSpillM, WordSpillM;
   logic [$clog2(LLENINBYTES)-1:0]      AccessByteOffsetM;
+  logic                                ValidAccess;
 
   /* verilator lint_off WIDTHEXPAND */
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
@@ -116,17 +118,18 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign WordMisalignedM = (ByteOffsetM[1:0] != '0) & Funct3M[1:0] == 2'b10;
   assign HalfSpillM = (IEUAdrM[OFFSET_BIT_POS-1:1] == '1) & HalfMisalignedM;
   assign WordSpillM = (IEUAdrM[OFFSET_BIT_POS-1:2] == '1) & WordMisalignedM;
+  assign ValidAccess = (|MemRWM) & ~SelHPTW;
 
   if(P.LLEN == 64) begin
     logic DoubleSpillM;
     logic DoubleMisalignedM;
     assign DoubleMisalignedM = (ByteOffsetM[2:0] != '0) & Funct3M[1:0] == 2'b11;
     assign DoubleSpillM = (IEUAdrM[OFFSET_BIT_POS-1:3] == '1) & DoubleMisalignedM;
-    assign MisalignedM = HalfMisalignedM | WordMisalignedM | DoubleMisalignedM;
+    assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM | DoubleMisalignedM);
-    assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM);
+    assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM | DoubleSpillM);
   end else begin
-    assign SpillM = (|MemRWM) & CacheableM & (HalfSpillM | WordSpillM);
+    assign SpillM = ValidAccess & CacheableM & (HalfSpillM | WordSpillM);
-    assign MisalignedM = HalfMisalignedM | WordMisalignedM;
+    assign MisalignedM = ValidAccess & (HalfMisalignedM | WordMisalignedM);
   end
       
   // align by shifting

src/lsu/lsu.sv

@@ -158,7 +158,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M,
                      .MemRWM, .CacheableM,
-                     .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM,
+                     .DCacheReadDataWordM, .CacheBusHPWTStall, .DTLBMissM, .DataUpdateDAM, .SelHPTW,
                      .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
                      .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .MemRWSpillM, .DCacheReadDataWordSpillM, .SpillStallM,
                      .SelStoreDelay);