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Updated for a better ILA rvvi debugger.

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This commit is contained in:
Rose Thompson 2024-07-22 17:44:04 -05:00
parent 121342f4cc
commit 8ca565ed53
2 changed files with 3 additions and 3 deletions
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4
config/derivlist.txt
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@ -57,9 +57,9 @@ EXT_MEM_RANGE 64'h0FFFFFFF
SDC_SUPPORTED 1 SDC_SUPPORTED 1
PLIC_SDC_ID 32'd20 PLIC_SDC_ID 32'd20
BPRED_SIZE 32'd12 BPRED_SIZE 32'd12
RVVI_SYNTH_SUPPORTED 0 RVVI_SYNTH_SUPPORTED 1
RVVI_INIT_TIME_OUT 32'd100000000 RVVI_INIT_TIME_OUT 32'd100000000
RVVI_PACKET_DELAY 32'd350 RVVI_PACKET_DELAY 32'd400
# The syn configurations are trimmed down for faster synthesis. # The syn configurations are trimmed down for faster synthesis.

2
fpga/constraints/small-debug-rvvi.xdc
View File

@ -1,5 +1,5 @@
create_debug_core u_ila_0 ila create_debug_core u_ila_0 ila
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 4096 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN true [get_debug_cores u_ila_0] set_property C_TRIGIN_EN true [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]