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Commented out rvvi debug probes in wally.tcl.

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This commit is contained in:
Jacob Pease 2024-08-08 13:52:53 -05:00
parent ed0c826d74
commit 8c96c06022
1 changed files with 2 additions and 2 deletions
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4
fpga/generator/wally.tcl
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@ -89,8 +89,8 @@ report_clock_interaction -file re
write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
#source ../constraints/small-debug.xdc
source ../constraints/small-debug-rvvi.xdc
source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
} else {
source ../constraints/vcu-small-debug.xdc
}