diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv
index 9a8bb9d8e..a12b095a4 100644
--- a/src/privileged/csrs.sv
+++ b/src/privileged/csrs.sv
@@ -29,61 +29,61 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module csrs import cvw::*;  #(parameter cvw_t P) (
-  input  logic             clk, reset, 
-  input  logic             CSRSWriteM, STrapM,
-  input  logic [11:0]      CSRAdrM,
+  input  logic              clk, reset, 
+  input  logic              CSRSWriteM, STrapM,
+  input  logic [11:0]       CSRAdrM,
   input  logic [P.XLEN-1:0] NextEPCM, NextMtvalM, SSTATUS_REGW, 
-  input  logic [4:0]       NextCauseM,
-  input  logic             STATUS_TVM,
-  input  logic             MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
+  input  logic [4:0]        NextCauseM,
+  input  logic              STATUS_TVM,
+  input  logic              MCOUNTEREN_TM, // TM bit (1) of MCOUNTEREN; cause illegal instruction when trying to access STIMECMP if clear
   input  logic [P.XLEN-1:0] CSRWriteValM,
-  input  logic [1:0]       PrivilegeModeW,
+  input  logic [1:0]        PrivilegeModeW,
   output logic [P.XLEN-1:0] CSRSReadValM, STVEC_REGW,
   output logic [P.XLEN-1:0] SEPC_REGW,      
-  output logic [31:0]      SCOUNTEREN_REGW, 
+  output logic [31:0]       SCOUNTEREN_REGW, 
   output logic [P.XLEN-1:0] SATP_REGW,
-  input  logic [11:0]      MIP_REGW, MIE_REGW, MIDELEG_REGW,
-  input  logic [63:0]      MTIME_CLINT,
-  output logic             WriteSSTATUSM,
-  output logic             IllegalCSRSAccessM,
-  output logic             STimerInt
+  input  logic [11:0]       MIP_REGW, MIE_REGW, MIDELEG_REGW,
+  input  logic [63:0]       MTIME_CLINT,
+  output logic              WriteSSTATUSM,
+  output logic              IllegalCSRSAccessM,
+  output logic              STimerInt
 );
 
   // Supervisor CSRs
-  localparam SSTATUS = 12'h100;
-  localparam SIE = 12'h104;
-  localparam STVEC = 12'h105;
-  localparam SCOUNTEREN = 12'h106;
-  localparam SSCRATCH = 12'h140;
-  localparam SEPC = 12'h141;
-  localparam SCAUSE = 12'h142;
-  localparam STVAL = 12'h143;
-  localparam SIP= 12'h144;
-  localparam STIMECMP = 12'h14D;
-  localparam STIMECMPH = 12'h15D;
-  localparam SATP = 12'h180;
+  localparam SSTATUS      = 12'h100;
+  localparam SIE          = 12'h104;
+  localparam STVEC        = 12'h105;
+  localparam SCOUNTEREN   = 12'h106;
+  localparam SSCRATCH     = 12'h140;
+  localparam SEPC         = 12'h141;
+  localparam SCAUSE       = 12'h142;
+  localparam STVAL        = 12'h143;
+  localparam SIP          = 12'h144;
+  localparam STIMECMP     = 12'h14D;
+  localparam STIMECMPH    = 12'h15D;
+  localparam SATP         = 12'h180;
   // Constants
-  localparam ZERO = {(P.XLEN){1'b0}};
+  localparam ZERO         = {(P.XLEN){1'b0}};
   localparam SEDELEG_MASK = ~(ZERO | {{P.XLEN-3{1'b0}}, 3'b111} << 9);
 
   logic                    WriteSTVECM;
   logic                    WriteSSCRATCHM, WriteSEPCM;
   logic                    WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
   logic                    WriteSTIMECMPM, WriteSTIMECMPHM;
-  logic [P.XLEN-1:0]        SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
+  logic [P.XLEN-1:0]       SSCRATCH_REGW, STVAL_REGW, SCAUSE_REGW;
   logic [63:0]             STIMECMP_REGW;
   
   // write enables
-  assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS);
-  assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC);
-  assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH);
-  assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
-  assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
-  assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
-  assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
+  assign WriteSSTATUSM    = CSRSWriteM & (CSRAdrM == SSTATUS);
+  assign WriteSTVECM      = CSRSWriteM & (CSRAdrM == STVEC);
+  assign WriteSSCRATCHM   = CSRSWriteM & (CSRAdrM == SSCRATCH);
+  assign WriteSEPCM       = STrapM | (CSRSWriteM & (CSRAdrM == SEPC));
+  assign WriteSCAUSEM     = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE));
+  assign WriteSTVALM      = STrapM | (CSRSWriteM & (CSRAdrM == STVAL));
+  assign WriteSATPM       = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == P.M_MODE | ~STATUS_TVM);
   assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN);
-  assign WriteSTIMECMPM = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM);
-  assign WriteSTIMECMPHM = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM) & (P.XLEN == 32);
+  assign WriteSTIMECMPM   = CSRSWriteM & (CSRAdrM == STIMECMP) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM);
+  assign WriteSTIMECMPHM  = CSRSWriteM & (CSRAdrM == STIMECMPH) & (PrivilegeModeW == P.M_MODE | MCOUNTEREN_TM) & (P.XLEN == 32);
 
   // CSRs
   flopenr #(P.XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[P.XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); 
@@ -95,7 +95,7 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
     flopenr #(P.XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
   else
     assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
-  flopenr #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
+  flopenr #(32)     SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
   if (P.SSTC_SUPPORTED) begin : sstc
     if (P.XLEN == 64) begin : sstc64
       flopenl #(P.XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW);
@@ -108,7 +108,7 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
   // Supervisor timer interrupt logic
   // Spec is a bit peculiar - Machine timer interrupts are produced in CLINT, while Supervisor timer interrupts are in CSRs
   if (P.SSTC_SUPPORTED)
-   assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
+    assign STimerInt = ({1'b0, MTIME_CLINT} >= {1'b0, STIMECMP_REGW}); // unsigned comparison
   else 
     assign STimerInt = 0;
     
@@ -140,10 +140,10 @@ module csrs import cvw::*;  #(parameter cvw_t P) (
                    CSRSReadValM = 0;
                    IllegalCSRSAccessM = 1;
                  end
-      default: begin
-                  CSRSReadValM = 0; 
-                  IllegalCSRSAccessM = 1;  
-               end       
+      default:   begin
+                   CSRSReadValM = 0; 
+                   IllegalCSRSAccessM = 1;  
+                 end       
     endcase
   end
 endmodule