Updated wrapper generation to be automatic without specifying WRAPPER=1; instead looks for cvw_t in the file. Also starting to add OSU 130 nm synthesis.

bin/libppa.pl

@@ -41,6 +41,16 @@ my @cr; my @cf; my @rt; my @ft;
 # cell and corners to analyze
 my $libpath; my $libbase; my $cellname; my @corners;
 
+# Sky130
+$libpath ="/opt/riscv/cad/lib/sky130_osu_sc_t12/12T_ms/lib";
+$libbase = "sky130_osu_sc_12T_ms_";
+$cellname = "sky130_osu_sc_12T_ms__inv_1";
+@corners = ("TT_1P8_25C.ccs", "tt_1P80_25C.ccs", "tt_1P62_25C.ccs", "tt_1P89_25C.ccs", "ss_1P60_-40C.ccs", "ss_1P60_100C.ccs", "ss_1P60_150C.ccs", "ff_1P95_-40C.ccs", "ff_1P95_100C.ccs", "ff_1P95_150C.ccs");
+printf("Library $libbase Cell $cellname\n");
+foreach my $corner (@corners) {
+    &analyzeCell($corner);
+}
+
 # Sky90
 $libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
 $libbase = "scc9gena_";
@@ -54,7 +64,7 @@ foreach my $corner (@corners) {
 # TSMC
 $libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
 $libbase = "tcbn28hpcplusbwp30p140";
-$cellname = "INVD1..."; // replace this with the full name of the library cell
+$cellname = "INVD1..."; # replace this with the full name of the library cell
 @corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
 printf("\nLibrary $libbase Cell $cellname\n");
 foreach my $corner (@corners) {
@@ -129,7 +139,7 @@ sub analyzeCell {
     my $delay = &computeDelay($cap);
     my $cornerr = sprintf("%20s", $corner);
     my $delayr = sprintf("%2.1f", $delay*1000);
-    my $leakager = sprintf("%3.1f", $leakage);
+    my $leakager = sprintf("%3.3f", $leakage);
     
     print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
     #print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");

bin/wally-tool-chain-install.sh

@@ -167,3 +167,7 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 sudo pip3 install testresources
 pip3 install git+https://github.com/riscv/riscof.git
 
+# Download OSU Skywater 130 cell library
+sudo mkdir -p $RISCV/cad/lib
+cd $RISCV/cad/lib
+sudo git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12

synthDC/Makefile

@@ -17,11 +17,9 @@ export TECH ?= sky90
 export MAXCORES ?= 1
 # MAXOPT turns on flattening, boundary optimization, and retiming
 # The output netlist is hard to interpret, but significantly better PPA
-# WRAPPER turns on wrapper generation
 export MAXOPT ?= 0
 export DRIVE ?= FLOP
 export USESRAM ?= 0
-export WRAPPER ?= 0
 
 
 time := $(shell date +%F-%H-%M)
@@ -120,11 +118,6 @@ ifeq ($(SAIFPOWER), 1)
 	cp -f ../sim/power.saif .
 endif
 
-
-mkwrapper:
-ifeq ($(WRAPPER),1)
-	python3 $(WALLY)/synthDC/scripts/wrapperGen.py $(DESIGN)
-endif
 mkdirecs:
 	@echo "DC Synthesis"
 	@mkdir -p $(OUTPUTDIR)
@@ -134,7 +127,7 @@ mkdirecs:
 	@mkdir -p $(OUTPUTDIR)/mapped
 	@mkdir -p $(OUTPUTDIR)/unmapped
 
-synth: mkwrapper mkdirecs configs rundc # clean
+synth: mkdirecs configs rundc # clean
 
 rundc:
 ifeq ($(TECH), tsmc28psyn)

synthDC/scripts/synth.tcl

@@ -24,18 +24,20 @@ set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
-set wrapper $::env(WRAPPER)
 
 eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
-#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
 eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
-if {$wrapper ==1 } {
+
+# Check if a wrapper is needed (when cvw_t parameters are used)
+set wrapper 0
+if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} {
+    set wrapper 1
+	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN)
     eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
 }
 
-
 # Only for FMA class project; comment out when done
 # eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
 

synthDC/scripts/wrapperGen.py

@@ -63,8 +63,8 @@ buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
 wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
 
 # clear wrappers directory 
-os.system(f"rm {os.getenv('WALLY')}/synthDC/wrappers/*")
+os.system(f"rm -f {os.getenv('WALLY')}/synthDC/wrappers/*")
-os.system(f"mkdir {os.getenv('WALLY')}/synthDC/wrappers")
+os.system(f"mkdir -p {os.getenv('WALLY')}/synthDC/wrappers")
 
 fout = open(wrapperPath, "w")
 
@@ -75,4 +75,4 @@ fout.close()
 
 
 
-print(buf)
+#print(buf)