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https://github.com/openhwgroup/cvw
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Install dtlb in dmem
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@ -48,13 +48,28 @@ module dmem (
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// faults
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// faults
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input logic DataAccessFaultM,
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input logic DataAccessFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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output logic StoreMisalignedFaultM, StoreAccessFaultM
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output logic StoreMisalignedFaultM, StoreAccessFaultM,
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// TLB management
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//input logic [`XLEN-1:0] PageTableEntryM,
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//input logic DTLBWriteM, DTLBFlushM,
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// *** satp value will come from CSRs
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// input logic [`XLEN-1:0] SATP,
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output logic DTLBMissM, DTLBHitM
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);
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);
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logic SquashSCM;
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logic SquashSCM;
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// Initially no MMU
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// Initially no MMU
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assign MemPAdrM = MemAdrM;
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// *** temporary hack until we can figure out how to get actual satp value
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// from priv unit -- Thomas F
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logic [`XLEN-1:0] SATP = '0;
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// *** temporary hack until walker is hooked up -- Thomas F
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logic [`XLEN-1:0] PageTableEntryM = '0;
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logic DTLBFlushM = '0;
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logic DTLBWriteM = '0;
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tlb #(3) dtlb(clk, reset, SATP, MemAdrM, PageTableEntryM, DTLBWriteM,
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DTLBFlushM, MemPAdrM, DTLBMissM, DTLBHitM);
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//assign MemPAdrM = MemAdrM;
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// Determine if an Unaligned access is taking place
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// Determine if an Unaligned access is taking place
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always_comb
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always_comb
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@ -52,7 +52,7 @@ module ifu (
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output logic IllegalIEUInstrFaultD,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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output logic InstrMisalignedFaultM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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// TLB Management
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// TLB management
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//input logic [`XLEN-1:0] PageTableEntryF,
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//input logic [`XLEN-1:0] PageTableEntryF,
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//input logic ITLBWriteF, ITLBFlushF,
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//input logic ITLBWriteF, ITLBFlushF,
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// *** satp value will come from CSRs
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// *** satp value will come from CSRs
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@ -89,6 +89,7 @@ module wallypipelinedhart (
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// memory management unit signals
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// memory management unit signals
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logic ITLBMissF, ITLBHitF;
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logic ITLBMissF, ITLBHitF;
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logic DTLBMissM, DTLBHitM;
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// bus interface to dmem
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// bus interface to dmem
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logic MemReadM, MemWriteM;
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logic MemReadM, MemWriteM;
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