diff --git a/.gitignore b/.gitignore
index 51dda9031..3a7513d12 100644
--- a/.gitignore
+++ b/.gitignore
@@ -213,9 +213,10 @@ sim/vcs/ucli.key
 sim/vcs/verdi_config_file
 sim/*/testbench.vcd 
 sim/questa/imperas.log
-sim/questa/regression.log
-sim/questa/regression_logs/*
-sim/questa/regression_ucdbs/*
+sim/questa/functcov.log
+sim/questa/functcov_logs/*
+sim/questa/functcov_ucdbs/*
+sim/questa/functcov
 sim/questa/riscv.ucdb
 sim/questa/riscv.ucdb.log
 sim/questa/riscv.ucdb.summary.log
@@ -233,3 +234,4 @@ examples/verilog/fulladder/verdi_config_file
 tests/functcov
 tests/functcov/*
 tests/functcov/*/*
+sim/vcs/simprofile*
diff --git a/Makefile b/Makefile
index 651933154..24d531917 100644
--- a/Makefile
+++ b/Makefile
@@ -5,25 +5,13 @@
 SIM = ${WALLY}/sim
 
 all:
-	make install
 	make riscof	
 	make testfloat
 #	make verify
-	make coverage
-	make benchmarks
-
-# install copies over the Makefile.include from riscv-isa-sim
-# And corrects the TARGETDIR path and the RISCV_PREFIX
-
-install:
-	# *** 1/15/23 dh: check if any of this is still needed
-	#cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-	#sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
-	#echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
-	##cd tests/linux-testgen/linux-testvectors; source ./tvLinker.sh # needs to be run in local directory
-	##rm tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
-	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
+#	make coverage
+#	make benchmarks
 
+# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
 riscof:
 	make -C sim
 
@@ -59,60 +47,66 @@ funcovreg:
 	iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
 	vcover report -details -html ${SIM}/questa/riscv.ucdb
 
+
+
 # test_name=riscv_arithmetic_basic_test
-rvdv: 
-	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile			>> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
-#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
-#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
-#	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
-	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/regression_logs/${test_name}.log 2>&1
-	cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression_ucdbs/${test_name}.ucdb
+riscvdv: 
+	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gen,gcc_compile			>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps gcc_compile	>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	python3 ${WALLY}/addins/riscv-dv/run.py --test ${test_name} --target rv64gc --output tests/riscvdv  --iterations 1 -si questa --iss spike --verbose --cov --seed 0 --steps iss_sim		>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+#	run-elf.bash --seed ${SIM}/questa/seed0.txt --verbose --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o													>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/riscv.ucdb --elf ${WALLY}/tests/riscvdv/asm_test/${test_name}_0.o								>> ${SIM}/questa/functcov_logs/${test_name}.log 2>&1
+	cp ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov_ucdbs/${test_name}.ucdb
 
-rvdv_regression:
-	mkdir -p ${SIM}/questa/regression_logs
-	mkdir -p ${SIM}/questa/regression_ucdbs
-	cd ${SIM}/questa/regression_logs && rm -rf *
-	cd ${SIM}/questa/regression_ucdbs && rm -rf *
-	make rvdv test_name=riscv_arithmetic_basic_test				>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_amo_test							>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_ebreak_debug_mode_test			>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_ebreak_test						>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_floating_point_arithmetic_test	>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_floating_point_mmu_stress_test	>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_floating_point_rand_test			>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_full_interrupt_test				>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_hint_instr_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_illegal_instr_test				>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_invalid_csr_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_jump_stress_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_loop_test							>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_machine_mode_rand_test			>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_mmu_stress_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_no_fence_test						>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_non_compressed_instr_test			>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_pmp_test							>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_privileged_mode_rand_test			>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_rand_instr_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_rand_jump_test					>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_sfence_exception_test				>> ${SIM}/questa/regression.log 2>&1
-	make rvdv test_name=riscv_unaligned_load_store_test			>> ${SIM}/questa/regression.log 2>&1
+riscvdv_functcov:
+	mkdir -p ${SIM}/questa/functcov_logs
+	mkdir -p ${SIM}/questa/functcov_ucdbs
+	cd ${SIM}/questa/functcov_logs && rm -rf *
+	cd ${SIM}/questa/functcov_ucdbs && rm -rf *
+	make riscvdv test_name=riscv_arithmetic_basic_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_amo_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_debug_mode_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_ebreak_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_arithmetic_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_mmu_stress_test	>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_floating_point_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_full_interrupt_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_hint_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_illegal_instr_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_invalid_csr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_jump_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_loop_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_machine_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_mmu_stress_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_no_fence_test						>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_non_compressed_instr_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_pmp_test							>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_privileged_mode_rand_test			>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_instr_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_rand_jump_test					>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_sfence_exception_test				>> ${SIM}/questa/functcov.log 2>&1
+	make riscvdv test_name=riscv_unaligned_load_store_test			>> ${SIM}/questa/functcov.log 2>&1
 
-rvdv_combine_coverage:
-	mkdir -p ${SIM}/questa/regcov
-	cd ${SIM}/questa/regcov && rm -rf *
-	vcover merge ${SIM}/questa/regcov/regcov.ucdb  ${SIM}/questa/regression_ucdbs/* -suppress 6854 -64
-	vcover report -details -html ${SIM}/questa/regcov/regcov.ucdb
-	vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg > ${SIM}/questa/regcov/regcov.ucdb.log
-	vcover report ${SIM}/questa/regcov/regcov.ucdb -testdetails -cvg > ${SIM}/questa/regcov/regcov.ucdb.testdetails.log
-	vcover report ${SIM}/questa/regcov/regcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/regcov/regcov.ucdb.summary.log
-	grep "Total Coverage By Instance" ${SIM}/questa/regcov/regcov.ucdb.log
+combine_functcov:
+	mkdir -p ${SIM}/questa/functcov
+	cd ${SIM}/questa/functcov && rm -rf *
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/add.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-add.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/and.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-and.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
+	run-elf-cov.bash --seed ${SIM}/questa/seed0.txt --verbose --coverdb ${SIM}/questa/functcov/ori.ucdb --elf ${WALLY}/tests/functcov/rv64/I/WALLY-COV-ori.elf								>> ${SIM}/questa/functcov_logs/add.log 2>&1
 
-remove_rvdv_artifacts:
-	rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/regression.log covhtmlreport/ ${SIM}/questa/regression_logs/ ${SIM}/questa/regression_ucdbs/ ${SIM}/questa/regcov/ -rf
+	vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov/*.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	# vcover merge ${SIM}/questa/functcov/functcov.ucdb ${SIM}/questa/functcov_ucdbs/* -suppress 6854 -64
+	vcover report -details -html ${SIM}/questa/functcov/functcov.ucdb
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg > ${SIM}/questa/functcov/functcov.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -testdetails -cvg > ${SIM}/questa/functcov/functcov.testdetails.log
+#	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg -below 100 | egrep "Coverpoint|Covergroup|Cross" | grep -v Metric > ${SIM}/questa/functcov/functcov.ucdb.summary.log
+	vcover report ${SIM}/questa/functcov/functcov.ucdb -details -cvg | egrep "Coverpoint|Covergroup|Cross|TYPE"  > ${SIM}/questa/functcov/functcov.summary.log
+	grep "Total Coverage By Instance" ${SIM}/questa/functcov/functcov.ucdb.log
 
-collect_riscvdv_regression_coverage: remove_rvdv_artifacts rvdv_regression rvdv_combine_coverage
-coverage:
-	regression-wally -coverage -fp
+remove_functcov_artifacts:
+	rm ${SIM}/questa/riscv.ucdb ${SIM}/questa/functcov.log covhtmlreport/ ${SIM}/questa/functcov_logs/ ${SIM}/questa/functcov_ucdbs/ ${SIM}/questa/functcov/ -rf
+
+collect_functcov: remove_functcov_artifacts riscvdv_functcov combine_functcov
 
 benchmarks:
 	make coremark
diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 78c31459e..3b08aea54 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -48,7 +48,7 @@ sudo apt update -y
 sudo apt upgrade -y
 sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev  gperf libtool patchutils bc mutt ssmtp
 # Other python libraries used through the book.
-sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown 
+sudo -H pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown pyyaml
 
 # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
 if ! command -v python &> /dev/null
diff --git a/testbench/testbench.sv b/testbench/testbench.sv
index 093522fc3..139261072 100644
--- a/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -320,7 +320,7 @@ module testbench;
   logic [P.XLEN-1:0] testadr;
   always_comb begin
   	begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
- 	end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
+ 	  end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
   	signature_size = end_signature_addr - begin_signature_addr;
   end
   logic EcallFaultM;
@@ -409,7 +409,8 @@ module testbench;
         if (!begin_signature_addr)
           $display("begin_signature addr not found in %s", ProgramLabelMapFile);
         else if (TEST != "embench") begin   // *** quick hack for embench.  need a better long term solution
-          CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+//          CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
+          CheckSignature(pathname, tests[test], riscofTest, ProgramAddrLabelArray["begin_signature"], errors);
           if(errors > 0) totalerrors = totalerrors + 1;
         end
       end
diff --git a/tests/fp/combined_IF_vectors/extract_arch_vectors.py b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
index e25a2c83e..d0fd3ab9c 100755
--- a/tests/fp/combined_IF_vectors/extract_arch_vectors.py
+++ b/tests/fp/combined_IF_vectors/extract_arch_vectors.py
@@ -194,7 +194,7 @@ def create_vectors(my_config):
                 # get answer from Ref...signature
                 # answers span two lines and are reversed
                 answer = src_file2.readline().strip()
-                print(f"Answer: {answer}")
+                # print(f"Answer: {answer}")
                 #print(answer1,answer2)
                 if not (answer == "6f5ca309"): # if there is still stuff to read
                     # parse through .S file
@@ -239,9 +239,9 @@ def create_vectors(my_config):
             while reading:
                 # get answer and flags from Ref...signature
                 answer = src_file2.readline()
-                print(answer)
+                #print(answer)
                 packed = src_file2.readline()[6:]
-                print("Packed: ", packed)
+                #print("Packed: ", packed)
                 if len(packed.strip())>0: # if there is still stuff to read
                     # print("packed")
                     # parse through .S file
diff --git a/tests/testgen/covergen.py b/tests/testgen/covergen.py
index d2170e476..44a0eea4c 100755
--- a/tests/testgen/covergen.py
+++ b/tests/testgen/covergen.py
@@ -33,6 +33,10 @@ def signedImm12(imm):
 
 def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen):
   lines = "\n# Testcase " + str(desc) + "\n"
+  if (rs1val < 0):
+    rs1val = rs1val + 2**xlen
+  if (rs2val < 0):
+    rs2val = rs2val + 2**xlen
   lines = lines + "li x" + str(rd) + ", " + formatstr.format(rdval) + " # initialize rd to a random value that should get changed\n"
   if (test in rtype):
     lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1 to a random value \n"
@@ -52,6 +56,10 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, stor
 def randomize():
     rs1 = randint(1, 31)
     rs2 = randint(1, 31)
+    # choose rd that is different than rs1 and rs2
+    rd = rs1
+    while (rd == rs1 or rd == rs2):
+      rd = randint(1, 31)
     rd = randint(1, 31)
     rs1val = randint(0, 2**xlen-1)
     rs2val = randint(0, 2**xlen-1)
@@ -80,25 +88,25 @@ def make_rs2(test, storecmd, xlen):
 def make_rd_rs1(test, storecmd, xlen):
   for r in range(32):
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    desc = "cp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")"
+    desc = "cmp_rd_rs1 (Test rd = rs1 = x" + str(r) + ")"
     writeCovVector(desc, r, rs2, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
 def make_rd_rs2(test, storecmd, xlen):
   for r in range(32):
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    desc = "cp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")"
+    desc = "cmp_rd_rs2 (Test rd = rs1 = x" + str(r) + ")"
     writeCovVector(desc, rs1, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
 def make_rd_rs1_rs2(test, storecmd, xlen):
   for r in range(32):
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    desc = "cp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")"
+    desc = "cmp_rd_rs1_rs2 (Test rd = rs1 = rs2 = x" + str(r) + ")"
     writeCovVector(desc, r, r, r, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
 def make_rs1_rs2(test, storecmd, xlen):
   for r in range(32):
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    desc = "cp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
+    desc = "cmp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
     writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
 def make_rs1_maxvals(test, storecmd, xlen):
@@ -140,14 +148,14 @@ def make_rs1_rs2_eqval(test, storecmd, xlen):
 def make_rs1_sign(test, storecmd, xlen):
    for v in [1, -1]:
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    rs1val = abs(rs1val) * v;
+    rs1val = abs(rs1val % 2**(xlen-1)) * v;
     desc = "cp_rs1_sign (Test source rs1 value = " + hex(rs1val) + ")"
     writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
 def make_rs2_sign(test, storecmd, xlen):
   for v in [1, -1]:
     [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-    rs2val = abs(rs2val) * v;
+    rs2val = abs(rs2val % 2**(xlen-1)) * v;
     desc = "cp_rs2_sign (Test source rs2 value = " + hex(rs2val) + ")"
     writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
@@ -155,8 +163,8 @@ def make_cr_rs1_rs2_sign(test, storecmd, xlen):
   for v1 in [1, -1]:
     for v2 in [1, -1]:
       [rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
-      rs1val = abs(rs1val) * v1;
-      rs2val = abs(rs2val) * v2;
+      rs1val = abs(rs1val % 2**(xlen-1)) * v1;
+      rs2val = abs(rs2val % 2**(xlen-1)) * v2;
       desc = "cr_rs1_rs2 (Test source rs1 = " + hex(rs1val) + " rs2 = " + hex(rs2val) + ")"
       writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, storecmd, xlen)
 
@@ -211,7 +219,7 @@ def write_tests(coverpoints, test, storecmd, xlen):
     elif (coverpoint == "cp_gpr_hazard"):
       pass # not yet implemented
     else:
-      print("Error: " + coverpoint + " not implemented yet for " + test)
+      print("Warning: " + coverpoint + " not implemented yet for " + test)
       
 def getcovergroups(coverdefdir, coverfiles):
   coverpoints = {}
diff --git a/tests/testgen/covergen_footer.S b/tests/testgen/covergen_footer.S
index 597a00f2a..2e4abbbfc 100644
--- a/tests/testgen/covergen_footer.S
+++ b/tests/testgen/covergen_footer.S
@@ -1,2 +1,5 @@
 
+self_loop:
+    j self_loop
+
 .end
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
deleted file mode 100644
index 26b2f501c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.914370//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
-
-# Testcase 0:  rs1:x20(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x3(0x0000000000000000)
-li x20, MASK_XLEN(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-ADD x3, x20, x22
-sd x3, 0(x6)
-
-# Testcase 1:  rs1:x1(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x21(0x0000000000000001)
-li x1, MASK_XLEN(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-ADD x21, x1, x4
-sd x21, 8(x6)
-
-# Testcase 2:  rs1:x7(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x27(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-li x20, MASK_XLEN(0xffffffffffffffff)
-ADD x27, x7, x20
-sd x27, 16(x6)
-
-# Testcase 3:  rs1:x19(0x0000000000000001), rs2:x4(0x0000000000000000), result rd:x13(0x0000000000000001)
-li x19, MASK_XLEN(0x0000000000000001)
-li x4, MASK_XLEN(0x0000000000000000)
-ADD x13, x19, x4
-sd x13, 24(x6)
-
-# Testcase 4:  rs1:x3(0x0000000000000001), rs2:x12(0x0000000000000001), result rd:x27(0x0000000000000002)
-li x3, MASK_XLEN(0x0000000000000001)
-li x12, MASK_XLEN(0x0000000000000001)
-ADD x27, x3, x12
-sd x27, 32(x6)
-
-# Testcase 5:  rs1:x4(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0xffffffffffffffff)
-ADD x20, x4, x2
-sd x20, 40(x6)
-
-# Testcase 6:  rs1:x1(0xffffffffffffffff), rs2:x7(0x0000000000000000), result rd:x31(0xffffffffffffffff)
-li x1, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-ADD x31, x1, x7
-sd x31, 48(x6)
-
-# Testcase 7:  rs1:x16(0xffffffffffffffff), rs2:x7(0x0000000000000001), result rd:x24(0x0000000000000000)
-li x16, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000001)
-ADD x24, x16, x7
-sd x24, 56(x6)
-
-# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x2(0xffffffffffffffff), result rd:x30(0xfffffffffffffffe)
-li x26, MASK_XLEN(0xffffffffffffffff)
-li x2, MASK_XLEN(0xffffffffffffffff)
-ADD x30, x26, x2
-sd x30, 64(x6)
-
-# Testcase 9:  rs1:x20(0x05d51433ade9b2b4), rs2:x4(0x6cf55b158b53031d), result rd:x27(0x72ca6f49393cb5d1)
-li x20, MASK_XLEN(0x05d51433ade9b2b4)
-li x4, MASK_XLEN(0x6cf55b158b53031d)
-ADD x27, x20, x4
-sd x27, 72(x6)
-
-# Testcase 10:  rs1:x21(0x11ebcd49428a1c22), rs2:x10(0x126cbc8f38884479), result rd:x12(0x245889d87b12609b)
-li x21, MASK_XLEN(0x11ebcd49428a1c22)
-li x10, MASK_XLEN(0x126cbc8f38884479)
-ADD x12, x21, x10
-sd x12, 80(x6)
-
-# Testcase 11:  rs1:x15(0x2e2950656fa231e9), rs2:x2(0x80ee526e0fa07a3f), result rd:x20(0xaf17a2d37f42ac28)
-li x15, MASK_XLEN(0x2e2950656fa231e9)
-li x2, MASK_XLEN(0x80ee526e0fa07a3f)
-ADD x20, x15, x2
-sd x20, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
deleted file mode 100644
index 8dd500f83..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.916813//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt)
-
-# Testcase 0:  rs1:x18(0x0000000000000000), rs2:x9(0x0000000000000000), result rd:x5(0x0000000000000000)
-li x18, MASK_XLEN(0x0000000000000000)
-li x9, MASK_XLEN(0x0000000000000000)
-SLT x5, x18, x9
-sd x5, 0(x6)
-
-# Testcase 1:  rs1:x8(0x0000000000000000), rs2:x25(0x0000000000000001), result rd:x31(0x0000000000000001)
-li x8, MASK_XLEN(0x0000000000000000)
-li x25, MASK_XLEN(0x0000000000000001)
-SLT x31, x8, x25
-sd x31, 8(x6)
-
-# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x12(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x16, MASK_XLEN(0x0000000000000000)
-li x12, MASK_XLEN(0xffffffffffffffff)
-SLT x20, x16, x12
-sd x20, 16(x6)
-
-# Testcase 3:  rs1:x10(0x0000000000000001), rs2:x22(0x0000000000000000), result rd:x12(0x0000000000000000)
-li x10, MASK_XLEN(0x0000000000000001)
-li x22, MASK_XLEN(0x0000000000000000)
-SLT x12, x10, x22
-sd x12, 24(x6)
-
-# Testcase 4:  rs1:x19(0x0000000000000001), rs2:x31(0x0000000000000001), result rd:x29(0x0000000000000000)
-li x19, MASK_XLEN(0x0000000000000001)
-li x31, MASK_XLEN(0x0000000000000001)
-SLT x29, x19, x31
-sd x29, 32(x6)
-
-# Testcase 5:  rs1:x21(0x0000000000000001), rs2:x28(0xffffffffffffffff), result rd:x20(0x0000000000000000)
-li x21, MASK_XLEN(0x0000000000000001)
-li x28, MASK_XLEN(0xffffffffffffffff)
-SLT x20, x21, x28
-sd x20, 40(x6)
-
-# Testcase 6:  rs1:x5(0xffffffffffffffff), rs2:x23(0x0000000000000000), result rd:x10(0x0000000000000001)
-li x5, MASK_XLEN(0xffffffffffffffff)
-li x23, MASK_XLEN(0x0000000000000000)
-SLT x10, x5, x23
-sd x10, 48(x6)
-
-# Testcase 7:  rs1:x13(0xffffffffffffffff), rs2:x24(0x0000000000000001), result rd:x14(0x0000000000000001)
-li x13, MASK_XLEN(0xffffffffffffffff)
-li x24, MASK_XLEN(0x0000000000000001)
-SLT x14, x13, x24
-sd x14, 56(x6)
-
-# Testcase 8:  rs1:x27(0xffffffffffffffff), rs2:x21(0xffffffffffffffff), result rd:x3(0x0000000000000000)
-li x27, MASK_XLEN(0xffffffffffffffff)
-li x21, MASK_XLEN(0xffffffffffffffff)
-SLT x3, x27, x21
-sd x3, 64(x6)
-
-# Testcase 9:  rs1:x8(0x983631890063e42f), rs2:x21(0xb2d650af313b32b7), result rd:x15(0x0000000000000001)
-li x8, MASK_XLEN(0x983631890063e42f)
-li x21, MASK_XLEN(0xb2d650af313b32b7)
-SLT x15, x8, x21
-sd x15, 72(x6)
-
-# Testcase 10:  rs1:x19(0xb5d97ef760ef1471), rs2:x28(0xac7c8803e01bbf50), result rd:x14(0x0000000000000000)
-li x19, MASK_XLEN(0xb5d97ef760ef1471)
-li x28, MASK_XLEN(0xac7c8803e01bbf50)
-SLT x14, x19, x28
-sd x14, 80(x6)
-
-# Testcase 11:  rs1:x19(0x66faf98908135d58), rs2:x14(0xb3ab1b2cdf26f517), result rd:x25(0x0000000000000000)
-li x19, MASK_XLEN(0x66faf98908135d58)
-li x14, MASK_XLEN(0xb3ab1b2cdf26f517)
-SLT x25, x19, x14
-sd x25, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
deleted file mode 100644
index 0aec30e56..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.917963//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu)
-
-# Testcase 0:  rs1:x22(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x2(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-li x23, MASK_XLEN(0x0000000000000000)
-SLTU x2, x22, x23
-sd x2, 0(x6)
-
-# Testcase 1:  rs1:x15(0x0000000000000000), rs2:x17(0x0000000000000001), result rd:x29(0x0000000000000001)
-li x15, MASK_XLEN(0x0000000000000000)
-li x17, MASK_XLEN(0x0000000000000001)
-SLTU x29, x15, x17
-sd x29, 8(x6)
-
-# Testcase 2:  rs1:x16(0x0000000000000000), rs2:x30(0xffffffffffffffff), result rd:x18(0x0000000000000001)
-li x16, MASK_XLEN(0x0000000000000000)
-li x30, MASK_XLEN(0xffffffffffffffff)
-SLTU x18, x16, x30
-sd x18, 16(x6)
-
-# Testcase 3:  rs1:x20(0x0000000000000001), rs2:x25(0x0000000000000000), result rd:x1(0x0000000000000000)
-li x20, MASK_XLEN(0x0000000000000001)
-li x25, MASK_XLEN(0x0000000000000000)
-SLTU x1, x20, x25
-sd x1, 24(x6)
-
-# Testcase 4:  rs1:x29(0x0000000000000001), rs2:x2(0x0000000000000001), result rd:x16(0x0000000000000000)
-li x29, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0x0000000000000001)
-SLTU x16, x29, x2
-sd x16, 32(x6)
-
-# Testcase 5:  rs1:x11(0x0000000000000001), rs2:x10(0xffffffffffffffff), result rd:x27(0x0000000000000001)
-li x11, MASK_XLEN(0x0000000000000001)
-li x10, MASK_XLEN(0xffffffffffffffff)
-SLTU x27, x11, x10
-sd x27, 40(x6)
-
-# Testcase 6:  rs1:x15(0xffffffffffffffff), rs2:x2(0x0000000000000000), result rd:x26(0x0000000000000000)
-li x15, MASK_XLEN(0xffffffffffffffff)
-li x2, MASK_XLEN(0x0000000000000000)
-SLTU x26, x15, x2
-sd x26, 48(x6)
-
-# Testcase 7:  rs1:x27(0xffffffffffffffff), rs2:x29(0x0000000000000001), result rd:x26(0x0000000000000000)
-li x27, MASK_XLEN(0xffffffffffffffff)
-li x29, MASK_XLEN(0x0000000000000001)
-SLTU x26, x27, x29
-sd x26, 56(x6)
-
-# Testcase 8:  rs1:x14(0xffffffffffffffff), rs2:x7(0xffffffffffffffff), result rd:x18(0x0000000000000000)
-li x14, MASK_XLEN(0xffffffffffffffff)
-li x7, MASK_XLEN(0xffffffffffffffff)
-SLTU x18, x14, x7
-sd x18, 64(x6)
-
-# Testcase 9:  rs1:x3(0xf689a4a5ffda0336), rs2:x27(0xfa83ada4a2121ac5), result rd:x24(0x0000000000000001)
-li x3, MASK_XLEN(0xf689a4a5ffda0336)
-li x27, MASK_XLEN(0xfa83ada4a2121ac5)
-SLTU x24, x3, x27
-sd x24, 72(x6)
-
-# Testcase 10:  rs1:x31(0xfca055362169df82), rs2:x22(0x66dd779403c54c71), result rd:x14(0x0000000000000000)
-li x31, MASK_XLEN(0xfca055362169df82)
-li x22, MASK_XLEN(0x66dd779403c54c71)
-SLTU x14, x31, x22
-sd x14, 80(x6)
-
-# Testcase 11:  rs1:x23(0x00de59f550f0fc2b), rs2:x25(0x03a8987936a98d74), result rd:x1(0x0000000000000001)
-li x23, MASK_XLEN(0x00de59f550f0fc2b)
-li x25, MASK_XLEN(0x03a8987936a98d74)
-SLTU x1, x23, x25
-sd x1, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
deleted file mode 100644
index 1157c194c..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.915580//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub)
-
-# Testcase 0:  rs1:x4(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x13(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000000)
-li x23, MASK_XLEN(0x0000000000000000)
-SUB x13, x4, x23
-sd x13, 0(x6)
-
-# Testcase 1:  rs1:x7(0x0000000000000000), rs2:x9(0x0000000000000001), result rd:x12(0xffffffffffffffff)
-li x7, MASK_XLEN(0x0000000000000000)
-li x9, MASK_XLEN(0x0000000000000001)
-SUB x12, x7, x9
-sd x12, 8(x6)
-
-# Testcase 2:  rs1:x29(0x0000000000000000), rs2:x24(0xffffffffffffffff), result rd:x16(0x0000000000000001)
-li x29, MASK_XLEN(0x0000000000000000)
-li x24, MASK_XLEN(0xffffffffffffffff)
-SUB x16, x29, x24
-sd x16, 16(x6)
-
-# Testcase 3:  rs1:x27(0x0000000000000001), rs2:x29(0x0000000000000000), result rd:x30(0x0000000000000001)
-li x27, MASK_XLEN(0x0000000000000001)
-li x29, MASK_XLEN(0x0000000000000000)
-SUB x30, x27, x29
-sd x30, 24(x6)
-
-# Testcase 4:  rs1:x22(0x0000000000000001), rs2:x7(0x0000000000000001), result rd:x31(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000001)
-li x7, MASK_XLEN(0x0000000000000001)
-SUB x31, x22, x7
-sd x31, 32(x6)
-
-# Testcase 5:  rs1:x25(0x0000000000000001), rs2:x2(0xffffffffffffffff), result rd:x26(0x0000000000000002)
-li x25, MASK_XLEN(0x0000000000000001)
-li x2, MASK_XLEN(0xffffffffffffffff)
-SUB x26, x25, x2
-sd x26, 40(x6)
-
-# Testcase 6:  rs1:x9(0xffffffffffffffff), rs2:x4(0x0000000000000000), result rd:x20(0xffffffffffffffff)
-li x9, MASK_XLEN(0xffffffffffffffff)
-li x4, MASK_XLEN(0x0000000000000000)
-SUB x20, x9, x4
-sd x20, 48(x6)
-
-# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x22(0xfffffffffffffffe)
-li x30, MASK_XLEN(0xffffffffffffffff)
-li x15, MASK_XLEN(0x0000000000000001)
-SUB x22, x30, x15
-sd x22, 56(x6)
-
-# Testcase 8:  rs1:x22(0xffffffffffffffff), rs2:x14(0xffffffffffffffff), result rd:x29(0x0000000000000000)
-li x22, MASK_XLEN(0xffffffffffffffff)
-li x14, MASK_XLEN(0xffffffffffffffff)
-SUB x29, x22, x14
-sd x29, 64(x6)
-
-# Testcase 9:  rs1:x10(0xdff3334b91b15f5d), rs2:x21(0xeae2025e82339e23), result rd:x12(0xf51130ed0f7dc13a)
-li x10, MASK_XLEN(0xdff3334b91b15f5d)
-li x21, MASK_XLEN(0xeae2025e82339e23)
-SUB x12, x10, x21
-sd x12, 72(x6)
-
-# Testcase 10:  rs1:x5(0xd670f668637e0edc), rs2:x18(0x403d1f83a859890c), result rd:x23(0x9633d6e4bb2485d0)
-li x5, MASK_XLEN(0xd670f668637e0edc)
-li x18, MASK_XLEN(0x403d1f83a859890c)
-SUB x23, x5, x18
-sd x23, 80(x6)
-
-# Testcase 11:  rs1:x11(0x753c7c99032f06ca), rs2:x24(0x143e2e04bdd7d19b), result rd:x2(0x60fe4e944557352f)
-li x11, MASK_XLEN(0x753c7c99032f06ca)
-li x24, MASK_XLEN(0x143e2e04bdd7d19b)
-SUB x2, x11, x24
-sd x2, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S
-// David_Harris@hmc.edu & Katherine Parry
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
deleted file mode 100644
index 949672e42..000000000
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
+++ /dev/null
@@ -1,142 +0,0 @@
-///////////////////////////////////////////
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
-// David_Harris@hmc.edu & Katherine Parry
-// Created 2022-06-17 22:58:09.919138//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-#include "model_test.h"
-#include "arch_test.h"
-RVTEST_ISA("RV64I")
-
-.section .text.init
-.globl rvtest_entry_point
-rvtest_entry_point:
-RVMODEL_BOOT
-RVTEST_CODE_BEGIN
-
-RVTEST_SIGBASE( x6, wally_signature)
-
-RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor)
-
-# Testcase 0:  rs1:x27(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x17(0x0000000000000000)
-li x27, MASK_XLEN(0x0000000000000000)
-li x22, MASK_XLEN(0x0000000000000000)
-XOR x17, x27, x22
-sd x17, 0(x6)
-
-# Testcase 1:  rs1:x20(0x0000000000000000), rs2:x4(0x0000000000000001), result rd:x7(0x0000000000000001)
-li x20, MASK_XLEN(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-XOR x7, x20, x4
-sd x7, 8(x6)
-
-# Testcase 2:  rs1:x4(0x0000000000000000), rs2:x20(0xffffffffffffffff), result rd:x21(0xffffffffffffffff)
-li x4, MASK_XLEN(0x0000000000000000)
-li x20, MASK_XLEN(0xffffffffffffffff)
-XOR x21, x4, x20
-sd x21, 16(x6)
-
-# Testcase 3:  rs1:x7(0x0000000000000001), rs2:x28(0x0000000000000000), result rd:x10(0x0000000000000001)
-li x7, MASK_XLEN(0x0000000000000001)
-li x28, MASK_XLEN(0x0000000000000000)
-XOR x10, x7, x28
-sd x10, 24(x6)
-
-# Testcase 4:  rs1:x4(0x0000000000000001), rs2:x16(0x0000000000000001), result rd:x28(0x0000000000000000)
-li x4, MASK_XLEN(0x0000000000000001)
-li x16, MASK_XLEN(0x0000000000000001)
-XOR x28, x4, x16
-sd x28, 32(x6)
-
-# Testcase 5:  rs1:x30(0x0000000000000001), rs2:x13(0xffffffffffffffff), result rd:x21(0xfffffffffffffffe)
-li x30, MASK_XLEN(0x0000000000000001)
-li x13, MASK_XLEN(0xffffffffffffffff)
-XOR x21, x30, x13
-sd x21, 40(x6)
-
-# Testcase 6:  rs1:x3(0xffffffffffffffff), rs2:x1(0x0000000000000000), result rd:x9(0xffffffffffffffff)
-li x3, MASK_XLEN(0xffffffffffffffff)
-li x1, MASK_XLEN(0x0000000000000000)
-XOR x9, x3, x1
-sd x9, 48(x6)
-
-# Testcase 7:  rs1:x30(0xffffffffffffffff), rs2:x15(0x0000000000000001), result rd:x26(0xfffffffffffffffe)
-li x30, MASK_XLEN(0xffffffffffffffff)
-li x15, MASK_XLEN(0x0000000000000001)
-XOR x26, x30, x15
-sd x26, 56(x6)
-
-# Testcase 8:  rs1:x26(0xffffffffffffffff), rs2:x4(0xffffffffffffffff), result rd:x28(0x0000000000000000)
-li x26, MASK_XLEN(0xffffffffffffffff)
-li x4, MASK_XLEN(0xffffffffffffffff)
-XOR x28, x26, x4
-sd x28, 64(x6)
-
-# Testcase 9:  rs1:x27(0x2227d96d41a93f90), rs2:x21(0x8557716aa7502a81), result rd:x21(0xa770a807e6f91511)
-li x27, MASK_XLEN(0x2227d96d41a93f90)
-li x21, MASK_XLEN(0x8557716aa7502a81)
-XOR x21, x27, x21
-sd x21, 72(x6)
-
-# Testcase 10:  rs1:x9(0x1d77ce4058d87776), rs2:x28(0x27896389df3277fd), result rd:x1(0x3afeadc987ea008b)
-li x9, MASK_XLEN(0x1d77ce4058d87776)
-li x28, MASK_XLEN(0x27896389df3277fd)
-XOR x1, x9, x28
-sd x1, 80(x6)
-
-# Testcase 11:  rs1:x9(0x0a68e88e0ad40415), rs2:x18(0xae55cdff34ab18fd), result rd:x11(0xa43d25713e7f1ce8)
-li x9, MASK_XLEN(0x0a68e88e0ad40415)
-li x18, MASK_XLEN(0xae55cdff34ab18fd)
-XOR x11, x9, x18
-sd x11, 88(x6)
-
-.EQU NUMTESTS,12
-
-RVTEST_CODE_END
-RVMODEL_HALT
-
-RVTEST_DATA_BEGIN
-.align 4
-rvtest_data:
-.word 0x98765432
-RVTEST_DATA_END
-
-RVMODEL_DATA_BEGIN
-
-
-wally_signature:
-    .fill NUMTESTS*(XLEN/32),4,0xdeadbeef
-
-#ifdef rvtest_mtrap_routine
-
-mtrap_sigptr:
-    .fill 64*(XLEN/32),4,0xdeadbeef
-
-#endif
-
-#ifdef rvtest_gpr_save
-
-gpr_save:
-    .fill 32*(XLEN/32),4,0xdeadbeef
-
-#endif
-sig_end_canary:
-.int 0x0
-rvtest_sig_end:
-
-RVMODEL_DATA_END
-// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S
-// David_Harris@hmc.edu & Katherine Parry