From 842f51dfebfb998bef8f6e8c61fd5bf66e115e26 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sun, 11 Jun 2023 15:14:02 -0500 Subject: [PATCH 1/2] Add notes for FP SoftFloat/TestFloat build as may be vague for some --- sim/FPbuild.txt | 60 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 sim/FPbuild.txt diff --git a/sim/FPbuild.txt b/sim/FPbuild.txt new file mode 100644 index 000000000..edb4a645c --- /dev/null +++ b/sim/FPbuild.txt @@ -0,0 +1,60 @@ +Procedure for Runnning SoftFloat/TestFloat with Wally + +1.) First, compile SoftFloat and TestFloat by going to the addins +directory and finding the specific build directory (e.g., +Linux_x86_64-GCC. Currently, we are using v3e of +SoftFloat/TestFloat. I am not sure of the order, but I always compile +SoftFloat first as I believe TestFloat uses the static library +SoftFloat creates. + +2.) Once compiled both, go to the tests/fp directory and run the +create_vectors.sh Linux script. In the past, we have automated this, +but I believe this has fallen into more of a manual state lately. + +3.) Then, run remove_spaces.sh which will remove spaces from the +output and put underscores between vectors (this helps differentiate +the vectors that are generated). Again, this can be combined with +Step 2. + +4.) TestFloat is run from wally/cvw/sim and sim-testfloat-batch with +its respective test. The format is ./sim-testfloat-add add. All of +the tests are listed below. This can be augmented or added to for +other FP tests given by the great SoftFloat/TestFloat output. + + cvtint - test integer conversion unit (fcvtint) + cvtfp - test floating-point conversion unit (fcvtfp) + cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + add - test addition + fma - test fma + mul - test mult with fma + sub - test subtraction + div - test division + sqrt - test square root + all - test everything + +4a.) Each test will test all its vectors - if you want to test a +subset of the vectors (e.g., only binary16), you should modify the +cvw/testbench/tests-fp.h and comment out the tests you do not want to +test. The best way to do this is to comment out each item out with +the // comment option in SV. For example, + +string f128div[] = '{ +// "f128_div_rne.tv", +// "f128_div_rz.tv", +// "f128_div_ru.tv", +// "f128_div_rd.tv", +// "f128_div_rnm.tv" +}; + + + + + + + + + + + + + From 67d21ae3a6662c7f70a00c5849e2956c73a9410f Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Sun, 11 Jun 2023 15:15:47 -0500 Subject: [PATCH 2/2] Update testbench-fp thanks to Kevin's help - also fixed add which was broken due to config --- testbench/testbench-fp.sv | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/testbench/testbench-fp.sv b/testbench/testbench-fp.sv index aaf280626..63660b025 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench-fp.sv @@ -113,8 +113,6 @@ module testbenchfp; `include "parameter-defs.vh" - - /////////////////////////////////////////////////////////////////////////////////////////////// // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| @@ -680,11 +678,11 @@ module testbenchfp; // instantiate devices under test if (TEST === "fma"| TEST === "mul" | TEST === "add" | TEST === "sub" | TEST === "all") begin : fma fma #(P) fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), - .Xe(Xe), .Ye(Ye), .Ze(Ze), - .Xm(Xm), .Ym(Ym), .Zm(Zm), - .XZero, .YZero, .ZZero, .Ss, .Se, - .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps, - .ASticky); + .Xe(Xe), .Ye(Ye), .Ze(Ze), + .Xm(Xm), .Ym(Ym), .Zm(Zm), + .XZero, .YZero, .ZZero, .Ss, .Se, + .OpCtrl(OpCtrlVal), .Sm, .InvA, .SCnt, .As, .Ps, + .ASticky); end postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), @@ -699,13 +697,13 @@ module testbenchfp; .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt - fcvt #(P) fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), + fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), .XZero(XZero), .OpCtrl(OpCtrlVal), .IntZero, .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResSubnormUf(CvtResSubnormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); end if (TEST === "cmp" | TEST === "all") begin: fcmp - fcmp #(P) fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); end @@ -892,13 +890,13 @@ always @(negedge clk) begin // check if result is correct // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((FDivBusyE===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin - ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); - FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); - divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; + assign ResMatch = (Res === Ans | NaNGood | NaNGood === 1'bx); + assign FlagMatch = (ResFlg === AnsFlg | AnsFlg === 5'bx); + assign divsqrtop = OpCtrlVal == `SQRT_OPCTRL | OpCtrlVal == `DIV_OPCTRL; assign DivDone = OldFDivBusyE & ~FDivBusyE; //assign divsqrtop = OpCtrl[TestNum] == `SQRT_OPCTRL | OpCtrl[TestNum] == `DIV_OPCTRL; - CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); + assign CheckNow = (DivDone | ~divsqrtop) & (UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT); if(~(ResMatch & FlagMatch) & CheckNow) begin // if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&(DivDone | (TEST != "sqrt" & TEST != "div"))&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin errors += 1; @@ -974,10 +972,10 @@ module readvectors ( output logic [`FLEN-1:0] Ans, output logic [`XLEN-1:0] SrcA, output logic [4:0] AnsFlg, - output logic Xs, Ys, Zs, // sign bits of XYZ - output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) - output logic XNaN, YNaN, ZNaN, // is XYZ a NaN + output logic Xs, Ys, Zs, // sign bits of XYZ + output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) + output logic XNaN, YNaN, ZNaN, // is XYZ a NaN output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN output logic XSubnorm, ZSubnorm, // is XYZ denormalized output logic XZero, YZero, ZZero, // is XYZ zero @@ -986,6 +984,7 @@ module readvectors ( output logic DivStart, output logic [`FLEN-1:0] X, Y, Z, XPostBox ); + logic XEn, YEn, ZEn; `include "parameter-defs.vh" @@ -1346,7 +1345,6 @@ module readvectors ( assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); assign ZEn = (Unit == `FMAUNIT); - unpack #(P) unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,