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fix many linting errors

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Matthew 2024-06-25 13:55:27 -05:00
parent bf4bdd46af
commit 8bd674ba17
17 changed files with 143 additions and 109 deletions
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28
src/debug/dm.sv
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@ -68,13 +68,14 @@ module dm import cvw::*; #(parameter cvw_t P) (
output logic DebugRegUpdate, // writes values from scan register after scanning in output logic DebugRegUpdate, // writes values from scan register after scanning in
// Program Buffer // Program Buffer
output logic [3:0] ProgBufAddr, output logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr,
output logic ProgBuffScanEn, output logic ProgBuffScanEn,
output logic ExecProgBuf output logic ExecProgBuf
); );
`include "debug.vh" `include "debug.vh"
localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4; localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
localparam DATA_COUNT = (P.LLEN/32);
// DMI Signals // DMI Signals
logic ReqReady; logic ReqReady;
@ -166,11 +167,11 @@ module dm import cvw::*; #(parameter cvw_t P) (
const logic ConfStrPtrValid = 0; // Used with SysBusAccess const logic ConfStrPtrValid = 0; // Used with SysBusAccess
const logic [3:0] Version = 3; // DM Version const logic [3:0] Version = 3; // DM Version
// AbstractCS // AbstractCS
const logic [4:0] ProgBufSize = PROGBUF_SIZE; const logic [4:0] ProgBufSize = PROGBUF_SIZE[4:0];
logic Busy; logic Busy;
const logic RelaxedPriv = 1; const logic RelaxedPriv = 1;
logic [2:0] CmdErr; logic [2:0] CmdErr;
const logic [3:0] DataCount = (P.LLEN/32); const logic [3:0] DataCount = DATA_COUNT[3:0];
// Core control signals // Core control signals
assign AllHaveReset = HaveReset; assign AllHaveReset = HaveReset;
@ -204,7 +205,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
State <= INACTIVE; State <= INACTIVE;
end else begin end else begin
case (State) case (State)
INACTIVE : begin default : begin // INACTIVE
// Reset Values // Reset Values
{HaltReq, ResumeReq, AckHaveReset, HaltOnReset, NdmReset} <= 0; {HaltReq, ResumeReq, AckHaveReset, HaltOnReset, NdmReset} <= 0;
RspData <= 0; RspData <= 0;
@ -246,9 +247,9 @@ module dm import cvw::*; #(parameter cvw_t P) (
{`OP_READ,`SBCS} : State <= R_SYSBUSCS; {`OP_READ,`SBCS} : State <= R_SYSBUSCS;
[{`OP_WRITE,`PROGBUF0}:{`OP_WRITE,`PROGBUF3}] : State <= W_PROGBUF; // TODO: update decode range dynamically using PROGBUF_RANGE [{`OP_WRITE,`PROGBUF0}:{`OP_WRITE,`PROGBUF3}] : State <= W_PROGBUF; // TODO: update decode range dynamically using PROGBUF_RANGE
[{`OP_READ,`PROGBUF0}:{`OP_READ,`PROGBUFF}], [{`OP_READ,`PROGBUF0}:{`OP_READ,`PROGBUFF}],
{2'bx,`HARTINFO}, {2'b??,`HARTINFO},
{2'bx,`ABSTRACTAUTO}, {2'b??,`ABSTRACTAUTO},
{2'bx,`NEXTDM} : State <= READ_ZERO; {2'b??,`NEXTDM} : State <= READ_ZERO;
default : State <= INVALID; default : State <= INVALID;
endcase endcase
end end
@ -261,6 +262,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
`DATA1 : RspData <= Data1; `DATA1 : RspData <= Data1;
`DATA2 : RspData <= Data2; `DATA2 : RspData <= Data2;
`DATA3 : RspData <= Data3; `DATA3 : RspData <= Data3;
default : RspData <= 32'b0;
endcase endcase
RspOP <= `OP_SUCCESS; RspOP <= `OP_SUCCESS;
State <= ACK; State <= ACK;
@ -346,7 +348,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
`ACCESS_REGISTER : begin `ACCESS_REGISTER : begin
if (~ReqData[`TRANSFER]) if (~ReqData[`TRANSFER])
State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK; // If not transfer, exec progbuf or do nothing State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK; // If not transfer, exec progbuf or do nothing
else if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)) else if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)[2:0])
CmdErr <= `CMDERR_BUS; // If AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing CmdErr <= `CMDERR_BUS; // If AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing
else if (InvalidRegNo) else if (InvalidRegNo)
CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing
@ -422,7 +424,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
AC_SCAN : begin AC_SCAN : begin
if (~MiscRegNo & AcWrite & (Cycle == ScanChainLen)) // Writes to CSR/GPR/FPR are shifted in len(CSR/GPR) or len(FPR) cycles if (~MiscRegNo & AcWrite & (Cycle == ScanChainLen)) // Writes to CSR/GPR/FPR are shifted in len(CSR/GPR) or len(FPR) cycles
AcState <= AC_UPDATE; AcState <= AC_UPDATE;
else if (~MiscRegNo & ~AcWrite & (Cycle == P.LLEN)) // Reads from CSR/GPR/FPR are shifted in len(ScanReg) cycles else if (~MiscRegNo & ~AcWrite & (Cycle == P.LLEN[9:0])) // Reads from CSR/GPR/FPR are shifted in len(ScanReg) cycles
AcState <= AC_IDLE; AcState <= AC_IDLE;
else if (MiscRegNo & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely else if (MiscRegNo & (Cycle == ScanChainLen)) // Misc scanchain must be scanned completely
AcState <= AC_IDLE; AcState <= AC_IDLE;
@ -440,6 +442,8 @@ module dm import cvw::*; #(parameter cvw_t P) (
else else
Cycle <= Cycle + 1; Cycle <= Cycle + 1;
end end
default:;
endcase endcase
end end
end end
@ -503,13 +507,15 @@ module dm import cvw::*; #(parameter cvw_t P) (
if (P.LLEN >= 64) begin if (P.LLEN >= 64) begin
assign Data1Wr = WriteMsgReg ? ReqData : MaskedScanReg[63:32]; assign Data1Wr = WriteMsgReg ? ReqData : MaskedScanReg[63:32];
flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1)); flopenr #(32) data1reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA1)), .d(Data1Wr), .q(Data1));
end end else
assign Data1 = '0;
if (P.LLEN == 128) begin if (P.LLEN == 128) begin
assign Data2Wr = WriteMsgReg ? ReqData : MaskedScanReg[95:64]; assign Data2Wr = WriteMsgReg ? ReqData : MaskedScanReg[95:64];
assign Data3Wr = WriteMsgReg ? ReqData : MaskedScanReg[127:96]; assign Data3Wr = WriteMsgReg ? ReqData : MaskedScanReg[127:96];
flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2)); flopenr #(32) data2reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA2)), .d(Data2Wr), .q(Data2));
flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3)); flopenr #(32) data3reg (.clk, .reset(rst), .en(StoreScanChain | WriteMsgReg & (ReqAddress == `DATA3)), .d(Data3Wr), .q(Data3));
end end else
assign {Data3,Data2} = '0;
rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.CSRegNo,.GPRegNo,.FPRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.RegAddr,.ARMask); rad #(P) regnodecode(.AarSize(ReqData[`AARSIZE]),.Regno(ReqData[`REGNO]),.CSRegNo,.GPRegNo,.FPRegNo,.ScanChainLen,.ShiftCount,.InvalidRegNo,.RegReadOnly,.RegAddr,.ARMask);

2
src/debug/dmc.sv
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@ -114,7 +114,6 @@ module dmc (
end end
end end
STEP : begin STEP : begin
if (~|Counter) begin if (~|Counter) begin
DebugCause <= `CAUSE_STEP; DebugCause <= `CAUSE_STEP;
@ -122,6 +121,7 @@ module dmc (
end else end else
Counter <= Counter - 1; Counter <= Counter - 1;
end end
default: ; // empty defualt case to make the linter happy
endcase endcase
end end
end end

4
src/debug/dtm.sv
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@ -83,13 +83,13 @@ module dtm #(parameter ADDR_WIDTH, parameter JTAG_DEVICE_ID) (
// Synchronize the edges of tck to the system clock // Synchronize the edges of tck to the system clock
synchronizer clksync (.clk(clk), .d(tck), .q(tcks)); synchronizer clksync (.clk(clk), .d(tck), .q(tcks));
jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.rst, .tck(tcks), .tdi, .tms, .tdo, jtag #(.ADDR_WIDTH(ADDR_WIDTH), .DEVICE_ID(JTAG_DEVICE_ID)) jtag (.tck(tcks), .tdi, .tms, .tdo,
.resetn, .UpdateDtmcs, .DtmcsIn, .DtmcsOut, .CaptureDmi, .UpdateDmi, .DmiIn, .DmiOut); .resetn, .UpdateDtmcs, .DtmcsIn, .DtmcsOut, .CaptureDmi, .UpdateDmi, .DmiIn, .DmiOut);
// DTMCS // DTMCS
assign DtmcsOut = {11'b0, ErrInfo, 3'b0, Idle, DmiStat, ABits, Version}; assign DtmcsOut = {11'b0, ErrInfo, 3'b0, Idle, DmiStat, ABits, Version};
always_ff @(posedge clk) begin always @(posedge clk) begin
if (rst | ~resetn | DtmHardReset) begin if (rst | ~resetn | DtmHardReset) begin
DtmHardReset <= 0; DtmHardReset <= 0;
DmiReset <= 0; DmiReset <= 0;

14
src/debug/ir.sv
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@ -57,20 +57,22 @@ module ir (
// 6.1.2 // 6.1.2
always_comb begin always_comb begin
unique case (shift_reg[INST_REG_WIDTH-1:0]) unique case (shift_reg[INST_REG_WIDTH-1:0])
5'h00 : decoded <= 4'b1000; // bypass 5'h00 : decoded = 4'b1000; // bypass
5'h01 : decoded <= 4'b0100; // idcode 5'h01 : decoded = 4'b0100; // idcode
5'h10 : decoded <= 4'b0010; // dtmcs 5'h10 : decoded = 4'b0010; // dtmcs
5'h11 : decoded <= 4'b0001; // dmi 5'h11 : decoded = 4'b0001; // dmi
5'h1F : decoded <= 4'b1000; // bypass 5'h1F : decoded = 4'b1000; // bypass
default : decoded <= 4'b1000; // bypass default : decoded = 4'b1000; // bypass
endcase endcase
end end
// Flop decoded instruction to minimizes switching during shiftIR // Flop decoded instruction to minimizes switching during shiftIR
/* verilator lint_off SYNCASYNCNET */
always @(posedge updateIR or negedge resetn) begin always @(posedge updateIR or negedge resetn) begin
if (~resetn) if (~resetn)
{BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100; {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= 4'b0100;
else if (updateIR) else if (updateIR)
{BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded; {BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr} <= decoded;
end end
/* verilator lint_on SYNCASYNCNET */
endmodule endmodule

23
src/debug/jtag.sv
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@ -26,7 +26,6 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module jtag #(parameter ADDR_WIDTH, parameter DEVICE_ID) ( module jtag #(parameter ADDR_WIDTH, parameter DEVICE_ID) (
input logic rst,
// JTAG signals // JTAG signals
input logic tck, input logic tck,
input logic tdi, input logic tdi,
@ -80,7 +79,7 @@ module jtag #(parameter ADDR_WIDTH, parameter DEVICE_ID) (
assign CaptureDmi = captureDR & DmiInstr; assign CaptureDmi = captureDR & DmiInstr;
assign UpdateDmi = updateDR & DmiInstr; assign UpdateDmi = updateDR & DmiInstr;
tap tap (.rst, .tck, .tms, .resetn, .tdo_en, .captureIR, tap tap (.tck, .tms, .resetn, .tdo_en, .captureIR,
.clockIR, .updateIR, .shiftDR, .captureDR, .clockDR, .updateDR, .select); .clockIR, .updateIR, .shiftDR, .captureDR, .clockDR, .updateDR, .select);
// IR/DR input demux // IR/DR input demux
@ -96,31 +95,31 @@ module jtag #(parameter ADDR_WIDTH, parameter DEVICE_ID) (
// DR demux // DR demux
always_comb begin always_comb begin
unique case ({BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr}) unique case ({BypassInstr, IDCodeInstr, DtmcsIntrs, DmiInstr})
4'b1000 : tdo_dr <= tdo_bypass; 4'b1000 : tdo_dr = tdo_bypass;
4'b0100 : tdo_dr <= tdo_idcode; 4'b0100 : tdo_dr = tdo_idcode;
4'b0010 : tdo_dr <= tdo_dtmcs; 4'b0010 : tdo_dr = tdo_dtmcs;
4'b0001 : tdo_dr <= tdo_dmi; 4'b0001 : tdo_dr = tdo_dmi;
default : tdo_dr <= tdo_bypass; default : tdo_dr = tdo_bypass;
endcase endcase
end end
flopr #(32) dtmcsreg (.clk(UpdateDtmcs), .reset(rst), .d(DtmcsShiftReg[31:0]), .q(DtmcsIn)); flop #(32) dtmcsreg (.clk(UpdateDtmcs), .d(DtmcsShiftReg[31:0]), .q(DtmcsIn));
flopr #(34+ADDR_WIDTH) dmireg (.clk(UpdateDmi), .reset(rst), .d(DmiShiftReg[34+ADDR_WIDTH-1:0]), .q(DmiIn)); flop #(34+ADDR_WIDTH) dmireg (.clk(UpdateDmi), .d(DmiShiftReg[34+ADDR_WIDTH-1:0]), .q(DmiIn));
assign DtmcsShiftReg[32] = tdi_dr; assign DtmcsShiftReg[32] = tdi_dr;
assign tdo_dtmcs = DtmcsShiftReg[0]; assign tdo_dtmcs = DtmcsShiftReg[0];
for (i = 0; i < 32; i = i + 1) for (i = 0; i < 32; i = i + 1)
flopr #(1) dtmcsshiftreg (.clk(clockDR), .reset(rst), .d(captureDR ? DtmcsOut[i] : DtmcsShiftReg[i+1]), .q(DtmcsShiftReg[i])); flop #(1) dtmcsshiftreg (.clk(clockDR), .d(captureDR ? DtmcsOut[i] : DtmcsShiftReg[i+1]), .q(DtmcsShiftReg[i]));
assign DmiShiftReg[34+ADDR_WIDTH] = tdi_dr; assign DmiShiftReg[34+ADDR_WIDTH] = tdi_dr;
assign tdo_dmi = DmiShiftReg[0]; assign tdo_dmi = DmiShiftReg[0];
for (i = 0; i < 34+ADDR_WIDTH; i = i + 1) for (i = 0; i < 34+ADDR_WIDTH; i = i + 1)
flopr #(1) dmishiftreg (.clk(clockDR), .reset(rst), .d(captureDR ? DmiOut[i] : DmiShiftReg[i+1]), .q(DmiShiftReg[i])); flop #(1) dmishiftreg (.clk(clockDR), .d(captureDR ? DmiOut[i] : DmiShiftReg[i+1]), .q(DmiShiftReg[i]));
// jtag id register // jtag id register
idreg #(DEVICE_ID) id (.tdi(tdi_dr), .clockDR, .captureDR, .tdo(tdo_idcode)); idreg #(DEVICE_ID) id (.tdi(tdi_dr), .clockDR, .captureDR, .tdo(tdo_idcode));
// bypass register // bypass register
flopr #(1) bypassreg (.clk(clockDR), .reset(rst), .d(tdi_dr & shiftDR), .q(tdo_bypass)); flop #(1) bypassreg (.clk(clockDR), .d(tdi_dr & shiftDR), .q(tdo_bypass));
endmodule endmodule

15
src/debug/rad.sv
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@ -63,7 +63,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
localparam IEUADRM_IDX = WRITEDATAM_IDX + IEUADRMLEN; localparam IEUADRM_IDX = WRITEDATAM_IDX + IEUADRMLEN;
localparam READDATAM_IDX = IEUADRM_IDX + READDATAMLEN; localparam READDATAM_IDX = IEUADRM_IDX + READDATAMLEN;
logic [P.LLEN:0] Mask; logic [P.LLEN-1:0] Mask;
assign RegAddr = Regno[11:0]; assign RegAddr = Regno[11:0];
assign ScanChainLen = (CSRegNo | GPRegNo) ? P.XLEN : FPRegNo ? P.FLEN : SCANCHAINLEN; assign ScanChainLen = (CSRegNo | GPRegNo) ? P.XLEN : FPRegNo ? P.FLEN : SCANCHAINLEN;
@ -168,15 +168,14 @@ module rad import cvw::*; #(parameter cvw_t P) (
// Mask calculator // Mask calculator
always_comb begin always_comb begin
Mask = 0;
case (Regno) inside case (Regno) inside
`TRAPM_REGNO : Mask = {1{1'b1}}; `TRAPM_REGNO : Mask = {{P.LLEN-1{1'b0}}, 1'b1};
`INSTRM_REGNO : Mask = {32{1'b1}}; `INSTRM_REGNO : Mask = {{P.LLEN-32{1'b0}}, {32{1'b1}}};
`MEMRWM_REGNO : Mask = {2{1'b1}}; `MEMRWM_REGNO : Mask = {{P.LLEN-2{1'b0}}, 2'b11};
`INSTRVALIDM_REGNO : Mask = {1{1'b1}}; `INSTRVALIDM_REGNO : Mask = {{P.LLEN-1{1'b0}}, 1'b1};
`READDATAM_REGNO : Mask = {P.LLEN{1'b1}}; `READDATAM_REGNO : Mask = {P.LLEN{1'b1}};
[`FP0_REGNO:`FP31_REGNO] : Mask = {P.FLEN{1'b1}}; [`FP0_REGNO:`FP31_REGNO] : Mask = {{P.LLEN-P.FLEN{1'b0}}, {P.FLEN{1'b1}}};
default : Mask = {P.XLEN{1'b1}}; default : Mask = {{P.LLEN-P.XLEN{1'b0}}, {P.XLEN{1'b1}}};
endcase endcase
end end

56
src/debug/tap.sv
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@ -26,7 +26,6 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module tap ( module tap (
input logic rst,
input logic tck, input logic tck,
input logic tms, input logic tms,
output logic resetn, output logic resetn,
@ -62,39 +61,36 @@ module tap (
TLReset = 4'hF TLReset = 4'hF
} State; } State;
always @(posedge rst, posedge tck) begin always @(posedge tck) begin
if (rst) case (State)
State <= TLReset; TLReset : State <= tms ? TLReset : RunTestIdle;
else RunTestIdle : State <= tms ? SelectDR : RunTestIdle;
case (State) SelectDR : State <= tms ? SelectIR : CaptureDR;
TLReset : State <= tms ? TLReset : RunTestIdle; CaptureDR : State <= tms ? Exit1DR : ShiftDR;
RunTestIdle : State <= tms ? SelectDR : RunTestIdle; ShiftDR : State <= tms ? Exit1DR : ShiftDR;
SelectDR : State <= tms ? SelectIR : CaptureDR; Exit1DR : State <= tms ? UpdateDR : PauseDR;
CaptureDR : State <= tms ? Exit1DR : ShiftDR; PauseDR : State <= tms ? Exit2DR : PauseDR;
ShiftDR : State <= tms ? Exit1DR : ShiftDR; Exit2DR : State <= tms ? UpdateDR : ShiftDR;
Exit1DR : State <= tms ? UpdateDR : PauseDR; UpdateDR : State <= tms ? SelectDR : RunTestIdle;
PauseDR : State <= tms ? Exit2DR : PauseDR; SelectIR : State <= tms ? TLReset : CaptureIR;
Exit2DR : State <= tms ? UpdateDR : ShiftDR; CaptureIR : State <= tms ? Exit1IR : ShiftIR;
UpdateDR : State <= tms ? SelectDR : RunTestIdle; ShiftIR : State <= tms ? Exit1IR : ShiftIR;
SelectIR : State <= tms ? TLReset : CaptureIR; Exit1IR : State <= tms ? UpdateIR : PauseIR;
CaptureIR : State <= tms ? Exit1IR : ShiftIR; PauseIR : State <= tms ? Exit2IR : PauseIR;
ShiftIR : State <= tms ? Exit1IR : ShiftIR; Exit2IR : State <= tms ? UpdateIR : ShiftIR;
Exit1IR : State <= tms ? UpdateIR : PauseIR; UpdateIR : State <= tms ? SelectDR : RunTestIdle;
PauseIR : State <= tms ? Exit2IR : PauseIR; endcase
Exit2IR : State <= tms ? UpdateIR : ShiftIR;
UpdateIR : State <= tms ? SelectDR : RunTestIdle;
endcase
end end
assign tckn = ~tck; assign tckn = ~tck;
flopr #(1) resetnreg (.clk(tckn), .reset(rst), .d(~(State == TLReset)), .q(resetn)); flop #(1) resetnreg (.clk(tckn), .d(~(State == TLReset)), .q(resetn));
flopr #(1) tdo_enreg (.clk(tckn), .reset(rst), .d(State == ShiftIR | State == ShiftDR), .q(tdo_en)); flop #(1) tdo_enreg (.clk(tckn), .d(State == ShiftIR | State == ShiftDR), .q(tdo_en));
flopr #(1) captureIRreg (.clk(tckn), .reset(rst), .d(State == CaptureIR), .q(captureIR)); flop #(1) captureIRreg (.clk(tckn), .d(State == CaptureIR), .q(captureIR));
flopr #(1) updateIRreg (.clk(tckn), .reset(rst), .d(State == UpdateIR), .q(updateIR)); flop #(1) updateIRreg (.clk(tckn), .d(State == UpdateIR), .q(updateIR));
flopr #(1) shiftDRreg (.clk(tckn), .reset(rst), .d(State == ShiftDR), .q(shiftDR)); flop #(1) shiftDRreg (.clk(tckn), .d(State == ShiftDR), .q(shiftDR));
flopr #(1) captureDRreg (.clk(tckn), .reset(rst), .d(State == CaptureDR), .q(captureDR)); flop #(1) captureDRreg (.clk(tckn), .d(State == CaptureDR), .q(captureDR));
flopr #(1) updateDRreg (.clk(tckn), .reset(rst), .d(State == UpdateDR), .q(updateDR)); flop #(1) updateDRreg (.clk(tckn), .d(State == UpdateDR), .q(updateDR));
assign clockIR = tck | State[0] | ~State[1] | ~State[3]; assign clockIR = tck | State[0] | ~State[1] | ~State[3];
assign clockDR = tck | State[0] | ~State[1] | State[3]; assign clockDR = tck | State[0] | ~State[1] | State[3];

1
src/ieu/controller.sv
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@ -454,6 +454,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM, flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE}, {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM}); {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
assign DebugScanOut = DebugScanIn;
end end
flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);

5
src/ieu/datapath.sv
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@ -124,6 +124,7 @@ module datapath import cvw::*; #(parameter cvw_t P) (
flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(DebugScanEn & GPRSel), .scanin(GPRScanIn), .scanout(GPRScanOut)); flopenrs #(P.XLEN) GPScanReg(.clk, .reset, .en(DebugCapture), .d(R1D), .q(DebugGPRWriteD), .scan(DebugScanEn & GPRSel), .scanin(GPRScanIn), .scanout(GPRScanOut));
end else begin end else begin
regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
assign GPRScanOut = GPRScanIn;
end end
// Execute stage pipeline register and logic // Execute stage pipeline register and logic
@ -145,8 +146,10 @@ module datapath import cvw::*; #(parameter cvw_t P) (
flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
if (P.DEBUG_SUPPORTED) if (P.DEBUG_SUPPORTED)
flopenrcs #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM, (DebugScanEn & MiscSel), DebugScanIn, DebugScanOut); flopenrcs #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM, (DebugScanEn & MiscSel), DebugScanIn, DebugScanOut);
else else begin
flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM);
assign DebugScanOut = DebugScanIn;
end
// Writeback stage pipeline register and logic // Writeback stage pipeline register and logic
flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);

4
src/ifu/ifu.sv
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@ -100,13 +100,15 @@ module ifu import cvw::*; #(parameter cvw_t P) (
input logic DRet, input logic DRet,
input logic ProgBuffScanEn, input logic ProgBuffScanEn,
// Debug scan chain // Debug scan chain
input logic [3:0] ProgBufAddr, input logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr,
input logic ProgBufScanIn, input logic ProgBufScanIn,
input logic DebugScanEn, input logic DebugScanEn,
input logic DebugScanIn, input logic DebugScanIn,
output logic DebugScanOut output logic DebugScanOut
); );
localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
localparam [31:0] nop = 32'h00000013; // instruction for NOP localparam [31:0] nop = 32'h00000013; // instruction for NOP
localparam LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN; localparam LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;

2
src/ifu/progbuf.sv
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@ -60,7 +60,7 @@ module progbuf import cvw::*; #(parameter cvw_t P) (
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (WriteProgBuf) if (WriteProgBuf)
RAM[AddrM] <= WriteData; RAM[AddrM] <= WriteData[31:0];
if (reset) if (reset)
ReadRaw <= 0; ReadRaw <= 0;
else else

15
src/lsu/lsu.sv
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@ -165,10 +165,14 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Zero-extend address to 34 bits for XLEN=32 // Zero-extend address to 34 bits for XLEN=32
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if (P.DEBUG_SUPPORTED) if (P.DEBUG_SUPPORTED) begin
flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR)); flopenrcs #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM),
else .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DSCR));
end else begin
flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM)); flopenrc #(P.XLEN) AddressMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(IEUAdrE), .q(IEUAdrM));
assign DSCR = DebugScanIn;
end
if(MISALIGN_SUPPORT) begin : ziccslm_align if(MISALIGN_SUPPORT) begin : ziccslm_align
logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM; logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM,
@ -429,7 +433,10 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// Capture ReadDataM // Capture ReadDataM
if (P.DEBUG_SUPPORTED) begin if (P.DEBUG_SUPPORTED) begin
flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(), .scan(DebugScanEn), .scanin(DSCR), .scanout(DebugScanOut)); flopenrs #(P.LLEN) ReadDataMScan (.clk, .reset, .en(DebugCapture), .d(ReadDataM), .q(),
.scan(DebugScanEn), .scanin(DSCR), .scanout(DebugScanOut));
end else begin
assign DebugScanOut = DSCR;
end end
// Compute byte masks // Compute byte masks

2
src/mmu/adrdecs.sv
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@ -49,6 +49,8 @@ module adrdecs import cvw::*; #(parameter cvw_t P) (
adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[9]); adrdec #(P.PA_BITS) plicdec(PhysicalAddress, P.PLIC_BASE[P.PA_BITS-1:0], P.PLIC_RANGE[P.PA_BITS-1:0], P.PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[9]);
adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]); adrdec #(P.PA_BITS) sdcdec(PhysicalAddress, P.SDC_BASE[P.PA_BITS-1:0], P.SDC_RANGE[P.PA_BITS-1:0], P.SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[10]);
adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]); adrdec #(P.PA_BITS) spidec(PhysicalAddress, P.SPI_BASE[P.PA_BITS-1:0], P.SPI_RANGE[P.PA_BITS-1:0], P.SPI_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[11]);
assign SelRegions[12] = 1'b0; // reserve for PLL_CONFIG
assign SelRegions[13] = 1'b0; // reserve for BSG_DMC_CONFIG
adrdec #(P.PA_BITS) progbufdec(PhysicalAddress, P.PROGBUF_BASE[P.PA_BITS-1:0], P.PROGBUF_RANGE[P.PA_BITS-1:0], P.DEBUG_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[14]); adrdec #(P.PA_BITS) progbufdec(PhysicalAddress, P.PROGBUF_BASE[P.PA_BITS-1:0], P.PROGBUF_RANGE[P.PA_BITS-1:0], P.DEBUG_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[14]);
assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected

4
src/privileged/csrd.sv
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@ -66,7 +66,7 @@ module csrd import cvw::*; #(parameter cvw_t P) (
logic [2:0] Cause; logic [2:0] Cause;
const logic V = 0; const logic V = 0;
const logic MPrvEn = 0; const logic MPrvEn = 0;
logic NMIP; // pending non-maskable interrupt const logic NMIP = 0; // pending non-maskable interrupt TODO: update
logic [1:0] Prv; logic [1:0] Prv;
@ -102,7 +102,7 @@ module csrd import cvw::*; #(parameter cvw_t P) (
IllegalCSRDAccessM = 1'b1; IllegalCSRDAccessM = 1'b1;
else else
case (CSRAdrM) case (CSRAdrM)
DCSR_ADDR : CSRDReadValM = DCSR; DCSR_ADDR : CSRDReadValM = {{(P.XLEN-32){1'b0}},DCSR};
DPC_ADDR : CSRDReadValM = DPC; DPC_ADDR : CSRDReadValM = DPC;
default: IllegalCSRDAccessM = 1'b1; default: IllegalCSRDAccessM = 1'b1;
endcase endcase

8
src/uncore/uncore.sv
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@ -58,17 +58,17 @@ module uncore import cvw::*; #(parameter cvw_t P)(
input logic SDCIntr, input logic SDCIntr,
input logic SPIIn, input logic SPIIn,
output logic SPIOut, output logic SPIOut,
output logic [3:0] SPICS output logic [3:0] SPICS
); );
logic [P.XLEN-1:0] HREADRam, HREADSDC; logic [P.XLEN-1:0] HREADRam, HREADSDC;
logic [11:0] HSELRegions; logic [14:0] HSELRegions;
logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI; logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSPI;
logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID; logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD, HSELSPID;
logic HRESPRam, HRESPSDC; logic HRESPRam, HRESPSDC;
logic HREADYRam, HRESPSDCD; logic HREADYRam, HRESPSDCD;
logic [P.XLEN-1:0] HREADBootRom; logic [P.XLEN-1:0] HREADBootRom;
logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC; logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
logic HSELNoneD; logic HSELNoneD;
logic UARTIntr,GPIOIntr, SPIIntr; logic UARTIntr,GPIOIntr, SPIIntr;
@ -183,7 +183,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
// takes more than 1 cycle to repsond it needs to hold on to the old select until the // takes more than 1 cycle to repsond it needs to hold on to the old select until the
// device is ready. Hense this register must be selectively enabled by HREADY. // device is ready. Hense this register must be selectively enabled by HREADY.
// However on reset None must be seleted. // However on reset None must be seleted.
flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 12'b1, flopenl #(12) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[11:0], 12'b1,
{HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD, {HSELSPID, HSELEXTSDCD, HSELPLICD, HSELUARTD, HSELGPIOD, HSELCLINTD,
HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD}); HSELRamD, HSELBootRomD, HSELEXTD, HSELIROMD, HSELDTIMD, HSELNoneD});
flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED);

20
src/wally/wallypipelinedcore.sv
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@ -68,10 +68,12 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
input logic [11:0] DebugRegAddr, // address for scanable regfiles (GPR, FPR, CSR) input logic [11:0] DebugRegAddr, // address for scanable regfiles (GPR, FPR, CSR)
input logic DebugCapture, // latches values into scan register before scanning out input logic DebugCapture, // latches values into scan register before scanning out
input logic DebugRegUpdate, // writes values from scan register after scanning in input logic DebugRegUpdate, // writes values from scan register after scanning in
input logic [3:0] ProgBufAddr, input logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr,
input logic ProgBuffScanEn input logic ProgBuffScanEn
); );
localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
logic StallF, StallD, StallE, StallM, StallW; logic StallF, StallD, StallE, StallM, StallW;
logic FlushD, FlushE, FlushM, FlushW; logic FlushD, FlushE, FlushM, FlushW;
logic TrapM, RetM; logic TrapM, RetM;
@ -329,7 +331,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.ResumeAck, .HaveReset, .DebugMode, .DebugCause, .DebugStall, .ExecProgBuf, .ResumeAck, .HaveReset, .DebugMode, .DebugCause, .DebugStall, .ExecProgBuf,
.DCall, .DRet, .ForceBreakPoint); .DCall, .DRet, .ForceBreakPoint);
end else begin end else begin
assign DebugStall = 1'b0; assign {DebugMode, DebugCause, ResumeAck, HaveReset, DebugStall, DCall, DRet, ForceBreakPoint} = '0;
end end
// privileged unit // privileged unit
@ -355,10 +357,14 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM, .FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM,
.ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .DCall, .DRet, .ExecProgBuf, .ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DPC, .DCall,
.DebugSel(CSRSel), .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut)); .DRet, .ExecProgBuf, .DebugSel(CSRSel), .DebugRegAddr, .DebugCapture,
.DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut));
if (P.DEBUG_SUPPORTED) begin if (P.DEBUG_SUPPORTED) begin
flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(), .scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0])); flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(),
.scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0]));
end else begin
assign DebugScanReg[0] = DebugScanIn;
end end
end else begin end else begin
assign {CSRReadValW, PrivilegeModeW, assign {CSRReadValW, PrivilegeModeW,
@ -366,7 +372,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
// PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW, // PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW,
ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE, ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE,
EPCM, TrapVectorM, RetM, TrapM, EPCM, TrapVectorM, RetM, TrapM,
sfencevmaM, BigEndianM, wfiM, IntPendingM} = '0; sfencevmaM, BigEndianM, wfiM, IntPendingM, CSRScanOut} = '0;
assign DebugScanReg[0] = DebugScanIn; assign DebugScanReg[0] = DebugScanIn;
end end
@ -417,7 +423,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM, assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM,
IllegalFPUInstrD, SetFflagsM, FpLoadStoreM, IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE} = '0; FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE, FPRScanOut} = '0;
end end
endmodule endmodule

49
src/wally/wallypipelinedsoc.sv
View File

@ -83,6 +83,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
logic HaveReset; logic HaveReset;
logic DebugStall; logic DebugStall;
logic ExecProgBuf; logic ExecProgBuf;
// Debug Module signals // Debug Module signals
logic DebugScanEn; logic DebugScanEn;
logic DebugScanIn; logic DebugScanIn;
@ -97,29 +98,33 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
logic [11:0] DebugRegAddr; logic [11:0] DebugRegAddr;
logic DebugCapture; logic DebugCapture;
logic DebugRegUpdate; logic DebugRegUpdate;
logic [3:0] ProgBufAddr; logic [$clog2(PROGBUF_SIZE)-1:0] ProgBufAddr;
logic ProgBuffScanEn; logic ProgBuffScanEn;
localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
// synchronize reset to SOC clock domain // synchronize reset to SOC clock domain
synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); synchronizer resetsync(.clk, .d(reset_ext), .q(reset));
// instantiate processor and internal memories // instantiate processor and internal memories
wallypipelinedcore #(P) core(.clk, .reset(reset || NdmReset), wallypipelinedcore #(P) core (
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .clk, .reset(reset || NdmReset), .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HPROT, .HTRANS, .HMASTLOCK, .HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset, .ResumeAck,
.HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset, .ResumeAck, .HaveReset, .DebugStall, .ExecProgBuf, .HaveReset, .DebugStall, .ExecProgBuf, .DebugScanEn, .DebugScanOut(DebugScanIn),
.DebugScanEn, .DebugScanOut(DebugScanIn), .GPRScanOut(GPRScanIn), .FPRScanOut(FPRScanIn), .CSRScanOut(CSRScanIn), .GPRScanOut(GPRScanIn), .FPRScanOut(FPRScanIn), .CSRScanOut(CSRScanIn),
.DebugScanIn(DebugScanOut), .MiscSel, .GPRSel, .FPRSel, .CSRSel, .DebugRegAddr, .DebugCapture, .DebugRegUpdate, .DebugScanIn(DebugScanOut), .MiscSel, .GPRSel, .FPRSel, .CSRSel, .DebugRegAddr, .DebugCapture,
.ProgBufAddr, .ProgBuffScanEn); .DebugRegUpdate, .ProgBufAddr, .ProgBuffScanEn
);
// instantiate uncore if a bus interface exists // instantiate uncore if a bus interface exists
if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769 if (P.BUS_SUPPORTED) begin : uncoregen // Hack to work around Verilator bug https://github.com/verilator/verilator/issues/4769
uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK, uncore #(P) uncore (
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HCLK, .HRESETn, .TIMECLK, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC, .HTRANS, .HMASTLOCK, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
.MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin, .HSELEXTSDC, .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOIN, .GPIOOUT, .GPIOEN, .UARTSin,
.UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS); .UARTSout, .MTIME_CLINT, .SDCIntr, .SPIIn, .SPIOut, .SPICS
);
end else begin end else begin
assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt, assign {HRDATA, HREADY, HRESP, HSELEXT, HSELEXTSDC, MTimerInt, MSwInt, MExtInt, SExtInt,
MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0; MTIME_CLINT, GPIOOUT, GPIOEN, UARTSout, SPIOut, SPICS} = '0;
@ -127,11 +132,17 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
// instantiate debug module // instantiate debug module
if (P.DEBUG_SUPPORTED) begin : dm if (P.DEBUG_SUPPORTED) begin : dm
dm #(P) dm (.clk, .rst(reset), .tck, .tdi, .tms, .tdo, .NdmReset, dm #(P) dm (
.HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset, .ResumeAck, .HaveReset, .DebugStall, .clk, .rst(reset), .tck, .tdi, .tms, .tdo, .NdmReset, .HaltReq, .ResumeReq, .HaltOnReset,
.DebugScanEn, .DebugScanIn, .GPRScanIn, .FPRScanIn, .CSRScanIn, .DebugScanOut, .AckHaveReset, .ResumeAck, .HaveReset, .DebugStall, .DebugScanEn, .DebugScanIn, .GPRScanIn,
.MiscSel, .GPRSel, .FPRSel, .CSRSel, .RegAddr(DebugRegAddr), .DebugCapture, .DebugRegUpdate, .FPRScanIn, .CSRScanIn, .DebugScanOut, .MiscSel, .GPRSel, .FPRSel, .CSRSel,
.ProgBufAddr, .ProgBuffScanEn, .ExecProgBuf); .RegAddr(DebugRegAddr), .DebugCapture, .DebugRegUpdate, .ProgBufAddr, .ProgBuffScanEn,
.ExecProgBuf
);
end else begin
assign {tdo, HaltReq, ResumeReq, HaltOnReset, AckHaveReset, DebugScanEn, DebugScanOut, MiscSel,
NdmReset, GPRSel, FPRSel, CSRSel, DebugRegAddr, DebugCapture, DebugRegUpdate,
ProgBufAddr, ProgBuffScanEn, ExecProgBuf} = '0;
end end
endmodule endmodule