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More cachefsm cleanup.

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This commit is contained in:
Ross Thompson 2022-02-06 21:50:44 -06:00
parent 347e9228f8
commit 8bcaadda6b
1 changed files with 12 additions and 16 deletions
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28
pipelined/src/cache/cachefsm.sv vendored
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@ -125,10 +125,6 @@ module cachefsm
// *** Ross simplify: factor out next state and output logic // *** Ross simplify: factor out next state and output logic
always_comb begin always_comb begin
PreSelAdr = 2'b00; PreSelAdr = 2'b00;
SetValid = 1'b0;
ClearValid = 1'b0;
SetDirty = 1'b0;
ClearDirty = 1'b0;
SRAMWordWriteEnable = 1'b0; SRAMWordWriteEnable = 1'b0;
SRAMLineWriteEnable = 1'b0; SRAMLineWriteEnable = 1'b0;
SelEvict = 1'b0; SelEvict = 1'b0;
@ -149,7 +145,6 @@ module cachefsm
PreSelAdr = 2'b00; PreSelAdr = 2'b00;
SRAMWordWriteEnable = 1'b0; SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
// TLB Miss // TLB Miss
@ -182,7 +177,6 @@ module cachefsm
end end
else begin else begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
@ -204,7 +198,6 @@ module cachefsm
else if (RW[0] & CacheHit) begin else if (RW[0] & CacheHit) begin
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
@ -248,8 +241,6 @@ module cachefsm
SRAMLineWriteEnable = 1'b1; SRAMLineWriteEnable = 1'b1;
NextState = STATE_MISS_READ_WORD; NextState = STATE_MISS_READ_WORD;
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
SetValid = 1'b1;
ClearDirty = 1'b1;
//LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write //LRUWriteEn = 1'b1; // DO not update LRU on SRAM fetch update. Wait for subsequent read/write
end end
@ -266,7 +257,6 @@ module cachefsm
STATE_MISS_READ_WORD_DELAY: begin STATE_MISS_READ_WORD_DELAY: begin
SRAMWordWriteEnable = 1'b0; SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
if(&RW & Atomic[1]) begin // amo write if(&RW & Atomic[1]) begin // amo write
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
@ -276,7 +266,6 @@ module cachefsm
end end
else begin else begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
@ -295,7 +284,6 @@ module cachefsm
STATE_MISS_WRITE_WORD: begin STATE_MISS_WRITE_WORD: begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
@ -334,7 +322,6 @@ module cachefsm
STATE_CPU_BUSY_FINISH_AMO: begin STATE_CPU_BUSY_FINISH_AMO: begin
PreSelAdr = 2'b01; PreSelAdr = 2'b01;
SRAMWordWriteEnable = 1'b0; SRAMWordWriteEnable = 1'b0;
SetDirty = 1'b0;
LRUWriteEn = 1'b0; LRUWriteEn = 1'b0;
restore = 1'b1; restore = 1'b1;
if(CPUBusy) begin if(CPUBusy) begin
@ -342,7 +329,6 @@ module cachefsm
end end
else begin else begin
SRAMWordWriteEnable = 1'b1; SRAMWordWriteEnable = 1'b1;
SetDirty = 1'b1;
LRUWriteEn = 1'b1; LRUWriteEn = 1'b1;
NextState = STATE_READY; NextState = STATE_READY;
end end
@ -395,7 +381,6 @@ module cachefsm
end end
STATE_FLUSH_CLEAR_DIRTY: begin STATE_FLUSH_CLEAR_DIRTY: begin
ClearDirty = 1'b1;
VDWriteEnable = 1'b1; VDWriteEnable = 1'b1;
SelFlush = 1'b1; SelFlush = 1'b1;
PreSelAdr = 2'b10; PreSelAdr = 2'b10;
@ -421,8 +406,8 @@ module cachefsm
end end
assign CacheCommitted = CurrState != STATE_READY; assign CacheCommitted = CurrState != STATE_READY;
// *** stall missing check on amo miss?
assign CacheStall = (CurrState == STATE_READY & (FlushCache | (|RW & ~CacheHit)) & ~IgnoreRequest) | assign CacheStall = (CurrState == STATE_READY & (FlushCache | (|RW & ~CacheHit)) & ~IgnoreRequest) |
(CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_WDV) |
(CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_FETCH_DONE) |
(CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
@ -433,6 +418,17 @@ module cachefsm
(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_INCR) |
(CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_WRITE_BACK) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushAdrFlag & FlushWayFlag)); (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushAdrFlag & FlushWayFlag));
assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
assign ClearValid = '0;
// *** setdirty can probably be simplified by not caring about cpubusy
assign SetDirty = (CurrState == STATE_READY & Atomic[1] & (&RW) & CacheHit & ~CPUBusy & ~IgnoreRequest) |
(CurrState == STATE_READY & RW[0] & CacheHit & ~IgnoreRequest) |
(CurrState == STATE_MISS_READ_WORD_DELAY & &RW & Atomic[1] & ~CPUBusy) |
(CurrState == STATE_MISS_WRITE_WORD) |
(CurrState == STATE_CPU_BUSY_FINISH_AMO & ~CPUBusy);
assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
(CurrState == STATE_FLUSH_CLEAR_DIRTY);
endmodule // cachefsm endmodule // cachefsm