Lint cleanup of unused signals

src/generic/mem/ram1p1rwbe.sv

@@ -82,7 +82,6 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
     ///////////////////////////////////////////////////////////////////////////////
   end else begin: ram
     bit [WIDTH-1:0] RAM[DEPTH-1:0];
-    integer i;
 
     if (PRELOAD_ENABLED) begin
       initial begin
@@ -102,11 +101,13 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
     // Write divided into part for bytes and part for extra msbs
     // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
     // Therefore these always blocks use the older always @(posedge clk) 
-    if(WIDTH >= 8) 
+    if(WIDTH >= 8) begin
+      integer i;
       always @(posedge clk) 
         if (ce & we) 
           for(i = 0; i < WIDTH/8; i++) 
             if(bwe[i]) RAM[addr][i*8 +: 8] <= din[i*8 +: 8];
+    end
   
     if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
       always @(posedge clk) 

src/generic/mem/ram1p1rwe.sv

@@ -71,8 +71,6 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
 
     bit [WIDTH-1:0]               RAM[DEPTH-1:0];
 
-    integer i;
-
     // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);

src/generic/mem/ram2p1r1wbe.sv

@@ -111,14 +111,6 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     ///////////////////////////////////////////////////////////////////////////////
 
     bit [WIDTH-1:0] RAM[DEPTH-1:0];
-    integer i;
-/*    
-    initial begin // initialize memory for simulation only; not needed because done in the testbench now
-      integer j;
-      for (j=0; j < DEPTH; j++) 
-        RAM[j] = '0;
-    end 
-*/
 
     // Read
     logic [$clog2(DEPTH)-1:0] ra1d;
@@ -128,11 +120,13 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     // Write divided into part for bytes and part for extra msbs
     // coverage off     
     //   when byte write enables are tied high, the last IF is always taken
-    if(WIDTH >= 8) 
+    if(WIDTH >= 8) begin
+      integer i;
       always @(posedge clk) 
         if (ce2 & we2) 
           for(i = 0; i < WIDTH/8; i++) 
             if(bwe2[i]) RAM[wa2][i*8 +: 8] <= wd2[i*8 +: 8];
+    end
     // coverage on
   
     if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8

src/ieu/aes/aes64ks1i.sv

@@ -26,11 +26,11 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aes64ks1i(
-   input  logic [3:0]  round,
+   input  logic [3:0]   round,
-   input  logic [63:0] rs1,
+   input  logic [63:32] rs1,
-   input  logic [31:0] Sbox0Out,
+   input  logic [31:0]  Sbox0Out,
-   output logic [31:0] SboxKIn,
+   output logic [31:0]  SboxKIn,
-   output logic [63:0] result
+   output logic [63:0]  result
 );                 
                  
    logic 			        finalround;

src/ieu/aes/aes64ks2.sv

@@ -26,9 +26,9 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aes64ks2(
-   input  logic [63:0] rs2,
+   input  logic [63:0]  rs2,
-   input  logic [63:0] rs1,
+   input  logic [63:32] rs1,
-   output logic [63:0] result
+   output logic [63:0]  result
 );
    
    logic [31:0] 		    w0, w1;

src/ieu/aes/aesinvshiftrows64.sv

@@ -26,7 +26,9 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aesinvshiftrows64(
-   input  logic [127:0] a, 
+   /* verilator lint_off UNUSEDSIGNAL */
+   input  logic [127:0] a,
+   /* verilator lint_on UNUSEDSIGNAL */
    output logic [63:0]  y
 );
 

src/ieu/aes/aesshiftrows64.sv

@@ -26,7 +26,9 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module aesshiftrows64(
+   /* verilator lint_off UNUSEDSIGNAL */
    input  logic [127:0] a, 
+   /* verilator lint_on UNUSEDSIGNAL */
    output logic [63:0] y
 );
 		    

src/ieu/aes/aesshiftrows64.xv

@@ -1,35 +0,0 @@
-///////////////////////////////////////////
-// aesshiftrows64.sv
-//
-// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
-// Created: 20 February 2024
-//
-// Purpose: aesshiftrow for taking in first Data line
-//
-// A component of the CORE-V-WALLY configurable RISC-V project.
-// https://github.com/openhwgroup/cvw
-// 
-// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
-//
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
-//
-// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
-// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
-// may obtain a copy of the License at
-//
-// https://solderpad.org/licenses/SHL-2.1/
-//
-// Unless required by applicable law or agreed to in writing, any work distributed under the 
-// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
-// either express or implied. See the License for the specific language governing permissions 
-// and limitations under the License.
-////////////////////////////////////////////////////////////////////////////////////////////////
-
-module aesshiftrows64(
-   input  logic [127:0] a, 
-   output logic [63:0]  y
-);
-		    
-   assign y = {a[31:24],   a[119:112], a[79:72],   a[39:32],
-               a[127:120], a[87:80],   a[47:40],   a[7:0]};   
-endmodule

src/ieu/bmu/bitmanipalu.sv

@@ -93,7 +93,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
 
   // ZBC and ZBKCUnit
   if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
-    zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
+    zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3(Funct3[1:0]), .ZBCResult);
   end else assign ZBCResult = '0;
 
   // ZBB Unit
@@ -108,7 +108,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
 
   // ZBKB Unit
   if (P.ZBKB_SUPPORTED) begin: zbkb
-    zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
+    zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU[P.XLEN/2-1:0]), .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
   end else assign ZBKBResult = '0;
 
   // ZBKX Unit
@@ -125,7 +125,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
   // ZKNH Unit
   if (P.ZKNH_SUPPORTED) begin: zknh
     if (P.XLEN == 32) zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
-    else              zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
+    else              zknh64 ZKNH64(.A(ABMU),           .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
   end else assign ZKNHResult = '0;
 
   // Result Select Mux

src/ieu/bmu/ext.sv

@@ -29,7 +29,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module ext #(parameter WIDTH = 32) (
-  input  logic [WIDTH-1:0] A,            // Operands
+  input  logic [15:0]      A,            // Operand to extend
   input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
   output logic [WIDTH-1:0] ExtResult);   // Extend Result
 

src/ieu/bmu/zbb.sv

@@ -46,7 +46,7 @@ module zbb #(parameter WIDTH=32) (
   mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
   cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
   byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
-  ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
+  ext #(WIDTH) ext(.A(A[15:0]), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
 
   // ZBBSelect[2] differentiates between min(u) vs max(u) instruction
   mux2 #(WIDTH) minmaxmux(B, A, ZBBSelect[2]^lt, MinMaxResult);

src/ieu/bmu/zbc.sv

@@ -30,7 +30,7 @@
 
 module zbc import cvw::*; #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] A, RevA, B,       // Operands
-  input  logic [2:0]        Funct3,           // Indicates operation to perform
+  input  logic [1:0]        Funct3,           // Indicates operation to perform
   output logic [P.XLEN-1:0] ZBCResult);       // ZBC result
 
   logic [P.XLEN-1:0] ClmulResult, RevClmulResult;

src/ieu/kmu/zbkb.sv

@@ -26,10 +26,11 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module zbkb #(parameter WIDTH=32) (
-   input  logic [WIDTH-1:0] A, B,
+  input  logic [WIDTH-1:0]   A, 
-  input  logic [2:0] 	    Funct3,
+  input  logic [WIDTH/2-1:0] B,
-   input  logic [2:0] 	    ZBKBSelect,
+  input  logic [2:0] 	     Funct3,
-   output logic [WIDTH-1:0] ZBKBResult
+  input  logic [2:0] 	     ZBKBSelect,
+  output logic [WIDTH-1:0]   ZBKBResult
 );
    
    logic [WIDTH-1:0] 	     Brev8Result;  // rev8, brev8

src/ieu/kmu/zbkx.sv

@@ -31,8 +31,10 @@ module zbkx #(parameter WIDTH=32) (
    output logic [WIDTH-1:0] ZBKXResult
 );
    
-   logic [WIDTH-1:0] 	     xperm4, xperm4lookup;
+   logic [WIDTH-1:0] 	     xperm4, xperm8;
-   logic [WIDTH-1:0] 	     xperm8, xperm8lookup;
+   /* verilator lint_off UNUSEDSIGNAL */
+   logic [WIDTH-1:0]         xperm4lookup, xperm8lookup; // not all bits are used
+   /* verilator lint_on UNUSEDSIGNAL */
    int 		     i;
    
    always_comb begin

src/ieu/kmu/zknde64.sv

@@ -48,8 +48,8 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
     aessbox32 sbox(Sbox0In, Sbox0Out);                       // Substitute bytes of value obtained for tmp2 using Rijndael sbox
 
     // Both ZKND and ZKNE support aes64ks1i and aes64ks2 instructions
-    aes64ks1i aes64ks1i(.round, .rs1(A), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes));
+    aes64ks1i aes64ks1i(.round, .rs1(A[63:32]), .Sbox0Out, .SboxKIn, .result(aes64ks1iRes));
-    aes64ks2  aes64ks2(.rs2(B), .rs1(A), .result(aes64ks2Res));
+    aes64ks2  aes64ks2(.rs2(B), .rs1(A[63:32]), .result(aes64ks2Res));
    
     // Choose among decrypt, encrypt, key schedule 1, key schedule 2 results
     mux4 #(64) zkndmux(aes64dRes, aes64eRes, aes64ks1iRes, aes64ks2Res, ZKNSelect[1:0], ZKNDEResult);

src/ieu/kmu/zknh64.sv

@@ -26,7 +26,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module zknh64 (
-   input  logic [63:0] A, B, 
+   input  logic [63:0] A,
    input  logic [3:0]  ZKNHSelect,
    output logic [63:0] ZKNHResult
 );

src/mmu/tlb/tlb.sv

@@ -110,7 +110,7 @@ module tlb import cvw::*;  #(parameter cvw_t P,
   assign NAPOT4 = (PPN[3:0] == 4'b1000); // 64 KiB contiguous region with pte.napot_bits = 4
 
   tlbcontrol #(P, ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
-    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation, .TLBFlush,
+    .PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM, .DisableTranslation,
     .PTEAccessBits, .CAMHit, .Misaligned, .NAPOT4, 
     .TLBMiss, .TLBHit, .TLBPageFault, 
     .UpdateDA, .SV39Mode, .Translate, .PTE_N, .PBMemoryType);

src/mmu/tlb/tlbcontrol.sv

@@ -38,7 +38,6 @@ module tlbcontrol import cvw::*;  #(parameter cvw_t P, ITLB = 0) (
   input  logic                     ReadAccess, WriteAccess,
   input  logic [3:0]               CMOpM,
   input  logic                     DisableTranslation,
-  input  logic                     TLBFlush,           // Invalidate all TLB entries
   input  logic [11:0]              PTEAccessBits,
   input  logic                     CAMHit,
   input  logic                     Misaligned,