Cleaned up LINT erors

This commit is contained in:
David Harris 2021-10-23 06:28:49 -07:00
parent 5142bfd624
commit 8b854bb1c2
6 changed files with 26 additions and 21 deletions

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@ -7,7 +7,7 @@ verilator=`which verilator`
basepath=$(dirname $0)/.. basepath=$(dirname $0)/..
for config in rv64g rv32g; do for config in rv64g rv32g; do
echo "$config linting..." echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then if !($verilator --lint-only --Wall "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv --relative-includes); then
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"
exit 1 exit 1
fi fi

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@ -1,4 +1,7 @@
// Depth is number of bits in one "word" of the memory, width is number of such words // Depth is number of bits in one "word" of the memory, width is number of such words
/* verilator lint_off ASSIGNDLY */
module sram1rw #(parameter DEPTH=128, WIDTH=256) ( module sram1rw #(parameter DEPTH=128, WIDTH=256) (
input logic clk, input logic clk,
// port 1 is read only // port 1 is read only
@ -19,3 +22,6 @@ module sram1rw #(parameter DEPTH=128, WIDTH=256) (
end end
end end
endmodule endmodule
/* verilator lint_on ASSIGNDLY */

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@ -66,7 +66,7 @@ module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, r
logic [59:0] d2, n2; logic [59:0] d2, n2;
logic [11:0] d3; logic [11:0] d3;
logic muxr_out, cout1, cout2, cout3, cout4, cout5, cout6, cout7; logic cout1, cout2, cout3, cout4, cout5, cout6, cout7;
// Check if exponent is odd for sqrt // Check if exponent is odd for sqrt
// If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA

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@ -36,8 +36,8 @@
`include "wally-config.vh" `include "wally-config.vh"
module SRAM2P1R1W module SRAM2P1R1W
#(parameter int Depth = 10, #(parameter int DEPTH = 10,
parameter int Width = 2 parameter int WIDTH = 2
) )
(input logic clk, (input logic clk,
@ -45,35 +45,35 @@ module SRAM2P1R1W
input logic reset, input logic reset,
// port 1 is read only // port 1 is read only
input logic [Depth-1:0] RA1, input logic [DEPTH-1:0] RA1,
output logic [Width-1:0] RD1, output logic [WIDTH-1:0] RD1,
input logic REN1, input logic REN1,
// port 2 is write only // port 2 is write only
input logic [Depth-1:0] WA1, input logic [DEPTH-1:0] WA1,
input logic [Width-1:0] WD1, input logic [WIDTH-1:0] WD1,
input logic WEN1, input logic WEN1,
input logic [Width-1:0] BitWEN1 input logic [WIDTH-1:0] BitWEN1
); );
logic [Depth-1:0] RA1Q, WA1Q; logic [DEPTH-1:0] RA1Q, WA1Q;
logic WEN1Q; logic WEN1Q;
logic [Width-1:0] WD1Q; logic [WIDTH-1:0] WD1Q;
logic [Width-1:0] memory [2**Depth-1:0]; logic [WIDTH-1:0] mem[2**DEPTH-1:0];
// SRAMs address busses are always registered first. // SRAMs address busses are always registered first.
flopenr #(Depth) RA1Reg(.clk(clk), flopenr #(DEPTH) RA1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(RA1), .d(RA1),
.q(RA1Q)); .q(RA1Q));
flopenr #(Depth) WA1Reg(.clk(clk), flopenr #(DEPTH) WA1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(WA1), .d(WA1),
@ -85,22 +85,22 @@ module SRAM2P1R1W
.d(WEN1), .d(WEN1),
.q(WEN1Q)); .q(WEN1Q));
flopenr #(Width) WD1Reg(.clk(clk), flopenr #(WIDTH) WD1Reg(.clk(clk),
.reset(reset), .reset(reset),
.en(REN1), .en(REN1),
.d(WD1), .d(WD1),
.q(WD1Q)); .q(WD1Q));
// read port // read port
assign RD1 = memory[RA1Q]; assign RD1 = mem[RA1Q];
genvar index; genvar index;
// write port // write port
generate generate
for (index = 0; index < Width; index = index + 1) begin:mem for (index = 0; index < WIDTH; index = index + 1) begin:bitwrite
always_ff @ (posedge clk) begin always_ff @ (posedge clk) begin
if (WEN1Q & BitWEN1[index]) begin if (WEN1Q & BitWEN1[index]) begin
memory[WA1Q][index] <= WD1Q[index]; mem[WA1Q][index] <= WD1Q[index];
end end
end end
end end

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@ -47,7 +47,6 @@ module csru #(parameter
generate generate
if (`F_SUPPORTED | `D_SUPPORTED) begin if (`F_SUPPORTED | `D_SUPPORTED) begin
logic [4:0] FFLAGS_REGW; logic [4:0] FFLAGS_REGW;
logic WriteFFLAGSM, WriteFRMM; //, WriteFCSRM;
logic [2:0] NextFRMM; logic [2:0] NextFRMM;
logic [4:0] NextFFLAGSM; logic [4:0] NextFFLAGSM;

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@ -323,8 +323,8 @@ logic [3:0] dummy;
if (`BPRED_ENABLED == 1) begin : bpred if (`BPRED_ENABLED == 1) begin : bpred
initial begin initial begin
$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
end end
end end
endgenerate endgenerate