From bace06e356a7c88d489aa525120765541afde243 Mon Sep 17 00:00:00 2001 From: Shreesh Kulkarni Date: Fri, 5 Apr 2024 23:16:11 +0530 Subject: [PATCH] Added CSV file extraction/tabulation support for Coremark Sweep. modified coremark_sweep.py to extract a csv file in the working directory with all the required Coremark performance metrics. Both 32-bit and 64-bit supported. --- benchmarks/coremark/coremark_sweep.py | 87 +++++++++++++++++++-------- 1 file changed, 62 insertions(+), 25 deletions(-) diff --git a/benchmarks/coremark/coremark_sweep.py b/benchmarks/coremark/coremark_sweep.py index e1b6c6573..82a596604 100755 --- a/benchmarks/coremark/coremark_sweep.py +++ b/benchmarks/coremark/coremark_sweep.py @@ -5,7 +5,7 @@ ## Written: Shreesh Kulkarni, kshreesh5@gmail.com ## Created: 20 March 2024 ## Modified: 22 March 2024 -## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs. +## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction. ## Documentation: @@ -30,6 +30,8 @@ import os +import re +import csv # list of architectures to run. arch32_list = [ "rv32gc_zba_zbb_zbc", @@ -39,32 +41,67 @@ arch32_list = [ "rv32im_zicsr", "rv32i_zicsr" ] -arch64_list = [ - "rv64gc_zba_zbb_zbc", - "rv64im_zicsr_zba_zbb_zbc", - "rv64gc", - "rv64imc_zicsr", - "rv64im_zicsr", - "rv64i_zicsr" -] -xlen_values = ['32','64'] -for xlen_value in xlen_values: - if(xlen_value=='32'): - for arch in arch32_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) - else: - for arch in arch64_list: - os.system("make clean") - make_all = f"make all XLEN={xlen_value} ARCH={arch}" - os.system(make_all) - make_run = f"make run XLEN={xlen_value} ARCH={arch}" - os.system(make_run) +#uncomment this array for 64bit configurations +#arch64_list = [ +# "rv64gc_zba_zbb_zbc", +# "rv64im_zicsr_zba_zbb_zbc", +# "rv64gc", +# "rv64imc_zicsr", +# "rv64im_zicsr", +# "rv64i_zicsr" +#] +xlen_value = '32' +#xlen_value = '64' #uncomment this for 64 bit. +# Define regular expressions to match the desired fields +mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)" +#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)" +#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)" +# Open a CSV file to write the results +with open('coremark_results.csv', mode='w', newline='') as csvfile: + fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses', + 'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses', + 'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong'] + writer = csv.DictWriter(csvfile, fieldnames=fieldnames) + writer.writeheader() + # Loop through each architecture and run the make commands + for arch in arch32_list: + os.system("make clean") + make_all = f"make all XLEN={xlen_value} ARCH={arch}" + os.system(make_all) + make_run = f"make run XLEN={xlen_value} ARCH={arch}" + output = os.popen(make_run).read() # Capture the output of the command + # Extract the Coremark values using regular expressions + mt_match = re.search(mt_regex, output,re.DOTALL) + #cpi_match = re.search(cpi_regex,output,re.DOTALL) + #cmhz_match = re.search(cmhz_regex,output,re.DOTALL) + #minstret_match = re.search(minstret_regex,output) + + # Write the architecture and extracted values to the CSV file + + mtime = mt_match.group(1) + minstret= mt_match.group(2) + cmhz= mt_match.group(3) + cpi= mt_match.group(4) + lstalls= mt_match.group(5) + swtalls= mt_match.group(6) + dacc= mt_match.group(7) + dmiss= mt_match.group(8) + iacc= mt_match.group(9) + imiss= mt_match.group(10) + br= mt_match.group(11) + brm= mt_match.group(12) + btb= mt_match.group(13) + jmp= mt_match.group(14) + ras= mt_match.group(15) + ret= mt_match.group(16) + bpc= mt_match.group(17) + #minstret = mt_instret_match.group(2) + writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi, + 'Load Stalls':lstalls, + 'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss, + 'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})