From 8b2e3688057f9748e6be64d3094d3bf8082731d6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 23 Aug 2022 12:57:18 -0700
Subject: [PATCH] Only stall FPU to IEU on convert instructions with
 dependencies

---
 pipelined/src/fpu/fctrl.sv   | 4 +++-
 pipelined/src/fpu/fpu.sv     | 3 ++-
 pipelined/src/ieu/forward.sv | 4 ++--
 pipelined/src/ieu/ieu.sv     | 4 ++--
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv
index 367983217..50961f27c 100755
--- a/pipelined/src/fpu/fctrl.sv
+++ b/pipelined/src/fpu/fctrl.sv
@@ -48,7 +48,7 @@ module fctrl (
   output logic 		         DivStartE,             // Start division or squareroot
   output logic              XEnE, YEnE, ZEnE,
   output logic              YEnForwardE, ZEnForwardE,
-  output logic 		         FWriteIntE, FWriteIntM,                         // Write to integer register
+  output logic 		         FWriteIntE, FCvtIntE, FWriteIntM,                         // Write to integer register
   output logic [2:0] 	      OpCtrlE, OpCtrlM,       // Select which opperation to do in each component
   output logic [1:0] 	      FResSelE, FResSelM, FResSelW,       // Select one of the results that finish in the memory stage
   output logic [1:0] 	      PostProcSelE, PostProcSelM, // select result in the post processing unit
@@ -264,6 +264,8 @@ module fctrl (
   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, 
                            {Adr1E, Adr2E, Adr3E});
   flopenrc #(1) DEDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, DivStartD, DivStartE);
+  assign FCvtIntE = (FResSelE == 2'b01);
+
   // E/M pipleine register
   flopenrc #(13+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM,
               {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE},
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index 57fd4aa18..fe69bb081 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -44,6 +44,7 @@ module fpu (
   output logic 		      FpLoadStoreM,  // Fp load instruction? (to LSU)
   output logic 		      FStallD,       // Stall the decode stage (To HZU)
   output logic 		      FWriteIntE,    // integer register write enable (to IEU)
+  output logic             FCvtIntE,      // Convert to int (to IEU)
   output logic [`FLEN-1:0] FWriteDataM,   // Data to be written to memory (to LSU) 
   output logic [`XLEN-1:0] FIntResM,      // data to be written to integer register (to IEU)
   output logic [`XLEN-1:0] FCvtIntResW,   // convert result to to be written to integer register (to IEU)
@@ -163,7 +164,7 @@ module fpu (
    fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .InstrD,
                .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE,
                .reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE,
-               .DivStartE, .FWriteIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
+               .DivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE,
                .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E);
 
    // FP register file
diff --git a/pipelined/src/ieu/forward.sv b/pipelined/src/ieu/forward.sv
index 07bd89d3d..856fbded1 100644
--- a/pipelined/src/ieu/forward.sv
+++ b/pipelined/src/ieu/forward.sv
@@ -35,7 +35,7 @@ module forward(
   input logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
   input logic        MemReadE, MDUE, CSRReadE,
   input logic        RegWriteM, RegWriteW,
-  input logic	       FWriteIntE, 
+  input logic	       FCvtIntE, 
   input logic        SCE,
   // Forwarding controls
   output logic [1:0] ForwardAE, ForwardBE,
@@ -58,7 +58,7 @@ module forward(
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
   assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
-  assign FPUStallD = 0; // FWriteIntE & MatchDE; // FPU to Integer transfers have single-cycle latency
+  assign FPUStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
   assign LoadStallD = (MemReadE|SCE) & MatchDE;  
   assign MDUStallD = MDUE & MatchDE; 
   assign CSRRdStallD = CSRReadE & MatchDE;
diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv
index d7101b873..6258566ff 100644
--- a/pipelined/src/ieu/ieu.sv
+++ b/pipelined/src/ieu/ieu.sv
@@ -39,7 +39,7 @@ module ieu (
   // Execute Stage interface
   input logic [`XLEN-1:0]  PCE, 
   input logic [`XLEN-1:0]  PCLinkE,
-  input logic 		   FWriteIntE, FCvtIntW,
+  input logic 		   FWriteIntE, FCvtIntE, FCvtIntW,
   output logic [`XLEN-1:0] IEUAdrE,
   output logic 		   MDUE, W64E,
   output logic [2:0] 	   Funct3E,
@@ -112,7 +112,7 @@ module ieu (
   forward    fw(
     .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
     .MemReadE, .MDUE, .CSRReadE, .RegWriteM, .RegWriteW,
-    .FWriteIntE, .SCE, .ForwardAE, .ForwardBE,
+    .FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
     .FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
 endmodule