diff --git a/.gitignore b/.gitignore index 0a25e7d3d..49d1e1603 100644 --- a/.gitignore +++ b/.gitignore @@ -7,9 +7,9 @@ __pycache__/ .vscode/ #External repos -addins addins/riscv-arch-test/Makefile.include addins/riscv-tests/target +benchmarks/embench/wally*.json #vsim work files to ignore transcript @@ -28,6 +28,10 @@ testsBP/*/*/*.elf* testsBP/*/OBJ/* testsBP/*/*.a tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/* +tests/riscof/riscof_work/ +tests/riscof/config32.ini +tests/riscof/config32e.ini +tests/riscof/config64.ini tests/linux-testgen/linux-testvectors/* !tests/linux-testgen/linux-testvectors/tvCopier.py !tests/linux-testgen/linux-testvectors/tvLinker.sh @@ -68,6 +72,11 @@ synthDC/alib-52 synthDC/*.log synthDC/*.svf synthDC/runs/ +synthDC/newRuns +synthDC/ppa/PPAruns +synthDC/ppa/plots +synthDC/plots/ +synthDC/runArchive synthDC/hdl /pipelined/regression/power.saif tests/fp/vectors/*.tv @@ -103,3 +112,8 @@ pipelined/config/rv64ic_noMulDiv pipelined/config/rv64ic_noPriv pipelined/config/rv64ic_orig synthDC/Summary.csv +pipelined/srt/exptestgen +pipelined/srt/testgen +pipelined/srt/qslc_r4a2 +pipelined/srt/qslc_r4a2.sv +pipelined/srt/testvectors diff --git a/.gitmodules b/.gitmodules index b396b1d43..ab45d3f96 100644 --- a/.gitmodules +++ b/.gitmodules @@ -17,9 +17,7 @@ [submodule "addins/embench-iot"] path = addins/embench-iot url = https://github.com/embench/embench-iot -[submodule "addins/sky130_osu_sc_t18"] - path = addins/sky130_osu_sc_t18 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18 -[submodule "addins/sky130_osu_sc_t12"] - path = addins/sky130_osu_sc_t12 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 + branch = embench-1.0-branch +[submodule "addins/coremark"] + path = addins/coremark + url = https://github.com/eembc/coremark diff --git a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a index 442544836..69cd932a8 100644 Binary files a/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a and b/addins/SoftFloat-3e/build/Linux-x86_64-GCC/softfloat.a differ diff --git a/addins/coremark b/addins/coremark new file mode 160000 index 000000000..f3e8f2e09 --- /dev/null +++ b/addins/coremark @@ -0,0 +1 @@ +Subproject commit f3e8f2e0941e42961aadcc52750b1b5577c157c9 diff --git a/addins/embench-iot b/addins/embench-iot index 2d2aaa7b8..261a65e0a 160000 --- a/addins/embench-iot +++ b/addins/embench-iot @@ -1 +1 @@ -Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3 +Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9 diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index effd553a6..e5020bf7b 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f +Subproject commit e5020bf7b345f8efb96c6c939de3162525b7f545 diff --git a/addins/riscv-dv b/addins/riscv-dv index cb4295f9c..a7e27bc04 160000 --- a/addins/riscv-dv +++ b/addins/riscv-dv @@ -1 +1 @@ -Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071 +Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172 diff --git a/addins/riscv-tests b/addins/riscv-tests index 3e2bf06b0..cf04274f5 160000 --- a/addins/riscv-tests +++ b/addins/riscv-tests @@ -1 +1 @@ -Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94 +Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7 diff --git a/addins/sky130_osu_sc_t12 b/addins/sky130_osu_sc_t12 deleted file mode 160000 index f1eef8447..000000000 --- a/addins/sky130_osu_sc_t12 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit f1eef844734f73d3c79d83b82352118263eb7686 diff --git a/addins/sky130_osu_sc_t18 b/addins/sky130_osu_sc_t18 deleted file mode 160000 index 83f5245e1..000000000 --- a/addins/sky130_osu_sc_t18 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 83f5245e1a599c628d6c73e76c1774b8ab5cab91 diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile new file mode 100644 index 000000000..e41865986 --- /dev/null +++ b/benchmarks/coremark/Makefile @@ -0,0 +1,42 @@ +# Wally Coremark Makefile +# Daniel Torres & David Harris 28 July 2022 + +PORT_DIR = $(CURDIR)/riscv64-baremetal +cmbase=../../addins/coremark +work_dir= ../../benchmarks/coremark/work +XLEN ?=64 +sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ + $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \ + $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ + $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c +ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32) +ARCH := rv$(XLEN)im +PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \ + -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \ + -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \ + -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta \ + -nostdlib -nostartfiles -ffreestanding -mstrict-align \ + -DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN) + +all: $(work_dir)/coremark.bare.riscv.elf.memfile + +run: + (cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log)) + cd ../../benchmarks/coremark/ + +$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv + riscv64-unknown-elf-objdump -D $< > $<.elf.objdump + riscv64-unknown-elf-elf2hex --bit-width $(XLEN) --input $< --output $@ + extractFunctionRadix.sh $<.elf.objdump + +$(work_dir)/coremark.bare.riscv: $(sources) Makefile + make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)" + mkdir -p $(work_dir) + mv $(cmbase)/coremark.bare.riscv $(work_dir) + +.PHONY: clean + +clean: + rm -f $(work_dir)/* + + diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.c b/benchmarks/coremark/riscv64-baremetal/core_portme.c similarity index 93% rename from benchmarks/riscv-coremark/riscv64-baremetal/core_portme.c rename to benchmarks/coremark/riscv64-baremetal/core_portme.c index 86917f939..017bef74e 100755 --- a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.c +++ b/benchmarks/coremark/riscv64-baremetal/core_portme.c @@ -114,7 +114,12 @@ void portable_free(void *p) { #define read_csr(reg) ({ unsigned long __tmp; \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ __tmp; }) - #define GETMYTIME(_t) (_t = *(volatile unsigned long long*)0x0200BFF8) + // #if (XLEN==64) + // typedef unsigned long long ee_ptr_int; + // #else + // typedef unsigned long ee_ptr_int; + // #endif + #define GETMYTIME(_t) (_t = *(volatile ee_ptr_int*)0x0200BFF8) #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) // Changing TIMER_RES_DIVIDER to 1000000 sets EE_TICKS_PER_SEC to 1000 (now counting ticks per ms) #define TIMER_RES_DIVIDER 10000 @@ -196,10 +201,13 @@ void stop_time(void) { CORE_TICKS get_time(void) { CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); unsigned long instructions = minstretDiff(); - ee_printf(" Called get_time\n"); + ee_ptr_int cm100 = 1000000000 / elapsed; // coremark score * 100 + ee_ptr_int cpi100 = elapsed*100/instructions; // CPI * 100 + ee_printf(" WALLY CoreMark Results (from get_time)\n"); ee_printf(" Elapsed MTIME: %u\n", elapsed); ee_printf(" Elapsed MINSTRET: %lu\n", instructions); - ee_printf(" CPI: %lu / %lu\n", elapsed, instructions); + ee_printf(" COREMARK/MHz Score: 10,000,000 / %lu = %d.%02d \n", elapsed, cm100/100, cm100%100); + ee_printf(" CPI: %lu / %lu = %d.%02d\n", elapsed, instructions, cpi100/100, cpi100%100); return elapsed; } /* Function: time_in_secs @@ -210,8 +218,11 @@ CORE_TICKS get_time(void) { */ secs_ret time_in_secs(CORE_TICKS ticks) { secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - int retvalint = (int)retval; - //ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retvalint); + // float retvalint = (float) retval; + // ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retvalint); + // ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %f\n", retvalint); + // ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %d\n", retval); + // ee_printf("RETURN VALUE FROM TIME IN SECS FUNCTION: %f\n", retval); return retval; } #else diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.h b/benchmarks/coremark/riscv64-baremetal/core_portme.h similarity index 96% rename from benchmarks/riscv-coremark/riscv64-baremetal/core_portme.h rename to benchmarks/coremark/riscv64-baremetal/core_portme.h index ef26e88ad..ce88f7239 100755 --- a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.h +++ b/benchmarks/coremark/riscv64-baremetal/core_portme.h @@ -28,7 +28,7 @@ Original Author: Shay Gal-on Define to 1 if the platform supports floating point. */ #ifndef HAS_FLOAT -#define HAS_FLOAT 1 +#define HAS_FLOAT 0 #endif /* Configuration: HAS_TIME_H Define to 1 if platform has the time.h header file, @@ -66,14 +66,19 @@ typedef size_t CORE_TICKS; #elif HAS_TIME_H #include typedef clock_t CORE_TICKS; -#else +// #elif (XLEN==32) +// #include +// typedef ee_u32 CORE_TICKS; /* Configuration: size_t and clock_t Note these need to match the size of the clock output and the xLen the processor supports */ +#elif (XLEN==64) typedef unsigned long int size_t; typedef unsigned long int clock_t; -typedef clock_t CORE_TICKS; +#else +#include #endif +typedef clock_t CORE_TICKS; /* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION Initialize these strings per platform @@ -89,7 +94,7 @@ typedef clock_t CORE_TICKS; #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ #endif #ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" + #define MEM_LOCATION "Code and Data in external RAM" #define MEM_LOCATION_UNSPEC 1 #endif @@ -105,11 +110,16 @@ typedef signed int ee_s32; typedef double ee_f32; typedef unsigned char ee_u8; typedef unsigned int ee_u32; -typedef unsigned long long ee_ptr_int; +#if (XLEN==64) + typedef unsigned long long ee_ptr_int; +#else + typedef ee_u32 ee_ptr_int; +#endif typedef size_t ee_size_t; /* align an offset to point to a 32b value */ #define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) + /* Configuration: SEED_METHOD Defines method to get seed values that cannot be computed at compile time. diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.mak b/benchmarks/coremark/riscv64-baremetal/core_portme.mak similarity index 96% rename from benchmarks/riscv-coremark/riscv64-baremetal/core_portme.mak rename to benchmarks/coremark/riscv64-baremetal/core_portme.mak index 4bae943dc..27e31b859 100755 --- a/benchmarks/riscv-coremark/riscv64-baremetal/core_portme.mak +++ b/benchmarks/coremark/riscv64-baremetal/core_portme.mak @@ -33,13 +33,13 @@ CC = $(RISCVTOOLS)/bin/$(RISCVTYPE)-gcc # Flag: CFLAGS # Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" #PORT_CFLAGS = -O2 -static -std=gnu99 -PORT_CFLAGS = -O2 -mcmodel=medany -static -fno-tree-loop-distribute-patterns -std=gnu99 -fno-common -nostartfiles -lm -lgcc -T $(PORT_DIR)/link.ld +PORT_CFLAGS = -mcmodel=medany -fno-tree-loop-distribute-patterns -fno-common -lm -lgcc -T $(PORT_DIR)/link.ld FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" #Flag: LFLAGS_END # Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). # Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END += +LFLAGS_END += -static-libgcc -lgcc # Flag: PORT_SRCS # Port specific source files can be added here PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/syscalls.c $(PORT_DIR)/crt.S diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/crt.S b/benchmarks/coremark/riscv64-baremetal/crt.S similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/crt.S rename to benchmarks/coremark/riscv64-baremetal/crt.S diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/encoding.h b/benchmarks/coremark/riscv64-baremetal/encoding.h similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/encoding.h rename to benchmarks/coremark/riscv64-baremetal/encoding.h diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/link.ld b/benchmarks/coremark/riscv64-baremetal/link.ld similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/link.ld rename to benchmarks/coremark/riscv64-baremetal/link.ld diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/syscallbackup.c b/benchmarks/coremark/riscv64-baremetal/syscallbackup.c similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/syscallbackup.c rename to benchmarks/coremark/riscv64-baremetal/syscallbackup.c diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c b/benchmarks/coremark/riscv64-baremetal/syscalls.c similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c rename to benchmarks/coremark/riscv64-baremetal/syscalls.c diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/util.h b/benchmarks/coremark/riscv64-baremetal/util.h similarity index 100% rename from benchmarks/riscv-coremark/riscv64-baremetal/util.h rename to benchmarks/coremark/riscv64-baremetal/util.h diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index e26ed416d..21c30cf6e 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -1,15 +1,76 @@ # Makefile added 1/20/22 David_Harris@hmc.edu +# Expanded and developed by Daniel Torres dtorres@hmc.edu # Compile Embench for Wally -all: Makefile - ../../addins/embench-iot/build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cflags "-O2 -march=rv32i -mabi=ilp32 -mcmodel=medany" --cc riscv64-unknown-elf-gcc - ./benchmark_size.py - ./benchmark_speed.py +embench_dir = ../../addins/embench-iot -# view with -# more `ls -t | head -1` +all: build +run: size sim -# --cflags "-O2 -g -nostartfiles" +allClean: clean all +build: buildspeed buildsize +buildspeed: build_speedopt_speed build_sizeopt_speed +buildsize: build_speedopt_size build_sizeopt_size -#riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size +build_speedopt_speed: + $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done + +build_sizeopt_speed: + $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done + +# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size +build_speedopt_size: + $(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-O2 -msave-restore" --dummy-libs="libgcc libm libc crt0" + +build_sizeopt_size: + $(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0" + +# builds dependencies, then launches modelsim and finally runs python wrapper script to present results +sim: modelsim_build_memfile modelsim_run speed + +# launches modelsim to simulate tests on wally +modelsim_run: + (cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench") + cd ../../benchmarks/embench/ + +# builds the objdump based on the compiled c elf files +objdump: + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-objdump -S -D "$$f" > "$$f.objdump"; done + +# build memfiles, objdump.lab and objdump.addr files +modelsim_build_memfile: objdump + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find $(embench_dir)/bd_*_speed/ -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done + +# builds the tests for speed, runs them on spike and then launches python script to present results +# note that the speed python script benchmark_speed.py can get confused if there's both a .output file created from spike and modelsim +# you'll need to manually remove one of the two .output files, or run make clean +spike: buildspeed spike_run speed + +# command to run spike on all of the benchmarks +spike_run: + find $(embench_dir)/bd_*opt_speed/ -type f -name "*.elf" | while read f; do spike --isa=rv32imac +signature=$$f.spike.output +signature-granularity=4 $$f; done + +# python wrapper to present results of embench size benchmark +size: buildsize + $(embench_dir)/benchmark_size.py --builddir=bd_speedopt_size --json-output > wallySpeedOpt_size.json + $(embench_dir)/benchmark_size.py --builddir=bd_sizeopt_size --json-output > wallySizeOpt_size.json + +# python wrapper to present results of embench speed benchmark +speed: + $(embench_dir)/benchmark_speed.py --builddir=bd_sizeopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySizeOpt_speed.json + $(embench_dir)/benchmark_speed.py --builddir=bd_speedopt_speed --target-module run_wally --cpu-mhz=1 --json-output > wallySpeedOpt_speed.json + +# deletes all files +clean: + rm -rf $(embench_dir)/bd_*_speed/ + rm -rf $(embench_dir)/bd_*_size/ + +allclean: clean + rm -rf $(embench_dir)/logs/ + +# riscv64-unknown-elf-gcc -O2 -g -nostartfiles -I/home/harris/riscv-wally/addins/embench-iot/support -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/boards/ri5cyverilator -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32/chips/generic -I/home/harris/riscv-wally/addins/embench-iot/config/riscv32 -DCPU_MHZ=1 -DWARMUP_HEAT=1 -o main.o /home/harris/riscv-wally/addins/embench-iot/support/main.c \ No newline at end of file diff --git a/benchmarks/embench/Makefile~ b/benchmarks/embench/Makefile~ deleted file mode 100644 index ebd9a7e44..000000000 --- a/benchmarks/embench/Makefile~ +++ /dev/null @@ -1,7 +0,0 @@ -# Makefile added 1/20/22 David_Harris@hmc.edu -# Compile Embench for Wally - -all: Makefile - ./build_all.py --arch riscv32 --chip generic --board ri5cyverilator --cc riscv64-unknown-elf-gcc - ./benchmark_size.py - ./benchmark_speed.py diff --git a/benchmarks/graphGen.py b/benchmarks/graphGen.py new file mode 100755 index 000000000..de8b70ce9 --- /dev/null +++ b/benchmarks/graphGen.py @@ -0,0 +1,104 @@ +#!/usr/bin/env python +import subprocess +import sys +import json +import plotly.graph_objects as go +from plotly.subplots import make_subplots + +debug = True + +def loadCoremark(): + """loads the coremark data dictionary""" + coremarkPath = "riscv-coremark/work/coremark.sim.log" + + keywordlist = ["CoreMark 1.0", "CoreMark Size", "MTIME", "MINSTRET", "Branches Miss Predictions", "BTB Misses"] + for keyword in keywordlist: + bashInst = "cat " + coremarkPath + " | grep \"" + keyword + "\" | cut -d \':\' -f 2 | cut -d \" \" -f 2 | tail -1" + result = subprocess.run(bashInst, stdout=subprocess.PIPE, shell=True) + if (debug): print(result) + coremarkData[keyword] = int(result.stdout) + if (debug): print(coremarkData) + return coremarkData + +def loadEmbench(embenchPath, embenchData): + """loads the embench data dictionary""" + f = open(embenchPath) + embenchData = json.load(f) + if (debug): print(embenchData) + return embenchData + +def graphEmbench(embenchSpeedOpt_SpeedData, embenchSizeOpt_SpeedData, embenchSpeedOpt_SizeData, embenchSizeOpt_SizeData): + fig = make_subplots(rows=2, cols=4, + # subplot_titles( "Wally's Embench Cycles and Instret (with -O2)","Wally's Embench Cycles Per Instruction (with -O2)")) + subplot_titles=( "Wally's Embench Cycles and Instret (with -O2)","Wally's Embench Cycles Per Instruction (with -O2)","Wally's Embench Speed Score (with -O2)","Wally's Embench Size Score (with -O2)", + "Wally's Embench Cycles and Instret (with -Os)","Wally's Embench Cycles Per Instruction (with -Os)","Wally's Embench Speed Score (with -Os)","Wally's Embench Size Score (with -Os)")) + + ydata = list(embenchSpeedOpt_SpeedData["speed results"]["detailed speed results"].keys()) + ["speed geometric mean","speed geometric sd","speed geometric range"] + xdata = list(embenchSpeedOpt_SpeedData["speed results"]["detailed speed results"].values()) + [embenchSpeedOpt_SpeedData["speed results"]["speed geometric mean"],embenchSpeedOpt_SpeedData["speed results"]["speed geometric sd"],embenchSpeedOpt_SpeedData["speed results"]["speed geometric range"]] + + fig.add_trace( go.Bar( + y=ydata, + x=xdata, + textposition='outside', text=xdata, + orientation='h'), + row=1,col=3) + + ydata = list(embenchSizeOpt_SpeedData["speed results"]["detailed speed results"].keys()) + ["speed geometric mean","speed geometric sd","speed geometric range"] + xdata = list(embenchSizeOpt_SpeedData["speed results"]["detailed speed results"].values()) + [embenchSizeOpt_SpeedData["speed results"]["speed geometric mean"],embenchSizeOpt_SpeedData["speed results"]["speed geometric sd"],embenchSizeOpt_SpeedData["speed results"]["speed geometric range"]] + + fig.add_trace( go.Bar( + y=ydata, + x=xdata, + textposition='outside', text=xdata, + orientation='h'), + row=2,col=3) + + + ydata = list(embenchSpeedOpt_SizeData["size results"]["detailed size results"].keys()) + ["size geometric mean","size geometric sd","size geometric range"] + xdata = list(embenchSpeedOpt_SizeData["size results"]["detailed size results"].values()) + [embenchSpeedOpt_SizeData["size results"]["size geometric mean"],embenchSpeedOpt_SizeData["size results"]["size geometric sd"],embenchSpeedOpt_SizeData["size results"]["size geometric range"]] + + fig.add_trace( go.Bar( + y=ydata, + x=xdata, + textposition='outside', text=xdata, + orientation='h'), + row=1,col=4) + + ydata = list(embenchSizeOpt_SizeData["size results"]["detailed size results"].keys()) + ["size geometric mean","size geometric sd","size geometric range"] + xdata = list(embenchSizeOpt_SizeData["size results"]["detailed size results"].values()) + [embenchSizeOpt_SizeData["size results"]["size geometric mean"],embenchSizeOpt_SizeData["size results"]["size geometric sd"],embenchSizeOpt_SizeData["size results"]["size geometric range"]] + + fig.add_trace( go.Bar( + y=ydata, + x=xdata, + textposition='outside', text=xdata, + orientation='h'), + row=2,col=4) + + # facet_row="Score", facet_col="Optimization Flag", + # category_orders={"Score": ["Cycles & Instr", "CPI", "SpeedScore", "SizeScore"], + # "Optimization Flag": ["O2", "Os"]}), + # orientation='h') + fig.update_layout(height=1500,width=4000, title_text="Wally Embench Scores", showlegend=False) + + fig.write_image("figure.png", engine="kaleido") + # fig.show() + + +def main(): + coremarkData = {} + embenchSizeOpt_SpeedData = {} + embenchSpeedOpt_SpeedData = {} + embenchSizeOpt_SizeData = {} + embenchSpeedOpt_SizeData = {} + # coremarkData = loadCoremark() + embenchSpeedOpt_SpeedData = loadEmbench("embench/wallySpeedOpt_speed.json", embenchSpeedOpt_SpeedData) + embenchSizeOpt_SpeedData = loadEmbench("embench/wallySizeOpt_speed.json", embenchSizeOpt_SpeedData) + embenchSpeedOpt_SizeData = loadEmbench("embench/wallySpeedOpt_size.json", embenchSpeedOpt_SizeData) + embenchSizeOpt_SizeData = loadEmbench("embench/wallySizeOpt_size.json", embenchSizeOpt_SizeData) + + graphEmbench(embenchSpeedOpt_SpeedData, embenchSizeOpt_SpeedData, embenchSpeedOpt_SizeData, embenchSizeOpt_SizeData) + +if __name__ == '__main__': + sys.exit(main()) + +# "ls -Art ../addins/embench-iot/logs/*speed* | tail -n 1 " # gets most recent embench speed log \ No newline at end of file diff --git a/benchmarks/riscv-coremark/.gitignore b/benchmarks/riscv-coremark/.gitignore deleted file mode 100644 index 0f2251abe..000000000 --- a/benchmarks/riscv-coremark/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -coremark.riscv -coremark.bare.riscv \ No newline at end of file diff --git a/benchmarks/riscv-coremark/.gitmodules b/benchmarks/riscv-coremark/.gitmodules deleted file mode 100644 index 938028cb7..000000000 --- a/benchmarks/riscv-coremark/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "coremark"] - path = coremark - url = https://github.com/eembc/coremark diff --git a/benchmarks/riscv-coremark/LICENSE b/benchmarks/riscv-coremark/LICENSE deleted file mode 100644 index 860ca9cc6..000000000 --- a/benchmarks/riscv-coremark/LICENSE +++ /dev/null @@ -1,29 +0,0 @@ -BSD 3-Clause License - -Copyright (c) 2017, Christopher Celio -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -* Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/benchmarks/riscv-coremark/Makefile b/benchmarks/riscv-coremark/Makefile deleted file mode 100644 index 2100b784f..000000000 --- a/benchmarks/riscv-coremark/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -#cmbase=../../addins/coremark -PORT_DIR = $(CURDIR)/riscv64-baremetal -cmbase=coremark -sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \ - $(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \ - $(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \ - $(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c - -work/coremark.bare.riscv.elf.memfile: work/coremark.bare.riscv - riscv64-unknown-elf-objdump -D $< > $<.elf.objdump - riscv64-unknown-elf-elf2hex --bit-width 64 --input $< --output $@ - extractFunctionRadix.sh $<.elf.objdump - -work/coremark.bare.riscv.objdump: work/coremark.bare.riscv - riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump - -work/coremark.bare.riscv: $(sources) Makefile -# make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fno-toplevel-reorder --param=max-inline-insns-size=128 -fipa-pta" - # These flags were used by WD on CoreMark - make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="-march=rv64imd -mabi=lp64d -mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-7-series -Ofast -funroll-all-loops -fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 -funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta " -# -fno-toplevel-reorder --param=max-inline-insns-size=128 " # adding this bit caused a compiler error - mkdir -p work/ - mv $(cmbase)/coremark.bare.riscv work/ - -.PHONY: clean - -clean: - rm -f work/* diff --git a/benchmarks/riscv-coremark/coremark/LICENSE.md b/benchmarks/riscv-coremark/coremark/LICENSE.md deleted file mode 100644 index 14e53e9ee..000000000 --- a/benchmarks/riscv-coremark/coremark/LICENSE.md +++ /dev/null @@ -1,100 +0,0 @@ -# COREMARK® ACCEPTABLE USE AGREEMENT - -This ACCEPTABLE USE AGREEMENT (this “Agreement”) is offered by Embedded Microprocessor Benchmark Consortium, a California nonprofit corporation (“Licensor”), to users of its CoreMark® software (“Licensee”) exclusively on the following terms. - -Licensor offers benchmarking software (“Software”) pursuant to an open source license, but carefully controls use of its benchmarks and their associated goodwill. Licensor has registered its trademark in one of the benchmarks available through the Software, COREMARK, Ser. No. 85/487,290; Reg. No. 4,179,307 (the “Trademark”), and promotes the use of a standard metric as a benchmark for assessing the performance of embedded systems. Solely on the terms described herein, Licensee may use and display the Trademark in connection with the generation of data regarding measurement and analysis of computer and embedded system benchmarking via the Software (the “Licensed Use”). - -## Article 1 – License Grant. -1.1. License. Subject to the terms and conditions of this Agreement, Licensor hereby grants to Licensee, and Licensee hereby accepts from Licensor, a personal, non-exclusive, royalty-free, revocable right and license to use and display the Trademark during the term of this Agreement (the “Term”), solely and exclusively in connection with the Licensed Use. During the Term, Licensee (i) shall not modify or otherwise create derivative works of the Trademark, and (ii) may use the Trademark only to the extent permitted under this License. Neither Licensee nor any affiliate or agent thereof shall otherwise use the Trademark without the prior express written consent of Licensor, which may be withheld in its sole and absolute discretion. All rights not expressly granted to Licensee hereunder shall remain the exclusive property of Licensor. - -1.2. Modifications to the Software. Licensee shall not use the Trademark in connection with any use of a modified, derivative, or otherwise altered copy of the Software. - -1.3. Licensor’s Use. Nothing in this Agreement shall preclude Licensor or any of its successors or assigns from using or permitting other entities to use the Trademark, whether or not such entity directly or indirectly competes or conflicts with Licensee’s Licensed Use in any manner. - -1.4. Term and Termination. This Agreement is perpetual unless terminated by either of the parties. Licensee may terminate this Agreement for convenience, without cause or liability, for any reason or for no reason whatsoever, upon ten (10) business days written notice. Licensor may terminate this Agreement effective immediately upon notice of breach. Upon termination, Licensee shall immediately remove all implementations of the Trademark from the Licensed Use, and delete all digitals files and records of all materials related to the Trademark. - -## Article 2 – Ownership. -2.1. Ownership. Licensee acknowledges and agrees that Licensor is the owner of all right, title, and interest in and to the Trademark, and all such right, title, and interest shall remain with Licensor. Licensee shall not contest, dispute, challenge, oppose, or seek to cancel Licensor’s right, title, and interest in and to the Trademark. Licensee shall not prosecute any application for registration of the Trademark. Licensee shall display appropriate notices regarding ownership of the Trademark in connection with the Licensed Use. - -2.2. Goodwill. Licensee acknowledges that Licensee shall not acquire any right, title, or interest in the Trademark by virtue of this Agreement other than the license granted hereunder, and disclaims any such right, title, interest, or ownership. All goodwill and reputation generated by Licensee’s use of the Trademark shall inure to the exclusive benefit of Licensor. Licensee shall not by any act or omission use the Trademark in any manner that disparages or reflects adversely on Licensor or its Licensed Use or reputation. Licensee shall not take any action that would interfere with or prejudice Licensor’s ownership or registration of the Trademark, the validity of the Trademark or the validity of the license granted by this Agreement. If Licensor determines and notifies Licensee that any act taken in connection with the Licensed Use (i) is inaccurate, unlawful or offensive to good taste; (ii) fails to provide for proper trademark notices, or (iii) otherwise violates Licensee’s obligations under this Agreement, the license granted under this Agreement shall terminate. - -## Article 3 – Indemnification. -3.1. Indemnification Generally. Licensee agrees to indemnify, defend, and hold harmless (collectively “indemnify” or “indemnification”) Licensor, including Licensor’s members, managers, officers, and employees (collectively “Related Persons”), from and against, and pay or reimburse Licensor and such Related Persons for, any and all third-party actions, claims, demands, proceedings, investigations, inquiries (collectively, “Claims”), and any and all liabilities, obligations, fines, deficiencies, costs, expenses, royalties, losses, and damages (including reasonable outside counsel fees and expenses) associated with such Claims, to the extent that such Claim arises out of (i) Licensee’s material breach of this Agreement, or (ii) any allegation(s) that Licensee’s actions infringe or violate any third-party intellectual property right, including without limitation, any U.S. copyright, patent, or trademark, or are otherwise found to be tortious or criminal (whether or not such indemnified person is a named party in a legal proceeding). - -3.2. Notice and Defense of Claims. Licensor shall promptly notify Licensee of any Claim for which indemnification is sought, following actual knowledge of such Claim, provided however that the failure to give such notice shall not relieve Licensee of its obligations hereunder except to the extent that Licensee is materially prejudiced by such failure. In the event that any third-party Claim is brought, Licensee shall have the right and option to undertake and control the defense of such action with counsel of its choice, provided however that (i) Licensor at its own expense may participate and appear on an equal footing with Licensee in the defense of any such Claim, (ii) Licensor may undertake and control such defense in the event of the material failure of Licensee to undertake and control the same; and (iii) the defense of any Claim relating to the intellectual property rights of Licensor or its licensors and any related counterclaims shall be solely controlled by Licensor with counsel of its choice. Licensee shall not consent to judgment or concede or settle or compromise any Claim without the prior written approval of Licensor (whose approval shall not be unreasonably withheld), unless such concession or settlement or compromise includes a full and unconditional release of Licensor and any applicable Related Persons from all liabilities in respect of such Claim. - -## Article 4 – Miscellaneous. -4.1. Relationship of the Parties. This Agreement does not create a partnership, franchise, joint venture, agency, fiduciary, or employment relationship between the parties. - -4.2. No Third-Party Beneficiaries. Except for the rights of Related Persons under Article 3 (Indemnification), there are no third-party beneficiaries to this Agreement. - -4.3. Assignment. Licensee’s rights hereunder are non-assignable, and may not be sublicensed. - -4.4. Equitable Relief. Licensee acknowledges that the remedies available at law for any breach of this Agreement will, by their nature, be inadequate. Accordingly, Licensor may obtain injunctive relief or other equitable relief to restrain a breach or threatened breach of this Agreement or to specifically enforce this Agreement, without proving that any monetary damages have been sustained, and without the requirement of posting of a bond prior to obtaining such equitable relief. - -4.5. Governing Law. This Agreement will be interpreted, construed, and enforced in all respects in accordance with the laws of the State of California, without reference to its conflict of law principles. - -4.6. Attorneys’ Fees. If any legal action, arbitration or other proceeding is brought for the enforcement of this Agreement, or because of an alleged dispute, breach, default, or misrepresentation in connection with any of the provisions of this Agreement, the successful or prevailing party shall be entitled to recover its reasonable attorneys’ fees and other reasonable costs incurred in that action or proceeding, in addition to any other relief to which it may be entitled. - -4.7. Amendment; Waiver. This Agreement may not be amended, nor may any rights under it be waived, except in writing by Licensor. - -4.8. Severability. If any provision of this Agreement is held by a court of competent jurisdiction to be contrary to law, the provision shall be modified by the court and interpreted so as best to accomplish the objectives of the original provision to the fullest extent -permitted by law, and the remaining provisions of this Agreement shall remain in effect. - -4.9. Entire Agreement. This Agreement constitutes the entire agreement between the parties and supersedes all prior and contemporaneous agreements, proposals or representations, written or oral, concerning its subject matter. - - -# Apache License - -Version 2.0, January 2004 - -http://www.apache.org/licenses/ - -## TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - -1. Definitions. - -"License" shall mean the terms and conditions for use, reproduction, and distribution as defined by Sections 1 through 9 of this document. - -"Licensor" shall mean the copyright owner or entity authorized by the copyright owner that is granting the License. - -"Legal Entity" shall mean the union of the acting entity and all other entities that control, are controlled by, or are under common control with that entity. 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While redistributing the Work or Derivative Works thereof, You may choose to offer, and charge a fee for, acceptance of support, warranty, indemnity, or other liability obligations and/or rights consistent with this License. However, in accepting such obligations, You may act only on Your own behalf and on Your sole responsibility, not on behalf of any other Contributor, and only if You agree to indemnify, defend, and hold each Contributor harmless for any liability incurred by, or claims asserted against, such Contributor by reason of your accepting any such warranty or additional liability. - -END OF TERMS AND CONDITIONS diff --git a/benchmarks/riscv-coremark/coremark/Makefile b/benchmarks/riscv-coremark/coremark/Makefile deleted file mode 100644 index 51760d1dd..000000000 --- a/benchmarks/riscv-coremark/coremark/Makefile +++ /dev/null @@ -1,139 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -# Make sure the default target is to simply build and run the benchmark. -RSTAMP = v1.0 - -.PHONY: run score -run: $(OUTFILE) rerun score - -score: - @echo "Check run1.log and run2.log for results." - @echo "See README.md for run and reporting rules." - -ifndef PORT_DIR -# Ports for a couple of common self hosted platforms -UNAME=$(shell if command -v uname 2> /dev/null; then uname ; fi) -ifneq (,$(findstring CYGWIN,$(UNAME))) -PORT_DIR=cygwin -endif -ifneq (,$(findstring Linux,$(UNAME))) -MACHINE=$(shell uname -m) -ifneq (,$(findstring 64,$(MACHINE))) -PORT_DIR=linux64 -else -PORT_DIR=linux -endif -endif -endif -ifndef PORT_DIR -$(error PLEASE define PORT_DIR! (e.g. make PORT_DIR=simple)) -endif -vpath %.c $(PORT_DIR) -vpath %.h $(PORT_DIR) -vpath %.mak $(PORT_DIR) -include $(PORT_DIR)/core_portme.mak - -ifndef $(ITERATIONS) -ITERATIONS=0 -endif -ifdef REBUILD -FORCE_REBUILD=force_rebuild -endif - -CFLAGS += -DITERATIONS=$(ITERATIONS) - -CORE_FILES = core_list_join core_main core_matrix core_state core_util -ORIG_SRCS = $(addsuffix .c,$(CORE_FILES)) -SRCS = $(ORIG_SRCS) $(PORT_SRCS) -OBJS = $(addprefix $(OPATH),$(addsuffix $(OEXT),$(CORE_FILES)) $(PORT_OBJS)) -OUTNAME = coremark$(EXE) -OUTFILE = $(OPATH)$(OUTNAME) -LOUTCMD = $(OFLAG) $(OUTFILE) $(LFLAGS_END) -OUTCMD = $(OUTFLAG) $(OUTFILE) $(LFLAGS_END) - -HEADERS = coremark.h -CHECK_FILES = $(ORIG_SRCS) $(HEADERS) - -$(OPATH): - $(MKDIR) $(OPATH) - -.PHONY: compile link -ifdef SEPARATE_COMPILE -$(OPATH)$(PORT_DIR): - $(MKDIR) $(OPATH)$(PORT_DIR) - -compile: $(OPATH) $(OPATH)$(PORT_DIR) $(OBJS) $(HEADERS) -link: compile - $(LD) $(LFLAGS) $(XLFLAGS) $(OBJS) $(LOUTCMD) - -else - -compile: $(OPATH) $(SRCS) $(HEADERS) - $(CC) $(CFLAGS) $(XCFLAGS) $(SRCS) $(OUTCMD) -link: compile - @echo "Link performed along with compile" - -endif - -$(OUTFILE): $(SRCS) $(HEADERS) Makefile core_portme.mak $(FORCE_REBUILD) - $(MAKE) port_prebuild - $(MAKE) link - $(MAKE) port_postbuild - -.PHONY: rerun -rerun: - $(MAKE) XCFLAGS="$(XCFLAGS) -DPERFORMANCE_RUN=1" load run1.log - $(MAKE) XCFLAGS="$(XCFLAGS) -DVALIDATION_RUN=1" load run2.log - -PARAM1=$(PORT_PARAMS) 0x0 0x0 0x66 $(ITERATIONS) -PARAM2=$(PORT_PARAMS) 0x3415 0x3415 0x66 $(ITERATIONS) -PARAM3=$(PORT_PARAMS) 8 8 8 $(ITERATIONS) - -run1.log-PARAM=$(PARAM1) 7 1 2000 -run2.log-PARAM=$(PARAM2) 7 1 2000 -run3.log-PARAM=$(PARAM3) 7 1 1200 - -run1.log run2.log run3.log: load - $(MAKE) port_prerun - $(RUN) $(OUTFILE) $($(@)-PARAM) > $(OPATH)$@ - $(MAKE) port_postrun - -.PHONY: gen_pgo_data -gen_pgo_data: run3.log - -.PHONY: load -load: $(OUTFILE) - $(MAKE) port_preload - $(LOAD) $(OUTFILE) - $(MAKE) port_postload - -.PHONY: clean -clean: - rm -f $(OUTFILE) $(OPATH)*.log *.info $(OPATH)index.html $(PORT_CLEAN) - -.PHONY: force_rebuild -force_rebuild: - echo "Forcing Rebuild" - -.PHONY: check -check: - md5sum -c coremark.md5 - -ifdef ETC -# Targets related to testing and releasing CoreMark. Not part of the general release! -include Makefile.internal -endif diff --git a/benchmarks/riscv-coremark/coremark/README.md b/benchmarks/riscv-coremark/coremark/README.md deleted file mode 100644 index 16b54b7b3..000000000 --- a/benchmarks/riscv-coremark/coremark/README.md +++ /dev/null @@ -1,398 +0,0 @@ - -# Introduction - -CoreMark's primary goals are simplicity and providing a method for testing only a processor's core features. For more information about EEMBC's comprehensive embedded benchmark suites, please see www.eembc.org. - -For a more compute-intensive version of CoreMark that uses larger datasets and execution loops taken from common applications, please check out EEMBC's [CoreMark-PRO](https://www.github.com/eembc/coremark-pro) benchmark, also on GitHub. - -# Building and Running - -To build and run the benchmark, type - -`> make` - -Full results are available in the files `run1.log` and `run2.log`. CoreMark result can be found in `run1.log`. - -## Cross Compiling - -For cross compile platforms please adjust `core_portme.mak`, `core_portme.h` (and possibly `core_portme.c`) according to the specific platform used. When porting to a new platform, it is recommended to copy one of the default port folders (e.g. `mkdir && cp linux/* `), adjust the porting files, and run: -~~~ -% make PORT_DIR= -~~~ - -## Make Targets -`run` - Default target, creates `run1.log` and `run2.log`. -`run1.log` - Run the benchmark with performance parameters, and output to `run1.log` -`run2.log` - Run the benchmark with validation parameters, and output to `run2.log` -`run3.log` - Run the benchmark with profile generation parameters, and output to `run3.log` -`compile` - compile the benchmark executable -`link` - link the benchmark executable -`check` - test MD5 of sources that may not be modified -`clean` - clean temporary files - -### Make flag: `ITERATIONS` -By default, the benchmark will run between 10-100 seconds. To override, use `ITERATIONS=N` -~~~ -% make ITERATIONS=10 -~~~ -Will run the benchmark for 10 iterations. It is recommended to set a specific number of iterations in certain situations e.g.: - -* Running with a simulator -* Measuring power/energy -* Timing cannot be restarted - -Minimum required run time: **Results are only valid for reporting if the benchmark ran for at least 10 secs!** - -### Make flag: `XCFLAGS` -To add compiler flags from the command line, use `XCFLAGS` e.g.: - -~~~ -% make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1" -~~~ - -### Make flag: `CORE_DEBUG` - -Define to compile for a debug run if you get incorrect CRC. - -~~~ -% make XCFLAGS="-DCORE_DEBUG=1" -~~~ - -### Make flag: `REBUILD` - -Force a rebuild of the executable. - -## Systems Without `make` -The following files need to be compiled: -* `core_list_join.c` -* `core_main.c` -* `core_matrix.c` -* `core_state.c` -* `core_util.c` -* `PORT_DIR/core_portme.c` - -For example: -~~~ -% gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000 -% ./coremark.exe > run1.log -~~~ -The above will compile the benchmark for a performance run and 1000 iterations. Output is redirected to `run1.log`. - -# Parallel Execution -Use `XCFLAGS=-DMULTITHREAD=N` where N is number of threads to run in parallel. Several implementations are available to execute in multiple contexts, or you can implement your own in `core_portme.c`. - -~~~ -% make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD" -~~~ - -The above will compile the benchmark for execution on 4 cores, using POSIX Threads API. - -Note: linking may fail on the previous command if your linker does not automatically add the `pthread` library. If you encounter `undefined reference` errors, please modify the `core_portme.mak` file for your platform, (e.g. `linux/core_portme.mak`) and add `-lpthread` to the `LFLAGS_END` parameter. - -# Run Parameters for the Benchmark Executable -CoreMark's executable takes several parameters as follows (but only if `main()` accepts arguments): -1st - A seed value used for initialization of data. -2nd - A seed value used for initialization of data. -3rd - A seed value used for initialization of data. -4th - Number of iterations (0 for auto : default value) -5th - Reserved for internal use. -6th - Reserved for internal use. -7th - For malloc users only, ovreride the size of the input data buffer. - -The run target from make will run coremark with 2 different data initialization seeds. - -## Alternative parameters: -If not using `malloc` or command line arguments are not supported, the buffer size -for the algorithms must be defined via the compiler define `TOTAL_DATA_SIZE`. -`TOTAL_DATA_SIZE` must be set to 2000 bytes (default) for standard runs. -The default for such a target when testing different configurations could be: - -~~~ -% make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1" -~~~ - -# Submitting Results - -CoreMark results can be submitted on the web. Open a web browser and go to the [submission page](https://www.eembc.org/coremark/submit.php). After registering an account you may enter a score. - -# Run Rules -What is and is not allowed. - -## Required -1. The benchmark needs to run for at least 10 seconds. -2. All validation must succeed for seeds `0,0,0x66` and `0x3415,0x3415,0x66`, buffer size of 2000 bytes total. - * If not using command line arguments to main: -~~~ - % make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log - % make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log -~~~ -3. If using profile guided optimization, profile must be generated using seeds of `8,8,8`, and buffer size of 1200 bytes total. -~~~ - % make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log -~~~ -4. All source files must be compiled with the same flags. -5. All data type sizes must match size in bits such that: - * `ee_u8` is an unsigned 8-bit datatype. - * `ee_s16` is a signed 16-bit datatype. - * `ee_u16` is an unsigned 16-bit datatype. - * `ee_s32` is a signed 32-bit datatype. - * `ee_u32` is an unsigned 32-bit datatype. - -## Allowed - -1. Changing number of iterations -2. Changing toolchain and build/load/run options -3. Changing method of acquiring a data memory block -5. Changing the method of acquiring seed values -6. Changing implementation `in core_portme.c` -7. Changing configuration values in `core_portme.h` -8. Changing `core_portme.mak` - -## NOT ALLOWED -1. Changing of source file other then `core_portme*` (use `make check` to validate) - -# Reporting rules -Use the following syntax to report results on a data sheet: - -CoreMark 1.0 : N / C [/ P] [/ M] - -N - Number of iterations per second with seeds 0,0,0x66,size=2000) - -C - Compiler version and flags - -P - Parameters such as data and code allocation specifics - -* This parameter *may* be omitted if all data was allocated on the heap in RAM. -* This parameter *may not* be omitted when reporting CoreMark/MHz - -M - Type of parallel execution (if used) and number of contexts -* This parameter may be omitted if parallel execution was not used. - -e.g.: - -~~~ -CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2 -~~~ -or -~~~ -CoreMark 1.0 : 1400 / GCC 3.4 -O4 -~~~ - -If reporting scaling results, the results must be reported as follows: - -CoreMark/MHz 1.0 : N / C / P [/ M] - -P - When reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio. -1. If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included. - -e.g.: - -~~~ -CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache -~~~ - -# Log File Format -The log files have the following format - -~~~ -2K performance run parameters for coremark. (Run type) -CoreMark Size : 666 (Buffer size) -Total ticks : 25875 (platform dependent value) -Total time (secs) : 25.875000 (actual time in seconds) -Iterations/Sec : 3864.734300 (Performance value to report) -Iterations : 100000 (number of iterations used) -Compiler version : GCC3.4.4 (Compiler and version) -Compiler flags : -O2 (Compiler and linker flags) -Memory location : Code in flash, data in on chip RAM -seedcrc : 0xe9f5 (identifier for the input seeds) -[0]crclist : 0xe714 (validation for list part) -[0]crcmatrix : 0x1fd7 (validation for matrix part) -[0]crcstate : 0x8e3a (validation for state part) -[0]crcfinal : 0x33ff (iteration dependent output) -Correct operation validated. See README.md for run and reporting rules. (*Only when run is successful*) -CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap (*Only on a successful performance run*) -~~~ - -# Theory of Operation - -This section describes the initial goals of CoreMark and their implementation. - -## Small and easy to understand - -* X number of source code lines for timed portion of the benchmark. -* Meaningful names for variables and functions. -* Comments for each block of code more than 10 lines long. - -## Portability - -A thin abstraction layer will be provided for I/O and timing in a separate file. All I/O and timing of the benchmark will be done through this layer. - -### Code / data size - -* Compile with gcc on x86 and make sure all sizes are according to requirements. -* If dynamic memory allocation is used, take total memory allocated into account as well. -* Avoid recursive functions and keep track of stack usage. -* Use the same memory block as data site for all algorithms, and initialize the data before each algorithm – while this means that initialization with data happens during the timed portion, it will only happen once during the timed portion and so have negligible effect on the results. - -## Controlled output - -This may be the most difficult goal. Compilers are constantly improving and getting better at analyzing code. To create work that cannot be computed at compile time and must be computed at run time, we will rely on two assumptions: - -* Some system functions (e.g. time, scanf) and parameters cannot be computed at compile time. In most cases, marking a variable volatile means the compiler is force to read this variable every time it is read. This will be used to introduce a factor into the input that cannot be precomputed at compile time. Since the results are input dependent, that will make sure that computation has to happen at run time. - -* Either a system function or I/O (e.g. scanf) or command line parameters or volatile variables will be used before the timed portion to generate data which is not available at compile time. Specific method used is not relevant as long as it can be controlled, and that it cannot be computed or eliminated by the compiler at compile time. E.g. if the clock() functions is a compiler stub, it may not be used. The derived values will be reported on the output so that verification can be done on a different machine. - -* We cannot rely on command line parameters since some embedded systems do not have the capability to provide command line parameters. All 3 methods above will be implemented (time based, scanf and command line parameters) and all 3 are valid if the compiler cannot determine the value at compile time. - -* It is important to note that The actual values that are to be supplied at run time will be standardized. The methodology is not intended to provide random data, but simply to provide controlled data that cannot be precomputed at compile time. - -* Printed results must be valid at run time. This will be used to make sure the computation has been executed. - -* Some embedded systems do not provide “printf” or other I/O functionality. All I/O will be done through a thin abstraction interface to allow execution on such systems (e.g. allow output via JTAG). - -## Key Algorithms - -### Linked List - -The following linked list structure will be used: - -~~~ -typedef struct list_data_s { - ee_s16 data16; - ee_s16 idx; -} list_data; - -typedef struct list_head_s { - struct list_head_s *next; - struct list_data_s *info; -} list_head; -~~~ - -While adding a level of indirection accessing the data, this structure is realistic and used in many embedded applications for small to medium lists. - -The list itself will be initialized on a block of memory that will be passed in to the initialization function. While in general linked lists use malloc for new nodes, embedded applications sometime control the memory for small data structures such as arrays and lists directly to avoid the overhead of system calls, so this approach is realistic. - -The linked list will be initialized such that 1/4 of the list pointers point to sequential areas in memory, and 3/4 of the list pointers are distributed in a non sequential manner. This is done to emulate a linked list that had add/remove happen for a while disrupting the neat order, and then a series of adds that are likely to come from sequential memory locations. - -For the benchmark itself: -- Multiple find operations are going to be performed. These find operations may result in the whole list being traversed. The result of each find will become part of the output chain. -- The list will be sorted using merge sort based on the data16 value, and then derive CRC of the data16 item in order for part of the list. The CRC will become part of the output chain. -- The list will be sorted again using merge sort based on the idx value. This sort will guarantee that the list is returned to the primary state before leaving the function, so that multiple iterations of the function will have the same result. CRC of the data16 for part of the list will again be calculated and become part of the output chain. - -The actual `data16` in each cell will be pseudo random based on a single 16b input that cannot be determined at compile time. In addition, the part of the list which is used for CRC will also be passed to the function, and determined based on an input that cannot be determined at run time. - -### Matrix Multiply - -This very simple algorithm forms the basis of many more complex algorithms. The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing. - -The total available data space will be divided to 3 parts: -1. NxN matrix A. -2. NxN matrix B. -3. NxN matrix C. - -E.g. for 2K we will have 3 12x12 matrices (assuming data type of 32b 12(len)*12(wid)*4(size)*3(num) =1728 bytes). - -Matrix A will be initialized with small values (upper 3/4 of the bits all zero). -Matrix B will be initialized with medium values (upper half of the bits all zero). -Matrix C will be used for the result. - -For the benchmark itself: -- Multiple A by a constant into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. -- Multiple A by column X of B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. -- Multiple A by B into C, add the upper bits of each of the values in the result matrix. The result will become part of the output chain. - -The actual values for A and B must be derived based on input that is not available at compile time. - -### State Machine - -This part of the code needs to exercise switch and if statements. As such, we will use a small Moore state machine. In particular, this will be a state machine that identifies string input as numbers and divides them according to format. - -The state machine will parse the input string until either a “,” separator or end of input is encountered. An invalid number will cause the state machine to return invalid state and a valid number will cause the state machine to return with type of number format (int/float/scientific). - -This code will perform a realistic task, be small enough to easily understand, and exercise the required functionality. The other option used in embedded systems is a mealy based state machine, which is driven by a table. The table then determines the number of states and complexity of transitions. This approach, however, tests mainly the load/store and function call mechanisms and less the handling of branches. If analysis of the final results shows that the load/store functionality of the processor is not exercised thoroughly, it may be a good addition to the benchmark (codesize allowing). - -For input, the memory block will be initialized with comma separated values of mixed formats, as well as invalid inputs. - -For the benchmark itself: -- Invoke the state machine on all of the input and count final states and state transitions. CRC of all final states and transitions will become part of the output chain. -- Modify the input at intervals (inject errors) and repeat the state machine operation. -- Modify the input back to original form. - -The actual input must be initialized based on data that cannot be determined at compile time. In addition the intervals for modification of the input and the actual modification must be based on input that cannot be determined at compile time. - -# Validation - -This release was tested on the following platforms: -* x86 cygwin and gcc 3.4 (Quad, dual and single core systems) -* x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems) -* MIPS64 BE linux and gcc 3.4 16 cores system -* MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system -* PPC simulator with gcc 4.2.2 (No OS) -* PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system) -* BF533 with VDSP50 -* Renesas R8C/H8 MCU with HEW 4.05 -* NXP LPC1700 armcc v4.0.0.524 -* NEC 78K with IAR v4.61 -* ARM simulator with armcc v4 - -# Memory Analysis - -Valgrind 3.4.0 used and no errors reported. - -# Balance Analysis - -Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0. - -# Statistics - -Lines: -~~~ -Lines Blank Cmnts Source AESL -===== ===== ===== ===== ========== ======================================= - 469 66 170 251 627.5 core_list_join.c (C) - 330 18 54 268 670.0 core_main.c (C) - 256 32 80 146 365.0 core_matrix.c (C) - 240 16 51 186 465.0 core_state.c (C) - 165 11 20 134 335.0 core_util.c (C) - 150 23 36 98 245.0 coremark.h (C) - 1610 166 411 1083 2707.5 ----- Benchmark ----- (6 files) - 293 15 74 212 530.0 linux/core_portme.c (C) - 235 30 104 104 260.0 linux/core_portme.h (C) - 528 45 178 316 790.0 ----- Porting ----- (2 files) - -* For comparison, here are the stats for Dhrystone -Lines Blank Cmnts Source AESL -===== ===== ===== ===== ========== ======================================= - 311 15 242 54 135.0 dhry.h (C) - 789 132 119 553 1382.5 dhry_1.c (C) - 186 26 68 107 267.5 dhry_2.c (C) - 1286 173 429 714 1785.0 ----- C ----- (3 files) -~~~ - -# Credits -Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name; note that company names may no longer be accurate as this was written in 2009). -* Alan Anderson, ADI -* Adhikary Rajiv, ADI -* Elena Stohr, ARM -* Ian Rickards, ARM -* Andrew Pickard, ARM -* Trent Parker, CAVIUM -* Shay Gal-On, EEMBC -* Markus Levy, EEMBC -* Peter Torelli, EEMBC -* Ron Olson, IBM -* Eyal Barzilay, MIPS -* Jens Eltze, NEC -* Hirohiko Ono, NEC -* Ulrich Drees, NEC -* Frank Roscheda, NEC -* Rob Cosaro, NXP -* Shumpei Kawasaki, RENESAS - -# Legal -Please refer to LICENSE.md in this reposity for a description of your rights to use this code. - -# Copyright -Copyright © 2009 EEMBC All rights reserved. -CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium. - diff --git a/benchmarks/riscv-coremark/coremark/barebones/core_portme.c b/benchmarks/riscv-coremark/coremark/barebones/core_portme.c deleted file mode 100644 index 18967676b..000000000 --- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.c +++ /dev/null @@ -1,153 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ -#include "coremark.h" -#include "core_portme.h" - -#if VALIDATION_RUN -volatile ee_s32 seed1_volatile = 0x3415; -volatile ee_s32 seed2_volatile = 0x3415; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PERFORMANCE_RUN -volatile ee_s32 seed1_volatile = 0x0; -volatile ee_s32 seed2_volatile = 0x0; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PROFILE_RUN -volatile ee_s32 seed1_volatile = 0x8; -volatile ee_s32 seed2_volatile = 0x8; -volatile ee_s32 seed3_volatile = 0x8; -#endif -volatile ee_s32 seed4_volatile = ITERATIONS; -volatile ee_s32 seed5_volatile = 0; -/* Porting : Timing functions - How to capture time and convert to seconds must be ported to whatever is - supported by the platform. e.g. Read value from on board RTC, read value from - cpu clock cycles performance counter etc. Sample implementation for standard - time.h and windows.h definitions included. -*/ -CORETIMETYPE -barebones_clock() -{ -#error \ - "You must implement a method to measure time in barebones_clock()! This function should return current time.\n" -} -/* Define : TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be - measured. - - Use lower values to increase resolution, but make sure that overflow - does not occur. If there are issues with the return value overflowing, - increase this value. - */ -#define GETMYTIME(_t) (*_t = barebones_clock()) -#define MYTIMEDIFF(fin, ini) ((fin) - (ini)) -#define TIMER_RES_DIVIDER 1 -#define SAMPLE_TIME_IMPLEMENTATION 1 -#define EE_TICKS_PER_SEC (CLOCKS_PER_SEC / TIMER_RES_DIVIDER) - -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function : start_time - This function will be called right before starting the timed portion of - the benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or zeroing some system parameters - e.g. setting the cpu clocks - cycles to 0. -*/ -void -start_time(void) -{ - GETMYTIME(&start_time_val); -} -/* Function : stop_time - This function will be called right after ending the timed portion of the - benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or other system parameters - e.g. reading the current value of - cpu cycles counter. -*/ -void -stop_time(void) -{ - GETMYTIME(&stop_time_val); -} -/* Function : get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other - value, as long as it can be converted to seconds by . This - methodology is taken to accomodate any hardware or simulated platform. The - sample implementation returns millisecs by default, and the resolution is - controlled by -*/ -CORE_TICKS -get_time(void) -{ - CORE_TICKS elapsed - = (CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function : time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for - floating point. Default implementation implemented by the EE_TICKS_PER_SEC - macro above. -*/ -secs_ret -time_in_secs(CORE_TICKS ticks) -{ - secs_ret retval = ((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} - -ee_u32 default_num_contexts = 1; - -/* Function : portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void -portable_init(core_portable *p, int *argc, char *argv[]) -{ -#error \ - "Call board initialization routines in portable init (if needed), in particular initialize UART!\n" - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) - { - ee_printf( - "ERROR! Please define ee_ptr_int to a type that holds a " - "pointer!\n"); - } - if (sizeof(ee_u32) != 4) - { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } - p->portable_id = 1; -} -/* Function : portable_fini - Target specific final code -*/ -void -portable_fini(core_portable *p) -{ - p->portable_id = 0; -} diff --git a/benchmarks/riscv-coremark/coremark/barebones/core_portme.h b/benchmarks/riscv-coremark/coremark/barebones/core_portme.h deleted file mode 100644 index 55f643bf3..000000000 --- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.h +++ /dev/null @@ -1,210 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ -/* Topic : Description - This file contains configuration constants required to execute on - different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration : HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration : HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration : USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 1 -#endif -/* Configuration : HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 0 -#endif -/* Configuration : HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf - function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 0 -#endif - -/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION -#ifdef __GNUC__ -#define COMPILER_VERSION "GCC"__VERSION__ -#else -#define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" -#endif -#endif -#ifndef COMPILER_FLAGS -#define COMPILER_FLAGS \ - FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION -#define MEM_LOCATION "STACK" -#endif - -/* Data Types : - To avoid compiler issues, define the data types that need ot be used for - 8b, 16b and 32b in . - - *Imprtant* : - ee_ptr_int needs to be the data type used to hold pointers, otherwise - coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -#define NULL ((void *)0) -/* align_mem : - This macro is used to align an offset to point to a 32b value. It is - used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) - -/* Configuration : CORE_TICKS - Define type of return from the timing functions. - */ -#define CORETIMETYPE ee_u32 -typedef ee_u32 CORE_TICKS; - -/* Configuration : SEED_METHOD - Defines method to get seed values that cannot be computed at compile - time. - - Valid values : - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_VOLATILE -#endif - -/* Configuration : MEM_METHOD - Defines method to get a block of memry. - - Valid values : - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_STACK -#endif - -/* Configuration : MULTITHREAD - Define for parallel execution - - Valid values : - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note : - If this flag is defined to more then 1, an implementation for launching - parallel contexts must be defined. - - Two sample implementations are provided. Use or - to enable them. - - It is valid to have a different implementation of - and in , to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#define USE_PTHREAD 0 -#define USE_FORK 0 -#define USE_SOCKET 0 -#endif - -/* Configuration : MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values : - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported - - Note : - This flag only matters if MULTITHREAD has been defined to a value - greater then 1. -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration : MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values : - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable : default_num_contexts - Not used for this simple port, must cintain the value 1. -*/ -extern ee_u32 default_num_contexts; - -typedef struct CORE_PORTABLE_S -{ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) \ - && !defined(VALIDATION_RUN) -#if (TOTAL_DATA_SIZE == 1200) -#define PROFILE_RUN 1 -#elif (TOTAL_DATA_SIZE == 2000) -#define PERFORMANCE_RUN 1 -#else -#define VALIDATION_RUN 1 -#endif -#endif - -int ee_printf(const char *fmt, ...); - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/barebones/core_portme.mak b/benchmarks/riscv-coremark/coremark/barebones/core_portme.mak deleted file mode 100755 index 81594697d..000000000 --- a/benchmarks/riscv-coremark/coremark/barebones/core_portme.mak +++ /dev/null @@ -1,87 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File : core_portme.mak - -# Flag : OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag : CC -# Use this flag to define compiler to use -CC = gcc -# Flag : LD -# Use this flag to define compiler to use -LD = gld -# Flag : AS -# Use this flag to define compiler to use -AS = gas -# Flag : CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -PORT_CFLAGS = -O0 -g -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -#Flag : LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -SEPARATE_COMPILE=1 -# Flag : SEPARATE_COMPILE -# You must also define below how to create an object file, and how to link. -OBJOUT = -o -LFLAGS = -ASFLAGS = -OFLAG = -o -COUT = -c - -LFLAGS_END = -# Flag : PORT_SRCS -# Port specific source files can be added here -# You may also need cvt.c if the fcvt functions are not provided as intrinsics by your compiler! -PORT_SRCS = $(PORT_DIR)/core_portme.c $(PORT_DIR)/ee_printf.c -vpath %.c $(PORT_DIR) -vpath %.s $(PORT_DIR) - -# Flag : LOAD -# For a simple port, we assume self hosted compile and run, no load needed. - -# Flag : RUN -# For a simple port, we assume self hosted compile and run, simple invocation of the executable - -LOAD = echo "Please set LOAD to the process of loading the executable to the flash" -RUN = echo "Please set LOAD to the process of running the executable (e.g. via jtag, or board reset)" - -OEXT = .o -EXE = .bin - -$(OPATH)$(PORT_DIR)/%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -$(OPATH)%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -$(OPATH)$(PORT_DIR)/%$(OEXT) : %.s - $(AS) $(ASFLAGS) $< $(OBJOUT) $@ - -# Target : port_pre% and port_post% -# For the purpose of this simple port, no pre or post steps needed. - -.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload -port_pre% port_post% : - -# FLAG : OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - diff --git a/benchmarks/riscv-coremark/coremark/barebones/cvt.c b/benchmarks/riscv-coremark/coremark/barebones/cvt.c deleted file mode 100644 index 333e8ead2..000000000 --- a/benchmarks/riscv-coremark/coremark/barebones/cvt.c +++ /dev/null @@ -1,127 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -*/ -#include -#define CVTBUFSIZE 80 -static char CVTBUF[CVTBUFSIZE]; - -static char * -cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag) -{ - int r2; - double fi, fj; - char * p, *p1; - - if (ndigits < 0) - ndigits = 0; - if (ndigits >= CVTBUFSIZE - 1) - ndigits = CVTBUFSIZE - 2; - r2 = 0; - *sign = 0; - p = &buf[0]; - if (arg < 0) - { - *sign = 1; - arg = -arg; - } - arg = modf(arg, &fi); - p1 = &buf[CVTBUFSIZE]; - - if (fi != 0) - { - p1 = &buf[CVTBUFSIZE]; - while (fi != 0) - { - fj = modf(fi / 10, &fi); - *--p1 = (int)((fj + .03) * 10) + '0'; - r2++; - } - while (p1 < &buf[CVTBUFSIZE]) - *p++ = *p1++; - } - else if (arg > 0) - { - while ((fj = arg * 10) < 1) - { - arg = fj; - r2--; - } - } - p1 = &buf[ndigits]; - if (eflag == 0) - p1 += r2; - *decpt = r2; - if (p1 < &buf[0]) - { - buf[0] = '\0'; - return buf; - } - while (p <= p1 && p < &buf[CVTBUFSIZE]) - { - arg *= 10; - arg = modf(arg, &fj); - *p++ = (int)fj + '0'; - } - if (p1 >= &buf[CVTBUFSIZE]) - { - buf[CVTBUFSIZE - 1] = '\0'; - return buf; - } - p = p1; - *p1 += 5; - while (*p1 > '9') - { - *p1 = '0'; - if (p1 > buf) - ++*--p1; - else - { - *p1 = '1'; - (*decpt)++; - if (eflag == 0) - { - if (p > buf) - *p = '0'; - p++; - } - } - } - *p = '\0'; - return buf; -} - -char * -ecvt(double arg, int ndigits, int *decpt, int *sign) -{ - return cvt(arg, ndigits, decpt, sign, CVTBUF, 1); -} - -char * -ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf) -{ - return cvt(arg, ndigits, decpt, sign, buf, 1); -} - -char * -fcvt(double arg, int ndigits, int *decpt, int *sign) -{ - return cvt(arg, ndigits, decpt, sign, CVTBUF, 0); -} - -char * -fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf) -{ - return cvt(arg, ndigits, decpt, sign, buf, 0); -} diff --git a/benchmarks/riscv-coremark/coremark/barebones/ee_printf.c b/benchmarks/riscv-coremark/coremark/barebones/ee_printf.c deleted file mode 100644 index f2d362dc0..000000000 --- a/benchmarks/riscv-coremark/coremark/barebones/ee_printf.c +++ /dev/null @@ -1,700 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. -*/ - -#include -#include - -#define ZEROPAD (1 << 0) /* Pad with zero */ -#define SIGN (1 << 1) /* Unsigned/signed long */ -#define PLUS (1 << 2) /* Show plus */ -#define SPACE (1 << 3) /* Spacer */ -#define LEFT (1 << 4) /* Left justified */ -#define HEX_PREP (1 << 5) /* 0x */ -#define UPPERCASE (1 << 6) /* 'ABCDEF' */ - -#define is_digit(c) ((c) >= '0' && (c) <= '9') - -static char * digits = "0123456789abcdefghijklmnopqrstuvwxyz"; -static char * upper_digits = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; -static ee_size_t strnlen(const char *s, ee_size_t count); - -static ee_size_t -strnlen(const char *s, ee_size_t count) -{ - const char *sc; - for (sc = s; *sc != '\0' && count--; ++sc) - ; - return sc - s; -} - -static int -skip_atoi(const char **s) -{ - int i = 0; - while (is_digit(**s)) - i = i * 10 + *((*s)++) - '0'; - return i; -} - -static char * -number(char *str, long num, int base, int size, int precision, int type) -{ - char c, sign, tmp[66]; - char *dig = digits; - int i; - - if (type & UPPERCASE) - dig = upper_digits; - if (type & LEFT) - type &= ~ZEROPAD; - if (base < 2 || base > 36) - return 0; - - c = (type & ZEROPAD) ? '0' : ' '; - sign = 0; - if (type & SIGN) - { - if (num < 0) - { - sign = '-'; - num = -num; - size--; - } - else if (type & PLUS) - { - sign = '+'; - size--; - } - else if (type & SPACE) - { - sign = ' '; - size--; - } - } - - if (type & HEX_PREP) - { - if (base == 16) - size -= 2; - else if (base == 8) - size--; - } - - i = 0; - - if (num == 0) - tmp[i++] = '0'; - else - { - while (num != 0) - { - tmp[i++] = dig[((unsigned long)num) % (unsigned)base]; - num = ((unsigned long)num) / (unsigned)base; - } - } - - if (i > precision) - precision = i; - size -= precision; - if (!(type & (ZEROPAD | LEFT))) - while (size-- > 0) - *str++ = ' '; - if (sign) - *str++ = sign; - - if (type & HEX_PREP) - { - if (base == 8) - *str++ = '0'; - else if (base == 16) - { - *str++ = '0'; - *str++ = digits[33]; - } - } - - if (!(type & LEFT)) - while (size-- > 0) - *str++ = c; - while (i < precision--) - *str++ = '0'; - while (i-- > 0) - *str++ = tmp[i]; - while (size-- > 0) - *str++ = ' '; - - return str; -} - -static char * -eaddr(char *str, unsigned char *addr, int size, int precision, int type) -{ - char tmp[24]; - char *dig = digits; - int i, len; - - if (type & UPPERCASE) - dig = upper_digits; - len = 0; - for (i = 0; i < 6; i++) - { - if (i != 0) - tmp[len++] = ':'; - tmp[len++] = dig[addr[i] >> 4]; - tmp[len++] = dig[addr[i] & 0x0F]; - } - - if (!(type & LEFT)) - while (len < size--) - *str++ = ' '; - for (i = 0; i < len; ++i) - *str++ = tmp[i]; - while (len < size--) - *str++ = ' '; - - return str; -} - -static char * -iaddr(char *str, unsigned char *addr, int size, int precision, int type) -{ - char tmp[24]; - int i, n, len; - - len = 0; - for (i = 0; i < 4; i++) - { - if (i != 0) - tmp[len++] = '.'; - n = addr[i]; - - if (n == 0) - tmp[len++] = digits[0]; - else - { - if (n >= 100) - { - tmp[len++] = digits[n / 100]; - n = n % 100; - tmp[len++] = digits[n / 10]; - n = n % 10; - } - else if (n >= 10) - { - tmp[len++] = digits[n / 10]; - n = n % 10; - } - - tmp[len++] = digits[n]; - } - } - - if (!(type & LEFT)) - while (len < size--) - *str++ = ' '; - for (i = 0; i < len; ++i) - *str++ = tmp[i]; - while (len < size--) - *str++ = ' '; - - return str; -} - -#if HAS_FLOAT - -char * ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf); -char * fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf); -static void ee_bufcpy(char *d, char *s, int count); - -void -ee_bufcpy(char *pd, char *ps, int count) -{ - char *pe = ps + count; - while (ps != pe) - *pd++ = *ps++; -} - -static void -parse_float(double value, char *buffer, char fmt, int precision) -{ - int decpt, sign, exp, pos; - char *digits = NULL; - char cvtbuf[80]; - int capexp = 0; - int magnitude; - - if (fmt == 'G' || fmt == 'E') - { - capexp = 1; - fmt += 'a' - 'A'; - } - - if (fmt == 'g') - { - digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf); - magnitude = decpt - 1; - if (magnitude < -4 || magnitude > precision - 1) - { - fmt = 'e'; - precision -= 1; - } - else - { - fmt = 'f'; - precision -= decpt; - } - } - - if (fmt == 'e') - { - digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf); - - if (sign) - *buffer++ = '-'; - *buffer++ = *digits; - if (precision > 0) - *buffer++ = '.'; - ee_bufcpy(buffer, digits + 1, precision); - buffer += precision; - *buffer++ = capexp ? 'E' : 'e'; - - if (decpt == 0) - { - if (value == 0.0) - exp = 0; - else - exp = -1; - } - else - exp = decpt - 1; - - if (exp < 0) - { - *buffer++ = '-'; - exp = -exp; - } - else - *buffer++ = '+'; - - buffer[2] = (exp % 10) + '0'; - exp = exp / 10; - buffer[1] = (exp % 10) + '0'; - exp = exp / 10; - buffer[0] = (exp % 10) + '0'; - buffer += 3; - } - else if (fmt == 'f') - { - digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf); - if (sign) - *buffer++ = '-'; - if (*digits) - { - if (decpt <= 0) - { - *buffer++ = '0'; - *buffer++ = '.'; - for (pos = 0; pos < -decpt; pos++) - *buffer++ = '0'; - while (*digits) - *buffer++ = *digits++; - } - else - { - pos = 0; - while (*digits) - { - if (pos++ == decpt) - *buffer++ = '.'; - *buffer++ = *digits++; - } - } - } - else - { - *buffer++ = '0'; - if (precision > 0) - { - *buffer++ = '.'; - for (pos = 0; pos < precision; pos++) - *buffer++ = '0'; - } - } - } - - *buffer = '\0'; -} - -static void -decimal_point(char *buffer) -{ - while (*buffer) - { - if (*buffer == '.') - return; - if (*buffer == 'e' || *buffer == 'E') - break; - buffer++; - } - - if (*buffer) - { - int n = strnlen(buffer, 256); - while (n > 0) - { - buffer[n + 1] = buffer[n]; - n--; - } - - *buffer = '.'; - } - else - { - *buffer++ = '.'; - *buffer = '\0'; - } -} - -static void -cropzeros(char *buffer) -{ - char *stop; - - while (*buffer && *buffer != '.') - buffer++; - if (*buffer++) - { - while (*buffer && *buffer != 'e' && *buffer != 'E') - buffer++; - stop = buffer--; - while (*buffer == '0') - buffer--; - if (*buffer == '.') - buffer--; - while (buffer != stop) - *++buffer = 0; - } -} - -static char * -flt(char *str, double num, int size, int precision, char fmt, int flags) -{ - char tmp[80]; - char c, sign; - int n, i; - - // Left align means no zero padding - if (flags & LEFT) - flags &= ~ZEROPAD; - - // Determine padding and sign char - c = (flags & ZEROPAD) ? '0' : ' '; - sign = 0; - if (flags & SIGN) - { - if (num < 0.0) - { - sign = '-'; - num = -num; - size--; - } - else if (flags & PLUS) - { - sign = '+'; - size--; - } - else if (flags & SPACE) - { - sign = ' '; - size--; - } - } - - // Compute the precision value - if (precision < 0) - precision = 6; // Default precision: 6 - - // Convert floating point number to text - parse_float(num, tmp, fmt, precision); - - if ((flags & HEX_PREP) && precision == 0) - decimal_point(tmp); - if (fmt == 'g' && !(flags & HEX_PREP)) - cropzeros(tmp); - - n = strnlen(tmp, 256); - - // Output number with alignment and padding - size -= n; - if (!(flags & (ZEROPAD | LEFT))) - while (size-- > 0) - *str++ = ' '; - if (sign) - *str++ = sign; - if (!(flags & LEFT)) - while (size-- > 0) - *str++ = c; - for (i = 0; i < n; i++) - *str++ = tmp[i]; - while (size-- > 0) - *str++ = ' '; - - return str; -} - -#endif - -static int -ee_vsprintf(char *buf, const char *fmt, va_list args) -{ - int len; - unsigned long num; - int i, base; - char * str; - char * s; - - int flags; // Flags to number() - - int field_width; // Width of output field - int precision; // Min. # of digits for integers; max number of chars for - // from string - int qualifier; // 'h', 'l', or 'L' for integer fields - - for (str = buf; *fmt; fmt++) - { - if (*fmt != '%') - { - *str++ = *fmt; - continue; - } - - // Process flags - flags = 0; - repeat: - fmt++; // This also skips first '%' - switch (*fmt) - { - case '-': - flags |= LEFT; - goto repeat; - case '+': - flags |= PLUS; - goto repeat; - case ' ': - flags |= SPACE; - goto repeat; - case '#': - flags |= HEX_PREP; - goto repeat; - case '0': - flags |= ZEROPAD; - goto repeat; - } - - // Get field width - field_width = -1; - if (is_digit(*fmt)) - field_width = skip_atoi(&fmt); - else if (*fmt == '*') - { - fmt++; - field_width = va_arg(args, int); - if (field_width < 0) - { - field_width = -field_width; - flags |= LEFT; - } - } - - // Get the precision - precision = -1; - if (*fmt == '.') - { - ++fmt; - if (is_digit(*fmt)) - precision = skip_atoi(&fmt); - else if (*fmt == '*') - { - ++fmt; - precision = va_arg(args, int); - } - if (precision < 0) - precision = 0; - } - - // Get the conversion qualifier - qualifier = -1; - if (*fmt == 'l' || *fmt == 'L') - { - qualifier = *fmt; - fmt++; - } - - // Default base - base = 10; - - switch (*fmt) - { - case 'c': - if (!(flags & LEFT)) - while (--field_width > 0) - *str++ = ' '; - *str++ = (unsigned char)va_arg(args, int); - while (--field_width > 0) - *str++ = ' '; - continue; - - case 's': - s = va_arg(args, char *); - if (!s) - s = ""; - len = strnlen(s, precision); - if (!(flags & LEFT)) - while (len < field_width--) - *str++ = ' '; - for (i = 0; i < len; ++i) - *str++ = *s++; - while (len < field_width--) - *str++ = ' '; - continue; - - case 'p': - if (field_width == -1) - { - field_width = 2 * sizeof(void *); - flags |= ZEROPAD; - } - str = number(str, - (unsigned long)va_arg(args, void *), - 16, - field_width, - precision, - flags); - continue; - - case 'A': - flags |= UPPERCASE; - - case 'a': - if (qualifier == 'l') - str = eaddr(str, - va_arg(args, unsigned char *), - field_width, - precision, - flags); - else - str = iaddr(str, - va_arg(args, unsigned char *), - field_width, - precision, - flags); - continue; - - // Integer number formats - set up the flags and "break" - case 'o': - base = 8; - break; - - case 'X': - flags |= UPPERCASE; - - case 'x': - base = 16; - break; - - case 'd': - case 'i': - flags |= SIGN; - - case 'u': - break; - -#if HAS_FLOAT - - case 'f': - str = flt(str, - va_arg(args, double), - field_width, - precision, - *fmt, - flags | SIGN); - continue; - -#endif - - default: - if (*fmt != '%') - *str++ = '%'; - if (*fmt) - *str++ = *fmt; - else - --fmt; - continue; - } - - if (qualifier == 'l') - num = va_arg(args, unsigned long); - else if (flags & SIGN) - num = va_arg(args, int); - else - num = va_arg(args, unsigned int); - - str = number(str, num, base, field_width, precision, flags); - } - - *str = '\0'; - return str - buf; -} - -void -uart_send_char(char c) -{ -#error "You must implement the method uart_send_char to use this file!\n"; - /* Output of a char to a UART usually follows the following model: - Wait until UART is ready - Write char to UART - Wait until UART is done - - Or in code: - while (*UART_CONTROL_ADDRESS != UART_READY); - *UART_DATA_ADDRESS = c; - while (*UART_CONTROL_ADDRESS != UART_READY); - - Check the UART sample code on your platform or the board - documentation. - */ -} - -int -ee_printf(const char *fmt, ...) -{ - char buf[1024], *p; - va_list args; - int n = 0; - - va_start(args, fmt); - ee_vsprintf(buf, fmt, args); - va_end(args); - p = buf; - while (*p) - { - uart_send_char(*p); - n++; - p++; - } - - return n; -} diff --git a/benchmarks/riscv-coremark/coremark/core_list_join.c b/benchmarks/riscv-coremark/coremark/core_list_join.c deleted file mode 100644 index 4bffeeccf..000000000 --- a/benchmarks/riscv-coremark/coremark/core_list_join.c +++ /dev/null @@ -1,580 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include "coremark.h" -//#include -//#include -/* -Topic: Description - Benchmark using a linked list. - - Linked list is a common data structure used in many applications. - - For our purposes, this will excercise the memory units of the processor. - In particular, usage of the list pointers to find and alter data. - - We are not using Malloc since some platforms do not support this library. - - Instead, the memory block being passed in is used to create a list, - and the benchmark takes care not to add more items then can be - accomodated by the memory block. The porting layer will make sure - that we have a valid memory block. - - All operations are done in place, without using any extra memory. - - The list itself contains list pointers and pointers to data items. - Data items contain the following: - - idx - An index that captures the initial order of the list. - data - Variable data initialized based on the input parameters. The 16b are divided as follows: - o Upper 8b are backup of original data. - o Bit 7 indicates if the lower 7 bits are to be used as is or calculated. - o Bits 0-2 indicate type of operation to perform to get a 7b value. - o Bits 3-6 provide input for the operation. - -*/ - -/* local functions */ - -list_head *core_list_find(list_head *list,list_data *info); -list_head *core_list_reverse(list_head *list); -list_head *core_list_remove(list_head *item); -list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified); -list_head *core_list_insert_new(list_head *insert_point - , list_data *info, list_head **memblock, list_data **datablock - , list_head *memblock_end, list_data *datablock_end); -typedef ee_s32(*list_cmp)(list_data *a, list_data *b, core_results *res); -list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res); - -ee_s16 calc_func(ee_s16 *pdata, core_results *res) { - ee_s16 data=*pdata; - ee_s16 retval; - ee_u8 optype=(data>>7) & 1; /* bit 7 indicates if the function result has been cached */ - if (optype) /* if cached, use cache */ - return (data & 0x007f); - else { /* otherwise calculate and cache the result */ - ee_s16 flag=data & 0x7; /* bits 0-2 is type of function to perform */ - ee_s16 dtype=((data>>3) & 0xf); /* bits 3-6 is specific data for the operation */ - dtype |= dtype << 4; /* replicate the lower 4 bits to get an 8b value */ - switch (flag) { - case 0: - if (dtype<0x22) /* set min period for bit corruption */ - dtype=0x22; - retval=core_bench_state(res->size,res->memblock[3],res->seed1,res->seed2,dtype,res->crc); - if (res->crcstate==0) - res->crcstate=retval; - break; - case 1: - retval=core_bench_matrix(&(res->mat),dtype,res->crc); - if (res->crcmatrix==0) - res->crcmatrix=retval; - break; - default: - retval=data; - break; - } - res->crc=crcu16(retval,res->crc); - retval &= 0x007f; - *pdata = (data & 0xff00) | 0x0080 | retval; /* cache the result */ - return retval; - } -} -/* Function: cmp_complex - Compare the data item in a list cell. - - Can be used by mergesort. -*/ -ee_s32 cmp_complex(list_data *a, list_data *b, core_results *res) { - ee_s16 val1=calc_func(&(a->data16),res); - ee_s16 val2=calc_func(&(b->data16),res); - return val1 - val2; -} - -/* Function: cmp_idx - Compare the idx item in a list cell, and regen the data. - - Can be used by mergesort. -*/ -ee_s32 cmp_idx(list_data *a, list_data *b, core_results *res) { - if (res==NULL) { - a->data16 = (a->data16 & 0xff00) | (0x00ff & (a->data16>>8)); - b->data16 = (b->data16 & 0xff00) | (0x00ff & (b->data16>>8)); - } - return a->idx - b->idx; -} - -/*void ehitoa(int value, char *str, int base){ - if (value>100000) strcpy(str,"too big"); - else{ - int places[6] = {100000, 10000, 1000, 100, 10, 1}; - int col; - int pv; - for(col = 0; col<6; col++){ - pv = 0; - while (value >= places[col]){ - value=value -places[col]; - pv++; - - } - str[col]=pv+'0'; - } - str[6]=0; - } -}*/ - -void copy_info(list_data *to,list_data *from) { - to->data16=from->data16; - to->idx=from->idx; -} - -/* Benchmark for linked list: - - Try to find multiple data items. - - List sort - - Operate on data from list (crc) - - Single remove/reinsert - * At the end of this function, the list is back to original state -*/ -ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx) { - ee_u16 retval=0; - ee_u16 found=0,missed=0; - list_head *list=res->list; - ee_s16 find_num=res->seed3; - list_head *this_find; - list_head *finder, *remover; - list_data info; - ee_s16 i; - //ee_printf("entered corebenchlist \n"); - info.idx=finder_idx; - /* find values in the list, and change the list each time (reverse and cache if value found) */ - for (i=0; inext->info->data16 >> 8) & 1; - //ee_printf("if statement \n"); - } - else { - found++; - //ee_printf("else statement \n"); - if (this_find->info->data16 & 0x1) /* use found value */ - retval+=(this_find->info->data16 >> 9) & 1; - /* and cache next item at the head of the list (if any) */ - if (this_find->next != NULL) { - finder = this_find->next; - this_find->next = finder->next; - finder->next=list->next; - list->next=finder; - } - } - if (info.idx>=0) - info.idx++; -#if CORE_DEBUG - //ee_printf("List find %d: [%d,%d,%d]\n",i,retval,missed,found); -#endif - } - retval+=found*4-missed; - /* sort the list by data content and remove one item*/ - if (finder_idx>0) - list=core_list_mergesort(list,cmp_complex,res); - remover=core_list_remove(list->next); - /* CRC data content of list from location of index N forward, and then undo remove */ - finder=core_list_find(list,&info); - if (!finder) - finder=list->next; - while (finder) { - retval=crc16(list->info->data16,retval); - finder=finder->next; - } -#if CORE_DEBUG - //ee_printf("List sort 1: %04x\n",retval); -#endif - remover=core_list_undo_remove(remover,list->next); - /* sort the list by index, in effect returning the list to original state */ - list=core_list_mergesort(list,cmp_idx,NULL); - /* CRC data content of list */ - finder=list->next; - while (finder) { - retval=crc16(list->info->data16,retval); - finder=finder->next; - } -#if CORE_DEBUG - //ee_printf("List sort 2: %04x\n",retval); -#endif - return retval; -} -/* Function: core_list_init - Initialize list with data. - - Parameters: - blksize - Size of memory to be initialized. - memblock - Pointer to memory block. - seed - Actual values chosen depend on the seed parameter. - The seed parameter MUST be supplied from a source that cannot be determined at compile time - - Returns: - Pointer to the head of the list. - -*/ -list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed) { - /* calculated pointers for the list */ - //ee_printf("%d \n blksize", blksize); - ee_u32 per_item=16+sizeof(struct list_data_s); - //ee_printf("%d \n sizeof", sizeof(struct list_data_s)); - //ee_printf("%d \n per_item", per_item); - ee_u32 size=(blksize/per_item)-2; - //char bufftwo[200]; - //ehitoa(size, bufftwo, 10); - //ee_printf(" size = %s done \n", bufftwo); - //ee_printf("%d", size);/* to accomodate systems with 64b pointers, and make sure same code is executed, set max list elements */ - list_head *memblock_end=memblock+size; - - list_data *datablock=(list_data *)(memblock_end); - list_data *datablock_end=datablock+size; - //ee_printf("datablock_end"); - /* some useful variables */ - ee_u32 i; - list_head *finder,*list=memblock; - list_data info; - //ehitoa(size, bufftwo, 10); - //ee_printf(" size2 = %s done \n", bufftwo); - - /* create a fake items for the list head and tail */ - list->next=NULL; - list->info=datablock; - list->info->idx=0x0000; - list->info->data16=(ee_s16)0x8080; - memblock++; - datablock++; - info.idx=0x7fff; - info.data16=(ee_s16)0xffff; - //ehitoa(size, bufftwo, 10); - //ee_printf(" size3 = %s done \n", bufftwo); - core_list_insert_new(list,&info,&memblock,&datablock,memblock_end,datablock_end); - //ehitoa(size, bufftwo, 10); - //ee_printf(" size4 = %s done \n", bufftwo);; - /* then insert size items */ - for (i=0; inext; - i=1; - //ehitoa(i, bufftwo, 10); - //ee_printf(" i = %s done \n", bufftwo); - while (finder->next!=NULL) { - //ee_printf("enter while statement \n"); - if (iinfo->idx=i++; - //ehitoa(i, bufftwo, 10); - //ee_printf(" if i = %s done \n", bufftwo); - } - - else { - ee_u16 pat=(ee_u16)(i++ ^ seed); /* get a pseudo random number */ - finder->info->idx=0x3fff & (((i & 0x07) << 8) | pat); /* make sure the mixed items end up after the ones in sequence */ - //ehitoa(i, bufftwo, 10); - //ee_printf(" else i = %s done \n", bufftwo); - } - finder=finder->next; - } - //ehitoa(i, bufftwo, 10); - //ee_printf(" i2 = %s done \n", bufftwo); - list = core_list_mergesort(list,cmp_idx,NULL); -#if CORE_DEBUG - //ee_printf("Initialized list:\n"); - finder=list; - while (finder) { - //ee_printf("[%04x,%04x]",finder->info->idx,(ee_u16)finder->info->data16); - finder=finder->next; - } - //ee_printf("\n"); -#endif - return list; -} - -/* Function: core_list_insert - Insert an item to the list - - Parameters: - insert_point - where to insert the item. - info - data for the cell. - memblock - pointer for the list header - datablock - pointer for the list data - memblock_end - end of region for list headers - datablock_end - end of region for list data - - Returns: - Pointer to new item. -*/ -list_head *core_list_insert_new(list_head *insert_point, list_data *info, list_head **memblock, list_data **datablock - , list_head *memblock_end, list_data *datablock_end) { - list_head *newitem; - - if ((*memblock+1) >= memblock_end) - return NULL; - if ((*datablock+1) >= datablock_end) - return NULL; - - newitem=*memblock; - (*memblock)++; - newitem->next=insert_point->next; - insert_point->next=newitem; - - newitem->info=*datablock; - (*datablock)++; - copy_info(newitem->info,info); - - return newitem; -} - -/* Function: core_list_remove - Remove an item from the list. - - Operation: - For a singly linked list, remove by copying the data from the next item - over to the current cell, and unlinking the next item. - - Note: - since there is always a fake item at the end of the list, no need to check for NULL. - - Returns: - Removed item. -*/ -list_head *core_list_remove(list_head *item) { - list_data *tmp; - list_head *ret=item->next; - /* swap data pointers */ - tmp=item->info; - item->info=ret->info; - ret->info=tmp; - /* and eliminate item */ - item->next=item->next->next; - ret->next=NULL; - return ret; -} - -/* Function: core_list_undo_remove - Undo a remove operation. - - Operation: - Since we want each iteration of the benchmark to be exactly the same, - we need to be able to undo a remove. - Link the removed item back into the list, and switch the info items. - - Parameters: - item_removed - Return value from the - item_modified - List item that was modified during - - Returns: - The item that was linked back to the list. - -*/ -list_head *core_list_undo_remove(list_head *item_removed, list_head *item_modified) { - list_data *tmp; - /* swap data pointers */ - tmp=item_removed->info; - item_removed->info=item_modified->info; - item_modified->info=tmp; - /* and insert item */ - item_removed->next=item_modified->next; - item_modified->next=item_removed; - return item_removed; -} - -/* Function: core_list_find - Find an item in the list - - Operation: - Find an item by idx (if not 0) or specific data value - - Parameters: - list - list head - info - idx or data to find - - Returns: - Found item, or NULL if not found. -*/ -list_head *core_list_find(list_head *list,list_data *info) { - //ee_printf("entered core_list_find \n"); - if (info->idx>=0) { - //ee_printf("find if \n"); - while (list && (list->info->idx != info->idx)){ - list=list->next; - //ee_printf("find while if \n"); - } - //ee_printf("core_list_find end \n"); - return list; - } else { - //ee_printf("find else"); - while (list && ((list->info->data16 & 0xff) != info->data16)){ - list=list->next; - //ee_printf("find while else \n"); - } - //ee_printf("core list find end \n"); - return list; - } -} -/* Function: core_list_reverse - Reverse a list - - Operation: - Rearrange the pointers so the list is reversed. - - Parameters: - list - list head - info - idx or data to find - - Returns: - Found item, or NULL if not found. -*/ - -list_head *core_list_reverse(list_head *list) { -// ee_printf("entered core_list_reverse"); - list_head *next=NULL, *tmp; - while (list) { - tmp=list->next; - list->next=next; - next=list; - list=tmp; - } - //ee_printf("core_list_reverse done"); - return next; -} -/* Function: core_list_mergesort - Sort the list in place without recursion. - - Description: - Use mergesort, as for linked list this is a realistic solution. - Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm. - The sort can either return the list to original order (by idx) , - or use the data item to invoke other other algorithms and change the order of the list. - - Parameters: - list - list to be sorted. - cmp - cmp function to use - - Returns: - New head of the list. - - Note: - We have a special header for the list that will always be first, - but the algorithm could theoretically modify where the list starts. - - */ -list_head *core_list_mergesort(list_head *list, list_cmp cmp, core_results *res) { - list_head *p, *q, *e, *tail; - ee_s32 insize, nmerges, psize, qsize, i; - - insize = 1; - //char bufftwo[200]; - while (1) { - p = list; - list = NULL; - tail = NULL; - - nmerges = 0; /* count number of merges we do in this pass */ - //ehitoa(nmerges, bufftwo, 10); - //ee_printf(" nmerges default value = %s done \n", bufftwo); - while (p) { - nmerges++; /* there exists a merge to be done */ - //ehitoa(nmerges, bufftwo, 10); - //ee_printf(" current nmerges = %s done \n", bufftwo); - /* step `insize' places along from p */ - q = p; - psize = 0; - //ehitoa(insize, bufftwo, 10); - //ee_printf(" insize = %s done \n", bufftwo); - for (i = 0; i < insize; i++) { - //ehitoa(i, bufftwo, 10); - //ee_printf(" i = %s done \n", bufftwo); - psize++; - q = q->next; - if (!q) break; - } - - /* if q hasn't fallen off end, we have two lists to merge */ - qsize = insize; - //ehitoa(qsize, bufftwo, 10); - //ee_printf(" qsize = %s done \n", bufftwo); - - /* now we have two lists; merge them */ - while (psize > 0 || (qsize > 0 && q)) { - - /* decide whether next element of merge comes from p or q */ - if (psize == 0) { - //ee_printf("if \n"); - /* p is empty; e must come from q. */ - e = q; q = q->next; qsize--; - } else if (qsize == 0 || !q) { - //ee_printf("else if \n"); - /* q is empty; e must come from p. */ - e = p; p = p->next; psize--; - } else if (cmp(p->info,q->info,res) <= 0) { - //ee_printf("else if 2 \n"); - /* First element of p is lower (or same); e must come from p. */ - e = p; p = p->next; psize--; - } else { - //ee_printf("else \n"); - /* First element of q is lower; e must come from q. */ - e = q; q = q->next; qsize--; - } - - /* add the next element to the merged list */ - if (tail) { - //ee_printf("tail if \n"); - tail->next = e; - } else { - //ee_printf("tail else \n"); - list = e; - } - tail = e; - } - - /* now p has stepped `insize' places along, and q has too */ - p = q; - } - - tail->next = NULL; - - /* If we have done only one merge, we're finished. */ - if (nmerges <= 1) /* allow for nmerges==0, the empty list case */ - return list; - - /* Otherwise repeat, merging lists twice the size */ - insize *= 2; - //ehitoa(insize, bufftwo, 10); - //ee_printf(" insize2 = %s done \n", bufftwo); - } -#if COMPILER_REQUIRES_SORT_RETURN - return list; -#endif -} diff --git a/benchmarks/riscv-coremark/coremark/core_main.c b/benchmarks/riscv-coremark/coremark/core_main.c deleted file mode 100644 index 8467d9459..000000000 --- a/benchmarks/riscv-coremark/coremark/core_main.c +++ /dev/null @@ -1,448 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* File: core_main.c - This file contains the framework to acquire a block of memory, seed - initial parameters, tun t he benchmark and report the results. -*/ -#include "coremark.h" - -/* Function: iterate - Run the benchmark for a specified number of iterations. - - Operation: - For each type of benchmarked algorithm: - a - Initialize the data block for the algorithm. - b - Execute the algorithm N times. - - Returns: - NULL. -*/ -static ee_u16 list_known_crc[] = { (ee_u16)0xd4b0, - (ee_u16)0x3340, - (ee_u16)0x6a79, - (ee_u16)0xe714, - (ee_u16)0xe3c1 }; -static ee_u16 matrix_known_crc[] = { (ee_u16)0xbe52, - (ee_u16)0x1199, - (ee_u16)0x5608, - (ee_u16)0x1fd7, - (ee_u16)0x0747 }; -static ee_u16 state_known_crc[] = { (ee_u16)0x5e47, - (ee_u16)0x39bf, - (ee_u16)0xe5a4, - (ee_u16)0x8e3a, - (ee_u16)0x8d84 }; -void * -iterate(void *pres) -{ - ee_u32 i; - ee_u16 crc; - core_results *res = (core_results *)pres; - ee_u32 iterations = res->iterations; - res->crc = 0; - res->crclist = 0; - res->crcmatrix = 0; - res->crcstate = 0; - - for (i = 0; i < iterations; i++) - { - crc = core_bench_list(res, 1); - res->crc = crcu16(crc, res->crc); - crc = core_bench_list(res, -1); - res->crc = crcu16(crc, res->crc); - if (i == 0) - res->crclist = res->crc; - } - return NULL; -} - -#if (SEED_METHOD == SEED_ARG) -ee_s32 get_seed_args(int i, int argc, char *argv[]); -#define get_seed(x) (ee_s16) get_seed_args(x, argc, argv) -#define get_seed_32(x) get_seed_args(x, argc, argv) -#else /* via function or volatile */ -ee_s32 get_seed_32(int i); -#define get_seed(x) (ee_s16) get_seed_32(x) -#endif - -#if (MEM_METHOD == MEM_STATIC) -ee_u8 static_memblk[TOTAL_DATA_SIZE]; -#endif -char *mem_name[3] = { "Static", "Heap", "Stack" }; -/* Function: main - Main entry routine for the benchmark. - This function is responsible for the following steps: - - 1 - Initialize input seeds from a source that cannot be determined at - compile time. 2 - Initialize memory block for use. 3 - Run and time the - benchmark. 4 - Report results, testing the validity of the output if the - seeds are known. - - Arguments: - 1 - first seed : Any value - 2 - second seed : Must be identical to first for iterations to be - identical 3 - third seed : Any value, should be at least an order of - magnitude less then the input size, but bigger then 32. 4 - Iterations : - Special, if set to 0, iterations will be automatically determined such that - the benchmark will run between 10 to 100 secs - -*/ - -#if MAIN_HAS_NOARGC -MAIN_RETURN_TYPE -main(void) -{ - int argc = 0; - char *argv[1]; -#else -MAIN_RETURN_TYPE -main(int argc, char *argv[]) -{ -#endif - ee_printf("SHOWTIME\n"); - ee_u16 i, j = 0, num_algorithms = 0; - ee_s16 known_id = -1, total_errors = 0; - ee_u16 seedcrc = 0; - CORE_TICKS total_time; - core_results results[MULTITHREAD]; -#if (MEM_METHOD == MEM_STACK) - ee_u8 stack_memblock[TOTAL_DATA_SIZE * MULTITHREAD]; -#endif - /* first call any initializations needed */ - portable_init(&(results[0].port), &argc, argv); - /* First some checks to make sure benchmark will run ok */ - if (sizeof(struct list_head_s) > 128) - { - ee_printf("list_head structure too big for comparable data!\n"); - return MAIN_RETURN_VAL; - } - results[0].seed1 = get_seed(1); - results[0].seed2 = get_seed(2); - results[0].seed3 = get_seed(3); - results[0].iterations = get_seed_32(4); -#if CORE_DEBUG - results[0].iterations = 1; -#endif - results[0].execs = get_seed_32(5); - if (results[0].execs == 0) - { /* if not supplied, execute all algorithms */ - results[0].execs = ALL_ALGORITHMS_MASK; - } - /* put in some default values based on one seed only for easy testing */ - if ((results[0].seed1 == 0) && (results[0].seed2 == 0) - && (results[0].seed3 == 0)) - { /* perfromance run */ - results[0].seed1 = 0; - results[0].seed2 = 0; - results[0].seed3 = 0x66; - } - if ((results[0].seed1 == 1) && (results[0].seed2 == 0) - && (results[0].seed3 == 0)) - { /* validation run */ - results[0].seed1 = 0x3415; - results[0].seed2 = 0x3415; - results[0].seed3 = 0x66; - } -#if (MEM_METHOD == MEM_STATIC) - results[0].memblock[0] = (void *)static_memblk; - results[0].size = TOTAL_DATA_SIZE; - results[0].err = 0; -#if (MULTITHREAD > 1) -#error "Cannot use a static data area with multiple contexts!" -#endif -#elif (MEM_METHOD == MEM_MALLOC) - for (i = 0; i < MULTITHREAD; i++) - { - ee_s32 malloc_override = get_seed(7); - if (malloc_override != 0) - results[i].size = malloc_override; - else - results[i].size = TOTAL_DATA_SIZE; - results[i].memblock[0] = portable_malloc(results[i].size); - results[i].seed1 = results[0].seed1; - results[i].seed2 = results[0].seed2; - results[i].seed3 = results[0].seed3; - results[i].err = 0; - results[i].execs = results[0].execs; - } -#elif (MEM_METHOD == MEM_STACK) -for (i = 0; i < MULTITHREAD; i++) -{ - results[i].memblock[0] = stack_memblock + i * TOTAL_DATA_SIZE; - results[i].size = TOTAL_DATA_SIZE; - results[i].seed1 = results[0].seed1; - results[i].seed2 = results[0].seed2; - results[i].seed3 = results[0].seed3; - results[i].err = 0; - results[i].execs = results[0].execs; -} -#else -#error "Please define a way to initialize a memory block." -#endif - /* Data init */ - /* Find out how space much we have based on number of algorithms */ - for (i = 0; i < NUM_ALGORITHMS; i++) - { - if ((1 << (ee_u32)i) & results[0].execs) - num_algorithms++; - } - for (i = 0; i < MULTITHREAD; i++) - results[i].size = results[i].size / num_algorithms; - /* Assign pointers */ - for (i = 0; i < NUM_ALGORITHMS; i++) - { - ee_u32 ctx; - if ((1 << (ee_u32)i) & results[0].execs) - { - for (ctx = 0; ctx < MULTITHREAD; ctx++) - results[ctx].memblock[i + 1] - = (char *)(results[ctx].memblock[0]) + results[0].size * j; - j++; - } - } - /* call inits */ - for (i = 0; i < MULTITHREAD; i++) - { - if (results[i].execs & ID_LIST) - { - results[i].list = core_list_init( - results[0].size, results[i].memblock[1], results[i].seed1); - } - if (results[i].execs & ID_MATRIX) - { - core_init_matrix(results[0].size, - results[i].memblock[2], - (ee_s32)results[i].seed1 - | (((ee_s32)results[i].seed2) << 16), - &(results[i].mat)); - } - if (results[i].execs & ID_STATE) - { - core_init_state( - results[0].size, results[i].seed1, results[i].memblock[3]); - } - } - - /* automatically determine number of iterations if not set */ - // results[0].iterations = 2; // temporary for speed - if (results[0].iterations == 0) - { - secs_ret secs_passed = 0; - ee_u32 divisor; - results[0].iterations = 1; - while (secs_passed < (secs_ret)1) - { - results[0].iterations *= 10; - start_time(); - iterate(&results[0]); - stop_time(); - secs_passed = time_in_secs(get_time()); - } - /* now we know it executes for at least 1 sec, set actual run time at - * about 10 secs */ - divisor = (ee_u32)secs_passed; - if (divisor == 0) /* some machines cast float to int as 0 since this - conversion is not defined by ANSI, but we know at - least one second passed */ - divisor = 1; - results[0].iterations *= 1 + 10 / divisor; - } - /* perform actual benchmark */ - start_time(); -#if (MULTITHREAD > 1) - if (default_num_contexts > MULTITHREAD) - { - default_num_contexts = MULTITHREAD; - } - for (i = 0; i < default_num_contexts; i++) - { - results[i].iterations = results[0].iterations; - results[i].execs = results[0].execs; - core_start_parallel(&results[i]); - } - for (i = 0; i < default_num_contexts; i++) - { - core_stop_parallel(&results[i]); - } -#else - iterate(&results[0]); -#endif - stop_time(); - total_time = get_time(); - /* get a function of the input to report */ - seedcrc = crc16(results[0].seed1, seedcrc); - seedcrc = crc16(results[0].seed2, seedcrc); - seedcrc = crc16(results[0].seed3, seedcrc); - seedcrc = crc16(results[0].size, seedcrc); - - switch (seedcrc) - { /* test known output for common seeds */ - case 0x8a02: /* seed1=0, seed2=0, seed3=0x66, size 2000 per algorithm */ - known_id = 0; - ee_printf("6k performance run parameters for coremark.\n"); - break; - case 0x7b05: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 2000 per - algorithm */ - known_id = 1; - ee_printf("6k validation run parameters for coremark.\n"); - break; - case 0x4eaf: /* seed1=0x8, seed2=0x8, seed3=0x8, size 400 per algorithm - */ - known_id = 2; - ee_printf("Profile generation run parameters for coremark.\n"); - break; - case 0xe9f5: /* seed1=0, seed2=0, seed3=0x66, size 666 per algorithm */ - known_id = 3; - ee_printf("2K performance run parameters for coremark.\n"); - break; - case 0x18f2: /* seed1=0x3415, seed2=0x3415, seed3=0x66, size 666 per - algorithm */ - known_id = 4; - ee_printf("2K validation run parameters for coremark.\n"); - break; - default: - total_errors = -1; - break; - } - if (known_id >= 0) - { - for (i = 0; i < default_num_contexts; i++) - { - results[i].err = 0; - if ((results[i].execs & ID_LIST) - && (results[i].crclist != list_known_crc[known_id])) - { - ee_printf("[%u]ERROR! list crc 0x%04x - should be 0x%04x\n", - i, - results[i].crclist, - list_known_crc[known_id]); - results[i].err++; - } - if ((results[i].execs & ID_MATRIX) - && (results[i].crcmatrix != matrix_known_crc[known_id])) - { - ee_printf("[%u]ERROR! matrix crc 0x%04x - should be 0x%04x\n", - i, - results[i].crcmatrix, - matrix_known_crc[known_id]); - results[i].err++; - } - if ((results[i].execs & ID_STATE) - && (results[i].crcstate != state_known_crc[known_id])) - { - ee_printf("[%u]ERROR! state crc 0x%04x - should be 0x%04x\n", - i, - results[i].crcstate, - state_known_crc[known_id]); - results[i].err++; - } - total_errors += results[i].err; - } - } - total_errors += check_data_types(); - /* and report results */ - ee_printf("CoreMark Size : %lu\n", (long unsigned)results[0].size); - ee_printf("Total ticks : %lu\n", (long unsigned)total_time); -#if HAS_FLOAT - ee_printf("Total time (msecs): %ld\n", (long unsigned)(1000*time_in_secs(total_time))); - if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %lu / %lu\n", - default_num_contexts * results[0].iterations, - total_time); -#else - ee_printf("Total time (secs): %d\n", time_in_secs(total_time)); - if (time_in_secs(total_time) > 0) - ee_printf("Iterations/Sec : %d\n", - default_num_contexts * results[0].iterations - / time_in_secs(total_time)); -#endif - if (time_in_secs(total_time) < 10) - { - ee_printf( - "ERROR! Must execute for at least 10 secs for a valid result!\n"); - total_errors++; - } - - ee_printf("Iterations : %lu\n", - (long unsigned)default_num_contexts * results[0].iterations); - ee_printf("Compiler version : %s\n", COMPILER_VERSION); - ee_printf("Compiler flags : %s\n", COMPILER_FLAGS); -#if (MULTITHREAD > 1) - ee_printf("Parallel %s : %d\n", PARALLEL_METHOD, default_num_contexts); -#endif - ee_printf("Memory location : %s\n", MEM_LOCATION); - /* output for verification */ - ee_printf("seedcrc : 0x%04x\n", seedcrc); - if (results[0].execs & ID_LIST) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crclist : 0x%04x\n", i, results[i].crclist); - if (results[0].execs & ID_MATRIX) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcmatrix : 0x%04x\n", i, results[i].crcmatrix); - if (results[0].execs & ID_STATE) - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcstate : 0x%04x\n", i, results[i].crcstate); - for (i = 0; i < default_num_contexts; i++) - ee_printf("[%d]crcfinal : 0x%04x\n", i, results[i].crc); - if (total_errors == 0) - { - ee_printf( - "Correct operation validated. See README.md for run and reporting " - "rules.\n"); -#if HAS_FLOAT - if (known_id == 3) - { - unsigned long long tmp = (unsigned long long) 1000.0*default_num_contexts*results[0].iterations/time_in_secs(total_time); - secs_ret totalmsecs = time_in_secs(total_time); - int totalmint = (int) totalmsecs; - ee_printf("ELAPSED TIME: %d\n", totalmint); - - ee_printf("CoreMark 1.0 : %d / %s %s", - tmp, - COMPILER_VERSION, - COMPILER_FLAGS); -#if defined(MEM_LOCATION) && !defined(MEM_LOCATION_UNSPEC) - ee_printf(" / %s", MEM_LOCATION); -#else - ee_printf(" / %s", mem_name[MEM_METHOD]); -#endif - -#if (MULTITHREAD > 1) - ee_printf(" / %d:%s", default_num_contexts, PARALLEL_METHOD); -#endif - ee_printf("\n"); - } -#endif - } - if (total_errors > 0) - ee_printf("Errors detected\n"); - if (total_errors < 0) - ee_printf( - "Cannot validate operation for these seed values, please compare " - "with results on a known platform.\n"); - -#if (MEM_METHOD == MEM_MALLOC) - for (i = 0; i < MULTITHREAD; i++) - portable_free(results[i].memblock[0]); -#endif - /* And last call any target specific code for finalizing */ - portable_fini(&(results[0].port)); - - return MAIN_RETURN_VAL; -} diff --git a/benchmarks/riscv-coremark/coremark/core_matrix.c b/benchmarks/riscv-coremark/coremark/core_matrix.c deleted file mode 100644 index 29fd8ab45..000000000 --- a/benchmarks/riscv-coremark/coremark/core_matrix.c +++ /dev/null @@ -1,359 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include "coremark.h" -/* -Topic: Description - Matrix manipulation benchmark - - This very simple algorithm forms the basis of many more complex -algorithms. - - The tight inner loop is the focus of many optimizations (compiler as -well as hardware based) and is thus relevant for embedded processing. - - The total available data space will be divided to 3 parts: - NxN Matrix A - initialized with small values (upper 3/4 of the bits all -zero). NxN Matrix B - initialized with medium values (upper half of the bits all -zero). NxN Matrix C - used for the result. - - The actual values for A and B must be derived based on input that is not -available at compile time. -*/ -ee_s16 matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val); -ee_s16 matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval); -void matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val); -void matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B); -void matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val); - -#define matrix_test_next(x) (x + 1) -#define matrix_clip(x, y) ((y) ? (x)&0x0ff : (x)&0x0ffff) -#define matrix_big(x) (0xf000 | (x)) -#define bit_extract(x, from, to) (((x) >> (from)) & (~(0xffffffff << (to)))) - -#if CORE_DEBUG -void -printmat(MATDAT *A, ee_u32 N, char *name) -{ - ee_u32 i, j; - ee_printf("Matrix %s [%dx%d]:\n", name, N, N); - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - if (j != 0) - ee_printf(","); - ee_printf("%d", A[i * N + j]); - } - ee_printf("\n"); - } -} -void -printmatC(MATRES *C, ee_u32 N, char *name) -{ - ee_u32 i, j; - ee_printf("Matrix %s [%dx%d]:\n", name, N, N); - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - if (j != 0) - ee_printf(","); - ee_printf("%d", C[i * N + j]); - } - ee_printf("\n"); - } -} -#endif -/* Function: core_bench_matrix - Benchmark function - - Iterate N times, - changing the matrix values slightly by a constant amount each time. -*/ -ee_u16 -core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc) -{ - ee_u32 N = p->N; - MATRES *C = p->C; - MATDAT *A = p->A; - MATDAT *B = p->B; - MATDAT val = (MATDAT)seed; - - crc = crc16(matrix_test(N, C, A, B, val), crc); - - return crc; -} - -/* Function: matrix_test - Perform matrix manipulation. - - Parameters: - N - Dimensions of the matrix. - C - memory for result matrix. - A - input matrix - B - operator matrix (not changed during operations) - - Returns: - A CRC value that captures all results calculated in the function. - In particular, crc of the value calculated on the result matrix - after each step by . - - Operation: - - 1 - Add a constant value to all elements of a matrix. - 2 - Multiply a matrix by a constant. - 3 - Multiply a matrix by a vector. - 4 - Multiply a matrix by a matrix. - 5 - Add a constant value to all elements of a matrix. - - After the last step, matrix A is back to original contents. -*/ -ee_s16 -matrix_test(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B, MATDAT val) -{ - ee_u16 crc = 0; - MATDAT clipval = matrix_big(val); - - matrix_add_const(N, A, val); /* make sure data changes */ -#if CORE_DEBUG - printmat(A, N, "matrix_add_const"); -#endif - matrix_mul_const(N, C, A, val); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_const"); -#endif - matrix_mul_vect(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_vect"); -#endif - matrix_mul_matrix(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_matrix"); -#endif - matrix_mul_matrix_bitextract(N, C, A, B); - crc = crc16(matrix_sum(N, C, clipval), crc); -#if CORE_DEBUG - printmatC(C, N, "matrix_mul_matrix_bitextract"); -#endif - - matrix_add_const(N, A, -val); /* return matrix to initial value */ - return crc; -} - -/* Function : matrix_init - Initialize the memory block for matrix benchmarking. - - Parameters: - blksize - Size of memory to be initialized. - memblk - Pointer to memory block. - seed - Actual values chosen depend on the seed parameter. - p - pointers to containing initialized matrixes. - - Returns: - Matrix dimensions. - - Note: - The seed parameter MUST be supplied from a source that cannot be - determined at compile time -*/ -ee_u32 -core_init_matrix(ee_u32 blksize, void *memblk, ee_s32 seed, mat_params *p) -{ - ee_u32 N = 0; - MATDAT *A; - MATDAT *B; - ee_s32 order = 1; - MATDAT val; - ee_u32 i = 0, j = 0; - if (seed == 0) - seed = 1; - while (j < blksize) - { - i++; - j = i * i * 2 * 4; - } - N = i - 1; - A = (MATDAT *)align_mem(memblk); - B = A + N * N; - - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - seed = ((order * seed) % 65536); - val = (seed + order); - val = matrix_clip(val, 0); - B[i * N + j] = val; - val = (val + order); - val = matrix_clip(val, 1); - A[i * N + j] = val; - order++; - } - } - - p->A = A; - p->B = B; - p->C = (MATRES *)align_mem(B + N * N); - p->N = N; -#if CORE_DEBUG - printmat(A, N, "A"); - printmat(B, N, "B"); -#endif - return N; -} - -/* Function: matrix_sum - Calculate a function that depends on the values of elements in the - matrix. - - For each element, accumulate into a temporary variable. - - As long as this value is under the parameter clipval, - add 1 to the result if the element is bigger then the previous. - - Otherwise, reset the accumulator and add 10 to the result. -*/ -ee_s16 -matrix_sum(ee_u32 N, MATRES *C, MATDAT clipval) -{ - MATRES tmp = 0, prev = 0, cur = 0; - ee_s16 ret = 0; - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - cur = C[i * N + j]; - tmp += cur; - if (tmp > clipval) - { - ret += 10; - tmp = 0; - } - else - { - ret += (cur > prev) ? 1 : 0; - } - prev = cur; - } - } - return ret; -} - -/* Function: matrix_mul_const - Multiply a matrix by a constant. - This could be used as a scaler for instance. -*/ -void -matrix_mul_const(ee_u32 N, MATRES *C, MATDAT *A, MATDAT val) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = (MATRES)A[i * N + j] * (MATRES)val; - } - } -} - -/* Function: matrix_add_const - Add a constant value to all elements of a matrix. -*/ -void -matrix_add_const(ee_u32 N, MATDAT *A, MATDAT val) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - A[i * N + j] += val; - } - } -} - -/* Function: matrix_mul_vect - Multiply a matrix by a vector. - This is common in many simple filters (e.g. fir where a vector of - coefficients is applied to the matrix.) -*/ -void -matrix_mul_vect(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j; - for (i = 0; i < N; i++) - { - C[i] = 0; - for (j = 0; j < N; j++) - { - C[i] += (MATRES)A[i * N + j] * (MATRES)B[j]; - } - } -} - -/* Function: matrix_mul_matrix - Multiply a matrix by a matrix. - Basic code is used in many algorithms, mostly with minor changes such as - scaling. -*/ -void -matrix_mul_matrix(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j, k; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = 0; - for (k = 0; k < N; k++) - { - C[i * N + j] += (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; - } - } - } -} - -/* Function: matrix_mul_matrix_bitextract - Multiply a matrix by a matrix, and extract some bits from the result. - Basic code is used in many algorithms, mostly with minor changes such as - scaling. -*/ -void -matrix_mul_matrix_bitextract(ee_u32 N, MATRES *C, MATDAT *A, MATDAT *B) -{ - ee_u32 i, j, k; - for (i = 0; i < N; i++) - { - for (j = 0; j < N; j++) - { - C[i * N + j] = 0; - for (k = 0; k < N; k++) - { - MATRES tmp = (MATRES)A[i * N + k] * (MATRES)B[k * N + j]; - C[i * N + j] += bit_extract(tmp, 2, 4) * bit_extract(tmp, 5, 7); - } - } - } -} diff --git a/benchmarks/riscv-coremark/coremark/core_state.c b/benchmarks/riscv-coremark/coremark/core_state.c deleted file mode 100644 index 6dbab9dd9..000000000 --- a/benchmarks/riscv-coremark/coremark/core_state.c +++ /dev/null @@ -1,330 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include "coremark.h" -/* local functions */ -enum CORE_STATE core_state_transition(ee_u8 **instr, ee_u32 *transition_count); - -/* -Topic: Description - Simple state machines like this one are used in many embedded products. - - For more complex state machines, sometimes a state transition table -implementation is used instead, trading speed of direct coding for ease of -maintenance. - - Since the main goal of using a state machine in CoreMark is to excercise -the switch/if behaviour, we are using a small moore machine. - - In particular, this machine tests type of string input, - trying to determine whether the input is a number or something else. - (see core_state.png). -*/ - -/* Function: core_bench_state - Benchmark function - - Go over the input twice, once direct, and once after introducing some - corruption. -*/ -ee_u16 -core_bench_state(ee_u32 blksize, - ee_u8 *memblock, - ee_s16 seed1, - ee_s16 seed2, - ee_s16 step, - ee_u16 crc) -{ - ee_u32 final_counts[NUM_CORE_STATES]; - ee_u32 track_counts[NUM_CORE_STATES]; - ee_u8 *p = memblock; - ee_u32 i; - -#if CORE_DEBUG - ee_printf("State Bench: %d,%d,%d,%04x\n", seed1, seed2, step, crc); -#endif - for (i = 0; i < NUM_CORE_STATES; i++) - { - final_counts[i] = track_counts[i] = 0; - } - /* run the state machine over the input */ - while (*p != 0) - { - enum CORE_STATE fstate = core_state_transition(&p, track_counts); - final_counts[fstate]++; -#if CORE_DEBUG - ee_printf("%d,", fstate); - } - ee_printf("\n"); -#else - } -#endif - p = memblock; - while (p < (memblock + blksize)) - { /* insert some corruption */ - if (*p != ',') - *p ^= (ee_u8)seed1; - p += step; - } - p = memblock; - /* run the state machine over the input again */ - while (*p != 0) - { - enum CORE_STATE fstate = core_state_transition(&p, track_counts); - final_counts[fstate]++; -#if CORE_DEBUG - ee_printf("%d,", fstate); - } - ee_printf("\n"); -#else - } -#endif - p = memblock; - while (p < (memblock + blksize)) - { /* undo corruption is seed1 and seed2 are equal */ - if (*p != ',') - *p ^= (ee_u8)seed2; - p += step; - } - /* end timing */ - for (i = 0; i < NUM_CORE_STATES; i++) - { - crc = crcu32(final_counts[i], crc); - crc = crcu32(track_counts[i], crc); - } - return crc; -} - -/* Default initialization patterns */ -static ee_u8 *intpat[4] - = { (ee_u8 *)"5012", (ee_u8 *)"1234", (ee_u8 *)"-874", (ee_u8 *)"+122" }; -static ee_u8 *floatpat[4] = { (ee_u8 *)"35.54400", - (ee_u8 *)".1234500", - (ee_u8 *)"-110.700", - (ee_u8 *)"+0.64400" }; -static ee_u8 *scipat[4] = { (ee_u8 *)"5.500e+3", - (ee_u8 *)"-.123e-2", - (ee_u8 *)"-87e+832", - (ee_u8 *)"+0.6e-12" }; -static ee_u8 *errpat[4] = { (ee_u8 *)"T0.3e-1F", - (ee_u8 *)"-T.T++Tq", - (ee_u8 *)"1T3.4e4z", - (ee_u8 *)"34.0e-T^" }; - -/* Function: core_init_state - Initialize the input data for the state machine. - - Populate the input with several predetermined strings, interspersed. - Actual patterns chosen depend on the seed parameter. - - Note: - The seed parameter MUST be supplied from a source that cannot be - determined at compile time -*/ -void -core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p) -{ - ee_u32 total = 0, next = 0, i; - ee_u8 *buf = 0; -#if CORE_DEBUG - ee_u8 *start = p; - ee_printf("State: %d,%d\n", size, seed); -#endif - size--; - next = 0; - while ((total + next + 1) < size) - { - if (next > 0) - { - for (i = 0; i < next; i++) - *(p + total + i) = buf[i]; - *(p + total + i) = ','; - total += next + 1; - } - seed++; - switch (seed & 0x7) - { - case 0: /* int */ - case 1: /* int */ - case 2: /* int */ - buf = intpat[(seed >> 3) & 0x3]; - next = 4; - break; - case 3: /* float */ - case 4: /* float */ - buf = floatpat[(seed >> 3) & 0x3]; - next = 8; - break; - case 5: /* scientific */ - case 6: /* scientific */ - buf = scipat[(seed >> 3) & 0x3]; - next = 8; - break; - case 7: /* invalid */ - buf = errpat[(seed >> 3) & 0x3]; - next = 8; - break; - default: /* Never happen, just to make some compilers happy */ - break; - } - } - size++; - while (total < size) - { /* fill the rest with 0 */ - *(p + total) = 0; - total++; - } -#if CORE_DEBUG - ee_printf("State Input: %s\n", start); -#endif -} - -static ee_u8 -ee_isdigit(ee_u8 c) -{ - ee_u8 retval; - retval = ((c >= '0') & (c <= '9')) ? 1 : 0; - return retval; -} - -/* Function: core_state_transition - Actual state machine. - - The state machine will continue scanning until either: - 1 - an invalid input is detcted. - 2 - a valid number has been detected. - - The input pointer is updated to point to the end of the token, and the - end state is returned (either specific format determined or invalid). -*/ - -enum CORE_STATE -core_state_transition(ee_u8 **instr, ee_u32 *transition_count) -{ - ee_u8 * str = *instr; - ee_u8 NEXT_SYMBOL; - enum CORE_STATE state = CORE_START; - for (; *str && state != CORE_INVALID; str++) - { - NEXT_SYMBOL = *str; - if (NEXT_SYMBOL == ',') /* end of this input */ - { - str++; - break; - } - switch (state) - { - case CORE_START: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INT; - } - else if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') - { - state = CORE_S1; - } - else if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - } - else - { - state = CORE_INVALID; - transition_count[CORE_INVALID]++; - } - transition_count[CORE_START]++; - break; - case CORE_S1: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INT; - transition_count[CORE_S1]++; - } - else if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - transition_count[CORE_S1]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_S1]++; - } - break; - case CORE_INT: - if (NEXT_SYMBOL == '.') - { - state = CORE_FLOAT; - transition_count[CORE_INT]++; - } - else if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_INT]++; - } - break; - case CORE_FLOAT: - if (NEXT_SYMBOL == 'E' || NEXT_SYMBOL == 'e') - { - state = CORE_S2; - transition_count[CORE_FLOAT]++; - } - else if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_FLOAT]++; - } - break; - case CORE_S2: - if (NEXT_SYMBOL == '+' || NEXT_SYMBOL == '-') - { - state = CORE_EXPONENT; - transition_count[CORE_S2]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_S2]++; - } - break; - case CORE_EXPONENT: - if (ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_SCIENTIFIC; - transition_count[CORE_EXPONENT]++; - } - else - { - state = CORE_INVALID; - transition_count[CORE_EXPONENT]++; - } - break; - case CORE_SCIENTIFIC: - if (!ee_isdigit(NEXT_SYMBOL)) - { - state = CORE_INVALID; - transition_count[CORE_INVALID]++; - } - break; - default: - break; - } - } - *instr = str; - return state; -} diff --git a/benchmarks/riscv-coremark/coremark/core_util.c b/benchmarks/riscv-coremark/coremark/core_util.c deleted file mode 100644 index 67c5d7757..000000000 --- a/benchmarks/riscv-coremark/coremark/core_util.c +++ /dev/null @@ -1,249 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include "coremark.h" -/* Function: get_seed - Get a values that cannot be determined at compile time. - - Since different embedded systems and compilers are used, 3 different - methods are provided: 1 - Using a volatile variable. This method is only - valid if the compiler is forced to generate code that reads the value of a - volatile variable from memory at run time. Please note, if using this method, - you would need to modify core_portme.c to generate training profile. 2 - - Command line arguments. This is the preferred method if command line - arguments are supported. 3 - System function. If none of the first 2 methods - is available on the platform, a system function which is not a stub can be - used. - - e.g. read the value on GPIO pins connected to switches, or invoke - special simulator functions. -*/ -#if (SEED_METHOD == SEED_VOLATILE) -extern volatile ee_s32 seed1_volatile; -extern volatile ee_s32 seed2_volatile; -extern volatile ee_s32 seed3_volatile; -extern volatile ee_s32 seed4_volatile; -extern volatile ee_s32 seed5_volatile; -ee_s32 -get_seed_32(int i) -{ - ee_s32 retval; - switch (i) - { - case 1: - retval = seed1_volatile; - break; - case 2: - retval = seed2_volatile; - break; - case 3: - retval = seed3_volatile; - break; - case 4: - retval = seed4_volatile; - break; - case 5: - retval = seed5_volatile; - break; - default: - retval = 0; - break; - } - return retval; -} -#elif (SEED_METHOD == SEED_ARG) -ee_s32 -parseval(char *valstring) -{ - ee_s32 retval = 0; - ee_s32 neg = 1; - int hexmode = 0; - if (*valstring == '-') - { - neg = -1; - valstring++; - } - if ((valstring[0] == '0') && (valstring[1] == 'x')) - { - hexmode = 1; - valstring += 2; - } - /* first look for digits */ - if (hexmode) - { - while (((*valstring >= '0') && (*valstring <= '9')) - || ((*valstring >= 'a') && (*valstring <= 'f'))) - { - ee_s32 digit = *valstring - '0'; - if (digit > 9) - digit = 10 + *valstring - 'a'; - retval *= 16; - retval += digit; - valstring++; - } - } - else - { - while ((*valstring >= '0') && (*valstring <= '9')) - { - ee_s32 digit = *valstring - '0'; - retval *= 10; - retval += digit; - valstring++; - } - } - /* now add qualifiers */ - if (*valstring == 'K') - retval *= 1024; - if (*valstring == 'M') - retval *= 1024 * 1024; - - retval *= neg; - return retval; -} - -ee_s32 -get_seed_args(int i, int argc, char *argv[]) -{ - if (argc > i) - return parseval(argv[i]); - return 0; -} - -#elif (SEED_METHOD == SEED_FUNC) -/* If using OS based function, you must define and implement the functions below - * in core_portme.h and core_portme.c ! */ -ee_s32 -get_seed_32(int i) -{ - ee_s32 retval; - switch (i) - { - case 1: - retval = portme_sys1(); - break; - case 2: - retval = portme_sys2(); - break; - case 3: - retval = portme_sys3(); - break; - case 4: - retval = portme_sys4(); - break; - case 5: - retval = portme_sys5(); - break; - default: - retval = 0; - break; - } - return retval; -} -#endif - -/* Function: crc* - Service functions to calculate 16b CRC code. - -*/ -ee_u16 -crcu8(ee_u8 data, ee_u16 crc) -{ - ee_u8 i = 0, x16 = 0, carry = 0; - - for (i = 0; i < 8; i++) - { - x16 = (ee_u8)((data & 1) ^ ((ee_u8)crc & 1)); - data >>= 1; - - if (x16 == 1) - { - crc ^= 0x4002; - carry = 1; - } - else - carry = 0; - crc >>= 1; - if (carry) - crc |= 0x8000; - else - crc &= 0x7fff; - } - return crc; -} -ee_u16 -crcu16(ee_u16 newval, ee_u16 crc) -{ - crc = crcu8((ee_u8)(newval), crc); - crc = crcu8((ee_u8)((newval) >> 8), crc); - return crc; -} -ee_u16 -crcu32(ee_u32 newval, ee_u16 crc) -{ - crc = crc16((ee_s16)newval, crc); - crc = crc16((ee_s16)(newval >> 16), crc); - return crc; -} -ee_u16 -crc16(ee_s16 newval, ee_u16 crc) -{ - return crcu16((ee_u16)newval, crc); -} - -ee_u8 -check_data_types() -{ - ee_u8 retval = 0; - if (sizeof(ee_u8) != 1) - { - ee_printf("ERROR: ee_u8 is not an 8b datatype!\n"); - retval++; - } - if (sizeof(ee_u16) != 2) - { - ee_printf("ERROR: ee_u16 is not a 16b datatype!\n"); - retval++; - } - if (sizeof(ee_s16) != 2) - { - ee_printf("ERROR: ee_s16 is not a 16b datatype!\n"); - retval++; - } - if (sizeof(ee_s32) != 4) - { - ee_printf("ERROR: ee_s32 is not a 32b datatype!\n"); - retval++; - } - if (sizeof(ee_u32) != 4) - { - ee_printf("ERROR: ee_u32 is not a 32b datatype!\n"); - retval++; - } - if (sizeof(ee_ptr_int) != sizeof(int *)) - { - ee_printf( - "ERROR: ee_ptr_int is not a datatype that holds an int pointer!\n"); - retval++; - } - if (retval > 0) - { - ee_printf("ERROR: Please modify the datatypes in core_portme.h!\n"); - } - return retval; -} diff --git a/benchmarks/riscv-coremark/coremark/coremark.exe b/benchmarks/riscv-coremark/coremark/coremark.exe deleted file mode 100755 index 75b8e8468..000000000 Binary files a/benchmarks/riscv-coremark/coremark/coremark.exe and /dev/null differ diff --git a/benchmarks/riscv-coremark/coremark/coremark.h b/benchmarks/riscv-coremark/coremark/coremark.h deleted file mode 100644 index 9c5e4060a..000000000 --- a/benchmarks/riscv-coremark/coremark/coremark.h +++ /dev/null @@ -1,183 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains declarations of the various benchmark functions. -*/ - -/* Configuration: TOTAL_DATA_SIZE - Define total size for data algorithms will operate on -*/ -#ifndef TOTAL_DATA_SIZE -#define TOTAL_DATA_SIZE 2 * 1000 -#endif - -#define SEED_ARG 0 -#define SEED_FUNC 1 -#define SEED_VOLATILE 2 - -#define MEM_STATIC 0 -#define MEM_MALLOC 1 -#define MEM_STACK 2 - -#include "core_portme.h" - -#if HAS_STDIO -#include -#endif -#if HAS_PRINTF -#define ee_printf printf -#endif - -/* Actual benchmark execution in iterate */ -void *iterate(void *pres); - -/* Typedef: secs_ret - For machines that have floating point support, get number of seconds as - a double. Otherwise an unsigned int. -*/ -#if HAS_FLOAT -typedef double secs_ret; -#else -typedef ee_u32 secs_ret; -#endif - -#if MAIN_HAS_NORETURN -#define MAIN_RETURN_VAL -#define MAIN_RETURN_TYPE void -#else -#define MAIN_RETURN_VAL 0 -#define MAIN_RETURN_TYPE int -#endif - -void start_time(void); -void stop_time(void); -CORE_TICKS get_time(void); -secs_ret time_in_secs(CORE_TICKS ticks); - -/* Misc useful functions */ -ee_u16 crcu8(ee_u8 data, ee_u16 crc); -ee_u16 crc16(ee_s16 newval, ee_u16 crc); -ee_u16 crcu16(ee_u16 newval, ee_u16 crc); -ee_u16 crcu32(ee_u32 newval, ee_u16 crc); -ee_u8 check_data_types(void); -void * portable_malloc(ee_size_t size); -void portable_free(void *p); -ee_s32 parseval(char *valstring); - -/* Algorithm IDS */ -#define ID_LIST (1 << 0) -#define ID_MATRIX (1 << 1) -#define ID_STATE (1 << 2) -#define ALL_ALGORITHMS_MASK (ID_LIST | ID_MATRIX | ID_STATE) -#define NUM_ALGORITHMS 3 - -/* list data structures */ -typedef struct list_data_s -{ - ee_s16 data16; - ee_s16 idx; -} list_data; - -typedef struct list_head_s -{ - struct list_head_s *next; - struct list_data_s *info; -} list_head; - -/*matrix benchmark related stuff */ -#define MATDAT_INT 1 -#if MATDAT_INT -typedef ee_s16 MATDAT; -typedef ee_s32 MATRES; -#else -typedef ee_f16 MATDAT; -typedef ee_f32 MATRES; -#endif - -typedef struct MAT_PARAMS_S -{ - int N; - MATDAT *A; - MATDAT *B; - MATRES *C; -} mat_params; - -/* state machine related stuff */ -/* List of all the possible states for the FSM */ -typedef enum CORE_STATE -{ - CORE_START = 0, - CORE_INVALID, - CORE_S1, - CORE_S2, - CORE_INT, - CORE_FLOAT, - CORE_EXPONENT, - CORE_SCIENTIFIC, - NUM_CORE_STATES -} core_state_e; - -/* Helper structure to hold results */ -typedef struct RESULTS_S -{ - /* inputs */ - ee_s16 seed1; /* Initializing seed */ - ee_s16 seed2; /* Initializing seed */ - ee_s16 seed3; /* Initializing seed */ - void * memblock[4]; /* Pointer to safe memory location */ - ee_u32 size; /* Size of the data */ - ee_u32 iterations; /* Number of iterations to execute */ - ee_u32 execs; /* Bitmask of operations to execute */ - struct list_head_s *list; - mat_params mat; - /* outputs */ - ee_u16 crc; - ee_u16 crclist; - ee_u16 crcmatrix; - ee_u16 crcstate; - ee_s16 err; - /* ultithread specific */ - core_portable port; -} core_results; - -/* Multicore execution handling */ -#if (MULTITHREAD > 1) -ee_u8 core_start_parallel(core_results *res); -ee_u8 core_stop_parallel(core_results *res); -#endif - -/* list benchmark functions */ -list_head *core_list_init(ee_u32 blksize, list_head *memblock, ee_s16 seed); -ee_u16 core_bench_list(core_results *res, ee_s16 finder_idx); - -/* state benchmark functions */ -void core_init_state(ee_u32 size, ee_s16 seed, ee_u8 *p); -ee_u16 core_bench_state(ee_u32 blksize, - ee_u8 *memblock, - ee_s16 seed1, - ee_s16 seed2, - ee_s16 step, - ee_u16 crc); - -/* matrix benchmark functions */ -ee_u32 core_init_matrix(ee_u32 blksize, - void * memblk, - ee_s32 seed, - mat_params *p); -ee_u16 core_bench_matrix(mat_params *p, ee_s16 seed, ee_u16 crc); diff --git a/benchmarks/riscv-coremark/coremark/coremark.md5 b/benchmarks/riscv-coremark/coremark/coremark.md5 deleted file mode 100644 index 94160db22..000000000 --- a/benchmarks/riscv-coremark/coremark/coremark.md5 +++ /dev/null @@ -1,6 +0,0 @@ -8d082dc4a9676c02731a8cf209339072 core_list_join.c -c984863b84b59185d8b5fb81c1ca7535 core_main.c -5fa21a0f7c3964167c9691db531ca652 core_matrix.c -edcfc7a0b146a50028014f06e6826aa3 core_state.c -45540ba2145adea1ec7ea2c72a1fbbcb core_util.c -8ca974c013b380dc7f0d6d1afb76eb2d coremark.h diff --git a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.c b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.c deleted file mode 100755 index fe8d29983..000000000 --- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.c +++ /dev/null @@ -1,336 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.h b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.h deleted file mode 100755 index 9471b12ec..000000000 --- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.h +++ /dev/null @@ -1,293 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem: - This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.mak b/benchmarks/riscv-coremark/coremark/cygwin/core_portme.mak deleted file mode 100644 index 97b6d6ace..000000000 --- a/benchmarks/riscv-coremark/coremark/cygwin/core_portme.mak +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/coremark/docs/READM.md b/benchmarks/riscv-coremark/coremark/docs/READM.md deleted file mode 100644 index 6f71f426d..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/READM.md +++ /dev/null @@ -1 +0,0 @@ -This folder contains the original, unaltered documents from the CoreMark V1.0 release. diff --git a/benchmarks/riscv-coremark/coremark/docs/balance_O0_joined.png b/benchmarks/riscv-coremark/coremark/docs/balance_O0_joined.png deleted file mode 100644 index 46b41583a..000000000 Binary files a/benchmarks/riscv-coremark/coremark/docs/balance_O0_joined.png and /dev/null differ diff --git a/benchmarks/riscv-coremark/coremark/docs/html/files/PIC32/core_portme-mak.html b/benchmarks/riscv-coremark/coremark/docs/html/files/PIC32/core_portme-mak.html deleted file mode 100644 index c222bac2d..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/files/PIC32/core_portme-mak.html +++ /dev/null @@ -1,68 +0,0 @@ - - -core_portme.mak - CoreMark - - - - - - - -

core_portme.mak

Summary
core_portme.mak
Variables
OUTFLAGUse this flag to define how to to get an executable (e.g -o)
CFLAGSUse this flag to define compiler options.
LFLAGS_ENDDefine any libraries needed for linking or other flags that should come at the end of the link line (e.g.
SEPARATE_COMPILEDefine if you need to separate compilation from link stage.
PORT_OBJSPort specific object files can be added here
Build Targets
port_prebuildGenerate any files that are needed before actual build starts.
port_postbuildGenerate any files that are needed after actual build end.
port_postrunDo platform specific after run stuff.
port_prerunDo platform specific after run stuff.
port_postloadDo platform specific after load stuff.
port_preloadDo platform specific before load stuff.
Variables
OPATH
PERLDefine perl executable to calculate the geomean if running separate.
- -

Variables

- -

OUTFLAG

Use this flag to define how to to get an executable (e.g -o)

- -

CFLAGS

Use this flag to define compiler options.  Note, you can add compiler options from the command line using XCFLAGS=”other flags”

- -

LFLAGS_END

Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).  Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.

- -

SEPARATE_COMPILE

Define if you need to separate compilation from link stage.  In this case, you also need to define below how to create an object file, and how to link.

- -

PORT_OBJS

Port specific object files can be added here

- -

Build Targets

- -

port_prebuild

Generate any files that are needed before actual build starts.  E.g. generate profile guidance files.  Sample PGO generation for gcc enabled with PGO=1

  • First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
  • Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
NoteUsing REBUILD=1

Use make PGO=1 to invoke this sample processing.

- -

port_postbuild

Generate any files that are needed after actual build end.  E.g. change format to srec, bin, zip in order to be able to load into flash

- -

port_postrun

Do platform specific after run stuff.  E.g. reset the board, backup the logfiles etc.

- -

port_prerun

Do platform specific after run stuff.  E.g. reset the board, backup the logfiles etc.

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port_postload

Do platform specific after load stuff.  E.g. reset the reset power to the flash eraser

- -

port_preload

Do platform specific before load stuff.  E.g. reset the reset power to the flash eraser

- -

Variables

- -

OPATH

Path to the output folder.  Defaultcurrent folder.
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PERL

Define perl executable to calculate the geomean if running separate.

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core_list_join.c

Summary
core_list_join.c
DescriptionBenchmark using a linked list.
Functions
cmp_complexCompare the data item in a list cell.
cmp_idxCompare the idx item in a list cell, and regen the data.
core_list_initInitialize list with data.
core_list_insertInsert an item to the list
core_list_removeRemove an item from the list.
core_list_undo_removeUndo a remove operation.
core_list_findFind an item in the list
core_list_reverseReverse a list
core_list_mergesortSort the list in place without recursion.
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Description

Benchmark using a linked list.

Linked list is a common data structure used in many applications.

For our purposes, this will excercise the memory units of the processor.  In particular, usage of the list pointers to find and alter data.

We are not using Malloc since some platforms do not support this library.

Instead, the memory block being passed in is used to create a list, and the benchmark takes care not to add more items then can be accomodated by the memory block.  The porting layer will make sure that we have a valid memory block.

All operations are done in place, without using any extra memory.

The list itself contains list pointers and pointers to data items.  Data items contain the following:

idxAn index that captures the initial order of the list.
dataVariable data initialized based on the input parameters.  The 16b are divided as follows:
  • Upper 8b are backup of original data.
  • Bit 7 indicates if the lower 7 bits are to be used as is or calculated.
  • Bits 0-2 indicate type of operation to perform to get a 7b value.
  • Bits 3-6 provide input for the operation.
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Functions

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cmp_complex

ee_s32 cmp_complex(list_data *a,
list_data *b,
core_results *res)

Compare the data item in a list cell.

Can be used by mergesort.

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cmp_idx

ee_s32 cmp_idx(list_data *a,
list_data *b,
core_results *res)

Compare the idx item in a list cell, and regen the data.

Can be used by mergesort.

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core_list_init

list_head *core_list_init(ee_u32 blksize,
list_head *memblock,
ee_s16 seed)

Initialize list with data.

Parameters

blksizeSize of memory to be initialized.
memblockPointer to memory block.
seedActual values chosen depend on the seed parameter.  The seed parameter MUST be supplied from a source that cannot be determined at compile time

Returns

Pointer to the head of the list.

- -

core_list_insert

list_head *core_list_insert_new(list_head *insert_point,
list_data *info,
list_head **memblock,
list_data **datablock ,
list_head *memblock_end,
list_data *datablock_end)

Insert an item to the list

Parameters

insert_pointwhere to insert the item.
infodata for the cell.
memblockpointer for the list header
datablockpointer for the list data
memblock_endend of region for list headers
datablock_endend of region for list data

Returns

Pointer to new item.

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core_list_remove

list_head *core_list_remove(list_head *item)

Remove an item from the list.

Operation

For a singly linked list, remove by copying the data from the next item over to the current cell, and unlinking the next item.

Note

since there is always a fake item at the end of the list, no need to check for NULL.

Returns

Removed item.

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core_list_undo_remove

list_head *core_list_undo_remove(list_head *item_removed,
list_head *item_modified)

Undo a remove operation.

Operation

Since we want each iteration of the benchmark to be exactly the same, we need to be able to undo a remove.  Link the removed item back into the list, and switch the info items.

Parameters

item_removedReturn value from the core_list_remove
item_modifiedList item that was modified during core_list_remove

Returns

The item that was linked back to the list.

- -

core_list_find

list_head *core_list_find(list_head *list,
list_data *info)

Find an item in the list

Operation

Find an item by idx (if not 0) or specific data value

Parameters

listlist head
infoidx or data to find

Returns

Found item, or NULL if not found.

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core_list_reverse

list_head *core_list_reverse(list_head *list)

Reverse a list

Operation

Rearrange the pointers so the list is reversed.

Parameters

listlist head
infoidx or data to find

Returns

Found item, or NULL if not found.

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core_list_mergesort

list_head *core_list_mergesort(list_head *list,
list_cmp cmp,
core_results *res)

Sort the list in place without recursion.

Description

Use mergesort, as for linked list this is a realistic solution.  Also, since this is aimed at embedded, care was taken to use iterative rather then recursive algorithm.  The sort can either return the list to original order (by idx) , or use the data item to invoke other other algorithms and change the order of the list.

Parameters

listlist to be sorted.
cmpcmp function to use

Returns

New head of the list.

Note

We have a special header for the list that will always be first, but the algorithm could theoretically modify where the list starts.

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ee_s32 cmp_complex(list_data *a,
list_data *b,
core_results *res)
Compare the data item in a list cell.
ee_s32 cmp_idx(list_data *a,
list_data *b,
core_results *res)
Compare the idx item in a list cell, and regen the data.
list_head *core_list_init(ee_u32 blksize,
list_head *memblock,
ee_s16 seed)
Initialize list with data.
list_head *core_list_insert_new(list_head *insert_point,
list_data *info,
list_head **memblock,
list_data **datablock ,
list_head *memblock_end,
list_data *datablock_end)
Insert an item to the list
list_head *core_list_remove(list_head *item)
Remove an item from the list.
list_head *core_list_undo_remove(list_head *item_removed,
list_head *item_modified)
Undo a remove operation.
list_head *core_list_find(list_head *list,
list_data *info)
Find an item in the list
list_head *core_list_reverse(list_head *list)
Reverse a list
list_head *core_list_mergesort(list_head *list,
list_cmp cmp,
core_results *res)
Sort the list in place without recursion.
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core_main.c

This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.

Summary
core_main.cThis file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
Functions
iterateRun the benchmark for a specified number of iterations.
mainMain entry routine for the benchmark.
- -

Functions

- -

iterate

Run the benchmark for a specified number of iterations.

Operation

For each type of benchmarked algorithm: a - Initialize the data block for the algorithm. b - Execute the algorithm N times.

Returns

NULL.

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main

#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(void)

Main entry routine for the benchmark.  This function is responsible for the following steps:

1Initialize input seeds from a source that cannot be determined at compile time.
2Initialize memory block for use.
3Run and time the benchmark.
4Report results, testing the validity of the output if the seeds are known.

Arguments

1first seed : Any value
2second seed : Must be identical to first for iterations to be identical
3third seed : Any value, should be at least an order of magnitude less then the input size, but bigger then 32.
4Iterations : Special, if set to 0, iterations will be automatically determined such that the benchmark will run between 10 to 100 secs
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#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(void)
Main entry routine for the benchmark.
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core_matrix.c

Summary
core_matrix.c
DescriptionMatrix manipulation benchmark
Functions
core_bench_matrixBenchmark function
matrix_testPerform matrix manipulation.
matrix_sumCalculate a function that depends on the values of elements in the matrix.
matrix_mul_constMultiply a matrix by a constant.
matrix_add_constAdd a constant value to all elements of a matrix.
matrix_mul_vectMultiply a matrix by a vector.
matrix_mul_matrixMultiply a matrix by a matrix.
matrix_mul_matrix_bitextractMultiply a matrix by a matrix, and extract some bits from the result.
- -

Description

Matrix manipulation benchmark

This very simple algorithm forms the basis of many more complex algorithms.

The tight inner loop is the focus of many optimizations (compiler as well as hardware based) and is thus relevant for embedded processing.

The total available data space will be divided to 3 parts

NxN Matrix Ainitialized with small values (upper 3/4 of the bits all zero).
NxN Matrix Binitialized with medium values (upper half of the bits all zero).
NxN Matrix Cused for the result.

The actual values for A and B must be derived based on input that is not available at compile time.

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Functions

- -

core_bench_matrix

ee_u16 core_bench_matrix(mat_params *p,
ee_s16 seed,
ee_u16 crc)

Benchmark function

Iterate matrix_test N times, changing the matrix values slightly by a constant amount each time.

- -

matrix_test

ee_s16 matrix_test(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B,
MATDAT val)

Perform matrix manipulation.

Parameters

NDimensions of the matrix.
Cmemory for result matrix.
Ainput matrix
Boperator matrix (not changed during operations)

Returns

A CRC value that captures all results calculated in the function.  In particular, crc of the value calculated on the result matrix after each step by matrix_sum.

Operation

1Add a constant value to all elements of a matrix.
2Multiply a matrix by a constant.
3Multiply a matrix by a vector.
4Multiply a matrix by a matrix.
5Add a constant value to all elements of a matrix.

After the last step, matrix A is back to original contents.

- -

matrix_sum

ee_s16 matrix_sum(ee_u32 N,
MATRES *C,
MATDAT clipval)

Calculate a function that depends on the values of elements in the matrix.

For each element, accumulate into a temporary variable.

As long as this value is under the parameter clipval, add 1 to the result if the element is bigger then the previous.

Otherwise, reset the accumulator and add 10 to the result.

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matrix_mul_const

void matrix_mul_const(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT val)

Multiply a matrix by a constant.  This could be used as a scaler for instance.

- -

matrix_add_const

void matrix_add_const(ee_u32 N,
MATDAT *A,
MATDAT val)

Add a constant value to all elements of a matrix.

- -

matrix_mul_vect

void matrix_mul_vect(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)

Multiply a matrix by a vector.  This is common in many simple filters (e.g. fir where a vector of coefficients is applied to the matrix.)

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matrix_mul_matrix

void matrix_mul_matrix(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)

Multiply a matrix by a matrix.  Basic code is used in many algorithms, mostly with minor changes such as scaling.

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matrix_mul_matrix_bitextract

void matrix_mul_matrix_bitextract(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)

Multiply a matrix by a matrix, and extract some bits from the result.  Basic code is used in many algorithms, mostly with minor changes such as scaling.

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ee_u16 core_bench_matrix(mat_params *p,
ee_s16 seed,
ee_u16 crc)
Benchmark function
ee_s16 matrix_test(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B,
MATDAT val)
Perform matrix manipulation.
ee_s16 matrix_sum(ee_u32 N,
MATRES *C,
MATDAT clipval)
Calculate a function that depends on the values of elements in the matrix.
void matrix_mul_const(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT val)
Multiply a matrix by a constant.
void matrix_add_const(ee_u32 N,
MATDAT *A,
MATDAT val)
Add a constant value to all elements of a matrix.
void matrix_mul_vect(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a vector.
void matrix_mul_matrix(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix.
void matrix_mul_matrix_bitextract(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix, and extract some bits from the result.
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core_state.c

Summary
core_state.c
DescriptionSimple state machines like this one are used in many embedded products.
Functions
core_bench_stateBenchmark function
core_init_stateInitialize the input data for the state machine.
core_state_transitionActual state machine.
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Description

Simple state machines like this one are used in many embedded products.

For more complex state machines, sometimes a state transition table implementation is used instead, trading speed of direct coding for ease of maintenance.

Since the main goal of using a state machine in CoreMark is to excercise the switch/if behaviour, we are using a small moore machine.

In particular, this machine tests type of string input, trying to determine whether the input is a number or something else.  (see core_state).

core_state
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Functions

- -

core_bench_state

ee_u16 core_bench_state(ee_u32 blksize,
ee_u8 *memblock,
ee_s16 seed1,
ee_s16 seed2,
ee_s16 step,
ee_u16 crc)

Benchmark function

Go over the input twice, once direct, and once after introducing some corruption.

- -

core_init_state

void core_init_state(ee_u32 size,
ee_s16 seed,
ee_u8 *p)

Initialize the input data for the state machine.

Populate the input with several predetermined strings, interspersed.  Actual patterns chosen depend on the seed parameter.

Note

The seed parameter MUST be supplied from a source that cannot be determined at compile time

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core_state_transition

enum CORE_STATE core_state_transition(ee_u8 **instr ,
ee_u32 *transition_count)

Actual state machine.

The state machine will continue scanning until either

1an invalid input is detcted.
2a valid number has been detected.

The input pointer is updated to point to the end of the token, and the end state is returned (either specific format determined or invalid).

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ee_u16 core_bench_state(ee_u32 blksize,
ee_u8 *memblock,
ee_s16 seed1,
ee_s16 seed2,
ee_s16 step,
ee_u16 crc)
Benchmark function
void core_init_state(ee_u32 size,
ee_s16 seed,
ee_u8 *p)
Initialize the input data for the state machine.
enum CORE_STATE core_state_transition(ee_u8 **instr ,
ee_u32 *transition_count)
Actual state machine.
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core_util.c

Summary
core_util.c
Functions
get_seedGet a values that cannot be determined at compile time.
crc*Service functions to calculate 16b CRC code.
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Functions

- -

get_seed

Get a values that cannot be determined at compile time.

Since different embedded systems and compilers are used, 3 different methods are provided

1Using a volatile variable.  This method is only valid if the compiler is forced to generate code that reads the value of a volatile variable from memory at run time.  Please note, if using this method, you would need to modify core_portme.c to generate training profile.
2Command line arguments.  This is the preferred method if command line arguments are supported.
3System function.  If none of the first 2 methods is available on the platform, a system function which is not a stub can be used.

e.g. read the value on GPIO pins connected to switches, or invoke special simulator functions.

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crc*

Service functions to calculate 16b CRC code.

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coremark.h

Summary
coremark.h
DescriptionThis file contains declarations of the various benchmark functions.
Configuration
TOTAL_DATA_SIZEDefine total size for data algorithms will operate on
Types
secs_retFor machines that have floating point support, get number of seconds as a double.
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Description

This file contains declarations of the various benchmark functions.

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Configuration

- -

TOTAL_DATA_SIZE

Define total size for data algorithms will operate on

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Types

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secs_ret

For machines that have floating point support, get number of seconds as a double.  Otherwise an unsigned int.

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core_portme.c

Summary
core_portme.c
portable_mallocProvide malloc() functionality in a platform specific way.
portable_freeProvide free() functionality in a platform specific way.
TIMER_RES_DIVIDERDivider to trade off timer resolution and total time that can be measured.
start_timeThis function will be called right before starting the timed portion of the benchmark.
stop_timeThis function will be called right after ending the timed portion of the benchmark.
get_timeReturn an abstract “ticks” number that signifies time on the system.
time_in_secsConvert the value returned by get_time to seconds.
portable_initTarget specific initialization code Test for some common mistakes.
portable_finiTarget specific final code
core_start_parallelStart benchmarking in a parallel context.
core_stop_parallelStop a parallel context execution of coremark, and gather the results.
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portable_malloc

void *portable_malloc(size_t size)

Provide malloc() functionality in a platform specific way.

- -

portable_free

void portable_free(void *p)

Provide free() functionality in a platform specific way.

- -

TIMER_RES_DIVIDER

Divider to trade off timer resolution and total time that can be measured.

Use lower values to increase resolution, but make sure that overflow does not occur.  If there are issues with the return value overflowing, increase this value.

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start_time

void start_time(void)

This function will be called right before starting the timed portion of the benchmark.

Implementation may be capturing a system timer (as implemented in the example code) or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0.

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stop_time

void stop_time(void)

This function will be called right after ending the timed portion of the benchmark.

Implementation may be capturing a system timer (as implemented in the example code) or other system parameters - e.g. reading the current value of cpu cycles counter.

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get_time

CORE_TICKS get_time(void)

Return an abstract “ticks” number that signifies time on the system.

Actual value returned may be cpu cycles, milliseconds or any other value, as long as it can be converted to seconds by time_in_secs.  This methodology is taken to accomodate any hardware or simulated platform.  The sample implementation returns millisecs by default, and the resolution is controlled by TIMER_RES_DIVIDER

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time_in_secs

secs_ret time_in_secs(CORE_TICKS ticks)

Convert the value returned by get_time to seconds.

The secs_ret type is used to accomodate systems with no support for floating point.  Default implementation implemented by the EE_TICKS_PER_SEC macro above.

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portable_init

void portable_init(core_portable *p,
int *argc,
char *argv[])

Target specific initialization code Test for some common mistakes.

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portable_fini

void portable_fini(core_portable *p)

Target specific final code

- -

core_start_parallel

Start benchmarking in a parallel context.

Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.  Other implementations using MCAPI or other standards can easily be devised.

- -

core_stop_parallel

Stop a parallel context execution of coremark, and gather the results.

Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets.  Other implementations using MCAPI or other standards can easily be devised.

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void *portable_malloc(size_t size)
Provide malloc() functionality in a platform specific way.
void portable_free(void *p)
Provide free() functionality in a platform specific way.
void start_time(void)
This function will be called right before starting the timed portion of the benchmark.
void stop_time(void)
This function will be called right after ending the timed portion of the benchmark.
CORE_TICKS get_time(void)
Return an abstract “ticks” number that signifies time on the system.
secs_ret time_in_secs(CORE_TICKS ticks)
Convert the value returned by get_time to seconds.
void portable_init(core_portable *p,
int *argc,
char *argv[])
Target specific initialization code Test for some common mistakes.
void portable_fini(core_portable *p)
Target specific final code
Divider to trade off timer resolution and total time that can be measured.
For machines that have floating point support, get number of seconds as a double.
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core_portme.h

Summary
core_portme.h
DescriptionThis file contains configuration constants required to execute on different platforms
Configuration
HAS_FLOATDefine to 1 if the platform supports floating point.
HAS_TIME_HDefine to 1 if platform has the time.h header file, and implementation of functions thereof.
USE_CLOCKDefine to 1 if platform has the time.h header file, and implementation of functions thereof.
HAS_STDIODefine to 1 if the platform has stdio.h.
HAS_PRINTFDefine to 1 if the platform has stdio.h and implements the printf function.
CORE_TICKSDefine type of return from the timing functions.
SEED_METHODDefines method to get seed values that cannot be computed at compile time.
MEM_METHODDefines method to get a block of memry.
MULTITHREADDefine for parallel execution
USE_PTHREADSample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.
USE_FORKSample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.
USE_SOCKETSample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom
MAIN_HAS_NOARGCNeeded if platform does not support getting arguments to main.
MAIN_HAS_NORETURNNeeded if platform does not support returning a value from main.
Variables
default_num_contextsNumber of contexts to spawn in multicore context.
- -

Description

This file contains configuration constants required to execute on different platforms

- -

Configuration

- -

HAS_FLOAT

Define to 1 if the platform supports floating point.

- -

HAS_TIME_H

Define to 1 if platform has the time.h header file, and implementation of functions thereof.

- -

USE_CLOCK

Define to 1 if platform has the time.h header file, and implementation of functions thereof.

- -

HAS_STDIO

Define to 1 if the platform has stdio.h.

- -

HAS_PRINTF

Define to 1 if the platform has stdio.h and implements the printf function.

- -

CORE_TICKS

Define type of return from the timing functions.

- -

SEED_METHOD

Defines method to get seed values that cannot be computed at compile time.

Valid values

SEED_ARGfrom command line.
SEED_FUNCfrom a system function.
SEED_VOLATILEfrom volatile variables.
- -

MEM_METHOD

Defines method to get a block of memry.

Valid values

MEM_MALLOCfor platforms that implement malloc and have malloc.h.
MEM_STATICto use a static memory array.
MEM_STACKto allocate the data block on the stack (NYI).
- -

MULTITHREAD

Define for parallel execution

Valid values

1only one context (default).
N>1will execute N copies in parallel.

Note

If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined.

Two sample implementations are provided.  Use USE_PTHREAD or USE_FORK to enable them.

It is valid to have a different implementation of core_start_parallel and <core_end_parallel> in core_portme.c, to fit a particular architecture.

- -

USE_PTHREAD

Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.

Valid values

0Do not use pthreads API.
1Use pthreads API

Note

This flag only matters if MULTITHREAD has been defined to a value greater then 1.

- -

USE_FORK

Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.

Valid values

0Do not use fork API.
1Use fork API

Note

This flag only matters if MULTITHREAD has been defined to a value greater then 1.

- -

USE_SOCKET

Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom

Valid values

0Do not use fork and sockets API.
1Use fork and sockets API

Note

This flag only matters if MULTITHREAD has been defined to a value greater then 1.

- -

MAIN_HAS_NOARGC

Needed if platform does not support getting arguments to main.

Valid values

0argc/argv to main is supported
1argc/argv to main is not supported
- -

MAIN_HAS_NORETURN

Needed if platform does not support returning a value from main.

Valid values

0main returns an int, and return value will be 0.
1platform does not support returning a value from main
- -

Variables

- -

default_num_contexts

extern ee_u32 default_num_contexts

Number of contexts to spawn in multicore context.  Override this global value to change number of contexts used.

Note

This value may not be set higher then the MULTITHREAD define.

To experiment, you can set the MULTITHREAD define to the highest value expected, and use argc/argv in the portable_init to set this value from the command line.

- -
- - - - - - - - - - -
extern ee_u32 default_num_contexts
Number of contexts to spawn in multicore context.
Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.
Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.
Start benchmarking in a parallel context.
Define for parallel execution
void portable_init(core_portable *p,
int *argc,
char *argv[])
Target specific initialization code Test for some common mistakes.
- - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-mak.html b/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-mak.html deleted file mode 100644 index ffd6cbe66..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/files/linux/core_portme-mak.html +++ /dev/null @@ -1,76 +0,0 @@ - - -core_portme.mak - CoreMark - - - - - - - -

core_portme.mak

Summary
core_portme.mak
Variables
OUTFLAGUse this flag to define how to to get an executable (e.g -o)
CCUse this flag to define compiler to use
CFLAGSUse this flag to define compiler options.
LFLAGS_ENDDefine any libraries needed for linking or other flags that should come at the end of the link line (e.g.
PORT_SRCSPort specific source files can be added here
LOADDefine this flag if you need to load to a target, as in a cross compile environment.
RUNDefine this flag if running does not consist of simple invocation of the binary.
SEPARATE_COMPILEDefine if you need to separate compilation from link stage.
PORT_OBJSPort specific object files can be added here
Build Targets
port_prebuildGenerate any files that are needed before actual build starts.
port_postbuildGenerate any files that are needed after actual build end.
port_postrunDo platform specific after run stuff.
port_prerunDo platform specific after run stuff.
port_postloadDo platform specific after load stuff.
port_preloadDo platform specific before load stuff.
Variables
OPATH
PERLDefine perl executable to calculate the geomean if running separate.
- -

Variables

- -

OUTFLAG

Use this flag to define how to to get an executable (e.g -o)

- -

CC

Use this flag to define compiler to use

- -

CFLAGS

Use this flag to define compiler options.  Note, you can add compiler options from the command line using XCFLAGS=”other flags”

- -

LFLAGS_END

Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts).  Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt.

- -

PORT_SRCS

Port specific source files can be added here

- -

LOAD

Define this flag if you need to load to a target, as in a cross compile environment.

- -

RUN

Define this flag if running does not consist of simple invocation of the binary.  In a cross compile environment, you need to define this.

- -

SEPARATE_COMPILE

Define if you need to separate compilation from link stage.  In this case, you also need to define below how to create an object file, and how to link.

- -

PORT_OBJS

Port specific object files can be added here

- -

Build Targets

- -

port_prebuild

Generate any files that are needed before actual build starts.  E.g. generate profile guidance files.  Sample PGO generation for gcc enabled with PGO=1

  • First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line.
  • Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it.
NoteUsing REBUILD=1

Use make PGO=1 to invoke this sample processing.

- -

port_postbuild

Generate any files that are needed after actual build end.  E.g. change format to srec, bin, zip in order to be able to load into flash

- -

port_postrun

Do platform specific after run stuff.  E.g. reset the board, backup the logfiles etc.

- -

port_prerun

Do platform specific after run stuff.  E.g. reset the board, backup the logfiles etc.

- -

port_postload

Do platform specific after load stuff.  E.g. reset the reset power to the flash eraser

- -

port_preload

Do platform specific before load stuff.  E.g. reset the reset power to the flash eraser

- -

Variables

- -

OPATH

Path to the output folder.  Defaultcurrent folder.
- -

PERL

Define perl executable to calculate the geomean if running separate.

- -
- - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/files/readme-txt.html b/benchmarks/riscv-coremark/coremark/docs/html/files/readme-txt.html deleted file mode 100644 index 2b57f37f4..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/files/readme-txt.html +++ /dev/null @@ -1,71 +0,0 @@ - - -CoreMark - - - - - - - -

CoreMark

Summary
CoreMark
WelcomeCopyright © 2009 EEMBC All rights reserved.
Building and runningDownload the release files from the www.coremark.org.
DocumentationWhen you unpack the documentation (tar -vzxf coremark_<version>_docs.tgz) a docs folder will be created.
Submitting resultsCoreMark results can be submitted on the web.
Run rulesWhat is and is not allowed.
Reporting rulesHow to report results on a data sheet?
Log File FormatThe log files have the following format
LegalSee LICENSE.txt or the word document file under docs/LICENSE.doc.
CreditsMany thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)
- -

Welcome

Copyright © 2009 EEMBC All rights reserved.  CoreMark is a trademark of EEMBC and EEMBC is a registered trademark of the Embedded Microprocessor Benchmark Consortium.

CoreMark’s primary goals are simplicity and providing a method for testing only a processor’s core features.

For more information about EEMBC’s comprehensive embedded benchmark suites, please see www.eembc.org.

- -

Building and running

Download the release files from the www.coremark.org.  You can verify the download using the coremark_<version>.md5 file

md5sum -c coremark_<version>.md5

Unpack the distribution (tar -vzxf coremark_<version>.tgz && tar -vzxf coremark_<version>_docs.tgz) then change to the coremark_<version> folder.

To build and run the benchmark, type

make

Full results are available in the files run1.log and run2.log.  CoreMark result can be found in run1.log.

For self hosted Linux or Cygwin platforms, a simple make should work.

Cross Compile

For cross compile platforms please adjust core_portme.mak, core_portme.h (and possibly core_portme.c) according to the specific platform used.  When porting to a new platform, it is recommended to copy one of the default port folders (e.g. mkdir <platform> && cp linux/* <platform>), adjust the porting files, and run

make PORT_DIR=<platform>

Systems without make

The following files need to be compiled:

For example

gcc -O2 -o coremark.exe core_list_join.c core_main.c core_matrix.c core_state.c core_util.c simple/core_portme.c -DPERFORMANCE_RUN=1 -DITERATIONS=1000
-./coremark.exe > run1.log

The above will compile the benchmark for a performance run and 1000 iterations.  Output is redirected to run1.log.

Make targets

runDefault target, creates run1.log and run2.log.
run1.logRun the benchmark with performance parameters, and output to run1.log
run2.logRun the benchmark with validation parameters, and output to run2.log
run3.logRun the benchmark with profile generation parameters, and output to run3.log
compilecompile the benchmark executable
linklink the benchmark executable
checktest MD5 of sources that may not be modified
cleanclean temporary files

ITERATIONS

By default, the benchmark will run between 10-100 seconds.  To override, use ITERATIONS=N

make ITERATIONS=10

Will run the benchmark for 10 iterations.  It is recommended to set a specific number of iterations in certain situations e.g.:

  • Running with a simulator
  • Measuring power/energy
  • Timing cannot be restarted

Minimum required run time

Results are only valid for reporting if the benchmark ran for at least 10 secs!

XCFLAGS

To add compiler flags from the command line, use XCFLAGS e.g.

make XCFLAGS="-g -DMULTITHREAD=4 -DUSE_FORK=1"
  • CORE_DEBUG

Define to compile for a debug run if you get incorrect CRC.

make XCFLAGS="-DCORE_DEBUG=1"
  • Parallel Execution

Use XCFLAGS=-DMULTITHREAD=N where N is number of threads to run in parallel.  Several implementations are available to execute in multiple contexts, or you can implement your own in core_portme.c.

make XCFLAGS="-DMULTITHREAD=4 -DUSE_PTHREAD"

Above will compile the benchmark for execution on 4 cores, using POSIX Threads API.

REBUILD

To force rebuild, add the flag REBUILD to the command line

make REBUILD=1

Check core_portme.mak for more important options.

Run parameters for the benchmark executable

Coremark executable takes several parameters as follows (if main accepts arguments).  1st - A seed value used for initialization of data.  2nd - A seed value used for initialization of data.  3rd - A seed value used for initialization of data.  4th - Number of iterations (0 for auto : default value) 5th - Reserved for internal use.  6th - Reserved for internal use.  7th - For malloc users only, ovreride the size of the input data buffer.

The run target from make will run coremark with 2 different data initialization seeds.

Alternative parameters

If not using malloc or command line arguments are not supported, the buffer size for the algorithms must be defined via the compiler define TOTAL_DATA_SIZE.  TOTAL_DATA_SIZE must be set to 2000 bytes (default) for standard runs.  The default for such a target when testing different configurations could be ...

make XCFLAGS="-DTOTAL_DATA_SIZE=6000 -DMAIN_HAS_NOARGC=1"
- -

Documentation

When you unpack the documentation (tar -vzxf coremark_<version>_docs.tgz) a docs folder will be created.  Check the file docs/html/index.html and the website http://www.coremark.org for more info.

- -

Submitting results

CoreMark results can be submitted on the web.

Open a web browser and go to http://www.coremark.org- /benchmark- /index.php?pg=benchmark Select the link to add a new score and follow the instructions.

- -

Run rules

What is and is not allowed.

Required

1The benchmark needs to run for at least 10 seconds.
2All validation must succeed for seeds 0,0,0x66 and 0x3415,0x3415,0x66, buffer size of 2000 bytes total.
  • If not using command line arguments to main:
make XCFLAGS="-DPERFORMANCE_RUN=1" REBUILD=1 run1.log
-make XCFLAGS="-DVALIDATION_RUN=1" REBUILD=1 run2.log
3If using profile guided optimization, profile must be generated using seeds of 8,8,8, and buffer size of 1200 bytes total.
make XCFLAGS="-DTOTAL_DATA_SIZE=1200 -DPROFILE_RUN=1" REBUILD=1 run3.log
4All source files must be compiled with the same flags.
5All data type sizes must match size in bits such that:
  • ee_u8 is an 8 bits datatype.
  • ee_s16 is an 16 bits datatype.
  • ee_u16 is an 16 bits datatype.
  • ee_s32 is an 32 bits datatype.
  • ee_u32 is an 32 bits datatype.

Allowed

  • Changing number of iterations
  • Changing toolchain and build/load/run options
  • Changing method of acquiring a data memory block
  • Changing the method of acquiring seed values
  • Changing implementation in core_portme.c
  • Changing configuration values in core_portme.h
  • Changing core_portme.mak

Not allowed

  • Changing of source file other then core_portme* (use make check to validate)
- -

Reporting rules

How to report results on a data sheet?

CoreMark 1.0 : N / C [/ P] [/ M]

NNumber of iterations per second with seeds 0,0,0x66,size=2000)
CCompiler version and flags
PParameters such as data and code allocation specifics
  • This parameter may be omitted if all data was allocated on the heap in RAM.
  • This parameter may not be omitted when reporting CoreMark/MHz
MType of parallel execution (if used) and number of contexts This parameter may be omitted if parallel execution was not used.

e.g.

CoreMark 1.0 : 128 / GCC 4.1.2 -O2 -fprofile-use / Heap in TCRAM / FORK:2

or

CoreMark 1.0 : 1400 / GCC 3.4 -O4

If reporting scaling results, the results must be reported as follows

CoreMark/MHz 1.0 : N / C / P [/ M]

PWhen reporting scaling results, memory parameter must also indicate memory frequency:core frequency ratio.
  • If the core has cache and cache frequency to core frequency ratio is configurable, that must also be included.

e.g.

CoreMark/MHz 1.0 : 1.47 / GCC 4.1.2 -O2 / DDR3(Heap) 30:1 Memory 1:1 Cache
- -

Log File Format

The log files have the following format

2K performance run parameters for coremark. (Run type)
-CoreMark Size       : 666                   (Buffer size)
-Total ticks         : 25875                 (platform dependent value)
-Total time (secs)   : 25.875000             (actual time in seconds)
-Iterations/Sec      : 3864.734300           (Performance value to report)
-Iterations          : 100000                (number of iterations used)
-Compiler version    : GCC3.4.4              (Compiler and version)
-Compiler flags      : -O2                   (Compiler and linker flags)
-Memory location     : Code in flash, data in on chip RAM
-seedcrc             : 0xe9f5                (identifier for the input seeds)
-[0]crclist          : 0xe714                (validation for list part)
-[0]crcmatrix        : 0x1fd7                (validation for matrix part)
-[0]crcstate         : 0x8e3a                (validation for state part)
-[0]crcfinal         : 0x33ff                (iteration dependent output)
-Correct operation validated. See README.md for run and reporting rules.  (*Only when run is successful*)
-CoreMark 1.0 : 6508.490622 / GCC3.4.4 -O2 / Heap                          (*Only on a successful performance run*)
- -

Legal

See LICENSE.txt or the word document file under docs/LICENSE.doc.  For more information on your legal rights to use this benchmark, please see http://www.coremark.org- /download- /register.php?pg=register

- -

Credits

Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)

  • Alan Anderson, ADI
  • Adhikary Rajiv, ADI
  • Elena Stohr, ARM
  • Ian Rickards, ARM
  • Andrew Pickard, ARM
  • Trent Parker, CAVIUM
  • Shay Gal-On, EEMBC
  • Markus Levy, EEMBC
  • Ron Olson, IBM
  • Eyal Barzilay, MIPS
  • Jens Eltze, NEC
  • Hirohiko Ono, NEC
  • Ulrich Drees, NEC
  • Frank Roscheda, NEC
  • Rob Cosaro, NXP
  • Shumpei Kawasaki, RENESAS
- -
- - - - - - - - - - -
This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
- - - - - - - - diff --git a/benchmarks/riscv-coremark/coremark/docs/html/files/release_notes-txt.html b/benchmarks/riscv-coremark/coremark/docs/html/files/release_notes-txt.html deleted file mode 100644 index 6658c7141..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/files/release_notes-txt.html +++ /dev/null @@ -1,56 +0,0 @@ - - -Release Notes - CoreMark - - - - - - - -

Release Notes

Version: 1.01

History

Version 1.01

  • Added validation testing the sizes of datatypes.

Version 1.00

  • First public version.

Validation

This release was tested on the following platforms

  • x86 cygwin and gcc 3.4 (Quad, dual and single core systems)
  • x86 linux (Ubuntu/Fedora) and gcc (4.2/4.1) (Quad and single core systems)
  • MIPS64 BE linux and gcc 3.4 16 cores system
  • MIPS32 BE linux with CodeSourcery compiler 4.2-177 on Malta/Linux with a 1004K 3-core system
  • PPC simulator with gcc 4.2.2 (No OS)
  • PPC 64b BE linux (yellowdog) with gcc 3.4 and 4.1 (Dual core system)
  • BF533 with VDSP50
  • Renesas R8C/H8 MCU with HEW 4.05
  • NXP LPC1700 armcc v4.0.0.524
  • NEC 78K with IAR v4.61
  • ARM simulator with armcc v4

Coverage

GCOV results can be found on SVN under cover.

Memory analysis

Valgrind 3.4.0 used and no errors reported.

Balance analysis

Number of instructions executed for each function tested with cachegrind and found balanced with gcc and -O0.

Statistics

Lines

Lines  Blank  Cmnts  Source     AESL
-=====  =====  =====  =====  ==========  =======================================
-  469     66    170    251       627.5  core_list_join.c  (C)
-  330     18     54    268       670.0  core_main.c  (C)
-  256     32     80    146       365.0  core_matrix.c  (C)
-  240     16     51    186       465.0  core_state.c  (C)
-  165     11     20    134       335.0  core_util.c  (C)
-  150     23     36     98       245.0  coremark.h  (C)
- 1610    166    411   1083      2707.5  ----- Benchmark -----  (6 files)
-  293     15     74    212       530.0  linux/core_portme.c  (C)
-  235     30    104    104       260.0  linux/core_portme.h  (C)
-  528     45    178    316       790.0  ----- Porting -----  (2 files)
-
-
-* For comparison, here are the stats for Dhrystone
-Lines  Blank  Cmnts  Source     AESL
-=====  =====  =====  =====  ==========  =======================================
-  311     15    242     54       135.0  dhry.h  (C)
-  789    132    119    553      1382.5  dhry_1.c  (C)
-  186     26     68    107       267.5  dhry_2.c  (C)
- 1286    173    429    714      1785.0  ----- C -----  (3 files)
- -
- - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index.html b/benchmarks/riscv-coremark/coremark/docs/html/index.html deleted file mode 100644 index f7a88682a..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index.html +++ /dev/null @@ -1 +0,0 @@ - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/BuildTargets.html b/benchmarks/riscv-coremark/coremark/docs/html/index/BuildTargets.html deleted file mode 100644 index 635c0ff78..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/BuildTargets.html +++ /dev/null @@ -1,31 +0,0 @@ - - -Build Target Index - CoreMark - - - - - - - -
Build Target Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
P
 port_postbuild
linux/ core_portme.makPIC32/ core_portme.mak
 port_postload
linux/ core_portme.makPIC32/ core_portme.mak
 port_postrun
linux/ core_portme.makPIC32/ core_portme.mak
 port_prebuild
linux/ core_portme.makPIC32/ core_portme.mak
 port_preload
linux/ core_portme.makPIC32/ core_portme.mak
 port_prerun
linux/ core_portme.makPIC32/ core_portme.mak
- -
Generate any files that are needed after actual build end.
Do platform specific after load stuff.
Do platform specific after run stuff.
Generate any files that are needed before actual build starts.
Do platform specific before load stuff.
Do platform specific after run stuff.
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/Configuration.html b/benchmarks/riscv-coremark/coremark/docs/html/index/Configuration.html deleted file mode 100644 index 8e5ef3aab..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/Configuration.html +++ /dev/null @@ -1,51 +0,0 @@ - - -Configuration Index - CoreMark - - - - - - - -
Configuration Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
C
 CORE_TICKS
H
 HAS_FLOAT
 HAS_PRINTF
 HAS_STDIO
 HAS_TIME_H
M
 MAIN_HAS_NOARGC
 MAIN_HAS_NORETURN
 MEM_METHOD
 MULTITHREAD
S
 SEED_METHOD
T
 TOTAL_DATA_SIZE
U
 USE_CLOCK
 USE_FORK
 USE_PTHREAD
 USE_SOCKET
- -
Define type of return from the timing functions.
- - - -
Define to 1 if the platform supports floating point.
Define to 1 if the platform has stdio.h and implements the printf function.
Define to 1 if the platform has stdio.h.
Define to 1 if platform has the time.h header file, and implementation of functions thereof.
- - - -
Needed if platform does not support getting arguments to main.
Needed if platform does not support returning a value from main.
Defines method to get a block of memry.
Define for parallel execution
- - - -
Defines method to get seed values that cannot be computed at compile time.
- - - -
Define total size for data algorithms will operate on
- - - -
Define to 1 if platform has the time.h header file, and implementation of functions thereof.
Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.
Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.
Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom
- -
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Configuration Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
H
 HAS_FLOAT
 HAS_STDIO
 HAS_TIME_H
M
 MEM_METHOD
S
 SEED_METHOD
T
 TOTAL_DATA_SIZE
- -
Define to 1 if the platform supports floating point.
Define to 1 if the platform has stdio.h and implements the printf function.
Define to 1 if platform has the time.h header file, and implementation of functions thereof.
- - - -
Defines method to get a block of memry.
- - - -
Defines method to get seed values that cannot be computed at compile time.
- - - -
Define total size for data algorithms will operate on
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/Files.html b/benchmarks/riscv-coremark/coremark/docs/html/index/Files.html deleted file mode 100644 index 7e6d2fa04..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/Files.html +++ /dev/null @@ -1,35 +0,0 @@ - - -File Index - CoreMark - - - - - - - -
File Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
C
 core_list_join.c
 core_main.c
 core_matrix.c
 core_portme.c
 core_portme.h
 core_portme.mak
linux/ core_portme.makPIC32/ core_portme.mak
 core_state.c
 core_util.c
 CoreMark
 coremark.h
R
 Release Notes
- -
This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
- - - -
Version: 1.01
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/Functions.html b/benchmarks/riscv-coremark/coremark/docs/html/index/Functions.html deleted file mode 100644 index a249d5186..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/Functions.html +++ /dev/null @@ -1,55 +0,0 @@ - - -Function Index - CoreMark - - - - - - - -
Function Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
C
 cmp_complex
 cmp_idx
 core_bench_matrix
 core_bench_state
 core_init_state
 core_list_find
 core_list_init
 core_list_insert
 core_list_mergesort
 core_list_remove
 core_list_reverse
 core_list_undo_remove
 core_start_parallel
 core_state_transition
 core_stop_parallel
 crc*
G
 get_seed
 get_time
I
 iterate
M
 main
 matrix_add_const
 matrix_mul_const
 matrix_mul_matrix
 matrix_mul_matrix_bitextract
 matrix_mul_vect
 matrix_sum
 matrix_test
P
 portable_fini
 portable_free
 portable_init
 portable_malloc
S
 start_time
 stop_time
T
 time_in_secs
- -
ee_s32 cmp_complex(list_data *a,
list_data *b,
core_results *res)
Compare the data item in a list cell.
ee_s32 cmp_idx(list_data *a,
list_data *b,
core_results *res)
Compare the idx item in a list cell, and regen the data.
ee_u16 core_bench_matrix(mat_params *p,
ee_s16 seed,
ee_u16 crc)
Benchmark function
ee_u16 core_bench_state(ee_u32 blksize,
ee_u8 *memblock,
ee_s16 seed1,
ee_s16 seed2,
ee_s16 step,
ee_u16 crc)
Benchmark function
void core_init_state(ee_u32 size,
ee_s16 seed,
ee_u8 *p)
Initialize the input data for the state machine.
list_head *core_list_find(list_head *list,
list_data *info)
Find an item in the list
list_head *core_list_init(ee_u32 blksize,
list_head *memblock,
ee_s16 seed)
Initialize list with data.
list_head *core_list_insert_new(list_head *insert_point,
list_data *info,
list_head **memblock,
list_data **datablock ,
list_head *memblock_end,
list_data *datablock_end)
Insert an item to the list
list_head *core_list_mergesort(list_head *list,
list_cmp cmp,
core_results *res)
Sort the list in place without recursion.
list_head *core_list_remove(list_head *item)
Remove an item from the list.
list_head *core_list_reverse(list_head *list)
Reverse a list
list_head *core_list_undo_remove(list_head *item_removed,
list_head *item_modified)
Undo a remove operation.
Start benchmarking in a parallel context.
enum CORE_STATE core_state_transition(ee_u8 **instr ,
ee_u32 *transition_count)
Actual state machine.
Stop a parallel context execution of coremark, and gather the results.
Service functions to calculate 16b CRC code.
- - - -
Get a values that cannot be determined at compile time.
CORE_TICKS get_time(void)
Return an abstract “ticks” number that signifies time on the system.
- - - -
Run the benchmark for a specified number of iterations.
- - - -
#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(void)
Main entry routine for the benchmark.
void matrix_add_const(ee_u32 N,
MATDAT *A,
MATDAT val)
Add a constant value to all elements of a matrix.
void matrix_mul_const(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT val)
Multiply a matrix by a constant.
void matrix_mul_matrix(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix.
void matrix_mul_matrix_bitextract(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix, and extract some bits from the result.
void matrix_mul_vect(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a vector.
ee_s16 matrix_sum(ee_u32 N,
MATRES *C,
MATDAT clipval)
Calculate a function that depends on the values of elements in the matrix.
ee_s16 matrix_test(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B,
MATDAT val)
Perform matrix manipulation.
- - - -
void portable_fini(core_portable *p)
Target specific final code
void portable_free(void *p)
Provide free() functionality in a platform specific way.
void portable_init(core_portable *p,
int *argc,
char *argv[])
Target specific initialization code Test for some common mistakes.
void *portable_malloc(size_t size)
Provide malloc() functionality in a platform specific way.
- - - -
void start_time(void)
This function will be called right before starting the timed portion of the benchmark.
void stop_time(void)
This function will be called right after ending the timed portion of the benchmark.
- - - -
secs_ret time_in_secs(CORE_TICKS ticks)
Convert the value returned by get_time to seconds.
- -
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Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
B
 Build Targets
linux/ core_portme.makPIC32/ core_portme.mak
 Building and running
C
 CC
 CFLAGS
linux/ core_portme.makPIC32/ core_portme.mak
 cmp_complex
 cmp_idx
 Configuration
coremark.hlinux/ core_portme.h
 core_bench_matrix
 core_bench_state
 core_init_state
 core_list_find
 core_list_init
 core_list_insert
 core_list_join.c
 core_list_mergesort
 core_list_remove
 core_list_reverse
 core_list_undo_remove
 core_main.c
 core_matrix.c
 core_portme.c
 core_portme.h
 core_portme.mak
linux/ core_portme.makPIC32/ core_portme.mak
 core_start_parallel
 core_state.c
 core_state_transition
 core_stop_parallel
 CORE_TICKS
 core_util.c
 CoreMark
 coremark.h
 crc*
 Credits
D
 default_num_contexts
 Description
core_list_join.ccore_matrix.ccore_state.ccoremark.hlinux/ core_portme.h
 Documentation
F
 Functions
core_list_join.ccore_main.ccore_matrix.ccore_state.ccore_util.c
G
 get_seed
 get_time
H
 HAS_FLOAT
 HAS_PRINTF
 HAS_STDIO
 HAS_TIME_H
I
 iterate
L
 Legal
 LFLAGS_END
linux/ core_portme.makPIC32/ core_portme.mak
 LOAD
 Log File Format
M
 main
 MAIN_HAS_NOARGC
 MAIN_HAS_NORETURN
 matrix_add_const
 matrix_mul_const
 matrix_mul_matrix
 matrix_mul_matrix_bitextract
 matrix_mul_vect
 matrix_sum
 matrix_test
 MEM_METHOD
 MULTITHREAD
O
 OPATH
linux/ core_portme.makPIC32/ core_portme.mak
 OUTFLAG
linux/ core_portme.makPIC32/ core_portme.mak
P
 PERL
linux/ core_portme.makPIC32/ core_portme.mak
 PORT_OBJS
linux/ core_portme.makPIC32/ core_portme.mak
 port_postbuild
linux/ core_portme.makPIC32/ core_portme.mak
 port_postload
linux/ core_portme.makPIC32/ core_portme.mak
 port_postrun
linux/ core_portme.makPIC32/ core_portme.mak
 port_prebuild
linux/ core_portme.makPIC32/ core_portme.mak
 port_preload
linux/ core_portme.makPIC32/ core_portme.mak
 port_prerun
linux/ core_portme.makPIC32/ core_portme.mak
 PORT_SRCS
 portable_fini
 portable_free
 portable_init
 portable_malloc
R
 Release Notes
 Reporting rules
 RUN
 Run rules
- -
Download the release files from the www.coremark.org.
- - - -
Use this flag to define compiler to use
Use this flag to define compiler options.
ee_s32 cmp_complex(list_data *a,
list_data *b,
core_results *res)
Compare the data item in a list cell.
ee_s32 cmp_idx(list_data *a,
list_data *b,
core_results *res)
Compare the idx item in a list cell, and regen the data.
ee_u16 core_bench_matrix(mat_params *p,
ee_s16 seed,
ee_u16 crc)
Benchmark function
ee_u16 core_bench_state(ee_u32 blksize,
ee_u8 *memblock,
ee_s16 seed1,
ee_s16 seed2,
ee_s16 step,
ee_u16 crc)
Benchmark function
void core_init_state(ee_u32 size,
ee_s16 seed,
ee_u8 *p)
Initialize the input data for the state machine.
list_head *core_list_find(list_head *list,
list_data *info)
Find an item in the list
list_head *core_list_init(ee_u32 blksize,
list_head *memblock,
ee_s16 seed)
Initialize list with data.
list_head *core_list_insert_new(list_head *insert_point,
list_data *info,
list_head **memblock,
list_data **datablock ,
list_head *memblock_end,
list_data *datablock_end)
Insert an item to the list
list_head *core_list_mergesort(list_head *list,
list_cmp cmp,
core_results *res)
Sort the list in place without recursion.
list_head *core_list_remove(list_head *item)
Remove an item from the list.
list_head *core_list_reverse(list_head *list)
Reverse a list
list_head *core_list_undo_remove(list_head *item_removed,
list_head *item_modified)
Undo a remove operation.
This file contains the framework to acquire a block of memory, seed initial parameters, tun t he benchmark and report the results.
Start benchmarking in a parallel context.
enum CORE_STATE core_state_transition(ee_u8 **instr ,
ee_u32 *transition_count)
Actual state machine.
Stop a parallel context execution of coremark, and gather the results.
Define type of return from the timing functions.
Service functions to calculate 16b CRC code.
Many thanks to all of the individuals who helped with the development or testing of CoreMark including (Sorted by company name)
- - - -
extern ee_u32 default_num_contexts
Number of contexts to spawn in multicore context.
Benchmark using a linked list.
When you unpack the documentation (tar -vzxf coremark_version_docs.tgz) a docs folder will be created.
- - - - - - - -
Get a values that cannot be determined at compile time.
CORE_TICKS get_time(void)
Return an abstract “ticks” number that signifies time on the system.
- - - -
Define to 1 if the platform supports floating point.
Define to 1 if the platform has stdio.h and implements the printf function.
Define to 1 if the platform has stdio.h.
Define to 1 if platform has the time.h header file, and implementation of functions thereof.
- - - -
Run the benchmark for a specified number of iterations.
- - - -
See LICENSE.txt or the word document file under docs/LICENSE.doc.
Define any libraries needed for linking or other flags that should come at the end of the link line (e.g.
Define this flag if you need to load to a target, as in a cross compile environment.
The log files have the following format
- - - -
#if MAIN_HAS_NOARGC MAIN_RETURN_TYPE main(void)
Main entry routine for the benchmark.
Needed if platform does not support getting arguments to main.
Needed if platform does not support returning a value from main.
void matrix_add_const(ee_u32 N,
MATDAT *A,
MATDAT val)
Add a constant value to all elements of a matrix.
void matrix_mul_const(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT val)
Multiply a matrix by a constant.
void matrix_mul_matrix(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix.
void matrix_mul_matrix_bitextract(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a matrix, and extract some bits from the result.
void matrix_mul_vect(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B)
Multiply a matrix by a vector.
ee_s16 matrix_sum(ee_u32 N,
MATRES *C,
MATDAT clipval)
Calculate a function that depends on the values of elements in the matrix.
ee_s16 matrix_test(ee_u32 N,
MATRES *C,
MATDAT *A,
MATDAT *B,
MATDAT val)
Perform matrix manipulation.
Defines method to get a block of memry.
Define for parallel execution
- - - -
Use this flag to define how to to get an executable (e.g -o)
- - - -
Define perl executable to calculate the geomean if running separate.
Port specific object files can be added here
Generate any files that are needed after actual build end.
Do platform specific after load stuff.
Do platform specific after run stuff.
Generate any files that are needed before actual build starts.
Do platform specific before load stuff.
Do platform specific after run stuff.
Port specific source files can be added here
void portable_fini(core_portable *p)
Target specific final code
void portable_free(void *p)
Provide free() functionality in a platform specific way.
void portable_init(core_portable *p,
int *argc,
char *argv[])
Target specific initialization code Test for some common mistakes.
void *portable_malloc(size_t size)
Provide malloc() functionality in a platform specific way.
- - - -
Version: 1.01
How to report results on a data sheet?
Define this flag if running does not consist of simple invocation of the binary.
What is and is not allowed.
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/General2.html b/benchmarks/riscv-coremark/coremark/docs/html/index/General2.html deleted file mode 100644 index 3852ab5aa..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/General2.html +++ /dev/null @@ -1,47 +0,0 @@ - - -Index - CoreMark - - - - - - - -
Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
S
 secs_ret
 SEED_METHOD
 SEPARATE_COMPILE
linux/ core_portme.makPIC32/ core_portme.mak
 start_time
 stop_time
 Submitting results
T
 time_in_secs
 TIMER_RES_DIVIDER
 TOTAL_DATA_SIZE
 Types
U
 USE_CLOCK
 USE_FORK
 USE_PTHREAD
 USE_SOCKET
V
 Variables
linux/ core_portme.hlinux/ core_portme.makPIC32/ core_portme.mak
W
 Welcome
- -
For machines that have floating point support, get number of seconds as a double.
Defines method to get seed values that cannot be computed at compile time.
Define if you need to separate compilation from link stage.
void start_time(void)
This function will be called right before starting the timed portion of the benchmark.
void stop_time(void)
This function will be called right after ending the timed portion of the benchmark.
CoreMark results can be submitted on the web.
- - - -
secs_ret time_in_secs(CORE_TICKS ticks)
Convert the value returned by get_time to seconds.
Divider to trade off timer resolution and total time that can be measured.
Define total size for data algorithms will operate on
- - - -
Define to 1 if platform has the time.h header file, and implementation of functions thereof.
Sample implementation for launching parallel contexts This implementation uses fork, waitpid, shmget,shmat and shmdt.
Sample implementation for launching parallel contexts This implementation uses pthread_thread_create and pthread_join.
Sample implementation for launching parallel contexts This implementation uses fork, socket, sendto and recvfrom
- - - - - - - -
Copyright 2009 EEMBC All rights reserved.
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/Types.html b/benchmarks/riscv-coremark/coremark/docs/html/index/Types.html deleted file mode 100644 index 1f4413653..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/Types.html +++ /dev/null @@ -1,31 +0,0 @@ - - -Type Index - CoreMark - - - - - - - -
Type Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
S
 secs_ret
- -
For machines that have floating point support, get number of seconds as a double.
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/index/Variables.html b/benchmarks/riscv-coremark/coremark/docs/html/index/Variables.html deleted file mode 100644 index 8c050daef..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/index/Variables.html +++ /dev/null @@ -1,55 +0,0 @@ - - -Variable Index - CoreMark - - - - - - - -
Variable Index
$#! · 0-9 · A · B · C · D · E · F · G · H · I · J · K · L · M · N · O · P · Q · R · S · T · U · V · W · X · Y · Z
C
 CC
 CFLAGS
linux/ core_portme.makPIC32/ core_portme.mak
D
 default_num_contexts
L
 LFLAGS_END
linux/ core_portme.makPIC32/ core_portme.mak
 LOAD
O
 OPATH
linux/ core_portme.makPIC32/ core_portme.mak
 OUTFLAG
linux/ core_portme.makPIC32/ core_portme.mak
P
 PERL
linux/ core_portme.makPIC32/ core_portme.mak
 PORT_OBJS
linux/ core_portme.makPIC32/ core_portme.mak
 PORT_SRCS
R
 RUN
S
 SEPARATE_COMPILE
linux/ core_portme.makPIC32/ core_portme.mak
- -
Use this flag to define compiler to use
Use this flag to define compiler options.
- - - -
extern ee_u32 default_num_contexts
Number of contexts to spawn in multicore context.
- - - -
Define any libraries needed for linking or other flags that should come at the end of the link line (e.g.
Define this flag if you need to load to a target, as in a cross compile environment.
- - - -
Use this flag to define how to to get an executable (e.g -o)
- - - -
Define perl executable to calculate the geomean if running separate.
Port specific object files can be added here
Port specific source files can be added here
- - - -
Define this flag if running does not consist of simple invocation of the binary.
- - - -
Define if you need to separate compilation from link stage.
- -
- - - - - - - - - - - - \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/javascript/main.js b/benchmarks/riscv-coremark/coremark/docs/html/javascript/main.js deleted file mode 100644 index 91991f507..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/javascript/main.js +++ /dev/null @@ -1,836 +0,0 @@ -// This file is part of Natural Docs, which is Copyright (C) 2003-2008 Greg Valure -// Natural Docs is licensed under the GPL - - -// -// Browser Styles -// ____________________________________________________________________________ - -var agt=navigator.userAgent.toLowerCase(); -var browserType; -var browserVer; - -if (agt.indexOf("opera") != -1) - { - browserType = "Opera"; - - if (agt.indexOf("opera 7") != -1 || agt.indexOf("opera/7") != -1) - { browserVer = "Opera7"; } - else if (agt.indexOf("opera 8") != -1 || agt.indexOf("opera/8") != -1) - { browserVer = "Opera8"; } - else if (agt.indexOf("opera 9") != -1 || agt.indexOf("opera/9") != -1) - { browserVer = "Opera9"; } - } - -else if (agt.indexOf("applewebkit") != -1) - { - browserType = "Safari"; - - if (agt.indexOf("version/3") != -1) - { browserVer = "Safari3"; } - else if (agt.indexOf("safari/4") != -1) - { browserVer = "Safari2"; } - } - -else if (agt.indexOf("khtml") != -1) - { - browserType = "Konqueror"; - } - -else if (agt.indexOf("msie") != -1) - { - browserType = "IE"; - - if (agt.indexOf("msie 6") != -1) - { browserVer = "IE6"; } - else if (agt.indexOf("msie 7") != -1) - { browserVer = "IE7"; } - } - -else if (agt.indexOf("gecko") != -1) - { - browserType = "Firefox"; - - if (agt.indexOf("rv:1.7") != -1) - { browserVer = "Firefox1"; } - else if (agt.indexOf("rv:1.8)") != -1 || agt.indexOf("rv:1.8.0") != -1) - { browserVer = "Firefox15"; } - else if (agt.indexOf("rv:1.8.1") != -1) - { browserVer = "Firefox2"; } - } - - -// -// Support Functions -// ____________________________________________________________________________ - - -function GetXPosition(item) - { - var position = 0; - - if (item.offsetWidth != null) - { - while (item != document.body && item != null) - { - position += item.offsetLeft; - item = item.offsetParent; - }; - }; - - return position; - }; - - -function GetYPosition(item) - { - var position = 0; - - if (item.offsetWidth != null) - { - while (item != document.body && item != null) - { - position += item.offsetTop; - item = item.offsetParent; - }; - }; - - return position; - }; - - -function MoveToPosition(item, x, y) - { - // Opera 5 chokes on the px extension, so it can use the Microsoft one instead. - - if (item.style.left != null) - { - item.style.left = x + "px"; - item.style.top = y + "px"; - } - else if (item.style.pixelLeft != null) - { - item.style.pixelLeft = x; - item.style.pixelTop = y; - }; - }; - - -// -// Menu -// ____________________________________________________________________________ - - -function ToggleMenu(id) - { - if (!window.document.getElementById) - { return; }; - - var display = window.document.getElementById(id).style.display; - - if (display == "none") - { display = "block"; } - else - { display = "none"; } - - window.document.getElementById(id).style.display = display; - } - -function HideAllBut(ids, max) - { - if (document.getElementById) - { - ids.sort( function(a,b) { return a - b; } ); - var number = 1; - - while (number < max) - { - if (ids.length > 0 && number == ids[0]) - { ids.shift(); } - else - { - document.getElementById("MGroupContent" + number).style.display = "none"; - }; - - number++; - }; - }; - } - - -// -// Tooltips -// ____________________________________________________________________________ - - -var tooltipTimer = 0; - -function ShowTip(event, tooltipID, linkID) - { - if (tooltipTimer) - { clearTimeout(tooltipTimer); }; - - var docX = event.clientX + window.pageXOffset; - var docY = event.clientY + window.pageYOffset; - - var showCommand = "ReallyShowTip('" + tooltipID + "', '" + linkID + "', " + docX + ", " + docY + ")"; - - tooltipTimer = setTimeout(showCommand, 1000); - } - -function ReallyShowTip(tooltipID, linkID, docX, docY) - { - tooltipTimer = 0; - - var tooltip; - var link; - - if (document.getElementById) - { - tooltip = document.getElementById(tooltipID); - link = document.getElementById(linkID); - } -/* else if (document.all) - { - tooltip = eval("document.all['" + tooltipID + "']"); - link = eval("document.all['" + linkID + "']"); - } -*/ - if (tooltip) - { - var left = GetXPosition(link); - var top = GetYPosition(link); - top += link.offsetHeight; - - - // The fallback method is to use the mouse X and Y relative to the document. We use a separate if and test if its a number - // in case some browser snuck through the above if statement but didn't support everything. - - if (!isFinite(top) || top == 0) - { - left = docX; - top = docY; - } - - // Some spacing to get it out from under the cursor. - - top += 10; - - // Make sure the tooltip doesnt get smushed by being too close to the edge, or in some browsers, go off the edge of the - // page. We do it here because Konqueror does get offsetWidth right even if it doesnt get the positioning right. - - if (tooltip.offsetWidth != null) - { - var width = tooltip.offsetWidth; - var docWidth = document.body.clientWidth; - - if (left + width > docWidth) - { left = docWidth - width - 1; } - - // If there's a horizontal scroll bar we could go past zero because it's using the page width, not the window width. - if (left < 0) - { left = 0; }; - } - - MoveToPosition(tooltip, left, top); - tooltip.style.visibility = "visible"; - } - } - -function HideTip(tooltipID) - { - if (tooltipTimer) - { - clearTimeout(tooltipTimer); - tooltipTimer = 0; - } - - var tooltip; - - if (document.getElementById) - { tooltip = document.getElementById(tooltipID); } - else if (document.all) - { tooltip = eval("document.all['" + tooltipID + "']"); } - - if (tooltip) - { tooltip.style.visibility = "hidden"; } - } - - -// -// Blockquote fix for IE -// ____________________________________________________________________________ - - -function NDOnLoad() - { - if (browserVer == "IE6") - { - var scrollboxes = document.getElementsByTagName('blockquote'); - - if (scrollboxes.item(0)) - { - NDDoResize(); - window.onresize=NDOnResize; - }; - }; - }; - - -var resizeTimer = 0; - -function NDOnResize() - { - if (resizeTimer != 0) - { clearTimeout(resizeTimer); }; - - resizeTimer = setTimeout(NDDoResize, 250); - }; - - -function NDDoResize() - { - var scrollboxes = document.getElementsByTagName('blockquote'); - - var i; - var item; - - i = 0; - while (item = scrollboxes.item(i)) - { - item.style.width = 100; - i++; - }; - - i = 0; - while (item = scrollboxes.item(i)) - { - item.style.width = item.parentNode.offsetWidth; - i++; - }; - - clearTimeout(resizeTimer); - resizeTimer = 0; - } - - - -/* ________________________________________________________________________________________________________ - - Class: SearchPanel - ________________________________________________________________________________________________________ - - A class handling everything associated with the search panel. - - Parameters: - - name - The name of the global variable that will be storing this instance. Is needed to be able to set timeouts. - mode - The mode the search is going to work in. Pass CommandLineOption()>, so the - value will be something like "HTML" or "FramedHTML". - - ________________________________________________________________________________________________________ -*/ - - -function SearchPanel(name, mode, resultsPath) - { - if (!name || !mode || !resultsPath) - { alert("Incorrect parameters to SearchPanel."); }; - - - // Group: Variables - // ________________________________________________________________________ - - /* - var: name - The name of the global variable that will be storing this instance of the class. - */ - this.name = name; - - /* - var: mode - The mode the search is going to work in, such as "HTML" or "FramedHTML". - */ - this.mode = mode; - - /* - var: resultsPath - The relative path from the current HTML page to the results page directory. - */ - this.resultsPath = resultsPath; - - /* - var: keyTimeout - The timeout used between a keystroke and when a search is performed. - */ - this.keyTimeout = 0; - - /* - var: keyTimeoutLength - The length of in thousandths of a second. - */ - this.keyTimeoutLength = 500; - - /* - var: lastSearchValue - The last search string executed, or an empty string if none. - */ - this.lastSearchValue = ""; - - /* - var: lastResultsPage - The last results page. The value is only relevant if is set. - */ - this.lastResultsPage = ""; - - /* - var: deactivateTimeout - - The timeout used between when a control is deactivated and when the entire panel is deactivated. Is necessary - because a control may be deactivated in favor of another control in the same panel, in which case it should stay - active. - */ - this.deactivateTimout = 0; - - /* - var: deactivateTimeoutLength - The length of in thousandths of a second. - */ - this.deactivateTimeoutLength = 200; - - - - - // Group: DOM Elements - // ________________________________________________________________________ - - - // Function: DOMSearchField - this.DOMSearchField = function() - { return document.getElementById("MSearchField"); }; - - // Function: DOMSearchType - this.DOMSearchType = function() - { return document.getElementById("MSearchType"); }; - - // Function: DOMPopupSearchResults - this.DOMPopupSearchResults = function() - { return document.getElementById("MSearchResults"); }; - - // Function: DOMPopupSearchResultsWindow - this.DOMPopupSearchResultsWindow = function() - { return document.getElementById("MSearchResultsWindow"); }; - - // Function: DOMSearchPanel - this.DOMSearchPanel = function() - { return document.getElementById("MSearchPanel"); }; - - - - - // Group: Event Handlers - // ________________________________________________________________________ - - - /* - Function: OnSearchFieldFocus - Called when focus is added or removed from the search field. - */ - this.OnSearchFieldFocus = function(isActive) - { - this.Activate(isActive); - }; - - - /* - Function: OnSearchFieldChange - Called when the content of the search field is changed. - */ - this.OnSearchFieldChange = function() - { - if (this.keyTimeout) - { - clearTimeout(this.keyTimeout); - this.keyTimeout = 0; - }; - - var searchValue = this.DOMSearchField().value.replace(/ +/g, ""); - - if (searchValue != this.lastSearchValue) - { - if (searchValue != "") - { - this.keyTimeout = setTimeout(this.name + ".Search()", this.keyTimeoutLength); - } - else - { - if (this.mode == "HTML") - { this.DOMPopupSearchResultsWindow().style.display = "none"; }; - this.lastSearchValue = ""; - }; - }; - }; - - - /* - Function: OnSearchTypeFocus - Called when focus is added or removed from the search type. - */ - this.OnSearchTypeFocus = function(isActive) - { - this.Activate(isActive); - }; - - - /* - Function: OnSearchTypeChange - Called when the search type is changed. - */ - this.OnSearchTypeChange = function() - { - var searchValue = this.DOMSearchField().value.replace(/ +/g, ""); - - if (searchValue != "") - { - this.Search(); - }; - }; - - - - // Group: Action Functions - // ________________________________________________________________________ - - - /* - Function: CloseResultsWindow - Closes the results window. - */ - this.CloseResultsWindow = function() - { - this.DOMPopupSearchResultsWindow().style.display = "none"; - this.Activate(false, true); - }; - - - /* - Function: Search - Performs a search. - */ - this.Search = function() - { - this.keyTimeout = 0; - - var searchValue = this.DOMSearchField().value.replace(/^ +/, ""); - var searchTopic = this.DOMSearchType().value; - - var pageExtension = searchValue.substr(0,1); - - if (pageExtension.match(/^[a-z]/i)) - { pageExtension = pageExtension.toUpperCase(); } - else if (pageExtension.match(/^[0-9]/)) - { pageExtension = 'Numbers'; } - else - { pageExtension = "Symbols"; }; - - var resultsPage; - var resultsPageWithSearch; - var hasResultsPage; - - // indexSectionsWithContent is defined in searchdata.js - if (indexSectionsWithContent[searchTopic][pageExtension] == true) - { - resultsPage = this.resultsPath + '/' + searchTopic + pageExtension + '.html'; - resultsPageWithSearch = resultsPage+'?'+escape(searchValue); - hasResultsPage = true; - } - else - { - resultsPage = this.resultsPath + '/NoResults.html'; - resultsPageWithSearch = resultsPage; - hasResultsPage = false; - }; - - var resultsFrame; - if (this.mode == "HTML") - { resultsFrame = window.frames.MSearchResults; } - else if (this.mode == "FramedHTML") - { resultsFrame = window.top.frames['Content']; }; - - - if (resultsPage != this.lastResultsPage || - - // Bug in IE. If everything becomes hidden in a run, none of them will be able to be reshown in the next for some - // reason. It counts the right number of results, and you can even read the display as "block" after setting it, but it - // just doesn't work in IE 6 or IE 7. So if we're on the right page but the previous search had no results, reload the - // page anyway to get around the bug. - (browserType == "IE" && hasResultsPage && - (!resultsFrame.searchResults || resultsFrame.searchResults.lastMatchCount == 0)) ) - - { - resultsFrame.location.href = resultsPageWithSearch; - } - - // So if the results page is right and there's no IE bug, reperform the search on the existing page. We have to check if there - // are results because NoResults.html doesn't have any JavaScript, and it would be useless to do anything on that page even - // if it did. - else if (hasResultsPage) - { - // We need to check if this exists in case the frame is present but didn't finish loading. - if (resultsFrame.searchResults) - { resultsFrame.searchResults.Search(searchValue); } - - // Otherwise just reload instead of waiting. - else - { resultsFrame.location.href = resultsPageWithSearch; }; - }; - - - var domPopupSearchResultsWindow = this.DOMPopupSearchResultsWindow(); - - if (this.mode == "HTML" && domPopupSearchResultsWindow.style.display != "block") - { - var domSearchType = this.DOMSearchType(); - - var left = GetXPosition(domSearchType); - var top = GetYPosition(domSearchType) + domSearchType.offsetHeight; - - MoveToPosition(domPopupSearchResultsWindow, left, top); - domPopupSearchResultsWindow.style.display = 'block'; - }; - - - this.lastSearchValue = searchValue; - this.lastResultsPage = resultsPage; - }; - - - - // Group: Activation Functions - // Functions that handle whether the entire panel is active or not. - // ________________________________________________________________________ - - - /* - Function: Activate - - Activates or deactivates the search panel, resetting things to their default values if necessary. You can call this on every - control's OnBlur() and it will handle not deactivating the entire panel when focus is just switching between them transparently. - - Parameters: - - isActive - Whether you're activating or deactivating the panel. - ignoreDeactivateDelay - Set if you're positive the action will deactivate the panel and thus want to skip the delay. - */ - this.Activate = function(isActive, ignoreDeactivateDelay) - { - // We want to ignore isActive being false while the results window is open. - if (isActive || (this.mode == "HTML" && this.DOMPopupSearchResultsWindow().style.display == "block")) - { - if (this.inactivateTimeout) - { - clearTimeout(this.inactivateTimeout); - this.inactivateTimeout = 0; - }; - - this.DOMSearchPanel().className = 'MSearchPanelActive'; - - var searchField = this.DOMSearchField(); - - if (searchField.value == 'Search') - { searchField.value = ""; } - } - else if (!ignoreDeactivateDelay) - { - this.inactivateTimeout = setTimeout(this.name + ".InactivateAfterTimeout()", this.inactivateTimeoutLength); - } - else - { - this.InactivateAfterTimeout(); - }; - }; - - - /* - Function: InactivateAfterTimeout - - Called by , which is set by . Inactivation occurs on a timeout because a control may - receive OnBlur() when focus is really transferring to another control in the search panel. In this case we don't want to - actually deactivate the panel because not only would that cause a visible flicker but it could also reset the search value. - So by doing it on a timeout instead, there's a short period where the second control's OnFocus() can cancel the deactivation. - */ - this.InactivateAfterTimeout = function() - { - this.inactivateTimeout = 0; - - this.DOMSearchPanel().className = 'MSearchPanelInactive'; - this.DOMSearchField().value = "Search"; - - this.lastSearchValue = ""; - this.lastResultsPage = ""; - }; - }; - - - - -/* ________________________________________________________________________________________________________ - - Class: SearchResults - _________________________________________________________________________________________________________ - - The class that handles everything on the search results page. - _________________________________________________________________________________________________________ -*/ - - -function SearchResults(name, mode) - { - /* - var: mode - The mode the search is going to work in, such as "HTML" or "FramedHTML". - */ - this.mode = mode; - - /* - var: lastMatchCount - The number of matches from the last run of . - */ - this.lastMatchCount = 0; - - - /* - Function: Toggle - Toggles the visibility of the passed element ID. - */ - this.Toggle = function(id) - { - if (this.mode == "FramedHTML") - { return; }; - - var parentElement = document.getElementById(id); - - var element = parentElement.firstChild; - - while (element && element != parentElement) - { - if (element.nodeName == 'DIV' && element.className == 'ISubIndex') - { - if (element.style.display == 'block') - { element.style.display = "none"; } - else - { element.style.display = 'block'; } - }; - - if (element.nodeName == 'DIV' && element.hasChildNodes()) - { element = element.firstChild; } - else if (element.nextSibling) - { element = element.nextSibling; } - else - { - do - { - element = element.parentNode; - } - while (element && element != parentElement && !element.nextSibling); - - if (element && element != parentElement) - { element = element.nextSibling; }; - }; - }; - }; - - - /* - Function: Search - - Searches for the passed string. If there is no parameter, it takes it from the URL query. - - Always returns true, since other documents may try to call it and that may or may not be possible. - */ - this.Search = function(search) - { - if (!search) - { - search = window.location.search; - search = search.substring(1); // Remove the leading ? - search = unescape(search); - }; - - search = search.replace(/^ +/, ""); - search = search.replace(/ +$/, ""); - search = search.toLowerCase(); - - if (search.match(/[^a-z0-9]/)) // Just a little speedup so it doesn't have to go through the below unnecessarily. - { - search = search.replace(/\_/g, "_und"); - search = search.replace(/\ +/gi, "_spc"); - search = search.replace(/\~/g, "_til"); - search = search.replace(/\!/g, "_exc"); - search = search.replace(/\@/g, "_att"); - search = search.replace(/\#/g, "_num"); - search = search.replace(/\$/g, "_dol"); - search = search.replace(/\%/g, "_pct"); - search = search.replace(/\^/g, "_car"); - search = search.replace(/\&/g, "_amp"); - search = search.replace(/\*/g, "_ast"); - search = search.replace(/\(/g, "_lpa"); - search = search.replace(/\)/g, "_rpa"); - search = search.replace(/\-/g, "_min"); - search = search.replace(/\+/g, "_plu"); - search = search.replace(/\=/g, "_equ"); - search = search.replace(/\{/g, "_lbc"); - search = search.replace(/\}/g, "_rbc"); - search = search.replace(/\[/g, "_lbk"); - search = search.replace(/\]/g, "_rbk"); - search = search.replace(/\:/g, "_col"); - search = search.replace(/\;/g, "_sco"); - search = search.replace(/\"/g, "_quo"); - search = search.replace(/\'/g, "_apo"); - search = search.replace(/\/g, "_ran"); - search = search.replace(/\,/g, "_com"); - search = search.replace(/\./g, "_per"); - search = search.replace(/\?/g, "_que"); - search = search.replace(/\//g, "_sla"); - search = search.replace(/[^a-z0-9\_]i/gi, "_zzz"); - }; - - var resultRows = document.getElementsByTagName("div"); - var matches = 0; - - var i = 0; - while (i < resultRows.length) - { - var row = resultRows.item(i); - - if (row.className == "SRResult") - { - var rowMatchName = row.id.toLowerCase(); - rowMatchName = rowMatchName.replace(/^sr\d*_/, ''); - - if (search.length <= rowMatchName.length && rowMatchName.substr(0, search.length) == search) - { - row.style.display = "block"; - matches++; - } - else - { row.style.display = "none"; }; - }; - - i++; - }; - - document.getElementById("Searching").style.display="none"; - - if (matches == 0) - { document.getElementById("NoMatches").style.display="block"; } - else - { document.getElementById("NoMatches").style.display="none"; } - - this.lastMatchCount = matches; - - return true; - }; - }; - diff --git a/benchmarks/riscv-coremark/coremark/docs/html/javascript/searchdata.js b/benchmarks/riscv-coremark/coremark/docs/html/javascript/searchdata.js deleted file mode 100644 index 901318e77..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/javascript/searchdata.js +++ /dev/null @@ -1,212 +0,0 @@ -var indexSectionsWithContent = { - "General": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": true, - "D": true, - "E": false, - "F": true, - "G": true, - "H": false, - "I": true, - "J": false, - "K": false, - "L": false, - "M": true, - "N": false, - "O": false, - "P": false, - "Q": false, - "R": false, - "S": true, - "T": true, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "Variables": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": true, - "D": true, - "E": false, - "F": false, - "G": false, - "H": false, - "I": false, - "J": false, - "K": false, - "L": true, - "M": false, - "N": false, - "O": true, - "P": true, - "Q": false, - "R": true, - "S": true, - "T": false, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "Functions": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": true, - "D": false, - "E": false, - "F": false, - "G": true, - "H": false, - "I": true, - "J": false, - "K": false, - "L": false, - "M": true, - "N": false, - "O": false, - "P": true, - "Q": false, - "R": false, - "S": true, - "T": true, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "Files": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": true, - "D": false, - "E": false, - "F": false, - "G": false, - "H": false, - "I": false, - "J": false, - "K": false, - "L": false, - "M": false, - "N": false, - "O": false, - "P": false, - "Q": false, - "R": true, - "S": false, - "T": false, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "Configuration": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": true, - "D": false, - "E": false, - "F": false, - "G": false, - "H": true, - "I": false, - "J": false, - "K": false, - "L": false, - "M": true, - "N": false, - "O": false, - "P": false, - "Q": false, - "R": false, - "S": true, - "T": true, - "U": true, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "Types": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": false, - "D": false, - "E": false, - "F": false, - "G": false, - "H": false, - "I": false, - "J": false, - "K": false, - "L": false, - "M": false, - "N": false, - "O": false, - "P": false, - "Q": false, - "R": false, - "S": true, - "T": false, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - }, - "BuildTargets": { - "Symbols": false, - "Numbers": false, - "A": false, - "B": false, - "C": false, - "D": false, - "E": false, - "F": false, - "G": false, - "H": false, - "I": false, - "J": false, - "K": false, - "L": false, - "M": false, - "N": false, - "O": false, - "P": true, - "Q": false, - "R": false, - "S": false, - "T": false, - "U": false, - "V": false, - "W": false, - "X": false, - "Y": false, - "Z": false - } - } \ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/search/BuildTargetsP.html b/benchmarks/riscv-coremark/coremark/docs/html/search/BuildTargetsP.html deleted file mode 100644 index 65e741d65..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/search/BuildTargetsP.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -
Loading...
Searching...
No Matches
\ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationC.html b/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationC.html deleted file mode 100644 index 84b49ca3a..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationC.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -
Loading...
Searching...
No Matches
\ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationH.html b/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationH.html deleted file mode 100644 index 3b0c39213..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationH.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -
Loading...
Searching...
No Matches
\ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationM.html b/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationM.html deleted file mode 100644 index 022606fa2..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationM.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -
Loading...
Searching...
No Matches
\ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationS.html b/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationS.html deleted file mode 100644 index d26de19b9..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/search/ConfigurationS.html +++ /dev/null @@ -1,18 +0,0 @@ - - - - - - - - - - -
Loading...
Searching...
No Matches
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\ No newline at end of file diff --git a/benchmarks/riscv-coremark/coremark/docs/html/styles/1.css b/benchmarks/riscv-coremark/coremark/docs/html/styles/1.css deleted file mode 100644 index d5a8bd6a2..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/styles/1.css +++ /dev/null @@ -1,767 +0,0 @@ -/* - IMPORTANT: If you're editing this file in the output directory of one of - your projects, your changes will be overwritten the next time you run - Natural Docs. Instead, copy this file to your project directory, make your - changes, and you can use it with -s. Even better would be to make a CSS - file in your project directory with only your changes, which you can then - use with -s [original style] [your changes]. - - On the other hand, if you're editing this file in the Natural Docs styles - directory, the changes will automatically be applied to all your projects - that use this style the next time Natural Docs is run on them. - - This file is part of Natural Docs, which is Copyright (C) 2003-2008 Greg Valure - Natural Docs is licensed under the GPL -*/ - -body { - font: 10pt Verdana, Arial, sans-serif; - color: #000000; - margin: 0; padding: 0; - } - -.ContentPage, -.IndexPage, -.FramedMenuPage { - background-color: #E8E8E8; - } -.FramedContentPage, -.FramedIndexPage, -.FramedSearchResultsPage, -.PopupSearchResultsPage { - background-color: #FFFFFF; - } - - -a:link, -a:visited { color: #900000; text-decoration: none } -a:hover { color: #900000; text-decoration: underline } -a:active { color: #FF0000; text-decoration: underline } - -td { - vertical-align: top } - -img { border: 0; } - - -/* - Comment out this line to use web-style paragraphs (blank line between - paragraphs, no indent) instead of print-style paragraphs (no blank line, - indented.) -*/ -p { - text-indent: 5ex; margin: 0 } - - -/* Can't use something like display: none or it won't break. */ -.HB { - font-size: 1px; - visibility: hidden; - } - -/* Blockquotes are used as containers for things that may need to scroll. */ -blockquote { - padding: 0; - margin: 0; - overflow: auto; - } - - -.Firefox1 blockquote { - padding-bottom: .5em; - } - -/* Turn off scrolling when printing. */ -@media print { - blockquote { - overflow: visible; - } - .IE blockquote { - width: auto; - } - } - - - -#Menu { - font-size: 9pt; - padding: 10px 0 0 0; - } -.ContentPage #Menu, -.IndexPage #Menu { - position: absolute; - top: 0; - left: 0; - width: 31ex; - overflow: hidden; - } -.ContentPage .Firefox #Menu, -.IndexPage .Firefox #Menu { - width: 27ex; - } - - - .MTitle { - font-size: 16pt; font-weight: bold; font-variant: small-caps; - text-align: center; - padding: 5px 10px 15px 10px; - border-bottom: 1px dotted #000000; - margin-bottom: 15px } - - .MSubTitle { - font-size: 9pt; font-weight: normal; font-variant: normal; - margin-top: 1ex; margin-bottom: 5px } - - - .MEntry a:link, - .MEntry a:hover, - .MEntry a:visited { color: #606060; margin-right: 0 } - .MEntry a:active { color: #A00000; margin-right: 0 } - - - .MGroup { - font-variant: small-caps; font-weight: bold; - margin: 1em 0 1em 10px; - } - - .MGroupContent { - font-variant: normal; font-weight: normal } - - .MGroup a:link, - .MGroup a:hover, - .MGroup a:visited { color: #545454; margin-right: 10px } - .MGroup a:active { color: #A00000; margin-right: 10px } - - - .MFile, - .MText, - .MLink, - .MIndex { - padding: 1px 17px 2px 10px; - margin: .25em 0 .25em 0; - } - - .MText { - font-size: 8pt; font-style: italic } - - .MLink { - font-style: italic } - - #MSelected { - color: #000000; background-color: #FFFFFF; - /* Replace padding with border. */ - padding: 0 10px 0 10px; - border-width: 1px 2px 2px 0; border-style: solid; border-color: #000000; - margin-right: 5px; - } - - /* Close off the left side when its in a group. */ - .MGroup #MSelected { - padding-left: 9px; border-left-width: 1px } - - /* A treat for Mozilla users. Blatantly non-standard. Will be replaced with CSS 3 attributes when finalized/supported. */ - .Firefox #MSelected { - -moz-border-radius-topright: 10px; - -moz-border-radius-bottomright: 10px } - .Firefox .MGroup #MSelected { - -moz-border-radius-topleft: 10px; - -moz-border-radius-bottomleft: 10px } - - - #MSearchPanel { - padding: 0px 6px; - margin: .25em 0; - } - - - #MSearchField { - font: italic 9pt Verdana, sans-serif; - color: #606060; - background-color: #E8E8E8; - border: none; - padding: 2px 4px; - width: 100%; - } - /* Only Opera gets it right. */ - .Firefox #MSearchField, - .IE #MSearchField, - .Safari #MSearchField { - width: 94%; - } - .Opera9 #MSearchField, - .Konqueror #MSearchField { - width: 97%; - } - .FramedMenuPage .Firefox #MSearchField, - .FramedMenuPage .Safari #MSearchField, - .FramedMenuPage .Konqueror #MSearchField { - width: 98%; - } - - /* Firefox doesn't do this right in frames without #MSearchPanel added on. - It's presence doesn't hurt anything other browsers. */ - #MSearchPanel.MSearchPanelInactive:hover #MSearchField { - background-color: #FFFFFF; - border: 1px solid #C0C0C0; - padding: 1px 3px; - } - .MSearchPanelActive #MSearchField { - background-color: #FFFFFF; - border: 1px solid #C0C0C0; - font-style: normal; - padding: 1px 3px; - } - - #MSearchType { - visibility: hidden; - font: 8pt Verdana, sans-serif; - width: 98%; - padding: 0; - border: 1px solid #C0C0C0; - } - .MSearchPanelActive #MSearchType, - /* As mentioned above, Firefox doesn't do this right in frames without #MSearchPanel added on. */ - #MSearchPanel.MSearchPanelInactive:hover #MSearchType, - #MSearchType:focus { - visibility: visible; - color: #606060; - } - #MSearchType option#MSearchEverything { - font-weight: bold; - } - - .Opera8 .MSearchPanelInactive:hover, - .Opera8 .MSearchPanelActive { - margin-left: -1px; - } - - - iframe#MSearchResults { - width: 60ex; - height: 15em; - } - #MSearchResultsWindow { - display: none; - position: absolute; - left: 0; top: 0; - border: 1px solid #000000; - background-color: #E8E8E8; - } - #MSearchResultsWindowClose { - font-weight: bold; - font-size: 8pt; - display: block; - padding: 2px 5px; - } - #MSearchResultsWindowClose:link, - #MSearchResultsWindowClose:visited { - color: #000000; - text-decoration: none; - } - #MSearchResultsWindowClose:active, - #MSearchResultsWindowClose:hover { - color: #800000; - text-decoration: none; - background-color: #F4F4F4; - } - - - - -#Content { - padding-bottom: 15px; - } - -.ContentPage #Content { - border-width: 0 0 1px 1px; - border-style: solid; - border-color: #000000; - background-color: #FFFFFF; - font-size: 9pt; /* To make 31ex match the menu's 31ex. */ - margin-left: 31ex; - } -.ContentPage .Firefox #Content { - margin-left: 27ex; - } - - - - .CTopic { - font-size: 10pt; - margin-bottom: 3em; - } - - - .CTitle { - font-size: 12pt; font-weight: bold; - border-width: 0 0 1px 0; border-style: solid; border-color: #A0A0A0; - margin: 0 15px .5em 15px } - - .CGroup .CTitle { - font-size: 16pt; font-variant: small-caps; - padding-left: 15px; padding-right: 15px; - border-width: 0 0 2px 0; border-color: #000000; - margin-left: 0; margin-right: 0 } - - .CClass .CTitle, - .CInterface .CTitle, - .CDatabase .CTitle, - .CDatabaseTable .CTitle, - .CSection .CTitle { - font-size: 18pt; - color: #FFFFFF; background-color: #A0A0A0; - padding: 10px 15px 10px 15px; - border-width: 2px 0; border-color: #000000; - margin-left: 0; margin-right: 0 } - - #MainTopic .CTitle { - font-size: 20pt; - color: #FFFFFF; background-color: #7070C0; - padding: 10px 15px 10px 15px; - border-width: 0 0 3px 0; border-color: #000000; - margin-left: 0; margin-right: 0 } - - .CBody { - margin-left: 15px; margin-right: 15px } - - - .CToolTip { - position: absolute; visibility: hidden; - left: 0; top: 0; - background-color: #FFFFE0; - padding: 5px; - border-width: 1px 2px 2px 1px; border-style: solid; border-color: #000000; - font-size: 8pt; - } - - .Opera .CToolTip { - max-width: 98%; - } - - /* Scrollbars would be useless. */ - .CToolTip blockquote { - overflow: hidden; - } - .IE6 .CToolTip blockquote { - overflow: visible; - } - - .CHeading { - font-weight: bold; font-size: 10pt; - margin: 1.5em 0 .5em 0; - } - - .CBody pre { - font: 10pt "Courier New", Courier, monospace; - margin: 1em 0; - } - - .CBody ul { - /* I don't know why CBody's margin doesn't apply, but it's consistent across browsers so whatever. - Reapply it here as padding. */ - padding-left: 15px; padding-right: 15px; - margin: .5em 5ex .5em 5ex; - } - - .CDescriptionList { - margin: .5em 5ex 0 5ex } - - .CDLEntry { - font: 10pt "Courier New", Courier, monospace; color: #808080; - padding-bottom: .25em; - white-space: nowrap } - - .CDLDescription { - font-size: 10pt; /* For browsers that don't inherit correctly, like Opera 5. */ - padding-bottom: .5em; padding-left: 5ex } - - - .CTopic img { - text-align: center; - display: block; - margin: 1em auto; - } - .CImageCaption { - font-variant: small-caps; - font-size: 8pt; - color: #808080; - text-align: center; - position: relative; - top: 1em; - } - - .CImageLink { - color: #808080; - font-style: italic; - } - a.CImageLink:link, - a.CImageLink:visited, - a.CImageLink:hover { color: #808080 } - - - - - -.Prototype { - font: 10pt "Courier New", Courier, monospace; - padding: 5px 3ex; - border-width: 1px; border-style: solid; - margin: 0 5ex 1.5em 5ex; - } - - .Prototype td { - font-size: 10pt; - } - - .PDefaultValue, - .PDefaultValuePrefix, - .PTypePrefix { - color: #8F8F8F; - } - .PTypePrefix { - text-align: right; - } - .PAfterParameters { - vertical-align: bottom; - } - - .IE .Prototype table { - padding: 0; - } - - .CFunction .Prototype { - background-color: #F4F4F4; border-color: #D0D0D0 } - .CProperty .Prototype { - background-color: #F4F4FF; border-color: #C0C0E8 } - .CVariable .Prototype { - background-color: #FFFFF0; border-color: #E0E0A0 } - - .CClass .Prototype { - border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0A0; - background-color: #F4F4F4; - } - .CInterface .Prototype { - border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0D0; - background-color: #F4F4FF; - } - - .CDatabaseIndex .Prototype, - .CConstant .Prototype { - background-color: #D0D0D0; border-color: #000000 } - .CType .Prototype, - .CEnumeration .Prototype { - background-color: #FAF0F0; border-color: #E0B0B0; - } - .CDatabaseTrigger .Prototype, - .CEvent .Prototype, - .CDelegate .Prototype { - background-color: #F0FCF0; border-color: #B8E4B8 } - - .CToolTip .Prototype { - margin: 0 0 .5em 0; - white-space: nowrap; - } - - - - - -.Summary { - margin: 1.5em 5ex 0 5ex } - - .STitle { - font-size: 12pt; font-weight: bold; - margin-bottom: .5em } - - - .SBorder { - background-color: #FFFFF0; - padding: 15px; - border: 1px solid #C0C060 } - - /* In a frame IE 6 will make them too long unless you set the width to 100%. Without frames it will be correct without a width - or slightly too long (but not enough to scroll) with a width. This arbitrary weirdness simply astounds me. IE 7 has the same - problem with frames, haven't tested it without. */ - .FramedContentPage .IE .SBorder { - width: 100% } - - /* A treat for Mozilla users. Blatantly non-standard. Will be replaced with CSS 3 attributes when finalized/supported. */ - .Firefox .SBorder { - -moz-border-radius: 20px } - - - .STable { - font-size: 9pt; width: 100% } - - .SEntry { - width: 30% } - .SDescription { - width: 70% } - - - .SMarked { - background-color: #F8F8D8 } - - .SDescription { padding-left: 2ex } - .SIndent1 .SEntry { padding-left: 1.5ex } .SIndent1 .SDescription { padding-left: 3.5ex } - .SIndent2 .SEntry { padding-left: 3.0ex } .SIndent2 .SDescription { padding-left: 5.0ex } - .SIndent3 .SEntry { padding-left: 4.5ex } .SIndent3 .SDescription { padding-left: 6.5ex } - .SIndent4 .SEntry { padding-left: 6.0ex } .SIndent4 .SDescription { padding-left: 8.0ex } - .SIndent5 .SEntry { padding-left: 7.5ex } .SIndent5 .SDescription { padding-left: 9.5ex } - - .SDescription a { color: #800000} - .SDescription a:active { color: #A00000 } - - .SGroup td { - padding-top: .5em; padding-bottom: .25em } - - .SGroup .SEntry { - font-weight: bold; font-variant: small-caps } - - .SGroup .SEntry a { color: #800000 } - .SGroup .SEntry a:active { color: #F00000 } - - - .SMain td, - .SClass td, - .SDatabase td, - .SDatabaseTable td, - .SSection td { - font-size: 10pt; - padding-bottom: .25em } - - .SClass td, - .SDatabase td, - .SDatabaseTable td, - .SSection td { - padding-top: 1em } - - .SMain .SEntry, - .SClass .SEntry, - .SDatabase .SEntry, - .SDatabaseTable .SEntry, - .SSection .SEntry { - font-weight: bold; - } - - .SMain .SEntry a, - .SClass .SEntry a, - .SDatabase .SEntry a, - .SDatabaseTable .SEntry a, - .SSection .SEntry a { color: #000000 } - - .SMain .SEntry a:active, - .SClass .SEntry a:active, - .SDatabase .SEntry a:active, - .SDatabaseTable .SEntry a:active, - .SSection .SEntry a:active { color: #A00000 } - - - - - -.ClassHierarchy { - margin: 0 15px 1em 15px } - - .CHEntry { - border-width: 1px 2px 2px 1px; border-style: solid; border-color: #A0A0A0; - margin-bottom: 3px; - padding: 2px 2ex; - font-size: 10pt; - background-color: #F4F4F4; color: #606060; - } - - .Firefox .CHEntry { - -moz-border-radius: 4px; - } - - .CHCurrent .CHEntry { - font-weight: bold; - border-color: #000000; - color: #000000; - } - - .CHChildNote .CHEntry { - font-style: italic; - font-size: 8pt; - } - - .CHIndent { - margin-left: 3ex; - } - - .CHEntry a:link, - .CHEntry a:visited, - .CHEntry a:hover { - color: #606060; - } - .CHEntry a:active { - color: #800000; - } - - - - - -#Index { - background-color: #FFFFFF; - } - -/* As opposed to .PopupSearchResultsPage #Index */ -.IndexPage #Index, -.FramedIndexPage #Index, -.FramedSearchResultsPage #Index { - padding: 15px; - } - -.IndexPage #Index { - border-width: 0 0 1px 1px; - border-style: solid; - border-color: #000000; - font-size: 9pt; /* To make 27ex match the menu's 27ex. */ - margin-left: 27ex; - } - - - .IPageTitle { - font-size: 20pt; font-weight: bold; - color: #FFFFFF; background-color: #7070C0; - padding: 10px 15px 10px 15px; - border-width: 0 0 3px 0; border-color: #000000; border-style: solid; - margin: -15px -15px 0 -15px } - - .FramedSearchResultsPage .IPageTitle { - margin-bottom: 15px; - } - - .INavigationBar { - font-size: 10pt; - text-align: center; - background-color: #FFFFF0; - padding: 5px; - border-bottom: solid 1px black; - margin: 0 -15px 15px -15px; - } - - .INavigationBar a { - font-weight: bold } - - .IHeading { - font-size: 16pt; font-weight: bold; - padding: 2.5em 0 .5em 0; - text-align: center; - width: 3.5ex; - } - #IFirstHeading { - padding-top: 0; - } - - .IEntry { - font-size: 10pt; - padding-left: 1ex; - } - .PopupSearchResultsPage .IEntry { - font-size: 8pt; - padding: 1px 5px; - } - .PopupSearchResultsPage .Opera9 .IEntry, - .FramedSearchResultsPage .Opera9 .IEntry { - text-align: left; - } - .FramedSearchResultsPage .IEntry { - padding: 0; - } - - .ISubIndex { - padding-left: 3ex; padding-bottom: .5em } - .PopupSearchResultsPage .ISubIndex { - display: none; - } - - /* While it may cause some entries to look like links when they aren't, I found it's much easier to read the - index if everything's the same color. */ - .ISymbol { - font-weight: bold; color: #900000 } - - .IndexPage .ISymbolPrefix, - .FramedIndexPage .ISymbolPrefix { - font-size: 10pt; - text-align: right; - color: #C47C7C; - background-color: #F8F8F8; - border-right: 3px solid #E0E0E0; - border-left: 1px solid #E0E0E0; - padding: 0 1px 0 2px; - } - .PopupSearchResultsPage .ISymbolPrefix, - .FramedSearchResultsPage .ISymbolPrefix { - color: #900000; - } - .PopupSearchResultsPage .ISymbolPrefix { - font-size: 8pt; - } - - .IndexPage #IFirstSymbolPrefix, - .FramedIndexPage #IFirstSymbolPrefix { - border-top: 1px solid #E0E0E0; - } - .IndexPage #ILastSymbolPrefix, - .FramedIndexPage #ILastSymbolPrefix { - border-bottom: 1px solid #E0E0E0; - } - .IndexPage #IOnlySymbolPrefix, - .FramedIndexPage #IOnlySymbolPrefix { - border-top: 1px solid #E0E0E0; - border-bottom: 1px solid #E0E0E0; - } - - a.IParent, - a.IFile { - display: block; - } - - .PopupSearchResultsPage .SRStatus { - padding: 2px 5px; - font-size: 8pt; - font-style: italic; - } - .FramedSearchResultsPage .SRStatus { - font-size: 10pt; - font-style: italic; - } - - .SRResult { - display: none; - } - - - -#Footer { - font-size: 8pt; - color: #989898; - text-align: right; - } - -#Footer p { - text-indent: 0; - margin-bottom: .5em; - } - -.ContentPage #Footer, -.IndexPage #Footer { - text-align: right; - margin: 2px; - } - -.FramedMenuPage #Footer { - text-align: center; - margin: 5em 10px 10px 10px; - padding-top: 1em; - border-top: 1px solid #C8C8C8; - } - - #Footer a:link, - #Footer a:hover, - #Footer a:visited { color: #989898 } - #Footer a:active { color: #A00000 } - diff --git a/benchmarks/riscv-coremark/coremark/docs/html/styles/2.css b/benchmarks/riscv-coremark/coremark/docs/html/styles/2.css deleted file mode 100644 index 69a1d1a7a..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/styles/2.css +++ /dev/null @@ -1,6 +0,0 @@ -#Menu { - padding: 48px 0 0 0; - background: url(file:../../coremark_logo.jpg) no-repeat; - background-position: 30px 10px; - } - diff --git a/benchmarks/riscv-coremark/coremark/docs/html/styles/main.css b/benchmarks/riscv-coremark/coremark/docs/html/styles/main.css deleted file mode 100644 index a672a9492..000000000 --- a/benchmarks/riscv-coremark/coremark/docs/html/styles/main.css +++ /dev/null @@ -1,2 +0,0 @@ -@import URL("1.css"); -@import URL("2.css"); diff --git a/benchmarks/riscv-coremark/coremark/freebsd/core_portme.mak b/benchmarks/riscv-coremark/coremark/freebsd/core_portme.mak deleted file mode 100644 index 97b6d6ace..000000000 --- a/benchmarks/riscv-coremark/coremark/freebsd/core_portme.mak +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/coremark/linux/core_portme.c b/benchmarks/riscv-coremark/coremark/linux/core_portme.c deleted file mode 100755 index 6b63610d1..000000000 --- a/benchmarks/riscv-coremark/coremark/linux/core_portme.c +++ /dev/null @@ -1,338 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - { - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/coremark/linux/core_portme.h b/benchmarks/riscv-coremark/coremark/linux/core_portme.h deleted file mode 100755 index 2cf4659a4..000000000 --- a/benchmarks/riscv-coremark/coremark/linux/core_portme.h +++ /dev/null @@ -1,290 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem: - This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/linux/core_portme.mak b/benchmarks/riscv-coremark/coremark/linux/core_portme.mak deleted file mode 100644 index 97b6d6ace..000000000 --- a/benchmarks/riscv-coremark/coremark/linux/core_portme.mak +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/coremark/linux64/core_portme.c b/benchmarks/riscv-coremark/coremark/linux64/core_portme.c deleted file mode 100755 index fe8d29983..000000000 --- a/benchmarks/riscv-coremark/coremark/linux64/core_portme.c +++ /dev/null @@ -1,336 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/coremark/linux64/core_portme.h b/benchmarks/riscv-coremark/coremark/linux64/core_portme.h deleted file mode 100755 index 1228a679b..000000000 --- a/benchmarks/riscv-coremark/coremark/linux64/core_portme.h +++ /dev/null @@ -1,291 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef unsigned long long ee_ptr_int; -typedef size_t ee_size_t; -/* align an offset to point to a 32b value */ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/linux64/core_portme.mak b/benchmarks/riscv-coremark/coremark/linux64/core_portme.mak deleted file mode 100755 index 5cfabee32..000000000 --- a/benchmarks/riscv-coremark/coremark/linux64/core_portme.mak +++ /dev/null @@ -1,140 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File: core_portme.mak - -# Flag: OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag: CC -# Use this flag to define compiler to use -CC = gcc -# Flag: CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -PORT_CFLAGS = -O2 -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -#Flag: LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END += -lrt -# Flag: PORT_SRCS -# Port specific source files can be added here -PORT_SRCS = $(PORT_DIR)/core_portme.c -# Flag: LOAD -# Define this flag if you need to load to a target, as in a cross compile environment. - -# Flag: RUN -# Define this flag if running does not consist of simple invocation of the binary. -# In a cross compile environment, you need to define this. - -#For flashing and using a tera term macro, you could use -#LOAD = flash ADDR -#RUN = ttpmacro coremark.ttl - -#For copying to target and executing via SSH connection, you could use -#LOAD = scp $(OUTFILE) user@target:~ -#RUN = ssh user@target -c - -#For native compilation and execution -LOAD = echo Loading done -RUN = - -OEXT = .o -EXE = .exe - -# Flag: SEPARATE_COMPILE -# Define if you need to separate compilation from link stage. -# In this case, you also need to define below how to create an object file, and how to link. -ifdef SEPARATE_COMPILE - -LD = gcc -OBJOUT = -o -LFLAGS = -OFLAG = -o -COUT = -c -# Flag: PORT_OBJS -# Port specific object files can be added here -PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT) -PORT_CLEAN = *$(OEXT) - -$(OPATH)%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -endif - -# Target: port_prebuild -# Generate any files that are needed before actual build starts. -# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1 -# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line. -# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it. -# Note - Using REBUILD=1 -# -# Use make PGO=1 to invoke this sample processing. - -ifdef PGO - ifeq (,$(findstring $(PGO),gen)) - PGO_STAGE=build_pgo_gcc - CFLAGS+=-fprofile-use - endif - PORT_CLEAN+=*.gcda *.gcno gmon.out -endif - -.PHONY: port_prebuild -port_prebuild: $(PGO_STAGE) - -.PHONY: build_pgo_gcc -build_pgo_gcc: - $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1 - -# Target: port_postbuild -# Generate any files that are needed after actual build end. -# E.g. change format to srec, bin, zip in order to be able to load into flash -.PHONY: port_postbuild -port_postbuild: - -# Target: port_postrun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_postrun -port_postrun: - -# Target: port_prerun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_prerun -port_prerun: - -# Target: port_postload -# Do platform specific after load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_postload -port_postload: - -# Target: port_preload -# Do platform specific before load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_preload -port_preload: - -# FLAG: OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - -# FLAG: PERL -# Define perl executable to calculate the geomean if running separate. -PERL=/usr/bin/perl diff --git a/benchmarks/riscv-coremark/coremark/macos/core_portme.mak b/benchmarks/riscv-coremark/coremark/macos/core_portme.mak deleted file mode 100644 index 6b27c3c41..000000000 --- a/benchmarks/riscv-coremark/coremark/macos/core_portme.mak +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -NO_LIBRT = 1 -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/coremark/posix/core_portme.c b/benchmarks/riscv-coremark/coremark/posix/core_portme.c deleted file mode 100644 index f5a7f5b3d..000000000 --- a/benchmarks/riscv-coremark/coremark/posix/core_portme.c +++ /dev/null @@ -1,419 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD == MEM_MALLOC) -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void * -portable_malloc(size_t size) -{ - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void -portable_free(void *p) -{ - free(p); -} -#else -void * -portable_malloc(size_t size) -{ - return NULL; -} -void -portable_free(void *p) -{ - p = NULL; -} -#endif - -#if (SEED_METHOD == SEED_VOLATILE) -#if VALIDATION_RUN -volatile ee_s32 seed1_volatile = 0x3415; -volatile ee_s32 seed2_volatile = 0x3415; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PERFORMANCE_RUN -volatile ee_s32 seed1_volatile = 0x0; -volatile ee_s32 seed2_volatile = 0x0; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PROFILE_RUN -volatile ee_s32 seed1_volatile = 0x8; -volatile ee_s32 seed2_volatile = 0x8; -volatile ee_s32 seed3_volatile = 0x8; -#endif -volatile ee_s32 seed4_volatile = ITERATIONS; -volatile ee_s32 seed5_volatile = 0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is - supported by the platform. e.g. Read value from on board RTC, read value from - cpu clock cycles performance counter etc. Sample implementation for standard - time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be - measured. - - Use lower values to increase resolution, but make sure that overflow - does not occur. If there are issues with the return value overflowing, - increase this value. - */ -#if USE_CLOCK -#define NSECS_PER_SEC CLOCKS_PER_SEC -#define EE_TIMER_TICKER_RATE 1000 -#define CORETIMETYPE clock_t -#define GETMYTIME(_t) (*_t = clock()) -#define MYTIMEDIFF(fin, ini) ((fin) - (ini)) -#define TIMER_RES_DIVIDER 1 -#define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) -#define NSECS_PER_SEC 10000000 -#define EE_TIMER_TICKER_RATE 1000 -#define CORETIMETYPE FILETIME -#define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) -#define MYTIMEDIFF(fin, ini) \ - (((*(__int64 *)&fin) - (*(__int64 *)&ini)) / TIMER_RES_DIVIDER) -/* setting to millisces resolution by default with MSDEV */ -#ifndef TIMER_RES_DIVIDER -#define TIMER_RES_DIVIDER 1000 -#endif -#define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H -#define NSECS_PER_SEC 1000000000 -#define EE_TIMER_TICKER_RATE 1000 -#define CORETIMETYPE struct timespec -#define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME, _t) -#define MYTIMEDIFF(fin, ini) \ - ((fin.tv_sec - ini.tv_sec) * (NSECS_PER_SEC / TIMER_RES_DIVIDER) \ - + (fin.tv_nsec - ini.tv_nsec) / TIMER_RES_DIVIDER) -/* setting to 1/1000 of a second resolution by default with linux */ -#ifndef TIMER_RES_DIVIDER -#define TIMER_RES_DIVIDER 1000000 -#endif -#define SAMPLE_TIME_IMPLEMENTATION 1 -#else -#define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of - the benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or zeroing some system parameters - e.g. setting the cpu clocks - cycles to 0. -*/ -void -start_time(void) -{ - GETMYTIME(&start_time_val); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3"); /*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the - benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or other system parameters - e.g. reading the current value of - cpu cycles counter. -*/ -void -stop_time(void) -{ -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3"); /*1 */ -#endif - GETMYTIME(&stop_time_val); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other - value, as long as it can be converted to seconds by . This - methodology is taken to accomodate any hardware or simulated platform. The - sample implementation returns millisecs by default, and the resolution is - controlled by -*/ -CORE_TICKS -get_time(void) -{ - CORE_TICKS elapsed - = (CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for - floating point. Default implementation implemented by the EE_TICKS_PER_SEC - macro above. -*/ -secs_ret -time_in_secs(CORE_TICKS ticks) -{ - secs_ret retval = ((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts = MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void -portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i = 0; i < *argc; i++) - { - ee_printf("Arg[%d]=%s\n", i, argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) - { - ee_printf( - "ERROR! Please define ee_ptr_int to a type that holds a " - "pointer!\n"); - } - if (sizeof(ee_u32) != 4) - { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD == SEED_ARG)) - ee_printf( - "ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD > 1) && (SEED_METHOD == SEED_ARG) - int nargs = *argc, i; - if ((nargs > 1) && (*argv[1] == 'M')) - { - default_num_contexts = parseval(argv[1] + 1); - if (default_num_contexts > MULTITHREAD) - default_num_contexts = MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not - * to coremark main */ - --nargs; - for (i = 1; i < nargs; i++) - argv[i] = argv[i + 1]; - *argc = nargs; - } -#endif /* sample of potential platform specific init via command line, reset \ - the number of contexts being used if first argument is M*/ - p->portable_id = 1; -} -/* Function: portable_fini - Target specific final code -*/ -void -portable_fini(core_portable *p) -{ - p->portable_id = 0; -} - -#if (MULTITHREAD > 1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork - and shared mem, and one using fork and sockets. Other implementations using - MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork - and shared mem, and one using fork and sockets. Other implementations using - MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 -core_start_parallel(core_results *res) -{ - return (ee_u8)pthread_create( - &(res->port.thread), NULL, iterate, (void *)res); -} -ee_u8 -core_stop_parallel(core_results *res) -{ - void *retval; - return (ee_u8)pthread_join(res->port.thread, &retval); -} -#elif USE_FORK -static int key_id = 0; -ee_u8 -core_start_parallel(core_results *res) -{ - key_t key = 4321 + key_id; - key_id++; - res->port.pid = fork(); - res->port.shmid = shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid < 0) - { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid == 0) - { - iterate(res); - res->port.shm = shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *)-1) - { - ee_printf("ERROR in child shmat!\n"); - } - else - { - memcpy(res->port.shm, &(res->crc), 8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 -core_stop_parallel(core_results *res) -{ - int status; - pid_t wpid = waitpid(res->port.pid, &status, WUNTRACED); - if (wpid != res->port.pid) - { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) - ee_printf("errno=No such child %d\n", res->port.pid); - if (errno == EINTR) - ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm = shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *)-1) - { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc), res->port.shm, 8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id = 0; -ee_u8 -core_start_parallel(core_results *res) -{ - int bound, buffer_length = 8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654 + key_id); - key_id++; - res->port.pid = fork(); - if (res->port.pid == 0) - { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ - { - ee_printf("Error Creating Socket"); - } - else - { - int bytes_sent = sendto(res->port.sock, - &(res->crc), - buffer_length, - 0, - (struct sockaddr *)&(res->port.sa), - sizeof(struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock, - (struct sockaddr *)&(res->port.sa), - sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n", strerror(errno)); - return 1; -} -ee_u8 -core_stop_parallel(core_results *res) -{ - int status; - int fromlen = sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, - &(res->crc), - 8, - 0, - (struct sockaddr *)&(res->port.sa), - &fromlen); - if (recsize < 0) - { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid, &status, WUNTRACED); - if (wpid != res->port.pid) - { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) - ee_printf("errno=No such child %d\n", res->port.pid); - if (errno == EINTR) - ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error \ - "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/coremark/posix/core_portme.h b/benchmarks/riscv-coremark/coremark/posix/core_portme.h deleted file mode 100644 index e49e474b1..000000000 --- a/benchmarks/riscv-coremark/coremark/posix/core_portme.h +++ /dev/null @@ -1,314 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on - different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H - -#include "core_portme_posix_overrides.h" - -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf - function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error \ - "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION -#ifdef __GNUC__ -#define COMPILER_VERSION "GCC"__VERSION__ -#else -#define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" -#endif -#endif -#ifndef COMPILER_FLAGS -#define COMPILER_FLAGS \ - FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION -#define MEM_LOCATION \ - "Please put data memory location here\n\t\t\t(e.g. code in flash, data " \ - "on heap etc)" -#define MEM_LOCATION_UNSPEC 1 -#endif - -#include - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for - 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise - coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef uintptr_t ee_ptr_int; -typedef size_t ee_size_t; -/* align an offset to point to a 32b value */ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile - time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching - parallel contexts must be defined. - - Two sample implementations are provided. Use or - to enable them. - - It is valid to have a different implementation of - and in , to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value - greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value - greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value - greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value - expected, and use argc/argv in the to set this value from the - command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD > 1) -#if USE_PTHREAD -#include -#define PARALLEL_METHOD "PThreads" -#elif USE_FORK -#include -#include -#include -#include -#include /* for memcpy */ -#define PARALLEL_METHOD "Fork" -#elif USE_SOCKET -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#define PARALLEL_METHOD "Sockets" -#else -#define PARALLEL_METHOD "Proprietary" -#error \ - "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S -{ -#if (MULTITHREAD > 1) -#if USE_PTHREAD - pthread_t thread; -#elif USE_FORK - pid_t pid; - int shmid; - void *shm; -#elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; -#endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD == SEED_VOLATILE) -#if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) -#define RUN_TYPE_FLAG 1 -#else -#if (TOTAL_DATA_SIZE == 1200) -#define PROFILE_RUN 1 -#else -#define PERFORMANCE_RUN 1 -#endif -#endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/posix/core_portme.mak b/benchmarks/riscv-coremark/coremark/posix/core_portme.mak deleted file mode 100755 index e6be71a7e..000000000 --- a/benchmarks/riscv-coremark/coremark/posix/core_portme.mak +++ /dev/null @@ -1,151 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File: core_portme.mak - -# Flag: OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag: CC -# Use this flag to define compiler to use -CC?= cc -# Flag: CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -PORT_CFLAGS = -O2 -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -Iposix -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -# Flag: NO_LIBRT -# Define if the platform does not provide a librt -ifndef NO_LIBRT -#Flag: LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END += -lrt -endif -# Flag: PORT_SRCS -# Port specific source files can be added here -PORT_SRCS = posix/core_portme.c -vpath %.c posix -vpath %.h posix -vpath %.mak posix -# Flag: EXTRA_DEPENDS -# Port specific extra build dependencies. -# Some ports inherit from us, so ensure this Makefile is always a dependency. -EXTRA_DEPENDS += posix/core_portme.mak -# Flag: LOAD -# Define this flag if you need to load to a target, as in a cross compile environment. - -# Flag: RUN -# Define this flag if running does not consist of simple invocation of the binary. -# In a cross compile environment, you need to define this. - -#For flashing and using a tera term macro, you could use -#LOAD = flash ADDR -#RUN = ttpmacro coremark.ttl - -#For copying to target and executing via SSH connection, you could use -#LOAD = scp $(OUTFILE) user@target:~ -#RUN = ssh user@target -c - -#For native compilation and execution -LOAD = echo Loading done -RUN = - -OEXT = .o -EXE = .exe - -# Flag: SEPARATE_COMPILE -# Define if you need to separate compilation from link stage. -# In this case, you also need to define below how to create an object file, and how to link. -ifdef SEPARATE_COMPILE - -LD = gcc -OBJOUT = -o -LFLAGS = -OFLAG = -o -COUT = -c -# Flag: PORT_OBJS -# Port specific object files can be added here -PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT) -PORT_CLEAN = *$(OEXT) - -$(OPATH)%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -endif - -# Target: port_prebuild -# Generate any files that are needed before actual build starts. -# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1 -# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line. -# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it. -# Note - Using REBUILD=1 -# -# Use make PGO=1 to invoke this sample processing. - -ifdef PGO - ifeq (,$(findstring $(PGO),gen)) - PGO_STAGE=build_pgo_gcc - CFLAGS+=-fprofile-use - endif - PORT_CLEAN+=*.gcda *.gcno gmon.out -endif - -.PHONY: port_prebuild -port_prebuild: $(PGO_STAGE) - -.PHONY: build_pgo_gcc -build_pgo_gcc: - $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1 - -# Target: port_postbuild -# Generate any files that are needed after actual build end. -# E.g. change format to srec, bin, zip in order to be able to load into flash -.PHONY: port_postbuild -port_postbuild: - -# Target: port_postrun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_postrun -port_postrun: - -# Target: port_prerun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_prerun -port_prerun: - -# Target: port_postload -# Do platform specific after load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_postload -port_postload: - -# Target: port_preload -# Do platform specific before load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_preload -port_preload: - -# FLAG: OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - -# FLAG: PERL -# Define perl executable to calculate the geomean if running separate. -PERL=/usr/bin/perl diff --git a/benchmarks/riscv-coremark/coremark/posix/core_portme_posix_overrides.h b/benchmarks/riscv-coremark/coremark/posix/core_portme_posix_overrides.h deleted file mode 100644 index c0e998adf..000000000 --- a/benchmarks/riscv-coremark/coremark/posix/core_portme_posix_overrides.h +++ /dev/null @@ -1,28 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains additional configuration constants required to execute on - different platforms over and above the POSIX defaults -*/ -#ifndef CORE_PORTME_POSIX_OVERRIDES_H -#define CORE_PORTME_POSIX_OVERRIDES_H - -/* None by default */ - -#endif diff --git a/benchmarks/riscv-coremark/coremark/rtems/core_portme.mak b/benchmarks/riscv-coremark/coremark/rtems/core_portme.mak deleted file mode 100644 index 6b27c3c41..000000000 --- a/benchmarks/riscv-coremark/coremark/rtems/core_portme.mak +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -NO_LIBRT = 1 -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/coremark/rtems/init.c b/benchmarks/riscv-coremark/coremark/rtems/init.c deleted file mode 100644 index 64d3e59ae..000000000 --- a/benchmarks/riscv-coremark/coremark/rtems/init.c +++ /dev/null @@ -1,63 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2021 Hesham Almatary - * - * This software was developed by SRI International and the University of - * Cambridge Computer Laboratory (Department of Computer Science and - * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the - * DARPA SSITH research programme. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include - -int main( - int argc, - void **args -); - -rtems_task Init( - rtems_task_argument ignored -); - -rtems_task Init( - rtems_task_argument ignored -) -{ - int ret = main(0, NULL); - exit(ret); -} - -/* configuration information */ -#define CONFIGURE_APPLICATION_NEEDS_SIMPLE_CONSOLE_DRIVER -#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER - -#define CONFIGURE_MAXIMUM_TASKS 20 - -#define CONFIGURE_RTEMS_INIT_TASKS_TABLE - -#define CONFIGURE_INIT - -#include diff --git a/benchmarks/riscv-coremark/coremark/simple/core_portme.c b/benchmarks/riscv-coremark/coremark/simple/core_portme.c deleted file mode 100644 index b95e3b21e..000000000 --- a/benchmarks/riscv-coremark/coremark/simple/core_portme.c +++ /dev/null @@ -1,149 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" - -#if VALIDATION_RUN -volatile ee_s32 seed1_volatile = 0x3415; -volatile ee_s32 seed2_volatile = 0x3415; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PERFORMANCE_RUN -volatile ee_s32 seed1_volatile = 0x0; -volatile ee_s32 seed2_volatile = 0x0; -volatile ee_s32 seed3_volatile = 0x66; -#endif -#if PROFILE_RUN -volatile ee_s32 seed1_volatile = 0x8; -volatile ee_s32 seed2_volatile = 0x8; -volatile ee_s32 seed3_volatile = 0x8; -#endif -volatile ee_s32 seed4_volatile = ITERATIONS; -volatile ee_s32 seed5_volatile = 0; -/* Porting : Timing functions - How to capture time and convert to seconds must be ported to whatever is - supported by the platform. e.g. Read value from on board RTC, read value from - cpu clock cycles performance counter etc. Sample implementation for standard - time.h and windows.h definitions included. -*/ -/* Define : TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be - measured. - - Use lower values to increase resolution, but make sure that overflow - does not occur. If there are issues with the return value overflowing, - increase this value. - */ -#define NSECS_PER_SEC CLOCKS_PER_SEC -#define CORETIMETYPE clock_t -#define GETMYTIME(_t) (*_t = clock()) -#define MYTIMEDIFF(fin, ini) ((fin) - (ini)) -#define TIMER_RES_DIVIDER 1 -#define SAMPLE_TIME_IMPLEMENTATION 1 -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function : start_time - This function will be called right before starting the timed portion of - the benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or zeroing some system parameters - e.g. setting the cpu clocks - cycles to 0. -*/ -void -start_time(void) -{ - GETMYTIME(&start_time_val); -} -/* Function : stop_time - This function will be called right after ending the timed portion of the - benchmark. - - Implementation may be capturing a system timer (as implemented in the - example code) or other system parameters - e.g. reading the current value of - cpu cycles counter. -*/ -void -stop_time(void) -{ - GETMYTIME(&stop_time_val); -} -/* Function : get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other - value, as long as it can be converted to seconds by . This - methodology is taken to accomodate any hardware or simulated platform. The - sample implementation returns millisecs by default, and the resolution is - controlled by -*/ -CORE_TICKS -get_time(void) -{ - CORE_TICKS elapsed - = (CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function : time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for - floating point. Default implementation implemented by the EE_TICKS_PER_SEC - macro above. -*/ -secs_ret -time_in_secs(CORE_TICKS ticks) -{ - secs_ret retval = ((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} - -ee_u32 default_num_contexts = 1; - -/* Function : portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void -portable_init(core_portable *p, int *argc, char *argv[]) -{ - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) - { - ee_printf( - "ERROR! Please define ee_ptr_int to a type that holds a " - "pointer!\n"); - } - if (sizeof(ee_u32) != 4) - { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } - p->portable_id = 1; -} -/* Function : portable_fini - Target specific final code -*/ -void -portable_fini(core_portable *p) -{ - p->portable_id = 0; -} diff --git a/benchmarks/riscv-coremark/coremark/simple/core_portme.h b/benchmarks/riscv-coremark/coremark/simple/core_portme.h deleted file mode 100644 index dfd94cbfc..000000000 --- a/benchmarks/riscv-coremark/coremark/simple/core_portme.h +++ /dev/null @@ -1,208 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic : Description - This file contains configuration constants required to execute on - different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration : HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration : HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration : USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 1 -#endif -/* Configuration : HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration : HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf - function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration : CORE_TICKS - Define type of return from the timing functions. - */ -#include -typedef clock_t CORE_TICKS; - -/* Definitions : COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION -#ifdef __GNUC__ -#define COMPILER_VERSION "GCC"__VERSION__ -#else -#define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" -#endif -#endif -#ifndef COMPILER_FLAGS -#define COMPILER_FLAGS \ - FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION -#define MEM_LOCATION "STACK" -#endif - -/* Data Types : - To avoid compiler issues, define the data types that need ot be used for - 8b, 16b and 32b in . - - *Imprtant* : - ee_ptr_int needs to be the data type used to hold pointers, otherwise - coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem : - This macro is used to align an offset to point to a 32b value. It is - used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x)-1) & ~3)) - -/* Configuration : SEED_METHOD - Defines method to get seed values that cannot be computed at compile - time. - - Valid values : - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_VOLATILE -#endif - -/* Configuration : MEM_METHOD - Defines method to get a block of memry. - - Valid values : - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_STACK -#endif - -/* Configuration : MULTITHREAD - Define for parallel execution - - Valid values : - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note : - If this flag is defined to more then 1, an implementation for launching - parallel contexts must be defined. - - Two sample implementations are provided. Use or - to enable them. - - It is valid to have a different implementation of - and in , to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#define USE_PTHREAD 0 -#define USE_FORK 0 -#define USE_SOCKET 0 -#endif - -/* Configuration : MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values : - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported - - Note : - This flag only matters if MULTITHREAD has been defined to a value - greater then 1. -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration : MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values : - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable : default_num_contexts - Not used for this simple port, must cintain the value 1. -*/ -extern ee_u32 default_num_contexts; - -typedef struct CORE_PORTABLE_S -{ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if !defined(PROFILE_RUN) && !defined(PERFORMANCE_RUN) \ - && !defined(VALIDATION_RUN) -#if (TOTAL_DATA_SIZE == 1200) -#define PROFILE_RUN 1 -#elif (TOTAL_DATA_SIZE == 2000) -#define PERFORMANCE_RUN 1 -#else -#define VALIDATION_RUN 1 -#endif -#endif - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/coremark/simple/core_portme.mak b/benchmarks/riscv-coremark/coremark/simple/core_portme.mak deleted file mode 100755 index 61c3db683..000000000 --- a/benchmarks/riscv-coremark/coremark/simple/core_portme.mak +++ /dev/null @@ -1,60 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File : core_portme.mak - -# Flag : OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag : CC -# Use this flag to define compiler to use -CC = gcc -# Flag : CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -PORT_CFLAGS = -O2 -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -#Flag : LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note : On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END = -# Flag : PORT_SRCS -# Port specific source files can be added here -PORT_SRCS = $(PORT_DIR)/core_portme.c -# Flag : LOAD -# For a simple port, we assume self hosted compile and run, no load needed. - -# Flag : RUN -# For a simple port, we assume self hosted compile and run, simple invocation of the executable - -#For native compilation and execution -LOAD = echo Loading done -RUN = - -OEXT = .o -EXE = .exe - -# Target : port_pre% and port_post% -# For the purpose of this simple port, no pre or post steps needed. - -.PHONY : port_prebuild port_postbuild port_prerun port_postrun port_preload port_postload -port_pre% port_post% : - -# FLAG : OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - diff --git a/benchmarks/riscv-coremark/old/README.md b/benchmarks/riscv-coremark/old/README.md deleted file mode 100644 index 7c02eb1bf..000000000 --- a/benchmarks/riscv-coremark/old/README.md +++ /dev/null @@ -1,23 +0,0 @@ -Coremark EEMBC Wrapper -====================== - -This repository provides the utility files to port [CoreMark EEMBC](https://www.eembc.org/coremark/) to RISC-V. - -### Requirements - - - You must have installed the RISC-V tools - -### Setup - - - `git submodule update --init` - - Run the `./build-coremark.sh` script that does the following - - Builds a version of Coremark for Linux or pk (coremark.riscv) - - Builds a version of Coremark for bare-metal (coremark.bare.riscv) - - Copies the output binaries into this directory - -### Default Files - -The default files target **RV64GC** and use minimal amount of compilation flags. Additionally, the `*.mak` file in the `riscv64` -folder setups `spike pk` as the default `run` rule. - -Feel free to change these to suit your needs. diff --git a/benchmarks/riscv-coremark/old/extraPortmes/README.md b/benchmarks/riscv-coremark/old/extraPortmes/README.md deleted file mode 100644 index 681fc4d8b..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/README.md +++ /dev/null @@ -1,7 +0,0 @@ -This directory is a backup for the portme files associated with cygwin, linux, and linux64 - -This backup is needed in the event that a user replaces the coremark directory with a clean version -from EEMBC's github page (the clean version does not have the cygwin, linux, -and linux64 files that our version does). - -Please do not delete this directory under any circumstance. \ No newline at end of file diff --git a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.c b/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.c deleted file mode 100755 index fe8d29983..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.c +++ /dev/null @@ -1,336 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.h b/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.h deleted file mode 100755 index 9471b12ec..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.h +++ /dev/null @@ -1,293 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem: - This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.mak b/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.mak deleted file mode 100644 index 97b6d6ace..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/cygwin/core_portme.mak +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.c b/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.c deleted file mode 100755 index 6b63610d1..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.c +++ /dev/null @@ -1,338 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - { - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.h b/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.h deleted file mode 100755 index 2cf4659a4..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.h +++ /dev/null @@ -1,290 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef ee_u32 ee_ptr_int; -typedef size_t ee_size_t; -/* align_mem: - This macro is used to align an offset to point to a 32b value. It is used in the Matrix algorithm to initialize the input memory blocks. -*/ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.mak b/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.mak deleted file mode 100644 index 97b6d6ace..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux/core_portme.mak +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -include posix/core_portme.mak diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.c b/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.c deleted file mode 100755 index fe8d29983..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.c +++ /dev/null @@ -1,336 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - #define SAMPLE_TIME_IMPLEMENTATION 0 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.h b/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.h deleted file mode 100755 index 1228a679b..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.h +++ /dev/null @@ -1,291 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 1 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -#error "Please define type of CORE_TICKS and implement start_time, end_time get_time and time_in_secs functions!" -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef unsigned long long ee_ptr_int; -typedef size_t ee_size_t; -/* align an offset to point to a 32b value */ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.mak b/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.mak deleted file mode 100755 index 5cfabee32..000000000 --- a/benchmarks/riscv-coremark/old/extraPortmes/linux64/core_portme.mak +++ /dev/null @@ -1,140 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File: core_portme.mak - -# Flag: OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag: CC -# Use this flag to define compiler to use -CC = gcc -# Flag: CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -PORT_CFLAGS = -O2 -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -#Flag: LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END += -lrt -# Flag: PORT_SRCS -# Port specific source files can be added here -PORT_SRCS = $(PORT_DIR)/core_portme.c -# Flag: LOAD -# Define this flag if you need to load to a target, as in a cross compile environment. - -# Flag: RUN -# Define this flag if running does not consist of simple invocation of the binary. -# In a cross compile environment, you need to define this. - -#For flashing and using a tera term macro, you could use -#LOAD = flash ADDR -#RUN = ttpmacro coremark.ttl - -#For copying to target and executing via SSH connection, you could use -#LOAD = scp $(OUTFILE) user@target:~ -#RUN = ssh user@target -c - -#For native compilation and execution -LOAD = echo Loading done -RUN = - -OEXT = .o -EXE = .exe - -# Flag: SEPARATE_COMPILE -# Define if you need to separate compilation from link stage. -# In this case, you also need to define below how to create an object file, and how to link. -ifdef SEPARATE_COMPILE - -LD = gcc -OBJOUT = -o -LFLAGS = -OFLAG = -o -COUT = -c -# Flag: PORT_OBJS -# Port specific object files can be added here -PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT) -PORT_CLEAN = *$(OEXT) - -$(OPATH)%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -endif - -# Target: port_prebuild -# Generate any files that are needed before actual build starts. -# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1 -# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line. -# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it. -# Note - Using REBUILD=1 -# -# Use make PGO=1 to invoke this sample processing. - -ifdef PGO - ifeq (,$(findstring $(PGO),gen)) - PGO_STAGE=build_pgo_gcc - CFLAGS+=-fprofile-use - endif - PORT_CLEAN+=*.gcda *.gcno gmon.out -endif - -.PHONY: port_prebuild -port_prebuild: $(PGO_STAGE) - -.PHONY: build_pgo_gcc -build_pgo_gcc: - $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1 - -# Target: port_postbuild -# Generate any files that are needed after actual build end. -# E.g. change format to srec, bin, zip in order to be able to load into flash -.PHONY: port_postbuild -port_postbuild: - -# Target: port_postrun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_postrun -port_postrun: - -# Target: port_prerun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_prerun -port_prerun: - -# Target: port_postload -# Do platform specific after load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_postload -port_postload: - -# Target: port_preload -# Do platform specific before load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_preload -port_preload: - -# FLAG: OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - -# FLAG: PERL -# Define perl executable to calculate the geomean if running separate. -PERL=/usr/bin/perl diff --git a/benchmarks/riscv-coremark/old/riscv64/core_portme.c b/benchmarks/riscv-coremark/old/riscv64/core_portme.c deleted file mode 100755 index 8f17cb8bd..000000000 --- a/benchmarks/riscv-coremark/old/riscv64/core_portme.c +++ /dev/null @@ -1,346 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -#include -#include -#include "coremark.h" -#if CALLGRIND_RUN -#include -#endif - -#if (MEM_METHOD==MEM_MALLOC) -#include -/* Function: portable_malloc - Provide malloc() functionality in a platform specific way. -*/ -void *portable_malloc(size_t size) { - return malloc(size); -} -/* Function: portable_free - Provide free() functionality in a platform specific way. -*/ -void portable_free(void *p) { - free(p); -} -#else -void *portable_malloc(size_t size) { - return NULL; -} -void portable_free(void *p) { - p=NULL; -} -#endif - -#if (SEED_METHOD==SEED_VOLATILE) -#if VALIDATION_RUN - volatile ee_s32 seed1_volatile=0x3415; - volatile ee_s32 seed2_volatile=0x3415; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PERFORMANCE_RUN - volatile ee_s32 seed1_volatile=0x0; - volatile ee_s32 seed2_volatile=0x0; - volatile ee_s32 seed3_volatile=0x66; -#endif -#if PROFILE_RUN - volatile ee_s32 seed1_volatile=0x8; - volatile ee_s32 seed2_volatile=0x8; - volatile ee_s32 seed3_volatile=0x8; -#endif - volatile ee_s32 seed4_volatile=ITERATIONS; - volatile ee_s32 seed5_volatile=0; -#endif -/* Porting: Timing functions - How to capture time and convert to seconds must be ported to whatever is supported by the platform. - e.g. Read value from on board RTC, read value from cpu clock cycles performance counter etc. - Sample implementation for standard time.h and windows.h definitions included. -*/ -/* Define: TIMER_RES_DIVIDER - Divider to trade off timer resolution and total time that can be measured. - - Use lower values to increase resolution, but make sure that overflow does not occur. - If there are issues with the return value overflowing, increase this value. - */ -#if USE_CLOCK - #define NSECS_PER_SEC CLOCKS_PER_SEC - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE clock_t - #define GETMYTIME(_t) (*_t=clock()) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif defined(_MSC_VER) - #define NSECS_PER_SEC 10000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE FILETIME - #define GETMYTIME(_t) GetSystemTimeAsFileTime(_t) - #define MYTIMEDIFF(fin,ini) (((*(__int64*)&fin)-(*(__int64*)&ini))/TIMER_RES_DIVIDER) - /* setting to millisces resolution by default with MSDEV */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#elif HAS_TIME_H - #define NSECS_PER_SEC 1000000000 - #define EE_TIMER_TICKER_RATE 1000 - #define CORETIMETYPE struct timespec - #define GETMYTIME(_t) clock_gettime(CLOCK_REALTIME,_t) - #define MYTIMEDIFF(fin,ini) ((fin.tv_sec-ini.tv_sec)*(NSECS_PER_SEC/TIMER_RES_DIVIDER)+(fin.tv_nsec-ini.tv_nsec)/TIMER_RES_DIVIDER) - /* setting to 1/1000 of a second resolution by default with linux */ - #ifndef TIMER_RES_DIVIDER - #define TIMER_RES_DIVIDER 1000000 - #endif - #define SAMPLE_TIME_IMPLEMENTATION 1 -#else - // Defined for RISCV - #define NSECS_PER_SEC 1000000000 // TODO: What freq are we assuming? - #define EE_TIMER_TICKER_RATE 1000 // TODO: What is this? - #define CORETIMETYPE clock_t - #define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - #define GETMYTIME(_t) (*_t=read_csr(cycle)) - #define MYTIMEDIFF(fin,ini) ((fin)-(ini)) - #define TIMER_RES_DIVIDER 1 - #define SAMPLE_TIME_IMPLEMENTATION 1 -#endif -#define EE_TICKS_PER_SEC (NSECS_PER_SEC / TIMER_RES_DIVIDER) - -#if SAMPLE_TIME_IMPLEMENTATION -/** Define Host specific (POSIX), or target specific global time variables. */ -static CORETIMETYPE start_time_val, stop_time_val; - -/* Function: start_time - This function will be called right before starting the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or zeroing some system parameters - e.g. setting the cpu clocks cycles to 0. -*/ -void start_time(void) { - GETMYTIME(&start_time_val ); -#if CALLGRIND_RUN - CALLGRIND_START_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif -} -/* Function: stop_time - This function will be called right after ending the timed portion of the benchmark. - - Implementation may be capturing a system timer (as implemented in the example code) - or other system parameters - e.g. reading the current value of cpu cycles counter. -*/ -void stop_time(void) { -#if CALLGRIND_RUN - CALLGRIND_STOP_INSTRUMENTATION -#endif -#if MICA - asm volatile("int3");/*1 */ -#endif - GETMYTIME(&stop_time_val ); -} -/* Function: get_time - Return an abstract "ticks" number that signifies time on the system. - - Actual value returned may be cpu cycles, milliseconds or any other value, - as long as it can be converted to seconds by . - This methodology is taken to accomodate any hardware or simulated platform. - The sample implementation returns millisecs by default, - and the resolution is controlled by -*/ -CORE_TICKS get_time(void) { - CORE_TICKS elapsed=(CORE_TICKS)(MYTIMEDIFF(stop_time_val, start_time_val)); - return elapsed; -} -/* Function: time_in_secs - Convert the value returned by get_time to seconds. - - The type is used to accomodate systems with no support for floating point. - Default implementation implemented by the EE_TICKS_PER_SEC macro above. -*/ -secs_ret time_in_secs(CORE_TICKS ticks) { - secs_ret retval=((secs_ret)ticks) / (secs_ret)EE_TICKS_PER_SEC; - return retval; -} -#else -#error "Please implement timing functionality in core_portme.c" -#endif /* SAMPLE_TIME_IMPLEMENTATION */ - -ee_u32 default_num_contexts=MULTITHREAD; - -/* Function: portable_init - Target specific initialization code - Test for some common mistakes. -*/ -void portable_init(core_portable *p, int *argc, char *argv[]) -{ -#if PRINT_ARGS - int i; - for (i=0; i<*argc; i++) { - ee_printf("Arg[%d]=%s\n",i,argv[i]); - } -#endif - if (sizeof(ee_ptr_int) != sizeof(ee_u8 *)) { - ee_printf("ERROR! Please define ee_ptr_int to a type that holds a pointer!\n"); - } - if (sizeof(ee_u32) != 4) { - ee_printf("ERROR! Please define ee_u32 to a 32b unsigned type!\n"); - } -#if (MAIN_HAS_NOARGC && (SEED_METHOD==SEED_ARG)) - ee_printf("ERROR! Main has no argc, but SEED_METHOD defined to SEED_ARG!\n"); -#endif - -#if (MULTITHREAD>1) && (SEED_METHOD==SEED_ARG) - int nargs=*argc,i; - if ((nargs>1) && (*argv[1]=='M')) { - default_num_contexts=parseval(argv[1]+1); - if (default_num_contexts>MULTITHREAD) - default_num_contexts=MULTITHREAD; - /* Shift args since first arg is directed to the portable part and not to coremark main */ - --nargs; - for (i=1; i*/ - p->portable_id=1; -} -/* Function: portable_fini - Target specific final code -*/ -void portable_fini(core_portable *p) -{ - p->portable_id=0; -} - -#if (MULTITHREAD>1) - -/* Function: core_start_parallel - Start benchmarking in a parallel context. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -/* Function: core_stop_parallel - Stop a parallel context execution of coremark, and gather the results. - - Three implementations are provided, one using pthreads, one using fork and shared mem, and one using fork and sockets. - Other implementations using MCAPI or other standards can easily be devised. -*/ -#if USE_PTHREAD -ee_u8 core_start_parallel(core_results *res) { - return (ee_u8)pthread_create(&(res->port.thread),NULL,iterate,(void *)res); -} -ee_u8 core_stop_parallel(core_results *res) { - void *retval; - return (ee_u8)pthread_join(res->port.thread,&retval); -} -#elif USE_FORK -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - key_t key=4321+key_id; - key_id++; - res->port.pid=fork(); - res->port.shmid=shmget(key, 8, IPC_CREAT | 0666); - if (res->port.shmid<0) { - ee_printf("ERROR in shmget!\n"); - } - if (res->port.pid==0) { - iterate(res); - res->port.shm=shmat(res->port.shmid, NULL, 0); - /* copy the validation values to the shared memory area and quit*/ - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in child shmat!\n"); - } else { - memcpy(res->port.shm,&(res->crc),8); - shmdt(res->port.shm); - } - exit(0); - } - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - /* after process is done, get the values from the shared memory area */ - res->port.shm=shmat(res->port.shmid, NULL, 0); - if (res->port.shm == (char *) -1) { - ee_printf("ERROR in parent shmat!\n"); - return 0; - } - memcpy(&(res->crc),res->port.shm,8); - shmdt(res->port.shm); - return 1; -} -#elif USE_SOCKET -static int key_id=0; -ee_u8 core_start_parallel(core_results *res) { - int bound, buffer_length=8; - res->port.sa.sin_family = AF_INET; - res->port.sa.sin_addr.s_addr = htonl(0x7F000001); - res->port.sa.sin_port = htons(7654+key_id); - key_id++; - res->port.pid=fork(); - if (res->port.pid==0) { /* benchmark child */ - iterate(res); - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - if (-1 == res->port.sock) /* if socket failed to initialize, exit */ { - ee_printf("Error Creating Socket"); - } else { - int bytes_sent = sendto(res->port.sock, &(res->crc), buffer_length, 0,(struct sockaddr*)&(res->port.sa), sizeof (struct sockaddr_in)); - if (bytes_sent < 0) - ee_printf("Error sending packet: %s\n", strerror(errno)); - close(res->port.sock); /* close the socket */ - } - exit(0); - } - /* parent process, open the socket */ - res->port.sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_UDP); - bound = bind(res->port.sock,(struct sockaddr*)&(res->port.sa), sizeof(struct sockaddr)); - if (bound < 0) - ee_printf("bind(): %s\n",strerror(errno)); - return 1; -} -ee_u8 core_stop_parallel(core_results *res) { - int status; - int fromlen=sizeof(struct sockaddr); - int recsize = recvfrom(res->port.sock, &(res->crc), 8, 0, (struct sockaddr*)&(res->port.sa), &fromlen); - if (recsize < 0) { - ee_printf("Error in receive: %s\n", strerror(errno)); - return 0; - } - pid_t wpid = waitpid(res->port.pid,&status,WUNTRACED); - if (wpid != res->port.pid) { - ee_printf("ERROR waiting for child.\n"); - if (errno == ECHILD) ee_printf("errno=No such child %d\n",res->port.pid); - if (errno == EINTR) ee_printf("errno=Interrupted\n"); - return 0; - } - return 1; -} -#else /* no standard multicore implementation */ -#error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* multithread implementations */ -#endif diff --git a/benchmarks/riscv-coremark/old/riscv64/core_portme.h b/benchmarks/riscv-coremark/old/riscv64/core_portme.h deleted file mode 100755 index 4e28afd36..000000000 --- a/benchmarks/riscv-coremark/old/riscv64/core_portme.h +++ /dev/null @@ -1,296 +0,0 @@ -/* -Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) - -Licensed under the Apache License, Version 2.0 (the "License"); -you may not use this file except in compliance with the License. -You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - -Unless required by applicable law or agreed to in writing, software -distributed under the License is distributed on an "AS IS" BASIS, -WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -See the License for the specific language governing permissions and -limitations under the License. - -Original Author: Shay Gal-on -*/ - -/* Topic: Description - This file contains configuration constants required to execute on different platforms -*/ -#ifndef CORE_PORTME_H -#define CORE_PORTME_H -/************************/ -/* Data types and settings */ -/************************/ -/* Configuration: HAS_FLOAT - Define to 1 if the platform supports floating point. -*/ -#ifndef HAS_FLOAT -#define HAS_FLOAT 1 -#endif -/* Configuration: HAS_TIME_H - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef HAS_TIME_H -#define HAS_TIME_H 0 -#endif -/* Configuration: USE_CLOCK - Define to 1 if platform has the time.h header file, - and implementation of functions thereof. -*/ -#ifndef USE_CLOCK -#define USE_CLOCK 0 -#endif -/* Configuration: HAS_STDIO - Define to 1 if the platform has stdio.h. -*/ -#ifndef HAS_STDIO -#define HAS_STDIO 1 -#endif -/* Configuration: HAS_PRINTF - Define to 1 if the platform has stdio.h and implements the printf function. -*/ -#ifndef HAS_PRINTF -#define HAS_PRINTF 1 -#endif - -/* Configuration: CORE_TICKS - Define type of return from the timing functions. - */ -#if defined(_MSC_VER) -#include -typedef size_t CORE_TICKS; -#elif HAS_TIME_H -#include -typedef clock_t CORE_TICKS; -#else -/* Configuration: size_t and clock_t - Note these need to match the size of the clock output and the xLen the processor supports - */ -typedef unsigned long int size_t; -typedef unsigned long int clock_t; -typedef clock_t CORE_TICKS; -#endif - -/* Definitions: COMPILER_VERSION, COMPILER_FLAGS, MEM_LOCATION - Initialize these strings per platform -*/ -#ifndef COMPILER_VERSION - #ifdef __GNUC__ - #define COMPILER_VERSION "GCC"__VERSION__ - #else - #define COMPILER_VERSION "Please put compiler version here (e.g. gcc 4.1)" - #endif -#endif -#ifndef COMPILER_FLAGS - #define COMPILER_FLAGS FLAGS_STR /* "Please put compiler flags here (e.g. -o3)" */ -#endif -#ifndef MEM_LOCATION - #define MEM_LOCATION "Please put data memory location here\n\t\t\t(e.g. code in flash, data on heap etc)" - #define MEM_LOCATION_UNSPEC 1 -#endif - -/* Data Types: - To avoid compiler issues, define the data types that need ot be used for 8b, 16b and 32b in . - - *Imprtant*: - ee_ptr_int needs to be the data type used to hold pointers, otherwise coremark may fail!!! -*/ -typedef signed short ee_s16; -typedef unsigned short ee_u16; -typedef signed int ee_s32; -typedef double ee_f32; -typedef unsigned char ee_u8; -typedef unsigned int ee_u32; -typedef unsigned long long ee_ptr_int; -typedef size_t ee_size_t; -/* align an offset to point to a 32b value */ -#define align_mem(x) (void *)(4 + (((ee_ptr_int)(x) - 1) & ~3)) - -/* Configuration: SEED_METHOD - Defines method to get seed values that cannot be computed at compile time. - - Valid values: - SEED_ARG - from command line. - SEED_FUNC - from a system function. - SEED_VOLATILE - from volatile variables. -*/ -#ifndef SEED_METHOD -#define SEED_METHOD SEED_ARG -#endif - -/* Configuration: MEM_METHOD - Defines method to get a block of memry. - - Valid values: - MEM_MALLOC - for platforms that implement malloc and have malloc.h. - MEM_STATIC - to use a static memory array. - MEM_STACK - to allocate the data block on the stack (NYI). -*/ -#ifndef MEM_METHOD -#define MEM_METHOD MEM_MALLOC -#endif - -/* Configuration: MULTITHREAD - Define for parallel execution - - Valid values: - 1 - only one context (default). - N>1 - will execute N copies in parallel. - - Note: - If this flag is defined to more then 1, an implementation for launching parallel contexts must be defined. - - Two sample implementations are provided. Use or to enable them. - - It is valid to have a different implementation of and in , - to fit a particular architecture. -*/ -#ifndef MULTITHREAD -#define MULTITHREAD 1 -#endif - -/* Configuration: USE_PTHREAD - Sample implementation for launching parallel contexts - This implementation uses pthread_thread_create and pthread_join. - - Valid values: - 0 - Do not use pthreads API. - 1 - Use pthreads API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_PTHREAD -#define USE_PTHREAD 0 -#endif - -/* Configuration: USE_FORK - Sample implementation for launching parallel contexts - This implementation uses fork, waitpid, shmget,shmat and shmdt. - - Valid values: - 0 - Do not use fork API. - 1 - Use fork API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_FORK -#define USE_FORK 0 -#endif - -/* Configuration: USE_SOCKET - Sample implementation for launching parallel contexts - This implementation uses fork, socket, sendto and recvfrom - - Valid values: - 0 - Do not use fork and sockets API. - 1 - Use fork and sockets API - - Note: - This flag only matters if MULTITHREAD has been defined to a value greater then 1. -*/ -#ifndef USE_SOCKET -#define USE_SOCKET 0 -#endif - -/* Configuration: MAIN_HAS_NOARGC - Needed if platform does not support getting arguments to main. - - Valid values: - 0 - argc/argv to main is supported - 1 - argc/argv to main is not supported -*/ -#ifndef MAIN_HAS_NOARGC -#define MAIN_HAS_NOARGC 0 -#endif - -/* Configuration: MAIN_HAS_NORETURN - Needed if platform does not support returning a value from main. - - Valid values: - 0 - main returns an int, and return value will be 0. - 1 - platform does not support returning a value from main -*/ -#ifndef MAIN_HAS_NORETURN -#define MAIN_HAS_NORETURN 0 -#endif - -/* Variable: default_num_contexts - Number of contexts to spawn in multicore context. - Override this global value to change number of contexts used. - - Note: - This value may not be set higher then the define. - - To experiment, you can set the define to the highest value expected, and use argc/argv in the to set this value from the command line. -*/ -extern ee_u32 default_num_contexts; - -#if (MULTITHREAD>1) -#if USE_PTHREAD - #include - #define PARALLEL_METHOD "PThreads" -#elif USE_FORK - #include - #include - #include - #include - #include /* for memcpy */ - #define PARALLEL_METHOD "Fork" -#elif USE_SOCKET - #include - #include - #include - #include - #include - #include - #include - #include - #include - #include - #define PARALLEL_METHOD "Sockets" -#else - #define PARALLEL_METHOD "Proprietary" - #error "Please implement multicore functionality in core_portme.c to use multiple contexts." -#endif /* Method for multithreading */ -#endif /* MULTITHREAD > 1 */ - -typedef struct CORE_PORTABLE_S { -#if (MULTITHREAD>1) - #if USE_PTHREAD - pthread_t thread; - #elif USE_FORK - pid_t pid; - int shmid; - void *shm; - #elif USE_SOCKET - pid_t pid; - int sock; - struct sockaddr_in sa; - #endif /* Method for multithreading */ -#endif /* MULTITHREAD>1 */ - ee_u8 portable_id; -} core_portable; - -/* target specific init/fini */ -void portable_init(core_portable *p, int *argc, char *argv[]); -void portable_fini(core_portable *p); - -#if (SEED_METHOD==SEED_VOLATILE) - #if (VALIDATION_RUN || PERFORMANCE_RUN || PROFILE_RUN) - #define RUN_TYPE_FLAG 1 - #else - #if (TOTAL_DATA_SIZE==1200) - #define PROFILE_RUN 1 - #else - #define PERFORMANCE_RUN 1 - #endif - #endif -#endif /* SEED_METHOD==SEED_VOLATILE */ - -#endif /* CORE_PORTME_H */ diff --git a/benchmarks/riscv-coremark/old/riscv64/core_portme.mak b/benchmarks/riscv-coremark/old/riscv64/core_portme.mak deleted file mode 100755 index edc341abc..000000000 --- a/benchmarks/riscv-coremark/old/riscv64/core_portme.mak +++ /dev/null @@ -1,147 +0,0 @@ -# Copyright 2018 Embedded Microprocessor Benchmark Consortium (EEMBC) -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -# Original Author: Shay Gal-on - -#File: core_portme.mak - -# Flag: RISCVTOOLS -# Use this flag to point to your RISCV tools -RISCVTOOLS=$(RISCV) -# Flag: RISCVTYPE -# Type of toolchain to use -RISCVTYPE=riscv64-unknown-elf -# Flag: OUTFLAG -# Use this flag to define how to to get an executable (e.g -o) -OUTFLAG= -o -# Flag: CC -# Use this flag to define compiler to use -CC = $(RISCVTOOLS)/bin/$(RISCVTYPE)-gcc -# Flag: CFLAGS -# Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags" -#PORT_CFLAGS = -O2 -static -std=gnu99 -PORT_CFLAGS = -O2 -FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)" -CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -#Flag: LFLAGS_END -# Define any libraries needed for linking or other flags that should come at the end of the link line (e.g. linker scripts). -# Note: On certain platforms, the default clock_gettime implementation is supported but requires linking of librt. -LFLAGS_END += -# Flag: PORT_SRCS -# Port specific source files can be added here -PORT_SRCS = $(PORT_DIR)/core_portme.c -# Flag: LOAD -# Define this flag if you need to load to a target, as in a cross compile environment. - -# Flag: RUN -# Define this flag if running does not consist of simple invocation of the binary. -# In a cross compile environment, you need to define this. - -#For flashing and using a tera term macro, you could use -#LOAD = flash ADDR -#RUN = ttpmacro coremark.ttl - -#For copying to target and executing via SSH connection, you could use -#LOAD = scp $(OUTFILE) user@target:~ -#RUN = ssh user@target -c - -#For native compilation and execution -LOAD = echo Loading done -RUN = spike pk - -OEXT = .o -EXE = .riscv - -# Flag: SEPARATE_COMPILE -# Define if you need to separate compilation from link stage. -# In this case, you also need to define below how to create an object file, and how to link. -ifdef SEPARATE_COMPILE - -LD = $(RISCVTOOLS)/bin/$(RISCVTYPE)-gcc -OBJOUT = -o -LFLAGS = -OFLAG = -o -COUT = -c -# Flag: PORT_OBJS -# Port specific object files can be added here -PORT_OBJS = $(PORT_DIR)/core_portme$(OEXT) -PORT_CLEAN = *$(OEXT) - -$(OPATH)%$(OEXT) : %.c - $(CC) $(CFLAGS) $(XCFLAGS) $(COUT) $< $(OBJOUT) $@ - -endif - -# Target: port_prebuild -# Generate any files that are needed before actual build starts. -# E.g. generate profile guidance files. Sample PGO generation for gcc enabled with PGO=1 -# - First, check if PGO was defined on the command line, if so, need to add -fprofile-use to compile line. -# - Second, if PGO reference has not yet been generated, add a step to the prebuild that will build a profile-generate version and run it. -# Note - Using REBUILD=1 -# -# Use make PGO=1 to invoke this sample processing. - -ifdef PGO - ifeq (,$(findstring $(PGO),gen)) - PGO_STAGE=build_pgo_gcc - CFLAGS+=-fprofile-use - endif - PORT_CLEAN+=*.gcda *.gcno gmon.out -endif - -.PHONY: port_prebuild -port_prebuild: $(PGO_STAGE) - -.PHONY: build_pgo_gcc -build_pgo_gcc: - $(MAKE) PGO=gen XCFLAGS="$(XCFLAGS) -fprofile-generate -DTOTAL_DATA_SIZE=1200" ITERATIONS=10 gen_pgo_data REBUILD=1 - -# Target: port_postbuild -# Generate any files that are needed after actual build end. -# E.g. change format to srec, bin, zip in order to be able to load into flash -.PHONY: port_postbuild -port_postbuild: - -# Target: port_postrun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_postrun -port_postrun: - -# Target: port_prerun -# Do platform specific after run stuff. -# E.g. reset the board, backup the logfiles etc. -.PHONY: port_prerun -port_prerun: - -# Target: port_postload -# Do platform specific after load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_postload -port_postload: - -# Target: port_preload -# Do platform specific before load stuff. -# E.g. reset the reset power to the flash eraser -.PHONY: port_preload -port_preload: - -# FLAG: OPATH -# Path to the output folder. Default - current folder. -OPATH = ./ -MKDIR = mkdir -p - -# FLAG: PERL -# Define perl executable to calculate the geomean if running separate. -PERL=/usr/bin/perl diff --git a/benchmarks/riscv-coremark/old/trace b/benchmarks/riscv-coremark/old/trace deleted file mode 100644 index 7c76d0bfa..000000000 --- a/benchmarks/riscv-coremark/old/trace +++ /dev/null @@ -1,48 +0,0 @@ -Imperas riscvOVPsimPlus - - -riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com. -Copyright (c) 2005-2021 Imperas Software Ltd. Contains Imperas Proprietary Information. -Licensed Software, All Rights Reserved. -Visit www.IMPERAS.com for multicore debug, verification and analysis solutions. - -riscvOVPsimPlus started: Wed May 12 17:55:33 2021 - - -Info (GDBT_PORT) Host: Tera.Eng.HMC.Edu, Port: 55460 -Info (DBC_LGDB) Starting Debugger /cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscv-none-embed-gdb -Info (GDBT_WAIT) Waiting for remote debugger to connect... -Info (OR_OF) Target 'riscvOVPsim/cpu' has object file read from 'coremark.bare.riscv' -Info (OR_PH) Program Headers: -Info (OR_PH) Type Offset VirtAddr PhysAddr -Info (OR_PH) FileSiz MemSiz Flags Align -Info (OR_PD) LOAD 0x0000000000001000 0x0000000080000000 0x0000000080000000 -Info (OR_PD) 0x0000000000000204 0x0000000000000204 R-E 1000 -Info (OR_PD) LOAD 0x0000000000002000 0x0000000080001000 0x0000000080001000 -Info (OR_PD) 0x00000000000047e0 0x0000000000004ff0 RWE 1000 -Info (GDBT_CONNECTED) Client connected -Info (GDBT_GON) Client disappeared 'riscvOVPsim/cpu' -Info -Info --------------------------------------------------- -Info CPU 'riscvOVPsim/cpu' STATISTICS -Info Type : riscv (RV64GC) -Info Nominal MIPS : 100 -Info Final program counter : 0x80003558 -Info Simulated instructions: 1,455,608 -Info Simulated MIPS : 0.0 -Info --------------------------------------------------- -Info -Info --------------------------------------------------- -Info SIMULATION TIME STATISTICS -Info Simulated time : 0.02 seconds -Info User time : 99.23 seconds -Info System time : 254.08 seconds -Info Elapsed time : 1107.49 seconds -Info --------------------------------------------------- - -riscvOVPsimPlus finished: Wed May 12 18:14:04 2021 - - -riscvOVPsimPlus (64-Bit) v20210329.0 Open Virtual Platform simulator from www.IMPERAS.com. -Visit www.IMPERAS.com for multicore debug, verification and analysis solutions. - diff --git a/benchmarks/riscv-coremark/old/transferobjdump.sh b/benchmarks/riscv-coremark/old/transferobjdump.sh deleted file mode 100755 index 69578566a..000000000 --- a/benchmarks/riscv-coremark/old/transferobjdump.sh +++ /dev/null @@ -1,8 +0,0 @@ -#!/usr/bin/env bash -./build-coremark.sh - -riscv64-unknown-elf-objdump -D coremark.bare.riscv > coremarkcodemod.bare.riscv.objdump -cp coremarkcodemod.bare.riscv.objdump ~/riscv-wally/tests/imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/. -pushd ~/riscv-wally/tests/imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark -./exe2memfile.pl coremarkcodemod.bare.riscv -popd diff --git a/bin/testlist.pl b/bin/testlist.pl index 745ff29e5..12be0a913 100755 --- a/bin/testlist.pl +++ b/bin/testlist.pl @@ -9,7 +9,7 @@ use warnings; import os; if ($#ARGV != 0) { - die("Usage: $0 workpath [e.g. $0 $WALLY/addins/riscv-arch-test/work") + die("Usage: $0 workpath [e.g. $0 \$WALLY/addins/riscv-arch-test/work") } my $mypath = $ARGV[0]; my @dirs = glob($mypath.'/*/*'); diff --git a/examples/C/fir/fir.S b/examples/C/fir/fir.S new file mode 100644 index 000000000..a96339ba7 --- /dev/null +++ b/examples/C/fir/fir.S @@ -0,0 +1,35 @@ +// fir.s +// mmasserfrye@hmc.edu 30 January 2022 +// FIR filter + +// a0 = N, a1 = M, a2 = &X, a3 = &c, a4 = &Y + +.global fir + +fir: + li t0, 0 # n = 0 = t0 + slli t6, a0, 3 # N*8 + slli t5, a1, 3 # M*8 + addi t4, t5, -8 # (M-1)*8 +for1: + bge t0, t6, end # exit outer for if n >= N + fmv.d.x f3, zero # sum = 0 = f3 + li t2, 0 # i = 0 = t2 + add t1, t4, t0 # [(M-1) + n]*8 +for2: + bge t2, t5, for1end # exit inner for if i >= M + sub t3, t1, t2 # [(M-1) + n - i]*8 + add t3, t3, a2 # t3 = offset + &X + fld f0, 0(t3) # X[n-i+(M-1)] + add t3, t2, a3 # t3 = offset + &c + fld f1, 0(t3) # c[i] + fmadd.d f3, f0, f1, f3 # sum += c[i]*X[n-i+(M-1)] + addi t2, t2, 8 # i++ + j for2 +for1end: + add t3, t0, a4 # t3 = offset + &Y + fsd f3, 0(t3) # Y[n] = sum + addi t0, t0, 8 # n++ + j for1 +end: + ret \ No newline at end of file diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile new file mode 100644 index 000000000..18c011f4f --- /dev/null +++ b/examples/C/lab1matrix/Makefile @@ -0,0 +1,33 @@ +TARGET = matMult + +$(TARGET).objdump: $(TARGET) + riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump + spike $(TARGET) + +$(TARGET): $(TARGET).c Makefile + riscv64-unknown-elf-gcc -o $(TARGET) -g -O\ + -march=rv64gc -mabi=lp64d -mcmodel=medany \ + -nostdlib -static -lm -fno-tree-loop-distribute-patterns \ + -T../common/test.ld -I../common \ + $(TARGET).c ../common/crt.S ../common/syscalls.c +# Compiler flags: +# -o $(TARGET) defines the name of the output file +# -g generates debugging symbols for gdb +# -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization +# -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits +# -static forces static linking (no dynamic shared libraries on bare metal) +# -lm links the math library if necessary (when #include math.h) +# -nostdlib avoids inserting standard startup files and default libraries +# because we are using crt.s on bare metal +# -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library +# -T specifies the linker file +# -I specifies the include path (e.g. for util.h) +# The last line defines the C files to compile. +# crt.S is needed as our startup file to initialize the processor +# syscalls.c implements printf through the HTIF for Spike +# other flags from riscv-tests makefiles that don't seem to be important +# -ffast-math -DPREALLOCATE=1 -std=gnu99 \ +# -fno-common -fno-builtin-printf -nostartfiles -lgcc \ + +clean: + rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult new file mode 100755 index 000000000..e3d3b25dd Binary files /dev/null and b/examples/C/lab1matrix/matMult differ diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c new file mode 100644 index 000000000..b794819f9 --- /dev/null +++ b/examples/C/lab1matrix/matMult.c @@ -0,0 +1,87 @@ +// matMult.c +// mmasserfrye@hmc.edu 30 January 2022 + +#include // supports printf +#include // supports fabs +#include "util.h" // supports verify + +// puts the indicated row of length n from matrix mat into array arr +void getRow(int n, int row, double *mat, double *arr){ + int ind; + for (int i=0; i ch5.debug - -ch5: ch5.S Makefile - riscv64-unknown-elf-gcc -nodefaultlibs -nostartfiles -o ch5 ch5.S -# -ffreestanding -# -nostdlib - -clean: - rm -f ch5 ch5.debug \ No newline at end of file diff --git a/examples/asm/ch5/ch5 b/examples/asm/ch5/ch5 deleted file mode 100755 index 3684ea383..000000000 Binary files a/examples/asm/ch5/ch5 and /dev/null differ diff --git a/examples/asm/ch5/ch5.S b/examples/asm/ch5/ch5.S deleted file mode 100644 index cfba56458..000000000 --- a/examples/asm/ch5/ch5.S +++ /dev/null @@ -1,16 +0,0 @@ -# ch5.s -# David_Harris@hmc.edu 14 December 2021 - -.section .text.init - -.globl _start -_start: - lw x1, 4(x0) - sw x1, 8(x0) - add x2, x1, x1 - beq x1, x2, done -loop: - jal x0, loop -done: - -.end diff --git a/examples/asm/ch5/ch5.debug b/examples/asm/ch5/ch5.debug deleted file mode 100644 index 28027a62e..000000000 --- a/examples/asm/ch5/ch5.debug +++ /dev/null @@ -1,38 +0,0 @@ - -ch5: file format elf64-littleriscv - - -Disassembly of section .text: - -0000000000010078 <_start>: - 10078: 00402083 lw ra,4(zero) # 4 <_start-0x10074> - 1007c: 00102423 sw ra,8(zero) # 8 <_start-0x10070> - 10080: 00108133 add sp,ra,ra - 10084: 00208463 beq ra,sp,1008c - -0000000000010088 : - 10088: 0000006f j 10088 - -Disassembly of section .riscv.attributes: - -0000000000000000 <.riscv.attributes>: - 0: 3241 addiw tp,tp,-16 - 2: 0000 unimp - 4: 7200 ld s0,32(a2) - 6: 7369 lui t1,0xffffa - 8: 01007663 bgeu zero,a6,14 <_start-0x10064> - c: 0028 addi a0,sp,8 - e: 0000 unimp - 10: 7205 lui tp,0xfffe1 - 12: 3676 fld fa2,376(sp) - 14: 6934 ld a3,80(a0) - 16: 7032 0x7032 - 18: 5f30 lw a2,120(a4) - 1a: 326d addiw tp,tp,-5 - 1c: 3070 fld fa2,224(s0) - 1e: 615f 7032 5f30 0x5f307032615f - 24: 3266 fld ft4,120(sp) - 26: 3070 fld fa2,224(s0) - 28: 645f 7032 5f30 0x5f307032645f - 2e: 30703263 0x30703263 - ... diff --git a/examples/asm/ch5/example b/examples/asm/ch5/example deleted file mode 100755 index a9b740479..000000000 Binary files a/examples/asm/ch5/example and /dev/null differ diff --git a/examples/asm/trap/Makefile b/examples/asm/trap/Makefile new file mode 100644 index 000000000..6e9f1b47c --- /dev/null +++ b/examples/asm/trap/Makefile @@ -0,0 +1,19 @@ +TARGET = trap + +$(TARGET).objdump: $(TARGET) + riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump + +$(TARGET): $(TARGET).S Makefile + riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64 -mcmodel=medany \ + -nostartfiles -T../../link/link.ld $(TARGET).S + +sim: + spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET) + diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit + echo "Signature matches! Success!" + +clean: + rm -f $(TARGET) $(TARGET).objdump $(TARGET).signature.output + + + diff --git a/examples/asm/trap/trap b/examples/asm/trap/trap new file mode 100755 index 000000000..1d7d3bbc6 Binary files /dev/null and b/examples/asm/trap/trap differ diff --git a/examples/asm/trap/trap.S b/examples/asm/trap/trap.S new file mode 100644 index 000000000..e479f7035 --- /dev/null +++ b/examples/asm/trap/trap.S @@ -0,0 +1,131 @@ +// trap.S +// David_Harris@hmc.edu 11 May 2022 +// +// Demonstrates setting up traps and invoking a trap handler. +// The trap handler accepts timer interrupts and ecalls. +// Saves cause and mtval into the signature +// Ecall takes one argument in a0 +// 0: change privilege mode to user +// 1: change privilege mode to supervisor +// 3: change privilege mode to machine +// 4: exit program with write tohost + +.EQU MTIME, 0x200bff8 +.EQU MTIMECMP, 0x2004000 + +.global rvtest_entry_point + +rvtest_entry_point: + la sp, topofstack # Initialize stack pointer (not used) + la s6, begin_signature # s6 points to signature + + # Set up timer + jal set_timecmp + + # Set up interrupts + la t0, trap_handler + csrw mtvec, t0 # Initialize MTVEC to trap_handler + csrw mideleg, zero # Don't delegate interrupts + csrw medeleg, zero # Don't delegate exceptions + li t0, 0x080 + csrw mie, t0 # Enable machine timer interrupt + la t0, topoftrapstack + csrw mscratch, t0 # MSCRATCH holds trap stack pointer + csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable + +main: + # Change to user mode + li a0, 0 # a0 = 0: argument to enter user mode + ecall # System call to enter user mode + + # Wait for timer interrupts + li t0, 0x1000 # loop counter start value +loop: + addi t0, t0, -1 # decrement counter + bne t0, zero, loop # and repeat until zero + +done: + li a0, 4 # argument to finish program + ecall # system call to finish program + j self_loop # wait forever (not taken) + +set_timecmp: # Set timer compare to 800 ticks later + la t0, MTIME + la t1, MTIMECMP + ld t0, 0(t0) # Read current timer + addi t0, t0, 0x60 # Increment timer + sd t0, 0(t1) # Set MTIMECMP = MTIME + 0x800 + ret + +.align 4 # trap handlers must be aligned to multiple of 4 +trap_handler: + # Load trap handler stack pointer tp + csrrw tp, mscratch, tp # swap MSCRATCH and tp + sd t0, 0(tp) # Save t0 and t1 on the stack + sd t1, -8(tp) + csrr t0, mcause # Check the cause + csrr t1, mtval # And the trap value + sd t0, 0(s6) # Save MCAUSE and MTVAL in the signature + sd t1, 8(s6) + addi s6, s6, 16 + bgez t0, exception # if msb is clear, it is an exception + +interrupt: # must be a timer interrupt + jal set_timecmp # Increment compare for next timer interrupt + j trap_return # clean up and return + +exception: + csrr t1, mepc # add 4 to MEPC to determine return Address + addi t1, t1, 4 + csrw mepc, t1 + li t1, 8 # is it an ecall trap? + andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 + bne t0, t1, trap_return # ignore other exceptions + +ecall: + li t0, 4 + beq a0, t0, write_tohost # call 4: terminate program + bltu a0, t0, changeprivilege # calls 0-3: change privilege level + j trap_return # ignore other ecalls + +changeprivilege: + li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12 + csrc mstatus, t0 + andi a0, a0, 0x003 # only keep bottom two bits of argument + slli a0, a0, 11 # move into mstatus.MPP position + csrs mstatus, a0 # set mstatus.MPP with desired privilege + +trap_return: # return from trap handler + ld t1, -8(tp) # restore t1 and t0 + ld t0, 0(tp) + csrrw tp, mscratch, tp # restore tp + mret # return from trap + +write_tohost: + la t1, tohost + li t0, 1 # 1 for success, 3 for failure + sd t0, 0(t1) # send success code + +self_loop: + j self_loop # wait + +.section .tohost +tohost: # write to HTIF + .dword 0 +fromhost: + .dword 0 + +.EQU XLEN,64 +begin_signature: + .fill 6*(XLEN/32),4,0xdeadbeef # +end_signature: + +# Initialize stack with room for 512 bytes +.bss + .space 512 +topofstack: +# And another stack for the trap handler +.bss + .space 512 +topoftrapstack: + diff --git a/examples/asm/trap/trap.reference_output b/examples/asm/trap/trap.reference_output new file mode 100644 index 000000000..ed4dbe0a9 --- /dev/null +++ b/examples/asm/trap/trap.reference_output @@ -0,0 +1,6 @@ +000000000000000b +0000000000000000 +8000000000000007 +0000000000000000 +0000000000000008 +0000000000000000 diff --git a/examples/fp/fpcalc/fpcalc.c b/examples/fp/fpcalc/fpcalc.c index f41494c70..94bfc9ac1 100644 --- a/examples/fp/fpcalc/fpcalc.c +++ b/examples/fp/fpcalc/fpcalc.c @@ -157,7 +157,7 @@ void softfloatInit(void) { // RM: softfloat_round_min softfloat_roundingMode = softfloat_round_near_even; softfloat_exceptionFlags = 0; // clear exceptions - softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess + softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess } uint64_t parseNum(char *num) { diff --git a/examples/fp/softfloat_demo/softfloat_demo.c b/examples/fp/softfloat_demo/softfloat_demo.c index 918682ba2..0f7ba6f00 100644 --- a/examples/fp/softfloat_demo/softfloat_demo.c +++ b/examples/fp/softfloat_demo/softfloat_demo.c @@ -37,7 +37,7 @@ void softfloatInit(void) { // RM: softfloat_round_min softfloat_roundingMode = softfloat_round_near_even; softfloat_exceptionFlags = 0; // clear exceptions - softfloat_detectTininess = softfloat_tininess_beforeRounding; // RISC-V behavior for tininess + softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess } int main() diff --git a/pipelined/src/fma/Makefile b/examples/verilog/fma/Makefile similarity index 100% rename from pipelined/src/fma/Makefile rename to examples/verilog/fma/Makefile diff --git a/pipelined/src/fma/baby_torture.tv b/examples/verilog/fma/baby_torture.tv similarity index 100% rename from pipelined/src/fma/baby_torture.tv rename to examples/verilog/fma/baby_torture.tv diff --git a/pipelined/src/fma/baby_torture_rz.tv b/examples/verilog/fma/baby_torture_rz.tv similarity index 100% rename from pipelined/src/fma/baby_torture_rz.tv rename to examples/verilog/fma/baby_torture_rz.tv diff --git a/pipelined/src/fma/fma.do b/examples/verilog/fma/fma.do similarity index 100% rename from pipelined/src/fma/fma.do rename to examples/verilog/fma/fma.do diff --git a/pipelined/src/fma/fma16.v b/examples/verilog/fma/fma16.v similarity index 100% rename from pipelined/src/fma/fma16.v rename to examples/verilog/fma/fma16.v diff --git a/pipelined/src/fma/fma16_template.v b/examples/verilog/fma/fma16_template.v similarity index 100% rename from pipelined/src/fma/fma16_template.v rename to examples/verilog/fma/fma16_template.v diff --git a/pipelined/src/fma/fma16_testgen.c b/examples/verilog/fma/fma16_testgen.c similarity index 100% rename from pipelined/src/fma/fma16_testgen.c rename to examples/verilog/fma/fma16_testgen.c diff --git a/pipelined/src/fma/lint-fma b/examples/verilog/fma/lint-fma similarity index 100% rename from pipelined/src/fma/lint-fma rename to examples/verilog/fma/lint-fma diff --git a/pipelined/src/fma/sim-fma b/examples/verilog/fma/sim-fma similarity index 100% rename from pipelined/src/fma/sim-fma rename to examples/verilog/fma/sim-fma diff --git a/pipelined/src/fma/sim-fma-batch b/examples/verilog/fma/sim-fma-batch similarity index 100% rename from pipelined/src/fma/sim-fma-batch rename to examples/verilog/fma/sim-fma-batch diff --git a/pipelined/src/fma/synth b/examples/verilog/fma/synth similarity index 100% rename from pipelined/src/fma/synth rename to examples/verilog/fma/synth diff --git a/pipelined/src/fma/testbench.v b/examples/verilog/fma/testbench.v similarity index 100% rename from pipelined/src/fma/testbench.v rename to examples/verilog/fma/testbench.v diff --git a/pipelined/src/fma/torture.tv b/examples/verilog/fma/torture.tv similarity index 100% rename from pipelined/src/fma/torture.tv rename to examples/verilog/fma/torture.tv diff --git a/pipelined/src/fma/torturegen.pl b/examples/verilog/fma/torturegen.pl similarity index 100% rename from pipelined/src/fma/torturegen.pl rename to examples/verilog/fma/torturegen.pl diff --git a/examples/verilog/fma/wave.do b/examples/verilog/fma/wave.do new file mode 100644 index 000000000..040248f64 --- /dev/null +++ b/examples/verilog/fma/wave.do @@ -0,0 +1,62 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench_fma16/clk +add wave -noupdate /testbench_fma16/reset +add wave -noupdate /testbench_fma16/x +add wave -noupdate /testbench_fma16/y +add wave -noupdate /testbench_fma16/z +add wave -noupdate /testbench_fma16/result +add wave -noupdate /testbench_fma16/rexpected +add wave -noupdate /testbench_fma16/dut/x +add wave -noupdate /testbench_fma16/dut/y +add wave -noupdate /testbench_fma16/dut/z +add wave -noupdate /testbench_fma16/dut/mul +add wave -noupdate /testbench_fma16/dut/add +add wave -noupdate /testbench_fma16/dut/negr +add wave -noupdate /testbench_fma16/dut/negz +add wave -noupdate /testbench_fma16/dut/roundmode +add wave -noupdate /testbench_fma16/dut/result +add wave -noupdate /testbench_fma16/dut/XManE +add wave -noupdate /testbench_fma16/dut/YManE +add wave -noupdate /testbench_fma16/dut/ZManE +add wave -noupdate /testbench_fma16/dut/XExpE +add wave -noupdate /testbench_fma16/dut/YExpE +add wave -noupdate /testbench_fma16/dut/ZExpE +add wave -noupdate /testbench_fma16/dut/PExpE +add wave -noupdate /testbench_fma16/dut/Ne +add wave -noupdate /testbench_fma16/dut/upOneExt +add wave -noupdate /testbench_fma16/dut/XSgnE +add wave -noupdate /testbench_fma16/dut/YSgnE +add wave -noupdate /testbench_fma16/dut/ZSgnE +add wave -noupdate /testbench_fma16/dut/PSgnE +add wave -noupdate /testbench_fma16/dut/ProdManE +add wave -noupdate /testbench_fma16/dut/NfracS +add wave -noupdate /testbench_fma16/dut/ProdManAl +add wave -noupdate /testbench_fma16/dut/ZManExt +add wave -noupdate /testbench_fma16/dut/ZManAl +add wave -noupdate /testbench_fma16/dut/Nfrac +add wave -noupdate /testbench_fma16/dut/res +add wave -noupdate -radix decimal /testbench_fma16/dut/AlignCnt +add wave -noupdate /testbench_fma16/dut/NSamt +add wave -noupdate /testbench_fma16/dut/ZExpGreater +add wave -noupdate /testbench_fma16/dut/ACLess +add wave -noupdate /testbench_fma16/dut/upOne +add wave -noupdate /testbench_fma16/dut/KillProd +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {3746 ns} 1} {{Cursor 2} {4169 ns} 0} +quietly wave cursor active 2 +configure wave -namecolwidth 237 +configure wave -valuecolwidth 64 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {4083 ns} {4235 ns} diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc index 378398899..de0afcaeb 100644 --- a/fpga/constraints/debug2.xdc +++ b/fpga/constraints/debug2.xdc @@ -95,22 +95,29 @@ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe19] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19] connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SCAUSE_REGW[63]} ]] + + create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe20] +set_property port_width 5 [get_debug_ports u_ila_0/probe20] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20] -connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/SEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe21] +set_property port_width 8 [get_debug_ports u_ila_0/probe21] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21] -connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9]} ]] +connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe22] +set_property port_width 64 [get_debug_ports u_ila_0/probe22] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22] -connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9]} ]] +connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] + + create_debug_port u_ila_0 probe set_property port_width 63 [get_debug_ports u_ila_0/probe23] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23] -connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/STVEC_REGW[63]} ]] +connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/STVEC_REGW[63]} ]] + create_debug_port u_ila_0 probe set_property port_width 4 [get_debug_ports u_ila_0/probe24] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24] @@ -123,10 +130,12 @@ create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe26] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26] connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/PendingIntsM[11]} ]] + create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe27] +set_property port_width 4 [get_debug_ports u_ila_0/probe27] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27] -connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/core/priv.priv/trap/MEPC_REGW[63]} ]] +connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]] + create_debug_port u_ila_0 probe set_property port_width 6 [get_debug_ports u_ila_0/probe28] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28] @@ -318,7 +327,7 @@ connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/core/hzu/BP create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe73] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73] -connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWritePendingDEM ]] +connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/core/hzu/CSRWriteFencePendingDEM ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe74] @@ -393,7 +402,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/core/hzu/Br create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe88] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88] -connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/core/hzu/InvalidateICacheM ]] +connect_debug_port u_ila_0/probe88 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe89] @@ -424,7 +433,8 @@ connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/core/hzu/St create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe94] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94] -connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/core/hzu/FlushF ]] +connect_debug_port u_ila_0/probe94 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RXerrIP} ]] + create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe95] @@ -526,9 +536,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113] connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/core/ebu/HPROT[0]} {wallypipelinedsoc/core/ebu/HPROT[1]} {wallypipelinedsoc/core/ebu/HPROT[2]} {wallypipelinedsoc/core/ebu/HPROT[3]}]] create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe114] +set_property port_width 4 [get_debug_ports u_ila_0/probe114] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114] -connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/core/ebu/HMASTLOCK}]] +connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe115] @@ -633,82 +643,76 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe133] connect_debug_port u_ila_0/probe133 [get_nets [list {wallypipelinedsoc/core/ifu/PCNextF[0]} {wallypipelinedsoc/core/ifu/PCNextF[1]} {wallypipelinedsoc/core/ifu/PCNextF[2]} {wallypipelinedsoc/core/ifu/PCNextF[3]} {wallypipelinedsoc/core/ifu/PCNextF[4]} {wallypipelinedsoc/core/ifu/PCNextF[5]} {wallypipelinedsoc/core/ifu/PCNextF[6]} {wallypipelinedsoc/core/ifu/PCNextF[7]} {wallypipelinedsoc/core/ifu/PCNextF[8]} {wallypipelinedsoc/core/ifu/PCNextF[9]} {wallypipelinedsoc/core/ifu/PCNextF[10]} {wallypipelinedsoc/core/ifu/PCNextF[11]} {wallypipelinedsoc/core/ifu/PCNextF[12]} {wallypipelinedsoc/core/ifu/PCNextF[13]} {wallypipelinedsoc/core/ifu/PCNextF[14]} {wallypipelinedsoc/core/ifu/PCNextF[15]} {wallypipelinedsoc/core/ifu/PCNextF[16]} {wallypipelinedsoc/core/ifu/PCNextF[17]} {wallypipelinedsoc/core/ifu/PCNextF[18]} {wallypipelinedsoc/core/ifu/PCNextF[19]} {wallypipelinedsoc/core/ifu/PCNextF[20]} {wallypipelinedsoc/core/ifu/PCNextF[21]} {wallypipelinedsoc/core/ifu/PCNextF[22]} {wallypipelinedsoc/core/ifu/PCNextF[23]} {wallypipelinedsoc/core/ifu/PCNextF[24]} {wallypipelinedsoc/core/ifu/PCNextF[25]} {wallypipelinedsoc/core/ifu/PCNextF[26]} {wallypipelinedsoc/core/ifu/PCNextF[27]} {wallypipelinedsoc/core/ifu/PCNextF[28]} {wallypipelinedsoc/core/ifu/PCNextF[29]} {wallypipelinedsoc/core/ifu/PCNextF[30]} {wallypipelinedsoc/core/ifu/PCNextF[31]} {wallypipelinedsoc/core/ifu/PCNextF[32]} {wallypipelinedsoc/core/ifu/PCNextF[33]} {wallypipelinedsoc/core/ifu/PCNextF[34]} {wallypipelinedsoc/core/ifu/PCNextF[35]} {wallypipelinedsoc/core/ifu/PCNextF[36]} {wallypipelinedsoc/core/ifu/PCNextF[37]} {wallypipelinedsoc/core/ifu/PCNextF[38]} {wallypipelinedsoc/core/ifu/PCNextF[39]} {wallypipelinedsoc/core/ifu/PCNextF[40]} {wallypipelinedsoc/core/ifu/PCNextF[41]} {wallypipelinedsoc/core/ifu/PCNextF[42]} {wallypipelinedsoc/core/ifu/PCNextF[43]} {wallypipelinedsoc/core/ifu/PCNextF[44]} {wallypipelinedsoc/core/ifu/PCNextF[45]} {wallypipelinedsoc/core/ifu/PCNextF[46]} {wallypipelinedsoc/core/ifu/PCNextF[47]} {wallypipelinedsoc/core/ifu/PCNextF[48]} {wallypipelinedsoc/core/ifu/PCNextF[49]} {wallypipelinedsoc/core/ifu/PCNextF[50]} {wallypipelinedsoc/core/ifu/PCNextF[51]} {wallypipelinedsoc/core/ifu/PCNextF[52]} {wallypipelinedsoc/core/ifu/PCNextF[53]} {wallypipelinedsoc/core/ifu/PCNextF[54]} {wallypipelinedsoc/core/ifu/PCNextF[55]} {wallypipelinedsoc/core/ifu/PCNextF[56]} {wallypipelinedsoc/core/ifu/PCNextF[57]} {wallypipelinedsoc/core/ifu/PCNextF[58]} {wallypipelinedsoc/core/ifu/PCNextF[59]} {wallypipelinedsoc/core/ifu/PCNextF[60]} {wallypipelinedsoc/core/ifu/PCNextF[61]} {wallypipelinedsoc/core/ifu/PCNextF[62]} {wallypipelinedsoc/core/ifu/PCNextF[63]}]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe134] +set_property port_width 8 [get_debug_ports u_ila_0/probe134] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe134] -connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[0]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[1]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[2]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[3]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[4]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[5]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[6]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[7]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[8]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[9]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[10]} {wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11]} ]] +connect_debug_port u_ila_0/probe134 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe135] +set_property port_width 8 [get_debug_ports u_ila_0/probe135] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe135] -connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]] +connect_debug_port u_ila_0/probe135 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe136] +set_property port_width 8 [get_debug_ports u_ila_0/probe136] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe136] -connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]] +connect_debug_port u_ila_0/probe136 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe137] +set_property port_width 8 [get_debug_ports u_ila_0/probe137] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137] -connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]] +connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]] create_debug_port u_ila_0 probe -set_property port_width 12 [get_debug_ports u_ila_0/probe138] +set_property port_width 2 [get_debug_ports u_ila_0/probe138] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138] -connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]] - +connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe139] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139] -connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]] +connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtInt}]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe140] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140] -connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]] +connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe141] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141] -connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]] +connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MTimerInt} ]] create_debug_port u_ila_0 probe set_property port_width 1 [get_debug_ports u_ila_0/probe142] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142] -connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]] - +connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MSwInt} ]] create_debug_port u_ila_0 probe -set_property port_width 70 [get_debug_ports u_ila_0/probe143] +set_property port_width 11 [get_debug_ports u_ila_0/probe143] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143] -connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]] +connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]] create_debug_port u_ila_0 probe -set_property port_width 3 [get_debug_ports u_ila_0/probe144] +set_property port_width 1 [get_debug_ports u_ila_0/probe144] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144] -connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]] +connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]] create_debug_port u_ila_0 probe -set_property port_width 10 [get_debug_ports u_ila_0/probe145] +set_property port_width 2 [get_debug_ports u_ila_0/probe145] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145] -connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]] - +connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]] create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe146] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146] connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]] - - create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe147] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147] connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]] - - create_debug_port u_ila_0 probe set_property port_width 12 [get_debug_ports u_ila_0/probe148] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148] @@ -744,75 +748,75 @@ set_property port_width 64 [get_debug_ports u_ila_0/probe154] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154] connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]] - create_debug_port u_ila_0 probe -set_property port_width 11 [get_debug_ports u_ila_0/probe155] +set_property port_width 8 [get_debug_ports u_ila_0/probe155] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155] -connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]] +connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]] + create_debug_port u_ila_0 probe -set_property port_width 1 [get_debug_ports u_ila_0/probe156] +set_property port_width 12 [get_debug_ports u_ila_0/probe156] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156] -connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]] - +connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/requests[1]} {wallypipelinedsoc/uncore/plic.plic/requests[2]} {wallypipelinedsoc/uncore/plic.plic/requests[3]} {wallypipelinedsoc/uncore/plic.plic/requests[4]} {wallypipelinedsoc/uncore/plic.plic/requests[5]} {wallypipelinedsoc/uncore/plic.plic/requests[6]} {wallypipelinedsoc/uncore/plic.plic/requests[7]} {wallypipelinedsoc/uncore/plic.plic/requests[8]} {wallypipelinedsoc/uncore/plic.plic/requests[9]} {wallypipelinedsoc/uncore/plic.plic/requests[10]} {wallypipelinedsoc/uncore/plic.plic/requests[11]} {wallypipelinedsoc/uncore/plic.plic/requests[12]}]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe157] +set_property port_width 12 [get_debug_ports u_ila_0/probe157] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157] -connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]] - +connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intInProgress[1]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[2]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[3]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[4]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[5]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[6]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[7]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[8]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[9]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[10]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[11]} {wallypipelinedsoc/uncore/plic.plic/intInProgress[12]}]] + create_debug_port u_ila_0 probe -set_property port_width 2 [get_debug_ports u_ila_0/probe158] +set_property port_width 12 [get_debug_ports u_ila_0/probe158] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158] -connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]] +connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe159] +set_property port_width 70 [get_debug_ports u_ila_0/probe159] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159] -connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]] +connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe160] +set_property port_width 3 [get_debug_ports u_ila_0/probe160] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160] -connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]] - +connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]] + create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe161] +set_property port_width 10 [get_debug_ports u_ila_0/probe161] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161] -connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]] +connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe162] +set_property port_width 3 [get_debug_ports u_ila_0/probe162] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162] -connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]] +connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/intrID[0]} {wallypipelinedsoc/uncore/uart.uart/u/intrID[1]} {wallypipelinedsoc/uncore/uart.uart/u/intrID[2]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe163] +set_property port_width 1 [get_debug_ports u_ila_0/probe163] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163] -connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]] +connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxdataavailintr} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe164] +set_property port_width 1 [get_debug_ports u_ila_0/probe164] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164] -connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]] +connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/fifoenabled} ]] create_debug_port u_ila_0 probe -set_property port_width 4 [get_debug_ports u_ila_0/probe165] +set_property port_width 1 [get_debug_ports u_ila_0/probe165] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165] -connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]] +connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifotriggered} ]] create_debug_port u_ila_0 probe -set_property port_width 5 [get_debug_ports u_ila_0/probe166] +set_property port_width 4 [get_debug_ports u_ila_0/probe166] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166] -connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]] +connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[1]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[2]} {wallypipelinedsoc/uncore/uart.uart/u/rxfifoentries[3]} ]] create_debug_port u_ila_0 probe -set_property port_width 8 [get_debug_ports u_ila_0/probe167] +set_property port_width 1 [get_debug_ports u_ila_0/probe167] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167] -connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]] +connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxdataready} ]] create_debug_port u_ila_0 probe -set_property port_width 64 [get_debug_ports u_ila_0/probe168] +set_property port_width 1 [get_debug_ports u_ila_0/probe168] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168] connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]] @@ -820,3 +824,4 @@ create_debug_port u_ila_0 probe set_property port_width 64 [get_debug_ports u_ila_0/probe169] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe169] connect_debug_port u_ila_0/probe169 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[0]__0[63]}]] + diff --git a/linux/testvector-generation/debug.sh b/linux/testvector-generation/debug.sh index 748f6e023..7ca3e9b15 100755 --- a/linux/testvector-generation/debug.sh +++ b/linux/testvector-generation/debug.sh @@ -4,18 +4,18 @@ tvDir=$RISCV/linux-testvectors tcpPort=1239 # QEMU Simulation -(qemu-system-riscv64 \ +qemu-system-riscv64 \ -M virt -dtb $imageDir/wally-virt.dtb \ -nographic \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ --singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on \ -> ./qemu-serial \ --gdb tcp::$tcpPort -S) \ -& riscv64-unknown-elf-gdb -quiet \ --ex "set pagination off" \ --ex "set logging overwrite on" \ --ex "set logging redirect on" \ --ex "set confirm off" \ --ex "target extended-remote :$tcpPort" \ --ex "maintenance packet Qqemu.PhyMemMode:1" \ --ex "file $imageDir/vmlinux" +-singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on +# > ./qemu-serial \ +# -gdb tcp::$tcpPort -S) \ +# & riscv64-unknown-elf-gdb -quiet \ +# -ex "set pagination off" \ +# -ex "set logging overwrite on" \ +# -ex "set logging redirect on" \ +# -ex "set confirm off" \ +# -ex "target extended-remote :$tcpPort" \ +# -ex "maintenance packet Qqemu.PhyMemMode:1" \ +# -ex "file $imageDir/vmlinux" diff --git a/pipelined/config/buildroot/BTBPredictor.txt b/pipelined/config/buildroot/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/buildroot/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/buildroot/twoBitPredictor.txt b/pipelined/config/buildroot/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/buildroot/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 1419cca90..383cab5b1 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -63,10 +63,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -124,13 +124,10 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/fpga/BTBPredictor.txt b/pipelined/config/fpga/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/fpga/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/fpga/twoBitPredictor.txt b/pipelined/config/fpga/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/fpga/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 83561e3e4..2d349c8d9 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -65,10 +65,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -141,5 +141,4 @@ `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/rv32e/BTBPredictor.txt b/pipelined/config/rv32e/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32e/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32e/twoBitPredictor.txt b/pipelined/config/rv32e/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32e/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index c849fc4ee..4160957b6 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -66,10 +66,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -130,12 +130,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/BTBPredictor.txt b/pipelined/config/rv32gc/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32gc/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32gc/twoBitPredictor.txt b/pipelined/config/rv32gc/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32gc/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 7cadca0bc..f15f15a33 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -64,10 +64,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -128,12 +128,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32i/BTBPredictor.txt b/pipelined/config/rv32i/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32i/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32i/twoBitPredictor.txt b/pipelined/config/rv32i/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32i/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index cb56b6b85..001157a13 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -66,10 +66,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -130,13 +130,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32i/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/BTBPredictor.txt b/pipelined/config/rv32ic/BTBPredictor.txt deleted file mode 100644 index fd3eedffb..000000000 --- a/pipelined/config/rv32ic/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 -000000000000000000000000000000000000 diff --git a/pipelined/config/rv32ic/twoBitPredictor.txt b/pipelined/config/rv32ic/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv32ic/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index ccdd3cb9e..4fcffd73c 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -64,10 +64,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -128,13 +128,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/BTBPredictor.txt b/pipelined/config/rv64BP/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/rv64BP/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/rv64BP/twoBitPredictor.txt b/pipelined/config/rv64BP/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv64BP/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 06525ec01..53ca026ce 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -66,10 +66,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 @@ -130,14 +130,10 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt" `define BPRED_ENABLED 1 //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE `define TESTSBP 1 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fp/BTBPredictor.txt b/pipelined/config/rv64fp/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/rv64fp/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/rv64fp/twoBitPredictor.txt b/pipelined/config/rv64fp/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv64fp/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 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-00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index c6f80d497..bf0831d14 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -32,13 +32,14 @@ `define DESIGN_COMPILER 0 // RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 +`define XLEN 32 // IEEE 754 compliance -`define IEEE754 1 +`define IEEE754 0 // MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +// ZYXWVUTSRQPONMLKJIHGFEDCBA +`define MISA 32'b0000000000101000001000100101101 `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 @@ -51,9 +52,11 @@ `define UARCH_SINGLECYCLE 0 `define DMEM `MEM_CACHE `define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 0 +`define BIGENDIAN_SUPPORTED 1 // TLB configuration. Entries should be a power of 2 `define ITLB_ENTRIES 32 @@ -63,10 +66,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -81,13 +84,13 @@ // Bus Interface width `define AHBW 64 +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 16 + // Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder @@ -129,13 +132,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 - -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh new file mode 100644 index 000000000..eb8b02662 --- /dev/null +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -0,0 +1,139 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// include shared configuration +`include "wally-shared.vh" + +`define FPGA 0 +`define QEMU 0 +`define DESIGN_COMPILER 0 + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +// IEEE 754 compliance +`define IEEE754 0 + +// MISA RISC-V configuration per specification +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) +`define ZICSR_SUPPORTED 1 +`define ZIFENCEI_SUPPORTED 1 +`define COUNTERS 32 +`define ZICOUNTERS_SUPPORTED 1 +`define ZFH_SUPPORTED 1 + +/// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define DMEM `MEM_CACHE +`define IMEM `MEM_CACHE +`define DBUS 1 +`define IBUS 1 +`define VIRTMEM_SUPPORTED 1 +`define VECTORED_INTERRUPTS_SUPPORTED 1 +`define BIGENDIAN_SUPPORTED 1 + +// TLB configuration. Entries should be a power of 2 +`define ITLB_ENTRIES 32 +`define DTLB_ENTRIES 32 + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +`define DCACHE_NUMWAYS 4 +`define DCACHE_WAYSIZEINBYTES 4096 +`define DCACHE_LINELENINBITS 512 +`define ICACHE_NUMWAYS 4 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_LINELENINBITS 512 + +// Integer Divider Configuration +// DIV_BITSPERCYCLE must be 1, 2, or 4 +`define DIV_BITSPERCYCLE 4 + +// Legal number of PMP entries are 0, 16, or 64 +`define PMP_ENTRIES 64 + +// Address space +`define RESET_VECTOR 64'h0000000080000000 + +// Bus Interface width +`define AHBW 64 + +// WFI Timeout Wait +`define WFI_TIMEOUT_BIT 16 + +// Peripheral Physiccal Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +`define BOOTROM_SUPPORTED 1'b1 +`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder +`define BOOTROM_RANGE 56'h00000FFF +`define RAM_SUPPORTED 1'b1 +`define RAM_BASE 56'h80000000 +`define RAM_RANGE 56'h7FFFFFFF +`define EXT_MEM_SUPPORTED 1'b0 +`define EXT_MEM_BASE 56'h80000000 +`define EXT_MEM_RANGE 56'h07FFFFFF +`define CLINT_SUPPORTED 1'b1 +`define CLINT_BASE 56'h02000000 +`define CLINT_RANGE 56'h0000FFFF +`define GPIO_SUPPORTED 1'b1 +`define GPIO_BASE 56'h10060000 +`define GPIO_RANGE 56'h000000FF +`define UART_SUPPORTED 1'b1 +`define UART_BASE 56'h10000000 +`define UART_RANGE 56'h00000007 +`define PLIC_SUPPORTED 1'b1 +`define PLIC_BASE 56'h0C000000 +`define PLIC_RANGE 56'h03FFFFFF +`define SDC_SUPPORTED 1'b0 +`define SDC_BASE 56'h00012100 +`define SDC_RANGE 56'h0000001F + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 1 + +// Hardware configuration +`define UART_PRESCALE 1 + +// Interrupt configuration +`define PLIC_NUM_SRC 10 +// comment out the following if >=32 sources +`define PLIC_NUM_SRC_LT_32 +`define PLIC_GPIO_ID 3 +`define PLIC_UART_ID 10 + +`define BPRED_ENABLED 1 +`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define TESTSBP 0 +`define BPRED_SIZE 10 + +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/BTBPredictor.txt b/pipelined/config/rv64gc/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/rv64gc/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/rv64gc/twoBitPredictor.txt b/pipelined/config/rv64gc/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv64gc/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 35b74c6d2..19750d6be 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -65,10 +65,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -131,12 +131,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64i/BTBPredictor.txt b/pipelined/config/rv64i/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/rv64i/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/rv64i/twoBitPredictor.txt b/pipelined/config/rv64i/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv64i/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index b9b2e0f6e..99c70cd68 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -65,10 +65,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -131,12 +131,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64i/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/BTBPredictor.txt b/pipelined/config/rv64ic/BTBPredictor.txt deleted file mode 100644 index b761147c6..000000000 --- a/pipelined/config/rv64ic/BTBPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 -00000000000000000000000000000000000000000000000000000000000000000000 diff --git a/pipelined/config/rv64ic/twoBitPredictor.txt b/pipelined/config/rv64ic/twoBitPredictor.txt deleted file mode 100644 index ff57bd473..000000000 --- a/pipelined/config/rv64ic/twoBitPredictor.txt +++ /dev/null @@ -1,1024 +0,0 @@ -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 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-00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 -00 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index fc77b8484..a31a555a5 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -65,10 +65,10 @@ // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines `define DCACHE_NUMWAYS 4 `define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 256 +`define DCACHE_LINELENINBITS 512 `define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 256 +`define ICACHE_LINELENINBITS 512 // Integer Divider Configuration // DIV_BITSPERCYCLE must be 1, 2, or 4 @@ -131,12 +131,9 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 -`define REPLAY 0 `define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 1538c5214..1f05a4f13 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -51,42 +51,74 @@ `define PMPCFG_ENTRIES (`PMP_ENTRIES/8) // Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 128 -`define Q_NE 15 -`define Q_NF 112 -`define Q_BIAS 16383 -`define D_LEN 64 -`define D_NE 11 -`define D_NF 52 -`define D_BIAS 1023 -`define S_LEN 32 -`define S_NE 8 -`define S_NF 23 -`define S_BIAS 127 -`define H_LEN 16 -`define H_NE 5 -`define H_NF 10 -`define H_BIAS 15 +`define Q_LEN 32'd128 +`define Q_NE 32'd15 +`define Q_NF 32'd112 +`define Q_BIAS 32'd16383 +`define Q_FMT 2'd3 +`define D_LEN 32'd64 +`define D_NE 32'd11 +`define D_NF 32'd52 +`define D_BIAS 32'd1023 +`define D_FMT 2'd1 +`define S_LEN 32'd32 +`define S_NE 32'd8 +`define S_NF 32'd23 +`define S_BIAS 32'd127 +`define S_FMT 2'd0 +`define H_LEN 32'd16 +`define H_NE 32'd5 +`define H_NF 32'd10 +`define H_BIAS 32'd15 +`define H_FMT 2'd2 // Floating point length FLEN and number of exponent (NE) and fraction (NF) bits `define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) `define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) `define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 3 : `D_SUPPORTED ? 1 : `F_SUPPORTED ? 0 : 2) +`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) `define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS) // Floating point constants needed for FPU paramerterization -`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0 : 2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) +`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) +`define FMTBITS ((32)'(`FPSIZES>=3)+1) +`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) +`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) +`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) +`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) `define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0 : 2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) +`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) +`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) +`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) + +// largest length in IEU/FPU +`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) +`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) +`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) +`define NORMSHIFTSZ ((`QLEN+`NF+1) > (3*`NF+8) ? (`QLEN+`NF+1) : (3*`NF+8)) +`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6)) + +// division constants +`define RADIX 32'h2 +`define DIVCOPIES 32'h1 +`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3)) +// `define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input +`define DIVN (`NF < `XLEN ? `XLEN : `NF+3) // length of input +`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 3) +`define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN + 3)) +`define DIVRESLEN ((`NF>`XLEN) ? `NF+4 : `XLEN) +`define LOGR ((`RADIX==2) ? 32'h1 : 32'h2) +// FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES)) +// one interation is required for the integer bit for minimally redundent radix-4 +`define FPDUR ((`DIVN+2+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4)) +`define DURLEN ($clog2(`FPDUR+1)) +`define QLEN (`FPDUR*`LOGR*`DIVCOPIES) +`define DIVb (`FPDUR*`LOGR*`DIVCOPIES)-1 + + +`define USE_SRAM 0 // Disable spurious Verilator warnings diff --git a/pipelined/regression/Makefile b/pipelined/regression/Makefile index 302ee4a92..f15013280 100644 --- a/pipelined/regression/Makefile +++ b/pipelined/regression/Makefile @@ -1,30 +1,9 @@ -make allclean: - make clean - make all - -make clean: - make clean -C ../../addins/riscv-arch-test - make clean -C ../../tests/wally-riscv-arch-test -# make allclean -C ../../tests/imperas-riscv-tests - -make all: +all: riscoftests memfiles # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired #make -C ../../tests/imperas-riscv-tests --jobs #make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs - - # Build riscv-arch-test 64 and 32-bit versions - make -C ../../addins/riscv-arch-test --jobs - make -C ../../addins/riscv-arch-test XLEN=32 --jobs - - # Build wally-riscv-arch-test - make -C ../../tests/wally-riscv-arch-test/ --jobs - make -C ../../tests/wally-riscv-arch-test/ XLEN=32 --jobs - -# build the memfiles and address files. - make -f makefile-memfile wally-sim-files --jobs - # Only compile Imperas tests if they are installed locally. # They are usually a symlink to $RISCV/imperas-riscv-tests and only # get compiled there manually during installation @@ -36,4 +15,19 @@ make all: # Link Linux test vectors (fix this later***) #cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh - +allclean: clean all + +clean: + make clean -C ../../tests/riscof +# make clean -C ../../tests/wally-riscv-arch-test +# make allclean -C ../../tests/imperas-riscv-tests + +riscoftests: +# Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions + make -C ../../tests/riscof/ +# make -C ../../tests/riscof/ XLEN=32 +# make -C ../../tests/riscof/ XLEN=32 build_rv32e +# make -C ../../tests/riscof/ XLEN=64 + +memfiles: + make -f makefile-memfile wally-sim-files --jobs diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 564973a39..750486c4e 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic ; do +for config in rv32e rv64gc rv32gc rv32ic rv64fpquad; do echo "$config linting..." if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then echo "Exiting after $config lint due to errors or warnings" diff --git a/pipelined/regression/linux-wave.do b/pipelined/regression/linux-wave.do index 62de1e0d2..10f98251e 100644 --- a/pipelined/regression/linux-wave.do +++ b/pipelined/regression/linux-wave.do @@ -11,11 +11,9 @@ add wave -noupdate -expand -group Testbench /testbench/interruptEpcVal add wave -noupdate -expand -group Testbench /testbench/interruptTVal add wave -noupdate -expand -group Testbench /testbench/interruptDesc add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/ExceptionM @@ -56,26 +54,25 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE -add wave -noupdate -group {Execution Stage} /testbench/MepcExpected add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {Execution Stage} /testbench/InstrEName add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -group {Execution Stage} /testbench/textE add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/checkInstrM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -group {Memory Stage} /testbench/ExpectedPCM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/textM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW -add wave -noupdate -group {WriteBack stage} /testbench/PCW -add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW -add wave -noupdate -group {WriteBack stage} /testbench/InstrW -add wave -noupdate -group {WriteBack stage} /testbench/InstrWName -add wave -noupdate -group {WriteBack stage} /testbench/textW +add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/textM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW +add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW +add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName +add wave -noupdate -expand -group {WriteBack stage} /testbench/textW add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} @@ -196,203 +193,202 @@ add wave -noupdate -group ifu -expand -group icache -expand -group memory /testb add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUPAdrM -add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData[69]} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V -add wave -noupdate -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead -add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUPAdrM +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr +add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA +add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status -color Maroon /testbench/dut/core/lsu/dmmu/dmmu/DAPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/UpperBitsUnequalPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead +add wave -noupdate -expand -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite +add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/ITLBMissOrDAFaultF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM @@ -424,55 +420,14 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb @@ -486,11 +441,6 @@ add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM @@ -517,7 +467,7 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {2240751 ns} 0} +WaveRestoreCursors {{Cursor 4} {87475 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 @@ -533,4 +483,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {2240730 ns} {2240764 ns} +WaveRestoreZoom {87386 ns} {87672 ns} diff --git a/pipelined/regression/make-tests.sh b/pipelined/regression/make-tests.sh index c5d3644d6..fe4555ff2 100755 --- a/pipelined/regression/make-tests.sh +++ b/pipelined/regression/make-tests.sh @@ -1,14 +1,16 @@ #!/bin/bash rm -r work* -cd ../../tests/imperas-riscv-tests/ make allclean make -cd ../wally-riscv-arch-test -make allclean -make -make XLEN=32 -exe2memfile.pl work/*/*/*.elf -cd ../linux-testgen/linux-testvectors -./tvLinker.sh -cd ../../../pipelined/regression +# cd ../../tests/imperas-riscv-tests/ +# make allclean +# make +# cd ../wally-riscv-arch-test +# make allclean +# make +# make XLEN=32 +# exe2memfile.pl work/*/*/*.elf +# cd ../linux-testgen/linux-testvectors +# ./tvLinker.sh +# cd ../../../pipelined/regression diff --git a/pipelined/regression/makefile-memfile b/pipelined/regression/makefile-memfile index 33af19538..d41af90c9 100644 --- a/pipelined/regression/makefile-memfile +++ b/pipelined/regression/makefile-memfile @@ -1,6 +1,6 @@ ROOT := ../.. SUFFIX := work -ARCHDIR := $(ROOT)/addins/riscv-arch-test +ARCHDIR := $(ROOT)/tests/riscof WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test # IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests # ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) $(IMPERASDIR)/$(SUFFIX) @@ -8,8 +8,9 @@ IMPERASDIR := $(ROOT)/tests/imperas-riscv-tests ALLDIRS := $(ARCHDIR)/$(SUFFIX) $(WALLYDIR)/$(SUFFIX) ELFFILES ?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf") +OBJDUMPFILES ?= $(shell find $(ALLDIRS) -type f -regex ".*\.elf.objdump") MEMFILES ?= $(ELFFILES:.elf=.elf.memfile) -ADDRFILES ?= $(ELFFILES:.elf=.elf.objdump.addr) +ADDRFILES ?= $(OBJDUMPFILES:.objdump=.objdump.addr) print: echo "files in $(ALLDIRS) are $(ELFFILES)." @@ -18,7 +19,7 @@ print: .PHONY: all wally-sim-files all: wally-sim-files -wally-sim-files: $(MEMFILES) $(ADDRFILES) +wally-sim-files: $(MEMFILES) $(ADDRFILES) echo "$@" # notes to self on how this works. diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index d98d59368..c86f19535 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -40,20 +40,22 @@ configs = [ TestCase( name="lints", variant="all", - cmd="./lint-wally &> {}", + cmd="./lint-wally | tee {}", grepstr="All lints run with no errors or warnings" ) ] -def getBuildrootTC(short): +def getBuildrootTC(boot): INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM - MAX_EXPECTED = 246000000 - if short: + MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt. + if boot: + name="buildrootboot" + BRcmd="vsim > {} -c < {} -c < {} -c <" prompt: -# do wally-pipelined.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -#switch $argc { -# 0 {vlog +incdir+../config/rv64ic +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -# 1 {vlog +incdir+$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583} -#} -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 -vopt +acc work.testbench -G TEST=imperas64d -o workopt -vsim workopt - -view wave --- display input and output signals as hexidecimal values -do ./wave-dos/generic.do - --- Run the Simulation -#run 3600 -run -all -#quit -#noview ../testbench/testbench-imperas.sv -noview ../testbench/testbench.sv -view wave +# wally-pipelined.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m" + +# Use this wally-pipelined.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-pipelined.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-pipelined.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +# $num = the added words after the call +vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 + +vsim -voptargs=+acc work.testbenchfp -G TEST=$2 + +view wave +#-- display input and output signals as hexidecimal values +#do ./wave-dos/peripheral-waves.do +#add log -recursive /* +#do wave.do deal with when ready + +do wave-fpu.do + +#-- Run the Simulation +#run 3600 +run -all +noview testbench-fp.sv +view wave + diff --git a/pipelined/regression/wally-coremark.do b/pipelined/regression/wally-coremark.do deleted file mode 100644 index a5fae409a..000000000 --- a/pipelined/regression/wally-coremark.do +++ /dev/null @@ -1,45 +0,0 @@ -# wally-coremark.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Use this wally-coremark.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-coremark.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-coremark.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work] { - vdel -all -} -vlib work - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/coremark, but allow this to be overridden at the command line. For example: -#vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-coremark_bare.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt +acc work.testbench -o workopt -vsim workopt - -mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM - -#add log -recursive /* -do wave.do -run -all -#run 21400 -#quit diff --git a/pipelined/regression/wally-fp64-batch.do b/pipelined/regression/wally-fp64-batch.do deleted file mode 100644 index 33398dc6c..000000000 --- a/pipelined/regression/wally-fp64-batch.do +++ /dev/null @@ -1,50 +0,0 @@ -# wally-pipelined-batch.do -# -# Modification by Oklahoma State University & Harvey Mudd College -# Use with Testbench -# James Stine, 2008; David Harris 2021 -# Go Cowboys!!!!!! -# -# Takes 1:10 to run RV64IC tests using gui - -# Usage: do wally-pipelined-batch.do -# Example: do wally-pipelined-batch.do rv32ic imperas-32i - -# Use this wally-pipelined-batch.do file to run this example. -# Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined-batch.do -# or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined-batch.do -c -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work_${1}_${2}] { - vdel -lib work_${1}_${2} -all -} -vlib work_${1}_${2} - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt - -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic rv32ic -vlog -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv ../src/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work_${1}_${2}.testbench -work work_${1}_${2} -G TEST=$2 -o testbenchopt -vsim -lib work_${1}_${2} testbenchopt -# Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time -#vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf -#vsim -coverage -lib work_$2 workopt_$2 - -run -all -#coverage report -file wally-pipelined-coverage.txt -# These aren't doing anything helpful -#coverage report -memory -#profile report -calltree -file wally-pipelined-calltree.rpt -cutoff 2 -quit diff --git a/pipelined/regression/wally-pipelined-batch.do b/pipelined/regression/wally-pipelined-batch.do index 6891c7d6c..698ba4a37 100644 --- a/pipelined/regression/wally-pipelined-batch.do +++ b/pipelined/regression/wally-pipelined-batch.do @@ -36,22 +36,36 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084 + vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084 -fatal 7 run -all run -all exec ./slack-notifier/slack-notifier.py +} elseif {$2 eq "buildroot-no-trace"} { + vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 + # start and run simulation + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=1 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 + + #-- Run the Simulation + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + echo "Don't forget to change DEBUG_LEVEL = 0." + echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" + run -all + run -all + exec ./slack-notifier/slack-notifier.py + } else { vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt - vsim -lib wkdir/work_${1}_${2} testbenchopt + vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 # Adding coverage increases runtime from 2:00 to 4:29. Can't run it all the time #vopt work_$2.testbench -work work_$2 -o workopt_$2 +cover=sbectf #vsim -coverage -lib work_$2 workopt_$2 - # power add generates the logging necessary for saif generation. + # power add generates the logging necessary for said generation. # power add -r /dut/core/* run -all # power off -r /dut/core/* diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index cf116da6d..381311397 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -34,11 +34,11 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 #-- Run the Simulation - run -all + #run -all add log -recursive /* do linux-wave.do run -all @@ -48,8 +48,8 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt - vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt + vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 -fatal 7 #-- Run the Simulation echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!" @@ -69,7 +69,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063 vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt - vsim workopt +nowarn3829 + vsim workopt +nowarn3829 -fatal 7 view wave #-- display input and output signals as hexidecimal values @@ -78,12 +78,12 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { do wave.do # power add generates the logging necessary for saif generation. - power add -r /dut/core/* + #power add -r /dut/core/* #-- Run the Simulation run -all - power off -r /dut/core/* - power report -all -bsaif power.saif + #power off -r /dut/core/* + #power report -all -bsaif power.saif noview ../testbench/testbench.sv view wave } diff --git a/pipelined/regression/wave-coremark.do b/pipelined/regression/wave-coremark.do deleted file mode 100644 index 20248f35f..000000000 --- a/pipelined/regression/wave-coremark.do +++ /dev/null @@ -1,502 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate /testbench/clk -add wave -noupdate /testbench/reset -add wave -noupdate /testbench/test -add wave -noupdate /testbench/memfilename -add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE -add wave -noupdate -group {Execution Stage} /testbench/InstrEName -add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/priv/trap/InstrValidM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/MemAdrM -add wave -noupdate /testbench/dut/core/ieu/dp/ResultM -add wave -noupdate /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/IllegalInstrFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/BreakpointFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/EcallFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InstrPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/LoadPageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/StorePageFaultM -add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/trap/InterruptM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/PendingIntsM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/CommittedM -add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/trap/InstrValidM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/TrapM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/ICacheStallF -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/MulDivStallD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM -add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight -add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong -add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 -add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/bus/icache/FinalInstrRawF -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -group {instruction pipeline} /testbench/InstrW -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD -add wave -noupdate -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D -add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D -add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3 -add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/FlagsE -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ltu -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM -add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE -add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE -add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -group PCS /testbench/dut/core/PCF -add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -group PCS /testbench/dut/core/PCE -add wave -noupdate -group PCS /testbench/dut/core/PCM -add wave -noupdate -group PCS /testbench/PCW -add wave -noupdate -group muldiv /testbench/dut/core/mdu/Funct3E -add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivE -add wave -noupdate -group muldiv /testbench/dut/core/mdu/W64E -add wave -noupdate -group muldiv /testbench/dut/core/mdu/StallM -add wave -noupdate -group muldiv /testbench/dut/core/mdu/StallW -add wave -noupdate -group muldiv /testbench/dut/core/mdu/FlushM -add wave -noupdate -group muldiv /testbench/dut/core/mdu/FlushW -add wave -noupdate -group muldiv /testbench/dut/core/mdu/MulDivResultW -add wave -noupdate -group muldiv /testbench/dut/core/mdu/DivBusyE -add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/controller/CurrState -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/HitWay -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/VictimWay -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/SetValid} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/ValidBits} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/ifu/bus/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/controller/NextState -add wave -noupdate -group icache /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/ITLBWriteF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/ReadLineF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/ReadLineF -add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/BasePAdrF -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/hit -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/spill -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/ICacheStallF -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/spillSave -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/spillSave -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/CntReset -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/PreCntEn -add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/controller/CntEn -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/InstrPAdrF -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/InstrInF -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/FetchCountFlag -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/FetchCount -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrReadF -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/InstrAckF -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/controller/ICacheMemWriteEnable -add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/ICacheBusWriteData -add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState -add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/InstrReadF -add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/MemSizeM -add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY -add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE -add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST -add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT -add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS -add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK -add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD -add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED -add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED -add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/core/lsu/arbiter/SelPTW -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/WalkerPageFaultM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/WriteDataM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWordWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWayWriteEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMWordEnable -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SRAMBlockWayWriteEnableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/SelAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/ReadDataBlockM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/DCacheBusWriteData -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/WriteWordEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetValid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/SetDirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/core/lsu.bus.dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu.bus.dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataBlockWayMaskedM -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/ReadDataWordMuxM -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemRWM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemAdrE -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/MemPAdrM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/Funct3M -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/Funct7M -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/AtomicM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/FlushDCacheM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/CacheableM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/WriteDataM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/ReadDataM -add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu.bus.dcache/DCacheStallM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/FlushAdrFlag -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/FetchCount -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/FetchCountFlag -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBPAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBRead -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBWrite -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/AHBAck -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/HRDATA -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/HWDATA -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/genblk1/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/genblk1/WalkerState -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/PCF -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/TranslationPAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/HPTWReadPTE -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/ITLBMissF -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/DTLBMissM -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/ITLBWriteF -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/DTLBWriteM -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerInstrPageFaultF -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerLoadPageFaultM -add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/WalkerStorePageFaultM -add wave -noupdate -group csr /testbench/dut/core/priv/csr/MIP_REGW -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/TLBWrite -add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF -add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/PhysicalAddress -add wave -noupdate /testbench/dut/core/lsu.bus.dcache/VAdr -add wave -noupdate /testbench/dut/core/lsu.bus.dcache/MemPAdrM -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb -add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb -add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -radix unsigned /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLE_REGW -add wave -noupdate -radix unsigned /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRET_REGW -add wave -noupdate -label LoadStall -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[3]} -add wave -noupdate -label {Branch Instr} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[5]} -add wave -noupdate -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[4]} -add wave -noupdate -label {Jump, Jal, Jalr} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[7]} -add wave -noupdate -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[8]} -add wave -noupdate -label {BTB Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[6]} -add wave -noupdate -label {BP Class Non CFI Wrong} -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[10]} -add wave -noupdate -label DCacheAccess -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[11]} -add wave -noupdate -label DCacheMiss -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[12]} -add wave -noupdate -label Return -radix unsigned {/testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[9]} -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/InstrValidNotFlushedM -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/BPPredDirWrongM -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/genblk1/LoadStallM -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/NextHPMCOUNTERM -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/DCacheMiss -add wave -noupdate /testbench/dut/core/priv/csr/genblk1/counters/DCacheAccess -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 6} {17923831 ns} 0} -quietly wave cursor active 1 -configure wave -namecolwidth 250 -configure wave -valuecolwidth 297 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -configure wave -timelineunits ns -update -WaveRestoreZoom {0 ns} {18715695 ns} diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/pipelined/regression/wave-dos/ahb-muldiv.do index 98df30a71..bd212f774 100644 --- a/pipelined/regression/wave-dos/ahb-muldiv.do +++ b/pipelined/regression/wave-dos/ahb-muldiv.do @@ -67,6 +67,7 @@ add wave -hex /testbench/dut/core/ebu/HTRANS add wave -hex /testbench/dut/core/ebu/HRDATA add wave -hex /testbench/dut/core/ebu/HWRITE add wave -hex /testbench/dut/core/ebu/HWDATA +add wave -hex /testbench/dut/core/ebu/HBURST add wave -hex /testbench/dut/core/ebu/CaptureDataM add wave -divider diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do new file mode 100644 index 000000000..f06fb6d63 --- /dev/null +++ b/pipelined/regression/wave-fpu.do @@ -0,0 +1,40 @@ + +add wave -noupdate /testbenchfp/clk +add wave -noupdate -radix decimal /testbenchfp/VectorNum +add wave -noupdate /testbenchfp/FrmNum +add wave -noupdate /testbenchfp/X +add wave -noupdate /testbenchfp/Y +add wave -noupdate /testbenchfp/Z +add wave -noupdate /testbenchfp/Res +add wave -noupdate /testbenchfp/Ans +add wave -noupdate /testbenchfp/DivStart +add wave -noupdate /testbenchfp/DivBusy +add wave -noupdate /testbenchfp/divsqrt/srtfsm/state +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/* +add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/* +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WC +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WS +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WCA +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/WSA +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/Q +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QM +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QNext +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/QMNext +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srt/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/otfc/otfc2/* +add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/qsel/qsel2/* +# add wave -group {Divide} -group inter0 -noupdate /testbenchfp/divsqrt/srt/interations[0]/divinteration/genblk1/qsel4/* +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/* +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtpreproc/expcalc/* +add wave -group {Divide} -noupdate /testbenchfp/divsqrt/srtfsm/* +add wave -group {Testbench} -noupdate /testbenchfp/* +add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index de6eb166c..a9a9feee9 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -5,38 +5,38 @@ add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset_ext add wave -noupdate /testbench/memfilename add wave -noupdate /testbench/dut/core/SATP_REGW -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM -add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM -add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM -add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWriteFencePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/MDUStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM +add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM -add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM +add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW add wave -noupdate -group {instruction pipeline} /testbench/InstrFName add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD @@ -55,10 +55,10 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE add wave -noupdate -group {Execution Stage} /testbench/InstrEName add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/PCM -add wave -noupdate -group {Memory Stage} /testbench/dut/core/InstrM -add wave -noupdate -group {Memory Stage} /testbench/InstrMName -add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM +add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName +add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM add wave -noupdate -group {WriteBack stage} /testbench/PCW add wave -noupdate -group {WriteBack stage} /testbench/InstrW add wave -noupdate -group {WriteBack stage} /testbench/InstrWName @@ -76,8 +76,6 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_RE add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIE_REGW -add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIP_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR @@ -192,195 +190,179 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED -add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState -add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall -add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr -add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA -add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA -add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay -add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM -add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData -add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr -add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF -add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA +add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr +add wave -noupdate -expand -group lsu -expand -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusRead +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusWrite +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusAdr +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusAck +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusHRDATA +add wave -noupdate -expand -group lsu -expand -group bus /testbench/dut/core/lsu/LSUBusHWDATA +add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay +add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM +add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr +add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF +add wave -noupdate -expand -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC -add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress @@ -394,43 +376,12 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/pl add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO -add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM -add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART -add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR @@ -472,11 +423,12 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM -add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState +add wave -noupdate -group ifu -color Gold /testbench/dut/core/ifu/bus/busdp/busfsm/BusCurrState add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA +add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUTransComplete add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 @@ -492,6 +444,57 @@ add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetDirtyWay +add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SetValidWay +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/StoredData} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ByteMask} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/ReadData} +add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/StoredData} add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress @@ -509,11 +512,9 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/NextPTE -add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 5} {0 ns} 0} -quietly wave cursor active 1 +WaveRestoreCursors {{Cursor 2} {989221 ns} 1} {{Cursor 3} {999815 ns} 1} {{Cursor 4} {311315 ns} 0} +quietly wave cursor active 3 configure wave -namecolwidth 250 configure wave -valuecolwidth 314 configure wave -justifyvalue left @@ -528,4 +529,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ns} {208 ns} +WaveRestoreZoom {311178 ns} {311464 ns} diff --git a/pipelined/regression/wkdir/.gitignore b/pipelined/regression/wkdir/.gitignore new file mode 100644 index 000000000..5e7d2734c --- /dev/null +++ b/pipelined/regression/wkdir/.gitignore @@ -0,0 +1,4 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 2374b4938..6c19436e0 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" -module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTERVAL, DCACHE) ( +module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTERVAL, DCACHE) ( input logic clk, input logic reset, // cpu side @@ -38,11 +38,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER input logic [1:0] RW, input logic [1:0] Atomic, input logic FlushCache, - input logic InvalidateCacheM, + input logic InvalidateCache, input logic [11:0] NextAdr, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] PAdr, // physical address - input logic [(`XLEN-1)/8:0] ByteMask, - input logic [`XLEN-1:0] FinalWriteData, + input logic [(WORDLEN-1)/8:0] ByteMask, + input logic [WORDLEN-1:0] FinalWriteData, output logic CacheCommitted, output logic CacheStall, // to performance counters to cpu @@ -57,7 +57,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER output logic CacheFetchLine, output logic CacheWriteLine, input logic CacheBusAck, - input logic [LOGWPL-1:0] WordCount, + input logic [LOGBWPL-1:0] WordCount, input logic LSUBusWriteCrit, output logic [`PA_BITS-1:0] CacheBusAdr, input logic [LINELEN-1:0] CacheBusWriteData, @@ -69,7 +69,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER localparam SETLEN = $clog2(NUMLINES); localparam SETTOP = SETLEN+OFFSETLEN; localparam TAGLEN = `PA_BITS - SETTOP; - localparam WORDSPERLINE = LINELEN/`XLEN; + localparam WORDSPERLINE = LINELEN/WORDLEN; localparam FlushAdrThreshold = NUMLINES - 1; logic SelAdr; @@ -78,7 +78,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] HitWay, HitWaySaved, HitWayFinal; + logic [NUMWAYS-1:0] HitWay; logic CacheHit; logic SetDirty; logic SetValid; @@ -104,9 +104,17 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [1:0] CacheRW, CacheAtomic; - logic [LINELEN-1:0] ReadDataLine; + logic [LINELEN-1:0] ReadDataLine, ReadDataLineCache; logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; - logic save, restore; + logic SelBusBuffer; + logic SRAMEnable; + + localparam LOGLLENBYTES = $clog2(WORDLEN/8); + localparam CACHEWORDSPERLINE = `DCACHE_LINELENINBITS/WORDLEN; + localparam LOGCWPL = $clog2(CACHEWORDSPERLINE); + logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; + logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, LineByteMux; + genvar index; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -120,50 +128,59 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) - CacheWays[NUMWAYS-1:0](.clk, .reset, .RAdr, .PAdr, .CacheWriteData, .ByteMask, + CacheWays[NUMWAYS-1:0](.clk, .reset, .ce(SRAMEnable), .RAdr, .PAdr, .CacheWriteData, .LineByteMask, .SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay, .FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .VictimDirtyWay, .VictimTagWay, - .Invalidate(InvalidateCacheM)); + .Invalidate(InvalidateCache)); if(NUMWAYS > 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .RAdr, .LRUWriteEn); + .clk, .reset, .HitWay, .VictimWay, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; // ReadDataLineWay is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. // Final part of the AO Mux. First is the AND in the cacheway. - or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine)); + or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLineCache)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Because of the sram clocked read when the ieu is stalled the read data maybe lost. - // There are two ways to resolve. 1. We can replay the read of the sram or we can save - // the data. Replay is eaiser but creates a longer critical path. - // save/restore only wayhit and readdata. - if(!`REPLAY) begin - flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); - mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); - end else assign HitWayFinal = HitWay; - // like to fix this. if(DCACHE) - mux2 #(LOGWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), + mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), .d1(WordCount), .s(LSUBusWriteCrit), .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; - subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL, LOGWPL) subcachelineread( - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + mux2 #(LINELEN) EarlyReturnMux(ReadDataLineCache, CacheBusWriteData, SelBusBuffer, ReadDataLine); + + subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread( + .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord); ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); - mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), - .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), + logic [LINELEN-1:0] FinalWriteDataDup; + assign FinalWriteDataDup = {WORDSPERLINE{FinalWriteData}}; + + onehotdecoder #(LOGCWPL) adrdec( + .bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); + for(index = 0; index < 2**LOGCWPL; index++) begin + assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; + end + + assign LineByteMux = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. + assign LineByteMask = ~SetValid & ~SetDirty ? '0 : ~SetValid & SetDirty ? DemuxedByteMask : '1; // if store hit only enable the word and subword bytes, else write all bytes. + + for(index = 0; index < LINELEN/8; index++) begin + mux2 #(8) WriteDataMux(.d0(FinalWriteDataDup[8*index+7:8*index]), + .d1(CacheBusWriteData[8*index+7:8*index]), .s(LineByteMux[index]), .y(CacheWriteData[8*index+7:8*index])); + end + //mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), +// .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); + mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d2({VictimTag, FlushAdr, {OFFSETLEN{1'b0}}}), .s({SelFlush, SelEvict}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// @@ -178,12 +195,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); assign FlushWayFlag = FlushWay[NUMWAYS-1]; - assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; + if(NUMWAYS > 1) assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; + else assign NextFlushWay = FlushWay[NUMWAYS-1]; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay, + mux3 #(NUMWAYS) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelectedWay); assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; @@ -202,7 +220,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTER .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, - .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, - .save, .restore, + .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelBusBuffer, + .InvalidateCache, + .SRAMEnable, .LRUWriteEn); endmodule diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 857884c43..a1c785dc7 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -32,50 +32,51 @@ module cachefsm (input logic clk, - input logic reset, + input logic reset, // inputs from IEU input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, - input logic FlushCache, + input logic FlushCache, + input logic InvalidateCache, // hazard inputs - input logic CPUBusy, + input logic CPUBusy, // interlock fsm - input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, + input logic IgnoreRequestTLB, + input logic IgnoreRequestTrapM, input logic TrapM, // Bus inputs - input logic CacheBusAck, + input logic CacheBusAck, // dcache internals - input logic CacheHit, - input logic VictimDirty, - input logic FlushAdrFlag, - input logic FlushWayFlag, + input logic CacheHit, + input logic VictimDirty, + input logic FlushAdrFlag, + input logic FlushWayFlag, // hazard outputs - output logic CacheStall, + output logic CacheStall, // counter outputs - output logic CacheMiss, - output logic CacheAccess, + output logic CacheMiss, + output logic CacheAccess, // Bus outputs - output logic CacheCommitted, - output logic CacheWriteLine, - output logic CacheFetchLine, + output logic CacheCommitted, + output logic CacheWriteLine, + output logic CacheFetchLine, // dcache internals - output logic SelAdr, - output logic ClearValid, - output logic ClearDirty, - output logic SetDirty, - output logic SetValid, - output logic SelEvict, - output logic LRUWriteEn, - output logic SelFlush, - output logic FlushAdrCntEn, - output logic FlushWayCntEn, - output logic FlushAdrCntRst, - output logic FlushWayCntRst, - output logic save, - output logic restore); + output logic SelAdr, + output logic ClearValid, + output logic ClearDirty, + output logic SetDirty, + output logic SetValid, + output logic SelEvict, + output logic LRUWriteEn, + output logic SelFlush, + output logic FlushAdrCntEn, + output logic FlushWayCntEn, + output logic FlushAdrCntRst, + output logic FlushWayCntRst, + output logic SelBusBuffer, + output logic SRAMEnable); logic resetDelay; logic AMO; @@ -87,20 +88,13 @@ module cachefsm typedef enum logic [3:0] {STATE_READY, // hit states // miss states STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, STATE_MISS_EVICT_DIRTY, STATE_MISS_WRITE_CACHE_LINE, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - // cpu stalled replay/restore state - STATE_CPU_BUSY, // flush cache STATE_FLUSH, STATE_FLUSH_CHECK, STATE_FLUSH_INCR, - STATE_FLUSH_WRITE_BACK, - STATE_FLUSH_CLEAR_DIRTY} statetype; + STATE_FLUSH_WRITE_BACK} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; logic IgnoreRequest; @@ -115,7 +109,7 @@ module cachefsm assign DoRead = CacheRW[1] & ~IgnoreRequest; assign DoWrite = CacheRW[0] & ~IgnoreRequest; - assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; + assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache; assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit); assign FlushFlag = FlushAdrFlag & FlushWayFlag; @@ -136,38 +130,31 @@ module cachefsm always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(IgnoreRequest) NextState = STATE_READY; - else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change - else NextState = STATE_READY; - STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE; - else NextState = STATE_MISS_FETCH_WDV; - STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; - else NextState = STATE_MISS_WRITE_CACHE_LINE; - STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; - STATE_MISS_READ_WORD: if(CacheRW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; - else NextState = STATE_MISS_READ_WORD_DELAY; - STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; - else NextState = STATE_MISS_EVICT_DIRTY; - STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; - else if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; - else NextState = STATE_FLUSH_WRITE_BACK; - STATE_FLUSH_CLEAR_DIRTY: if(FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - default: NextState = STATE_READY; + STATE_READY: if(IgnoreRequest | InvalidateCache) NextState = STATE_READY; + else if(DoFlush) NextState = STATE_FLUSH; + // Delayed LRU update. Cannot check if victim line is dirty on this cycle. + // To optimize do the fetch first, then eviction if necessary. + else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; + else NextState = STATE_READY; + STATE_MISS_FETCH_WDV: if(CacheBusAck & ~VictimDirty) NextState = STATE_MISS_WRITE_CACHE_LINE; + else if(CacheBusAck & VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else NextState = STATE_MISS_FETCH_WDV; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + else NextState = STATE_MISS_EVICT_DIRTY; + // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. + STATE_FLUSH: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + else if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_WRITE_BACK: if(CacheBusAck) begin + if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + end else NextState = STATE_FLUSH_WRITE_BACK; + default: NextState = STATE_READY; endcase end @@ -175,63 +162,48 @@ module cachefsm assign CacheCommitted = CurrState != STATE_READY; assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_MISS_READ_WORD) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | - (CurrState == STATE_FLUSH_WRITE_BACK) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + (CurrState == STATE_FLUSH_WRITE_BACK & ~(FlushFlag) & CacheBusAck); // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) | - (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | - (CurrState == STATE_MISS_WRITE_WORD); + (CurrState == STATE_MISS_WRITE_CACHE_LINE & (AMO | CacheRW[0])); assign ClearValid = '0; - assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY); + assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE & ~(AMO | CacheRW[0])) | + (CurrState == STATE_FLUSH_WRITE_BACK & CacheBusAck); assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | - (CurrState == STATE_MISS_READ_WORD_DELAY) | - (CurrState == STATE_MISS_WRITE_WORD); + (CurrState == STATE_MISS_WRITE_CACHE_LINE); // Flush and eviction controls - assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); + assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY) | + (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | - (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY); + (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK); assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag); + (CurrState == STATE_FLUSH_WRITE_BACK & FlushWayAndNotAdrFlag & CacheBusAck); assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~FlushFlag); + (CurrState == STATE_FLUSH_WRITE_BACK & ~FlushFlag & CacheBusAck); assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss); - assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | + assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); - // handle cpu stall. - assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY; - assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | CacheRW[1]) & CPUBusy) | - (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; - // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. // use the raw requests as we don't want IgnoreRequestTrapM in the critical path (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed - (CurrState == STATE_READY & (CacheRW[1] & CacheHit) & (CPUBusy & `REPLAY)) | - + (CurrState == STATE_READY & (DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_MISS_READ_WORD) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | - (CurrState == STATE_MISS_WRITE_WORD) | - - (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | resetDelay; + + assign SelBusBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE; + assign SRAMEnable = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset; endmodule // cachefsm diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index cb33480dc..d407bc284 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -59,8 +59,8 @@ module cachereplacementpolicy // Replacement Bits: Register file // Needs to be resettable for simulation, but could omit reset for synthesis *** always_ff @(posedge clk) - if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; - else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD; + if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0; + else if (LRUWriteEnD) ReplacementBits[RAdrD] <= NewReplacementD; assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index; diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index d9a478612..58f03e0eb 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -33,6 +33,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) ( input logic clk, + input logic ce, input logic reset, input logic [$clog2(NUMLINES)-1:0] RAdr, @@ -47,16 +48,19 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic VictimWay, input logic FlushWay, input logic Invalidate, - input logic [(`XLEN-1)/8:0] ByteMask, +// input logic [(`XLEN-1)/8:0] ByteMask, + input logic [LINELEN/8-1:0] LineByteMask, output logic [LINELEN-1:0] ReadDataLineWay, output logic HitWay, output logic VictimDirtyWay, output logic [TAGLEN-1:0] VictimTagWay); - localparam WORDSPERLINE = LINELEN/`XLEN; + localparam integer WORDSPERLINE = LINELEN/`XLEN; + localparam integer BYTESPERLINE = LINELEN/8; localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); + localparam integer BYTESPERWORD = `XLEN/8; logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; @@ -68,23 +72,23 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic SelTag; logic [$clog2(NUMLINES)-1:0] RAdrD; logic [2**LOGWPL-1:0] MemPAdrDecoded; - logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - logic [(`XLEN-1)/8:0] FinalByteMask; + logic SelectedWriteWordEn; +// logic [WORDSPERLINE-1:0] SelectedWriteWordEn; +// logic [(`XLEN-1)/8:0] FinalByteMask; + logic [LINELEN/8-1:0] FinalByteMask; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// - onehotdecoder #(LOGWPL) adrdec( - .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. - assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND - assign FinalByteMask = SetValidWay ? '1 : ByteMask; // OR + assign SelectedWriteWordEn = SetValidWay | SetDirtyWay;// ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND + assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, + sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce, .Adr(RAdr), .ReadData(ReadTag), .ByteMask('1), .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); @@ -98,13 +102,19 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Data Array ///////////////////////////////////////////////////////////////////////////////////////////// - // *** Potential optimization: if byte write enables are available, could remove subwordwrites genvar words; - for(words = 0; words < LINELEN/`XLEN; words++) begin: word - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk, .Adr(RAdr), - .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), - .CacheWriteData(CacheWriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SelectedWriteWordEn[words]), .ByteMask(FinalByteMask)); + + localparam integer SRAMLEN = 128; + localparam integer NUMSRAM = LINELEN/SRAMLEN; + localparam integer SRAMLENINBYTES = SRAMLEN/8; + localparam integer LOGNUMSRAM = $clog2(NUMSRAM); + + for(words = 0; words < NUMSRAM; words++) begin: word + sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce, .Adr(RAdr), + .ReadData(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), + .CacheWriteData(CacheWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), + //.WriteEnable(1'b1), .ByteMask(SRAMLineByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); + .WriteEnable(SelectedWriteWordEn), .ByteMask(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); end // AND portion of distributed read multiplexers @@ -120,7 +130,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; end - flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); + flopen #($clog2(NUMLINES)) RAdrDelayReg(clk, ce, RAdr, RAdrD); assign Valid = ValidBits[RAdrD]; ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/cache/sram1p1rw.sv b/pipelined/src/cache/sram1p1rw.sv index 5a7da75dd..ca1b07437 100644 --- a/pipelined/src/cache/sram1p1rw.sv +++ b/pipelined/src/cache/sram1p1rw.sv @@ -33,8 +33,11 @@ // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words +`include "wally-config.vh" + module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic clk, + input logic ce, input logic [$clog2(DEPTH)-1:0] Adr, input logic [WIDTH-1:0] CacheWriteData, input logic WriteEnable, @@ -43,42 +46,38 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( logic [WIDTH-1:0] StoredData[DEPTH-1:0]; logic [$clog2(DEPTH)-1:0] AdrD; - logic WriteEnableD; - always_ff @(posedge clk) AdrD <= Adr; + always_ff @(posedge clk) if(ce) AdrD <= Adr; genvar index; -/* -----\/----- EXCLUDED -----\/----- - for(index = 0; index < WIDTH/8; index++) begin - always_ff @(posedge clk) begin - if (WriteEnable & ByteMask[index]) begin - StoredData[Adr][8*(index+1)-1:8*index] <= #1 CacheWriteData[8*(index+1)-1:8*index]; - end - end - end - -----/\----- EXCLUDED -----/\----- */ - if (WIDTH%8 != 0) // handle msbs if not a multiple of 8 - always_ff @(posedge clk) - if (WriteEnable & ByteMask[WIDTH/8]) - StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 - CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; - - for(index = 0; index < WIDTH/8; index++) - always_ff @(posedge clk) - if(WriteEnable & ByteMask[index]) - StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; -/* - // if not a multiple of 8, MSByte is not 8 bits long. - if(WIDTH%8 != 0) begin - always_ff @(posedge clk) begin - if (WriteEnable & ByteMask[WIDTH/8]) begin - StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; - end - end - end -*/ - assign ReadData = StoredData[AdrD]; + + if (`USE_SRAM == 1) begin + // 64 x 128-bit SRAM + // check if the size is ok, complain if not*** + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = ByteMask[index/8]; + TS1N28HPCPSVTB64X128M4SWBASO sram( + .CLK(clk), .CEB(1'b0), .WEB(~WriteEnable), + .A(Adr), .D(CacheWriteData), + .BWEB(~BitWriteMask), .Q(ReadData) + ); + + end else begin + if (WIDTH%8 != 0) // handle msbs if not a multiple of 8 + always_ff @(posedge clk) + if (ce & WriteEnable & ByteMask[WIDTH/8]) + StoredData[Adr][WIDTH-1:WIDTH-WIDTH%8] <= #1 + CacheWriteData[WIDTH-1:WIDTH-WIDTH%8]; + + for(index = 0; index < WIDTH/8; index++) + always_ff @(posedge clk) + if(ce & WriteEnable & ByteMask[index]) + StoredData[Adr][index*8 +: 8] <= #1 CacheWriteData[index*8 +: 8]; + + assign ReadData = StoredData[AdrD]; + end endmodule diff --git a/pipelined/src/cache/subcachelineread.sv b/pipelined/src/cache/subcachelineread.sv index 2a3395ea5..a9db47c13 100644 --- a/pipelined/src/cache/subcachelineread.sv +++ b/pipelined/src/cache/subcachelineread.sv @@ -30,11 +30,8 @@ `include "wally-config.vh" -module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( - input logic clk, - input logic reset, +module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL)( input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, - input logic save, restore, input logic [LINELEN-1:0] ReadDataLine, output logic [WORDLEN-1:0] ReadDataWord); @@ -43,7 +40,6 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( localparam PADLEN = WORDLEN-MUXINTERVAL; logic [LINELEN+(WORDLEN-MUXINTERVAL)-1:0] ReadDataLinePad; logic [WORDLEN-1:0] ReadDataLineSets [(LINELEN/MUXINTERVAL)-1:0]; - logic [WORDLEN-1:0] ReadDataWordRaw, ReadDataWordSaved; if (PADLEN > 0) begin logic [PADLEN-1:0] Pad; @@ -56,11 +52,5 @@ module subcachelineread #(parameter LINELEN, WORDLEN, MUXINTERVAL, LOGWPL)( assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1: (index*MUXINTERVAL)]; end // variable input mux - // *** maybe remove REPLAY config later after deciding which way is best - assign ReadDataWordRaw = ReadDataLineSets[PAdr]; - if(!`REPLAY) begin - flopen #(WORDLEN) cachereaddatasavereg(clk, save, ReadDataWordRaw, ReadDataWordSaved); - mux2 #(WORDLEN) readdatasaverestoremux(ReadDataWordRaw, ReadDataWordSaved, - restore, ReadDataWord); - end else assign ReadDataWord = ReadDataWordRaw; + assign ReadDataWord = ReadDataLineSets[PAdr]; endmodule diff --git a/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v new file mode 120000 index 000000000..c81975209 --- /dev/null +++ b/pipelined/src/cache/ts1n28hpcpsvtb64x128m4swbaso_180a_tt1v25c.v @@ -0,0 +1 @@ +/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v \ No newline at end of file diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index a68370cdb..4203f0f52 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -45,6 +45,11 @@ module ahblite ( input logic IFUBusRead, output logic [`XLEN-1:0] IFUBusHRDATA, output logic IFUBusAck, + output logic IFUBusInit, + input logic [2:0] IFUBurstType, + input logic [1:0] IFUTransType, + input logic IFUTransComplete, + // Signals from Data Cache input logic [`PA_BITS-1:0] LSUBusAdr, input logic LSUBusRead, @@ -52,13 +57,18 @@ module ahblite ( input logic [`XLEN-1:0] LSUBusHWDATA, output logic [`XLEN-1:0] LSUBusHRDATA, input logic [2:0] LSUBusSize, + input logic [2:0] LSUBurstType, + input logic [1:0] LSUTransType, + input logic LSUTransComplete, output logic LSUBusAck, + output logic LSUBusInit, // AHB-Lite external signals (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) output logic HCLK, HRESETn, (* mark_debug = "true" *) output logic [31:0] HADDR, // *** one day switch to a different bus that supports the full physical address (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, (* mark_debug = "true" *) output logic HWRITE, (* mark_debug = "true" *) output logic [2:0] HSIZE, (* mark_debug = "true" *) output logic [2:0] HBURST, @@ -87,6 +97,9 @@ module ahblite ( // Data accesses have priority over instructions. However, if a data access comes // while an instruction read is occuring, the instruction read finishes before // the data access can take place. + // *** This is no longer true when adding burst mode. We need to finish the current + // read before doing another read. Need to work this out, but preliminarily we can + // store the current read type in a flop and use that to figure out what burst type to use. flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextBusState, IDLE, BusState); @@ -100,35 +113,54 @@ module ahblite ( // interface that might be used in place of the ahblite. always_comb case (BusState) - IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions - else if (LSUBusWrite)NextBusState = MEMWRITE; - else if (IFUBusRead) NextBusState = INSTRREAD; - else NextBusState = IDLE; - MEMREAD: if (~HREADY) NextBusState = MEMREAD; - else if (IFUBusRead) NextBusState = INSTRREAD; - else NextBusState = IDLE; - MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; - else if (IFUBusRead) NextBusState = INSTRREAD; - else NextBusState = IDLE; - INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; - else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait? - default: NextBusState = IDLE; + IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions + else if (LSUBusWrite) NextBusState = MEMWRITE; + else if (IFUBusRead) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMREAD: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; + else if (LSUTransComplete) NextBusState = IDLE; + else NextBusState = MEMREAD; + MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD; + else if (LSUTransComplete) NextBusState = IDLE; + else NextBusState = MEMWRITE; + INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD; + else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE; + else if (IFUTransComplete) NextBusState = IDLE; + else NextBusState = INSTRREAD; + default: NextBusState = IDLE; endcase // bus outputs assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); - assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; - assign #1 HADDR = AccessAddress; + assign AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; + assign HADDR = AccessAddress; assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; - assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + assign HBURST = (GrantData) ? LSUBurstType : IFUBurstType; // If doing memory accesses, use LSUburst, else use Instruction burst. + + /* Cache burst read/writes case statement (hopefully) WRAPS only have access to 4 wraps. X changes position based on HSIZE. + 000: Single (SINGLE) + 001: Increment burst of undefined length (INCR) + 010: 4-beat wrapping burst (WRAP4) [wraps if X in 000X0000] + 011: 4-beat incrementing burst (INCR4) + 100: 8-beat wrapping burst (WRAP8) [wraps if X in 00X00000 changes] + 101: 8-beat incrementing burst (INCR8) + 110: 16-beat wrapping burst (WRAP16) [wraps if X in 0X000000] + 111: 16-beat incrementing burst (INCR16) + *** Remove if not necessary + */ + + assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise + assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HMASTLOCK = 0; // no locking supported - assign HWRITE = NextBusState == MEMWRITE; + assign HWRITE = (NextBusState == MEMWRITE); + // Byte mask for HWSTRB + swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(HWSTRB)); + // delay write data by one cycle for - flop #(`XLEN) wdreg(HCLK, LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + flopen #(`XLEN) wdreg(HCLK, (LSUBusAck | LSUBusInit), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN // delay signals for subword writes flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); @@ -136,11 +168,10 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN - - assign IFUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA; - assign IFUBusAck = (BusState == INSTRREAD) & (NextBusState != INSTRREAD); - assign LSUBusAck = (BusState == MEMREAD) & (NextBusState != MEMREAD) | (BusState == MEMWRITE) & (NextBusState != MEMWRITE); - + assign IFUBusInit = (BusState != INSTRREAD) & (NextBusState == INSTRREAD); + assign LSUBusInit = (((BusState != MEMREAD) & (NextBusState == MEMREAD)) | (BusState != MEMWRITE) & (NextBusState == MEMWRITE)); + assign IFUBusAck = HREADY & (BusState == INSTRREAD); + assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE)); endmodule diff --git a/pipelined/src/fpu/adderparts.sv b/pipelined/src/fpu/adderparts.sv deleted file mode 100644 index 045a8accc..000000000 --- a/pipelined/src/fpu/adderparts.sv +++ /dev/null @@ -1,758 +0,0 @@ -// The following module make up the basic building blocks that -// are used by the cla64, cla_sub64, and cla52. - -module INVBLOCK ( GIN, GOUT ); - - input GIN; - output GOUT; - - assign GOUT = ~ GIN; - -endmodule // INVBLOCK - - -module XXOR1 ( A, B, GIN, SUM ); - - input A; - input B; - input GIN; - output SUM; - - assign SUM = ( ~ (A ^ B)) ^ GIN; - -endmodule // XXOR1 - - -module BLOCK0 ( A, B, POUT, GOUT ); - - input A; - input B; - output POUT; - output GOUT; - - assign POUT = ~ (A | B); - assign GOUT = ~ (A & B); - -endmodule // BLOCK0 - - -module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 | PIN2); - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1 - - -module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, POUT, GOUT ); - - input PIN1; - input PIN2; - input GIN1; - input GIN2; - output POUT; - output GOUT; - - assign POUT = ~ (PIN1 & PIN2); - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule // BLOCK2 - - -module BLOCK1A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 & (PIN2 | GIN1)); - -endmodule // BLOCK1A - - -module BLOCK2A ( PIN2, GIN1, GIN2, GOUT ); - - input PIN2; - input GIN1; - input GIN2; - output GOUT; - - assign GOUT = ~ (GIN2 | (PIN2 & GIN1)); - -endmodule -//***KEP all 0:63, 0:64 ect changed - changed due to lint warning -module PRESTAGE_64 ( A, B, CIN, POUT, GOUT ); - - input [63:0] A; - input [63:0] B; - input CIN; - - output [63:0] POUT; - output [64:0] GOUT; - - BLOCK0 U10 (A[0] , B[0] , POUT[0] , GOUT[1] ); - BLOCK0 U11 (A[1] , B[1] , POUT[1] , GOUT[2] ); - BLOCK0 U12 (A[2] , B[2] , POUT[2] , GOUT[3] ); - BLOCK0 U13 (A[3] , B[3] , POUT[3] , GOUT[4] ); - BLOCK0 U14 (A[4] , B[4] , POUT[4] , GOUT[5] ); - BLOCK0 U15 (A[5] , B[5] , POUT[5] , GOUT[6] ); - BLOCK0 U16 (A[6] , B[6] , POUT[6] , GOUT[7] ); - BLOCK0 U17 (A[7] , B[7] , POUT[7] , GOUT[8] ); - BLOCK0 U18 (A[8] , B[8] , POUT[8] , GOUT[9] ); - BLOCK0 U19 (A[9] , B[9] , POUT[9] , GOUT[10] ); - BLOCK0 U110 (A[10] , B[10] , POUT[10] , GOUT[11] ); - BLOCK0 U111 (A[11] , B[11] , POUT[11] , GOUT[12] ); - BLOCK0 U112 (A[12] , B[12] , POUT[12] , GOUT[13] ); - BLOCK0 U113 (A[13] , B[13] , POUT[13] , GOUT[14] ); - BLOCK0 U114 (A[14] , B[14] , POUT[14] , GOUT[15] ); - BLOCK0 U115 (A[15] , B[15] , POUT[15] , GOUT[16] ); - BLOCK0 U116 (A[16] , B[16] , POUT[16] , GOUT[17] ); - BLOCK0 U117 (A[17] , B[17] , POUT[17] , GOUT[18] ); - BLOCK0 U118 (A[18] , B[18] , POUT[18] , GOUT[19] ); - BLOCK0 U119 (A[19] , B[19] , POUT[19] , GOUT[20] ); - BLOCK0 U120 (A[20] , B[20] , POUT[20] , GOUT[21] ); - BLOCK0 U121 (A[21] , B[21] , POUT[21] , GOUT[22] ); - BLOCK0 U122 (A[22] , B[22] , POUT[22] , GOUT[23] ); - BLOCK0 U123 (A[23] , B[23] , POUT[23] , GOUT[24] ); - BLOCK0 U124 (A[24] , B[24] , POUT[24] , GOUT[25] ); - BLOCK0 U125 (A[25] , B[25] , POUT[25] , GOUT[26] ); - BLOCK0 U126 (A[26] , B[26] , POUT[26] , GOUT[27] ); - BLOCK0 U127 (A[27] , B[27] , POUT[27] , GOUT[28] ); - BLOCK0 U128 (A[28] , B[28] , POUT[28] , GOUT[29] ); - BLOCK0 U129 (A[29] , B[29] , POUT[29] , GOUT[30] ); - BLOCK0 U130 (A[30] , B[30] , POUT[30] , GOUT[31] ); - BLOCK0 U131 (A[31] , B[31] , POUT[31] , GOUT[32] ); - BLOCK0 U132 (A[32] , B[32] , POUT[32] , GOUT[33] ); - BLOCK0 U133 (A[33] , B[33] , POUT[33] , GOUT[34] ); - BLOCK0 U134 (A[34] , B[34] , POUT[34] , GOUT[35] ); - BLOCK0 U135 (A[35] , B[35] , POUT[35] , GOUT[36] ); - BLOCK0 U136 (A[36] , B[36] , POUT[36] , GOUT[37] ); - BLOCK0 U137 (A[37] , B[37] , POUT[37] , GOUT[38] ); - BLOCK0 U138 (A[38] , B[38] , POUT[38] , GOUT[39] ); - BLOCK0 U139 (A[39] , B[39] , POUT[39] , GOUT[40] ); - BLOCK0 U140 (A[40] , B[40] , POUT[40] , GOUT[41] ); - BLOCK0 U141 (A[41] , B[41] , POUT[41] , GOUT[42] ); - BLOCK0 U142 (A[42] , B[42] , POUT[42] , GOUT[43] ); - BLOCK0 U143 (A[43] , B[43] , POUT[43] , GOUT[44] ); - BLOCK0 U144 (A[44] , B[44] , POUT[44] , GOUT[45] ); - BLOCK0 U145 (A[45] , B[45] , POUT[45] , GOUT[46] ); - BLOCK0 U146 (A[46] , B[46] , POUT[46] , GOUT[47] ); - BLOCK0 U147 (A[47] , B[47] , POUT[47] , GOUT[48] ); - BLOCK0 U148 (A[48] , B[48] , POUT[48] , GOUT[49] ); - BLOCK0 U149 (A[49] , B[49] , POUT[49] , GOUT[50] ); - BLOCK0 U150 (A[50] , B[50] , POUT[50] , GOUT[51] ); - BLOCK0 U151 (A[51] , B[51] , POUT[51] , GOUT[52] ); - BLOCK0 U152 (A[52] , B[52] , POUT[52] , GOUT[53] ); - BLOCK0 U153 (A[53] , B[53] , POUT[53] , GOUT[54] ); - BLOCK0 U154 (A[54] , B[54] , POUT[54] , GOUT[55] ); - BLOCK0 U155 (A[55] , B[55] , POUT[55] , GOUT[56] ); - BLOCK0 U156 (A[56] , B[56] , POUT[56] , GOUT[57] ); - BLOCK0 U157 (A[57] , B[57] , POUT[57] , GOUT[58] ); - BLOCK0 U158 (A[58] , B[58] , POUT[58] , GOUT[59] ); - BLOCK0 U159 (A[59] , B[59] , POUT[59] , GOUT[60] ); - BLOCK0 U160 (A[60] , B[60] , POUT[60] , GOUT[61] ); - BLOCK0 U161 (A[61] , B[61] , POUT[61] , GOUT[62] ); - BLOCK0 U162 (A[62] , B[62] , POUT[62] , GOUT[63] ); - BLOCK0 U163 (A[63] , B[63] , POUT[63] , GOUT[64] ); - INVBLOCK U2 (CIN , GOUT[0] ); - -endmodule // PRESTAGE_64 - - -module DBLC_0_64 ( PIN, GIN, POUT, GOUT ); - - input [63:0] PIN; - input [64:0] GIN; - - output [62:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , GOUT[1] ); - BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , POUT[0] , GOUT[2] ); - BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , POUT[1] , GOUT[3] ); - BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , POUT[2] , GOUT[4] ); - BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , POUT[3] , GOUT[5] ); - BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , POUT[4] , GOUT[6] ); - BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , POUT[5] , GOUT[7] ); - BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , POUT[6] , GOUT[8] ); - BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , POUT[7] , GOUT[9] ); - BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , POUT[8] , GOUT[10] ); - BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , POUT[9] , GOUT[11] ); - BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , POUT[10] , GOUT[12] ); - BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , POUT[11] , GOUT[13] ); - BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , POUT[12] , GOUT[14] ); - BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , POUT[13] , GOUT[15] ); - BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , POUT[14] , GOUT[16] ); - BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , POUT[15] , GOUT[17] ); - BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , POUT[16] , GOUT[18] ); - BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , POUT[17] , GOUT[19] ); - BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , POUT[18] , GOUT[20] ); - BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , POUT[19] , GOUT[21] ); - BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , POUT[20] , GOUT[22] ); - BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , POUT[21] , GOUT[23] ); - BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , POUT[22] , GOUT[24] ); - BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , POUT[23] , GOUT[25] ); - BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , POUT[24] , GOUT[26] ); - BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , POUT[25] , GOUT[27] ); - BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , POUT[26] , GOUT[28] ); - BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , POUT[27] , GOUT[29] ); - BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , POUT[28] , GOUT[30] ); - BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , POUT[29] , GOUT[31] ); - BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , POUT[30] , GOUT[32] ); - BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , POUT[31] , GOUT[33] ); - BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , POUT[32] , GOUT[34] ); - BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , POUT[33] , GOUT[35] ); - BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , POUT[34] , GOUT[36] ); - BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , POUT[35] , GOUT[37] ); - BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , POUT[36] , GOUT[38] ); - BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , POUT[37] , GOUT[39] ); - BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , POUT[38] , GOUT[40] ); - BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , POUT[39] , GOUT[41] ); - BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , POUT[40] , GOUT[42] ); - BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , POUT[41] , GOUT[43] ); - BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , POUT[42] , GOUT[44] ); - BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , POUT[43] , GOUT[45] ); - BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , POUT[44] , GOUT[46] ); - BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , POUT[45] , GOUT[47] ); - BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , POUT[46] , GOUT[48] ); - BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , POUT[47] , GOUT[49] ); - BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , POUT[48] , GOUT[50] ); - BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , POUT[49] , GOUT[51] ); - BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , POUT[50] , GOUT[52] ); - BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , POUT[51] , GOUT[53] ); - BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , POUT[52] , GOUT[54] ); - BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , POUT[53] , GOUT[55] ); - BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , POUT[54] , GOUT[56] ); - BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , POUT[55] , GOUT[57] ); - BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , POUT[56] , GOUT[58] ); - BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , POUT[57] , GOUT[59] ); - BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , POUT[58] , GOUT[60] ); - BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , POUT[59] , GOUT[61] ); - BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , POUT[60] , GOUT[62] ); - BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , POUT[61] , GOUT[63] ); - BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , POUT[62] , GOUT[64] ); - -endmodule // DBLC_0_64 - - -module DBLC_1_64 ( PIN, GIN, POUT, GOUT ); - - input [62:0] PIN; - input [64:0] GIN; - - output [60:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , GOUT[2] ); - BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , GOUT[3] ); - BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , POUT[0] , GOUT[4] ); - BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , POUT[1] , GOUT[5] ); - BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , POUT[2] , GOUT[6] ); - BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , POUT[3] , GOUT[7] ); - BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , POUT[4] , GOUT[8] ); - BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , POUT[5] , GOUT[9] ); - BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , POUT[6] , GOUT[10] ); - BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , POUT[7] , GOUT[11] ); - BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , POUT[8] , GOUT[12] ); - BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , POUT[9] , GOUT[13] ); - BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , POUT[10] , GOUT[14] ); - BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , POUT[11] , GOUT[15] ); - BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , POUT[12] , GOUT[16] ); - BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , POUT[13] , GOUT[17] ); - BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , POUT[14] , GOUT[18] ); - BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , POUT[15] , GOUT[19] ); - BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , POUT[16] , GOUT[20] ); - BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , POUT[17] , GOUT[21] ); - BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , POUT[18] , GOUT[22] ); - BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , POUT[19] , GOUT[23] ); - BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , POUT[20] , GOUT[24] ); - BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , POUT[21] , GOUT[25] ); - BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , POUT[22] , GOUT[26] ); - BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , POUT[23] , GOUT[27] ); - BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , POUT[24] , GOUT[28] ); - BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , POUT[25] , GOUT[29] ); - BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , POUT[26] , GOUT[30] ); - BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , POUT[27] , GOUT[31] ); - BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , POUT[28] , GOUT[32] ); - BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , POUT[29] , GOUT[33] ); - BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , POUT[30] , GOUT[34] ); - BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , POUT[31] , GOUT[35] ); - BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , POUT[32] , GOUT[36] ); - BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , POUT[33] , GOUT[37] ); - BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , POUT[34] , GOUT[38] ); - BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , POUT[35] , GOUT[39] ); - BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , POUT[36] , GOUT[40] ); - BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , POUT[37] , GOUT[41] ); - BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , POUT[38] , GOUT[42] ); - BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , POUT[39] , GOUT[43] ); - BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , POUT[40] , GOUT[44] ); - BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , POUT[41] , GOUT[45] ); - BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , POUT[42] , GOUT[46] ); - BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , POUT[43] , GOUT[47] ); - BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , POUT[44] , GOUT[48] ); - BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , POUT[45] , GOUT[49] ); - BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , POUT[46] , GOUT[50] ); - BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , POUT[47] , GOUT[51] ); - BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , POUT[48] , GOUT[52] ); - BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , POUT[49] , GOUT[53] ); - BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , POUT[50] , GOUT[54] ); - BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , POUT[51] , GOUT[55] ); - BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , POUT[52] , GOUT[56] ); - BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , POUT[53] , GOUT[57] ); - BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , POUT[54] , GOUT[58] ); - BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , POUT[55] , GOUT[59] ); - BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , POUT[56] , GOUT[60] ); - BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , POUT[57] , GOUT[61] ); - BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , POUT[58] , GOUT[62] ); - BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , POUT[59] , GOUT[63] ); - BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , POUT[60] , GOUT[64] ); - -endmodule // DBLC_1_64 - - -module DBLC_2_64 ( PIN, GIN, POUT, GOUT ); - - input [60:0] PIN; - input [64:0] GIN; - - output [56:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , GOUT[4] ); - BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , GOUT[5] ); - BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , GOUT[6] ); - BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , GOUT[7] ); - BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , POUT[0] , GOUT[8] ); - BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , POUT[1] , GOUT[9] ); - BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , POUT[2] , GOUT[10] ); - BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , POUT[3] , GOUT[11] ); - BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , POUT[4] , GOUT[12] ); - BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , POUT[5] , GOUT[13] ); - BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , POUT[6] , GOUT[14] ); - BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , POUT[7] , GOUT[15] ); - BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , POUT[8] , GOUT[16] ); - BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , POUT[9] , GOUT[17] ); - BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , POUT[10] , GOUT[18] ); - BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , POUT[11] , GOUT[19] ); - BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , POUT[12] , GOUT[20] ); - BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , POUT[13] , GOUT[21] ); - BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , POUT[14] , GOUT[22] ); - BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , POUT[15] , GOUT[23] ); - BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , POUT[16] , GOUT[24] ); - BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , POUT[17] , GOUT[25] ); - BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , POUT[18] , GOUT[26] ); - BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , POUT[19] , GOUT[27] ); - BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , POUT[20] , GOUT[28] ); - BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , POUT[21] , GOUT[29] ); - BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , POUT[22] , GOUT[30] ); - BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , POUT[23] , GOUT[31] ); - BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , POUT[24] , GOUT[32] ); - BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , POUT[25] , GOUT[33] ); - BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , POUT[26] , GOUT[34] ); - BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , POUT[27] , GOUT[35] ); - BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , POUT[28] , GOUT[36] ); - BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , POUT[29] , GOUT[37] ); - BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , POUT[30] , GOUT[38] ); - BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , POUT[31] , GOUT[39] ); - BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , POUT[32] , GOUT[40] ); - BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , POUT[33] , GOUT[41] ); - BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , POUT[34] , GOUT[42] ); - BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , POUT[35] , GOUT[43] ); - BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , POUT[36] , GOUT[44] ); - BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , POUT[37] , GOUT[45] ); - BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , POUT[38] , GOUT[46] ); - BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , POUT[39] , GOUT[47] ); - BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , POUT[40] , GOUT[48] ); - BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , POUT[41] , GOUT[49] ); - BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , POUT[42] , GOUT[50] ); - BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , POUT[43] , GOUT[51] ); - BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , POUT[44] , GOUT[52] ); - BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , POUT[45] , GOUT[53] ); - BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , POUT[46] , GOUT[54] ); - BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , POUT[47] , GOUT[55] ); - BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , POUT[48] , GOUT[56] ); - BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , POUT[49] , GOUT[57] ); - BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , POUT[50] , GOUT[58] ); - BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , POUT[51] , GOUT[59] ); - BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , POUT[52] , GOUT[60] ); - BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , POUT[53] , GOUT[61] ); - BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , POUT[54] , GOUT[62] ); - BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , POUT[55] , GOUT[63] ); - BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , POUT[56] , GOUT[64] ); - -endmodule // DBLC_2_64 - - -module DBLC_3_64 ( PIN, GIN, POUT, GOUT ); - - input [56:0] PIN; - input [64:0] GIN; - - output [48:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , GOUT[8] ); - BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , GOUT[9] ); - BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , GOUT[10] ); - BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , GOUT[11] ); - BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , GOUT[12] ); - BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , GOUT[13] ); - BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , GOUT[14] ); - BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , GOUT[15] ); - BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , POUT[0] , GOUT[16] ); - BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , POUT[1] , GOUT[17] ); - BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , POUT[2] , GOUT[18] ); - BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , POUT[3] , GOUT[19] ); - BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , POUT[4] , GOUT[20] ); - BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , POUT[5] , GOUT[21] ); - BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , POUT[6] , GOUT[22] ); - BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , POUT[7] , GOUT[23] ); - BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , POUT[8] , GOUT[24] ); - BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , POUT[9] , GOUT[25] ); - BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , POUT[10] , GOUT[26] ); - BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , POUT[11] , GOUT[27] ); - BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , POUT[12] , GOUT[28] ); - BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , POUT[13] , GOUT[29] ); - BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , POUT[14] , GOUT[30] ); - BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , POUT[15] , GOUT[31] ); - BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , POUT[16] , GOUT[32] ); - BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , POUT[17] , GOUT[33] ); - BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , POUT[18] , GOUT[34] ); - BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , POUT[19] , GOUT[35] ); - BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , POUT[20] , GOUT[36] ); - BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , POUT[21] , GOUT[37] ); - BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , POUT[22] , GOUT[38] ); - BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , POUT[23] , GOUT[39] ); - BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , POUT[24] , GOUT[40] ); - BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , POUT[25] , GOUT[41] ); - BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , POUT[26] , GOUT[42] ); - BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , POUT[27] , GOUT[43] ); - BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , POUT[28] , GOUT[44] ); - BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , POUT[29] , GOUT[45] ); - BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , POUT[30] , GOUT[46] ); - BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , POUT[31] , GOUT[47] ); - BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , POUT[32] , GOUT[48] ); - BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , POUT[33] , GOUT[49] ); - BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , POUT[34] , GOUT[50] ); - BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , POUT[35] , GOUT[51] ); - BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , POUT[36] , GOUT[52] ); - BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , POUT[37] , GOUT[53] ); - BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , POUT[38] , GOUT[54] ); - BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , POUT[39] , GOUT[55] ); - BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , POUT[40] , GOUT[56] ); - BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , POUT[41] , GOUT[57] ); - BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , POUT[42] , GOUT[58] ); - BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , POUT[43] , GOUT[59] ); - BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , POUT[44] , GOUT[60] ); - BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , POUT[45] , GOUT[61] ); - BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , POUT[46] , GOUT[62] ); - BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , POUT[47] , GOUT[63] ); - BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , POUT[48] , GOUT[64] ); - -endmodule // DBLC_3_64 - - -module DBLC_4_64 ( PIN, GIN, POUT, GOUT ); - - input [48:0] PIN; - input [64:0] GIN; - - output [32:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , GOUT[16] ); - BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , GOUT[17] ); - BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , GOUT[18] ); - BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , GOUT[19] ); - BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , GOUT[20] ); - BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , GOUT[21] ); - BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , GOUT[22] ); - BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , GOUT[23] ); - BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , GOUT[24] ); - BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , GOUT[25] ); - BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , GOUT[26] ); - BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , GOUT[27] ); - BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , GOUT[28] ); - BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , GOUT[29] ); - BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , GOUT[30] ); - BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , GOUT[31] ); - BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , POUT[0] , GOUT[32] ); - BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , POUT[1] , GOUT[33] ); - BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , POUT[2] , GOUT[34] ); - BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , POUT[3] , GOUT[35] ); - BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , POUT[4] , GOUT[36] ); - BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , POUT[5] , GOUT[37] ); - BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , POUT[6] , GOUT[38] ); - BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , POUT[7] , GOUT[39] ); - BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , POUT[8] , GOUT[40] ); - BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , POUT[9] , GOUT[41] ); - BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , POUT[10] , GOUT[42] ); - BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , POUT[11] , GOUT[43] ); - BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , POUT[12] , GOUT[44] ); - BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , POUT[13] , GOUT[45] ); - BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , POUT[14] , GOUT[46] ); - BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , POUT[15] , GOUT[47] ); - BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , POUT[16] , GOUT[48] ); - BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , POUT[17] , GOUT[49] ); - BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , POUT[18] , GOUT[50] ); - BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , POUT[19] , GOUT[51] ); - BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , POUT[20] , GOUT[52] ); - BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , POUT[21] , GOUT[53] ); - BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , POUT[22] , GOUT[54] ); - BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , POUT[23] , GOUT[55] ); - BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , POUT[24] , GOUT[56] ); - BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , POUT[25] , GOUT[57] ); - BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , POUT[26] , GOUT[58] ); - BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , POUT[27] , GOUT[59] ); - BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , POUT[28] , GOUT[60] ); - BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , POUT[29] , GOUT[61] ); - BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , POUT[30] , GOUT[62] ); - BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , POUT[31] , GOUT[63] ); - BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , POUT[32] , GOUT[64] ); - -endmodule // DBLC_4_64 - - -module DBLC_5_64 ( PIN, GIN, POUT, GOUT ); - - input [32:0] PIN; - input [64:0] GIN; - - output [0:0] POUT; - output [64:0] GOUT; - - INVBLOCK U10 (GIN[0] , GOUT[0] ); - INVBLOCK U11 (GIN[1] , GOUT[1] ); - INVBLOCK U12 (GIN[2] , GOUT[2] ); - INVBLOCK U13 (GIN[3] , GOUT[3] ); - INVBLOCK U14 (GIN[4] , GOUT[4] ); - INVBLOCK U15 (GIN[5] , GOUT[5] ); - INVBLOCK U16 (GIN[6] , GOUT[6] ); - INVBLOCK U17 (GIN[7] , GOUT[7] ); - INVBLOCK U18 (GIN[8] , GOUT[8] ); - INVBLOCK U19 (GIN[9] , GOUT[9] ); - INVBLOCK U110 (GIN[10] , GOUT[10] ); - INVBLOCK U111 (GIN[11] , GOUT[11] ); - INVBLOCK U112 (GIN[12] , GOUT[12] ); - INVBLOCK U113 (GIN[13] , GOUT[13] ); - INVBLOCK U114 (GIN[14] , GOUT[14] ); - INVBLOCK U115 (GIN[15] , GOUT[15] ); - INVBLOCK U116 (GIN[16] , GOUT[16] ); - INVBLOCK U117 (GIN[17] , GOUT[17] ); - INVBLOCK U118 (GIN[18] , GOUT[18] ); - INVBLOCK U119 (GIN[19] , GOUT[19] ); - INVBLOCK U120 (GIN[20] , GOUT[20] ); - INVBLOCK U121 (GIN[21] , GOUT[21] ); - INVBLOCK U122 (GIN[22] , GOUT[22] ); - INVBLOCK U123 (GIN[23] , GOUT[23] ); - INVBLOCK U124 (GIN[24] , GOUT[24] ); - INVBLOCK U125 (GIN[25] , GOUT[25] ); - INVBLOCK U126 (GIN[26] , GOUT[26] ); - INVBLOCK U127 (GIN[27] , GOUT[27] ); - INVBLOCK U128 (GIN[28] , GOUT[28] ); - INVBLOCK U129 (GIN[29] , GOUT[29] ); - INVBLOCK U130 (GIN[30] , GOUT[30] ); - INVBLOCK U131 (GIN[31] , GOUT[31] ); - BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , GOUT[32] ); - BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , GOUT[33] ); - BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , GOUT[34] ); - BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , GOUT[35] ); - BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , GOUT[36] ); - BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , GOUT[37] ); - BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , GOUT[38] ); - BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , GOUT[39] ); - BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , GOUT[40] ); - BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , GOUT[41] ); - BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , GOUT[42] ); - BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , GOUT[43] ); - BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , GOUT[44] ); - BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , GOUT[45] ); - BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , GOUT[46] ); - BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , GOUT[47] ); - BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , GOUT[48] ); - BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , GOUT[49] ); - BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , GOUT[50] ); - BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , GOUT[51] ); - BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , GOUT[52] ); - BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , GOUT[53] ); - BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , GOUT[54] ); - BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , GOUT[55] ); - BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , GOUT[56] ); - BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , GOUT[57] ); - BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , GOUT[58] ); - BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , GOUT[59] ); - BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , GOUT[60] ); - BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , GOUT[61] ); - BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , GOUT[62] ); - BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , GOUT[63] ); - BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , POUT[0] , GOUT[64] ); - -endmodule // DBLC_5_64 - - -module XORSTAGE_64 ( A, B, PBIT, CARRY, SUM, COUT ); - - input [63:0] A; - input [63:0] B; - input PBIT; - input [64:0] CARRY; - - output [63:0] SUM; - output COUT; - - XXOR1 U20 (A[0] , B[0] , CARRY[0] , SUM[0] ); - XXOR1 U21 (A[1] , B[1] , CARRY[1] , SUM[1] ); - XXOR1 U22 (A[2] , B[2] , CARRY[2] , SUM[2] ); - XXOR1 U23 (A[3] , B[3] , CARRY[3] , SUM[3] ); - XXOR1 U24 (A[4] , B[4] , CARRY[4] , SUM[4] ); - XXOR1 U25 (A[5] , B[5] , CARRY[5] , SUM[5] ); - XXOR1 U26 (A[6] , B[6] , CARRY[6] , SUM[6] ); - XXOR1 U27 (A[7] , B[7] , CARRY[7] , SUM[7] ); - XXOR1 U28 (A[8] , B[8] , CARRY[8] , SUM[8] ); - XXOR1 U29 (A[9] , B[9] , CARRY[9] , SUM[9] ); - XXOR1 U210 (A[10] , B[10] , CARRY[10] , SUM[10] ); - XXOR1 U211 (A[11] , B[11] , CARRY[11] , SUM[11] ); - XXOR1 U212 (A[12] , B[12] , CARRY[12] , SUM[12] ); - XXOR1 U213 (A[13] , B[13] , CARRY[13] , SUM[13] ); - XXOR1 U214 (A[14] , B[14] , CARRY[14] , SUM[14] ); - XXOR1 U215 (A[15] , B[15] , CARRY[15] , SUM[15] ); - XXOR1 U216 (A[16] , B[16] , CARRY[16] , SUM[16] ); - XXOR1 U217 (A[17] , B[17] , CARRY[17] , SUM[17] ); - XXOR1 U218 (A[18] , B[18] , CARRY[18] , SUM[18] ); - XXOR1 U219 (A[19] , B[19] , CARRY[19] , SUM[19] ); - XXOR1 U220 (A[20] , B[20] , CARRY[20] , SUM[20] ); - XXOR1 U221 (A[21] , B[21] , CARRY[21] , SUM[21] ); - XXOR1 U222 (A[22] , B[22] , CARRY[22] , SUM[22] ); - XXOR1 U223 (A[23] , B[23] , CARRY[23] , SUM[23] ); - XXOR1 U224 (A[24] , B[24] , CARRY[24] , SUM[24] ); - XXOR1 U225 (A[25] , B[25] , CARRY[25] , SUM[25] ); - XXOR1 U226 (A[26] , B[26] , CARRY[26] , SUM[26] ); - XXOR1 U227 (A[27] , B[27] , CARRY[27] , SUM[27] ); - XXOR1 U228 (A[28] , B[28] , CARRY[28] , SUM[28] ); - XXOR1 U229 (A[29] , B[29] , CARRY[29] , SUM[29] ); - XXOR1 U230 (A[30] , B[30] , CARRY[30] , SUM[30] ); - XXOR1 U231 (A[31] , B[31] , CARRY[31] , SUM[31] ); - XXOR1 U232 (A[32] , B[32] , CARRY[32] , SUM[32] ); - XXOR1 U233 (A[33] , B[33] , CARRY[33] , SUM[33] ); - XXOR1 U234 (A[34] , B[34] , CARRY[34] , SUM[34] ); - XXOR1 U235 (A[35] , B[35] , CARRY[35] , SUM[35] ); - XXOR1 U236 (A[36] , B[36] , CARRY[36] , SUM[36] ); - XXOR1 U237 (A[37] , B[37] , CARRY[37] , SUM[37] ); - XXOR1 U238 (A[38] , B[38] , CARRY[38] , SUM[38] ); - XXOR1 U239 (A[39] , B[39] , CARRY[39] , SUM[39] ); - XXOR1 U240 (A[40] , B[40] , CARRY[40] , SUM[40] ); - XXOR1 U241 (A[41] , B[41] , CARRY[41] , SUM[41] ); - XXOR1 U242 (A[42] , B[42] , CARRY[42] , SUM[42] ); - XXOR1 U243 (A[43] , B[43] , CARRY[43] , SUM[43] ); - XXOR1 U244 (A[44] , B[44] , CARRY[44] , SUM[44] ); - XXOR1 U245 (A[45] , B[45] , CARRY[45] , SUM[45] ); - XXOR1 U246 (A[46] , B[46] , CARRY[46] , SUM[46] ); - XXOR1 U247 (A[47] , B[47] , CARRY[47] , SUM[47] ); - XXOR1 U248 (A[48] , B[48] , CARRY[48] , SUM[48] ); - XXOR1 U249 (A[49] , B[49] , CARRY[49] , SUM[49] ); - XXOR1 U250 (A[50] , B[50] , CARRY[50] , SUM[50] ); - XXOR1 U251 (A[51] , B[51] , CARRY[51] , SUM[51] ); - XXOR1 U252 (A[52] , B[52] , CARRY[52] , SUM[52] ); - XXOR1 U253 (A[53] , B[53] , CARRY[53] , SUM[53] ); - XXOR1 U254 (A[54] , B[54] , CARRY[54] , SUM[54] ); - XXOR1 U255 (A[55] , B[55] , CARRY[55] , SUM[55] ); - XXOR1 U256 (A[56] , B[56] , CARRY[56] , SUM[56] ); - XXOR1 U257 (A[57] , B[57] , CARRY[57] , SUM[57] ); - XXOR1 U258 (A[58] , B[58] , CARRY[58] , SUM[58] ); - XXOR1 U259 (A[59] , B[59] , CARRY[59] , SUM[59] ); - XXOR1 U260 (A[60] , B[60] , CARRY[60] , SUM[60] ); - XXOR1 U261 (A[61] , B[61] , CARRY[61] , SUM[61] ); - XXOR1 U262 (A[62] , B[62] , CARRY[62] , SUM[62] ); - XXOR1 U263 (A[63] , B[63] , CARRY[63] , SUM[63] ); - BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , COUT ); - -endmodule // XORSTAGE_64 - - -module DBLCTREE_64 ( PIN, GIN, GOUT, POUT ); - - input [63:0] PIN; - input [64:0] GIN; - - output [64:0] GOUT; - output [0:0] POUT; - - wire [62:0] INTPROP_0; - wire [64:0] INTGEN_0; - wire [60:0] INTPROP_1; - wire [64:0] INTGEN_1; - wire [56:0] INTPROP_2; - wire [64:0] INTGEN_2; - wire [48:0] INTPROP_3; - wire [64:0] INTGEN_3; - wire [32:0] INTPROP_4; - wire [64:0] INTGEN_4; - - DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) ); - DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) ); - DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) ); - DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) ); - DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) ); - DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .POUT(POUT) , .GOUT(GOUT) ); - -endmodule // DBLCTREE_64 - - -module DBLCADDER_64_64 ( OPA, OPB, CIN, SUM, COUT ); - - input [63:0] OPA; - input [63:0] OPB; - input CIN; - - output [63:0] SUM; - output COUT; - - wire [63:0] INTPROP; - wire [64:0] INTGEN; - wire [0:0] PBIT; - wire [64:0] CARRY; - - PRESTAGE_64 U1 (OPA , OPB , CIN , INTPROP , INTGEN ); - DBLCTREE_64 U2 (INTPROP , INTGEN , CARRY , PBIT ); - XORSTAGE_64 U3 (OPA[63:0] , OPB[63:0] , PBIT[0] , CARRY[64:0] , SUM , COUT ); - -endmodule diff --git a/pipelined/src/fpu/cla12.sv b/pipelined/src/fpu/cla12.sv deleted file mode 100644 index b098228c8..000000000 --- a/pipelined/src/fpu/cla12.sv +++ /dev/null @@ -1,332 +0,0 @@ -// This module implements a 12-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla12 (S, CO, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - output CO; - - wire [63:0] A,B,Q;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO = Q[12]; - -endmodule //cla52 - -// This module implements a 12-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub12 (S, X, Y); - - input [11:0] X; - input [11:0] Y; - - output [11:0] S; - - wire [63:0] A,B,Q,Bbar;//***KEP was 0:63 - changed due to lint warning - wire CO; - wire LOGIC0; - wire VDD; - logic CO_12; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign VDD = 1; - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = LOGIC0; - assign B[12] = LOGIC0; - assign A[13] = LOGIC0; - assign B[13] = LOGIC0; - assign A[14] = LOGIC0; - assign B[14] = LOGIC0; - assign A[15] = LOGIC0; - assign B[15] = LOGIC0; - assign A[16] = LOGIC0; - assign B[16] = LOGIC0; - assign A[17] = LOGIC0; - assign B[17] = LOGIC0; - assign A[18] = LOGIC0; - assign B[18] = LOGIC0; - assign A[19] = LOGIC0; - assign B[19] = LOGIC0; - assign A[20] = LOGIC0; - assign B[20] = LOGIC0; - assign A[21] = LOGIC0; - assign B[21] = LOGIC0; - assign A[22] = LOGIC0; - assign B[22] = LOGIC0; - assign A[23] = LOGIC0; - assign B[23] = LOGIC0; - assign A[24] = LOGIC0; - assign B[24] = LOGIC0; - assign A[25] = LOGIC0; - assign B[25] = LOGIC0; - assign A[26] = LOGIC0; - assign B[26] = LOGIC0; - assign A[27] = LOGIC0; - assign B[27] = LOGIC0; - assign A[28] = LOGIC0; - assign B[28] = LOGIC0; - assign A[29] = LOGIC0; - assign B[29] = LOGIC0; - assign A[30] = LOGIC0; - assign B[30] = LOGIC0; - assign A[31] = LOGIC0; - assign B[31] = LOGIC0; - assign A[32] = LOGIC0; - assign B[32] = LOGIC0; - assign A[33] = LOGIC0; - assign B[33] = LOGIC0; - assign A[34] = LOGIC0; - assign B[34] = LOGIC0; - assign A[35] = LOGIC0; - assign B[35] = LOGIC0; - assign A[36] = LOGIC0; - assign B[36] = LOGIC0; - assign A[37] = LOGIC0; - assign B[37] = LOGIC0; - assign A[38] = LOGIC0; - assign B[38] = LOGIC0; - assign A[39] = LOGIC0; - assign B[39] = LOGIC0; - assign A[40] = LOGIC0; - assign B[40] = LOGIC0; - assign A[41] = LOGIC0; - assign B[41] = LOGIC0; - assign A[42] = LOGIC0; - assign B[42] = LOGIC0; - assign A[43] = LOGIC0; - assign B[43] = LOGIC0; - assign A[44] = LOGIC0; - assign B[44] = LOGIC0; - assign A[45] = LOGIC0; - assign B[45] = LOGIC0; - assign A[46] = LOGIC0; - assign B[46] = LOGIC0; - assign A[47] = LOGIC0; - assign B[47] = LOGIC0; - assign A[48] = LOGIC0; - assign B[48] = LOGIC0; - assign A[49] = LOGIC0; - assign B[49] = LOGIC0; - assign A[50] = LOGIC0; - assign B[50] = LOGIC0; - assign A[51] = LOGIC0; - assign B[51] = LOGIC0; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign CO_12 = Q[12]; - -endmodule //cla_sub52 diff --git a/pipelined/src/fpu/cla52.sv b/pipelined/src/fpu/cla52.sv deleted file mode 100644 index 5f818fbd8..000000000 --- a/pipelined/src/fpu/cla52.sv +++ /dev/null @@ -1,409 +0,0 @@ -// This module implements a 52-bit carry lookahead adder. It is used -// for rounding in the floating point adder. - -module cla52 (S, CO, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - output CO; - - wire [63:0] A,B,Q;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_64; - - assign LOGIC0 = 0; - assign CIN = 0; - DBLCADDER_64_64 U1 (A , B , CIN, Q , CO_64); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO = Q[52]; - -endmodule //cla52 - -// This module implements a 52-bit carry lookahead subtractor. It is used -// for rounding in the floating point adder. - -module cla_sub52 (S, X, Y); - - input [51:0] X; - input [51:0] Y; - - output [51:0] S; - - wire [63:0] A,B,Q,Bbar;//***KEP was 0:63 - changed due to lint warning - wire LOGIC0; - wire CIN; - wire CO_52; - wire CO_64; - - assign Bbar = ~B; - assign LOGIC0 = 0; - assign CIN = 0; - - DBLCADDER_64_64 U1 (A , Bbar , CIN, Q , CO_64); - - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = LOGIC0; - assign B[52] = LOGIC0; - assign A[53] = LOGIC0; - assign B[53] = LOGIC0; - assign A[54] = LOGIC0; - assign B[54] = LOGIC0; - assign A[55] = LOGIC0; - assign B[55] = LOGIC0; - assign A[56] = LOGIC0; - assign B[56] = LOGIC0; - assign A[57] = LOGIC0; - assign B[57] = LOGIC0; - assign A[58] = LOGIC0; - assign B[58] = LOGIC0; - assign A[59] = LOGIC0; - assign B[59] = LOGIC0; - assign A[60] = LOGIC0; - assign B[60] = LOGIC0; - assign A[61] = LOGIC0; - assign B[61] = LOGIC0; - assign A[62] = LOGIC0; - assign B[62] = LOGIC0; - assign A[63] = LOGIC0; - assign B[63] = LOGIC0; - - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign CO_52 = Q[52]; - -endmodule //cla_sub52 diff --git a/pipelined/src/fpu/cla64.sv b/pipelined/src/fpu/cla64.sv deleted file mode 100755 index 6d28be10f..000000000 --- a/pipelined/src/fpu/cla64.sv +++ /dev/null @@ -1,420 +0,0 @@ -// This module implements a 64-bit carry lookehead adder/subtractor. -// It is used to perform the primary addition in the floating point -// adder - -module cla64 (S, X, Y, Sub); - - input [63:0] X; - input [63:0] Y; - input Sub; - output [63:0] S; - wire CO; - wire [63:0] A,B,Q, Bbar; //***KEP was 0:63 - changed due to lint warning - - DBLCADDER_64_64 U1 (A , Bbar , Sub , Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = B ^ {64{Sub}}; - -endmodule // cla64 - -// This module performs 64-bit subtraction. It is used to get the two's complement -// of main addition or subtraction in the floating point adder. - -module cla_sub64 (S, X, Y); - - input [63:0] X; - input [63:0] Y; - - output [63:0] S; - - wire CO; - wire VDD = 1'b1; - wire [63:0] A,B,Q, Bbar; //***KEP was 0:63 - changed due to lint warning - - DBLCADDER_64_64 U1 (A , Bbar , VDD, Q , CO ); - assign A[0] = X[0]; - assign B[0] = Y[0]; - assign A[1] = X[1]; - assign B[1] = Y[1]; - assign A[2] = X[2]; - assign B[2] = Y[2]; - assign A[3] = X[3]; - assign B[3] = Y[3]; - assign A[4] = X[4]; - assign B[4] = Y[4]; - assign A[5] = X[5]; - assign B[5] = Y[5]; - assign A[6] = X[6]; - assign B[6] = Y[6]; - assign A[7] = X[7]; - assign B[7] = Y[7]; - assign A[8] = X[8]; - assign B[8] = Y[8]; - assign A[9] = X[9]; - assign B[9] = Y[9]; - assign A[10] = X[10]; - assign B[10] = Y[10]; - assign A[11] = X[11]; - assign B[11] = Y[11]; - assign A[12] = X[12]; - assign B[12] = Y[12]; - assign A[13] = X[13]; - assign B[13] = Y[13]; - assign A[14] = X[14]; - assign B[14] = Y[14]; - assign A[15] = X[15]; - assign B[15] = Y[15]; - assign A[16] = X[16]; - assign B[16] = Y[16]; - assign A[17] = X[17]; - assign B[17] = Y[17]; - assign A[18] = X[18]; - assign B[18] = Y[18]; - assign A[19] = X[19]; - assign B[19] = Y[19]; - assign A[20] = X[20]; - assign B[20] = Y[20]; - assign A[21] = X[21]; - assign B[21] = Y[21]; - assign A[22] = X[22]; - assign B[22] = Y[22]; - assign A[23] = X[23]; - assign B[23] = Y[23]; - assign A[24] = X[24]; - assign B[24] = Y[24]; - assign A[25] = X[25]; - assign B[25] = Y[25]; - assign A[26] = X[26]; - assign B[26] = Y[26]; - assign A[27] = X[27]; - assign B[27] = Y[27]; - assign A[28] = X[28]; - assign B[28] = Y[28]; - assign A[29] = X[29]; - assign B[29] = Y[29]; - assign A[30] = X[30]; - assign B[30] = Y[30]; - assign A[31] = X[31]; - assign B[31] = Y[31]; - assign A[32] = X[32]; - assign B[32] = Y[32]; - assign A[33] = X[33]; - assign B[33] = Y[33]; - assign A[34] = X[34]; - assign B[34] = Y[34]; - assign A[35] = X[35]; - assign B[35] = Y[35]; - assign A[36] = X[36]; - assign B[36] = Y[36]; - assign A[37] = X[37]; - assign B[37] = Y[37]; - assign A[38] = X[38]; - assign B[38] = Y[38]; - assign A[39] = X[39]; - assign B[39] = Y[39]; - assign A[40] = X[40]; - assign B[40] = Y[40]; - assign A[41] = X[41]; - assign B[41] = Y[41]; - assign A[42] = X[42]; - assign B[42] = Y[42]; - assign A[43] = X[43]; - assign B[43] = Y[43]; - assign A[44] = X[44]; - assign B[44] = Y[44]; - assign A[45] = X[45]; - assign B[45] = Y[45]; - assign A[46] = X[46]; - assign B[46] = Y[46]; - assign A[47] = X[47]; - assign B[47] = Y[47]; - assign A[48] = X[48]; - assign B[48] = Y[48]; - assign A[49] = X[49]; - assign B[49] = Y[49]; - assign A[50] = X[50]; - assign B[50] = Y[50]; - assign A[51] = X[51]; - assign B[51] = Y[51]; - assign A[52] = X[52]; - assign B[52] = Y[52]; - assign A[53] = X[53]; - assign B[53] = Y[53]; - assign A[54] = X[54]; - assign B[54] = Y[54]; - assign A[55] = X[55]; - assign B[55] = Y[55]; - assign A[56] = X[56]; - assign B[56] = Y[56]; - assign A[57] = X[57]; - assign B[57] = Y[57]; - assign A[58] = X[58]; - assign B[58] = Y[58]; - assign A[59] = X[59]; - assign B[59] = Y[59]; - assign A[60] = X[60]; - assign B[60] = Y[60]; - assign A[61] = X[61]; - assign B[61] = Y[61]; - assign A[62] = X[62]; - assign B[62] = Y[62]; - assign A[63] = X[63]; - assign B[63] = Y[63]; - assign S[0] = Q[0]; - assign S[1] = Q[1]; - assign S[2] = Q[2]; - assign S[3] = Q[3]; - assign S[4] = Q[4]; - assign S[5] = Q[5]; - assign S[6] = Q[6]; - assign S[7] = Q[7]; - assign S[8] = Q[8]; - assign S[9] = Q[9]; - assign S[10] = Q[10]; - assign S[11] = Q[11]; - assign S[12] = Q[12]; - assign S[13] = Q[13]; - assign S[14] = Q[14]; - assign S[15] = Q[15]; - assign S[16] = Q[16]; - assign S[17] = Q[17]; - assign S[18] = Q[18]; - assign S[19] = Q[19]; - assign S[20] = Q[20]; - assign S[21] = Q[21]; - assign S[22] = Q[22]; - assign S[23] = Q[23]; - assign S[24] = Q[24]; - assign S[25] = Q[25]; - assign S[26] = Q[26]; - assign S[27] = Q[27]; - assign S[28] = Q[28]; - assign S[29] = Q[29]; - assign S[30] = Q[30]; - assign S[31] = Q[31]; - assign S[32] = Q[32]; - assign S[33] = Q[33]; - assign S[34] = Q[34]; - assign S[35] = Q[35]; - assign S[36] = Q[36]; - assign S[37] = Q[37]; - assign S[38] = Q[38]; - assign S[39] = Q[39]; - assign S[40] = Q[40]; - assign S[41] = Q[41]; - assign S[42] = Q[42]; - assign S[43] = Q[43]; - assign S[44] = Q[44]; - assign S[45] = Q[45]; - assign S[46] = Q[46]; - assign S[47] = Q[47]; - assign S[48] = Q[48]; - assign S[49] = Q[49]; - assign S[50] = Q[50]; - assign S[51] = Q[51]; - assign S[52] = Q[52]; - assign S[53] = Q[53]; - assign S[54] = Q[54]; - assign S[55] = Q[55]; - assign S[56] = Q[56]; - assign S[57] = Q[57]; - assign S[58] = Q[58]; - assign S[59] = Q[59]; - assign S[60] = Q[60]; - assign S[61] = Q[61]; - assign S[62] = Q[62]; - assign S[63] = Q[63]; - assign Bbar = ~B; - -endmodule // cla_sub64 \ No newline at end of file diff --git a/pipelined/src/fpu/convert_inputs.sv b/pipelined/src/fpu/convert_inputs.sv deleted file mode 100755 index aec1aa017..000000000 --- a/pipelined/src/fpu/convert_inputs.sv +++ /dev/null @@ -1,74 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Floating point divider/square root top unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module convert_inputs( - input [63:0] op1, // 1st input operand (A) - input [63:0] op2, // 2nd input operand (B) - input [2:0] op_type, // Function opcode - input P, // Result Precision (0 for double, 1 for single) - - output [63:0] Float1, // Converted 1st input operand - output [63:0] Float2 // Converted 2nd input operand -); - - wire conv_SP; // Convert from SP to DP - wire Zexp1; // One if the exponent of op1 is zero - wire Zexp2; // One if the exponent of op2 is zero - wire Oexp1; // One if the exponent of op1 is all ones - wire Oexp2; // One if the exponent of op2 is all ones - - // Convert from single precision to double precision if (op_type is 11X - // and P is 0) or (op_type is not 11X and P is one). - assign conv_SP = ~P; - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(|op1[30:23]); - assign Zexp2 = ~(|op2[30:23]); - assign Oexp1 = (&op1[30:23]); - assign Oexp2 = (&op2[30:23]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = conv_SP ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~conv_SP}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = conv_SP ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~conv_SP}}; - - // Set the sign of Float1 based on its original sign and if the operation - // is negation (op_type = 101) or absolute value (op_type = 100) - - assign Float1[63] = conv_SP ? op1[31] : op1[63]; - assign Float2[63] = conv_SP ? op2[31] : op2[63]; - -endmodule // convert_inputs - diff --git a/pipelined/src/fpu/convert_inputs_div.sv b/pipelined/src/fpu/convert_inputs_div.sv deleted file mode 100755 index 9d6d75c22..000000000 --- a/pipelined/src/fpu/convert_inputs_div.sv +++ /dev/null @@ -1,47 +0,0 @@ -// This module takes as inputs two operands (op1 and op2) -// and the result precision (P). Based on the operation and precision, -// it conditionally converts single precision values to double -// precision values and modifies the sign of op1. -// The converted operands are Float1 and Float2. -module convert_inputs_div ( - - input logic [63:0] op1, // 1st input operand (A) - input logic [63:0] op2, // 2nd input operand (B) - input logic P, // Result Precision (0 for double, 1 for single) - input logic op_type, // Operation - - output logic [63:0] Float1, // Converted 1st input operand - output logic [63:0] Float2b // Converted 2nd input operand -); - - logic [63:0] Float2; - logic Zexp1; // One if the exponent of op1 is zero - logic Zexp2; // One if the exponent of op2 is zero - logic Oexp1; // One if the exponent of op1 is all ones - logic Oexp2; // One if the exponent of op2 is all ones - - // Test if the input exponent is zero, because if it is then the - // exponent of the converted number should be zero. - assign Zexp1 = ~(|op1[30:23]); - assign Zexp2 = ~(|op2[30:23]); - assign Oexp1 = (&op1[30:23]); - assign Oexp2 = (&op2[30:23]); - - // Conditionally convert op1. Lower 29 bits are zero for single precision. - assign Float1[62:29] = P ? {op1[30], {3{(~op1[30]&~Zexp1)|Oexp1}}, op1[29:0]} - : op1[62:29]; - assign Float1[28:0] = op1[28:0] & {29{~P}}; - - // Conditionally convert op2. Lower 29 bits are zero for single precision. - assign Float2[62:29] = P ? {op2[30], {3{(~op2[30]&~Zexp2)|Oexp2}}, op2[29:0]} - : op2[62:29]; - assign Float2[28:0] = op2[28:0] & {29{~P}}; - - // Set the sign of Float1 based on its original sign - assign Float1[63] = P ? op1[31] : op1[63]; - assign Float2[63] = P ? op2[31] : op2[63]; - - // For sqrt, assign Float2 same as Float1 for simplicity - assign Float2b = op_type ? Float1 : Float2; - -endmodule // convert_inputs \ No newline at end of file diff --git a/pipelined/src/fpu/cvtshiftcalc.sv b/pipelined/src/fpu/cvtshiftcalc.sv new file mode 100644 index 000000000..aef894f90 --- /dev/null +++ b/pipelined/src/fpu/cvtshiftcalc.sv @@ -0,0 +1,99 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Conversion shift calculation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module cvtshiftcalc( + input logic XZero, + input logic ToInt, + input logic IntToFp, + input logic [`NE:0] CvtCe, // the calculated expoent + input logic [`NF:0] Xm, // input mantissas + input logic [`FMTBITS-1:0] OutFmt, // output format + input logic [`CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (priority encoder) + input logic CvtResDenormUf, + output logic CvtResUf, + output logic [`CVTLEN+`NF:0] CvtShiftIn // number to be shifted +); + logic [$clog2(`NF):0] ResNegNF; // the result's fraction length negated (-NF) + + + /////////////////////////////////////////////////////////////////////////// + // shifter + /////////////////////////////////////////////////////////////////////////// + + // seclect the input to the shifter + // fp -> int: + // | `XLEN zeros | Mantissa | 0's if nessisary | + // Other problems: + // - if shifting to the right (neg CalcExp) then don't a 1 in the round bit (to prevent an incorrect plus 1 later durring rounding) + // - we do however want to keep the one in the sticky bit so set one of bits in the sticky bit area to 1 + // - ex: for the case 0010000.... (double) + // ??? -> fp: + // - if result is denormalized or underflowed then we want to shift right i.e. shift right then shift left: + // | `NF-1 zeros | Mantissa | 0's if nessisary | + // - otherwise: + // | LzcInM | 0's if nessisary | + // change to int shift to the left one + + always_comb + if (ToInt) CvtShiftIn = {{`XLEN{1'b0}}, Xm[`NF]&~CvtCe[`NE], Xm[`NF-1]|(CvtCe[`NE]&Xm[`NF]), Xm[`NF-2:0], {`CVTLEN-`XLEN{1'b0}}}; + else if (CvtResDenormUf) CvtShiftIn = {{`NF-1{1'b0}}, Xm, {`CVTLEN-`NF+1{1'b0}}}; + else CvtShiftIn = {CvtLzcIn, {`NF+1{1'b0}}}; + + // choose the negative of the fraction size + if (`FPSIZES == 1) begin + assign ResNegNF = -($clog2(`NF)+1)'(`NF); + + end else if (`FPSIZES == 2) begin + assign ResNegNF = OutFmt ? -($clog2(`NF)+1)'(`NF) : -($clog2(`NF)+1)'(`NF1); + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: ResNegNF = -($clog2(`NF)+1)'(`NF); + `FMT1: ResNegNF = -($clog2(`NF)+1)'(`NF1); + `FMT2: ResNegNF = -($clog2(`NF)+1)'(`NF2); + default: ResNegNF = 1'bx; + endcase + + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: ResNegNF = -($clog2(`NF)+1)'(`Q_NF); + 2'h1: ResNegNF = -($clog2(`NF)+1)'(`D_NF); + 2'h0: ResNegNF = -($clog2(`NF)+1)'(`S_NF); + 2'h2: ResNegNF = -($clog2(`NF)+1)'(`H_NF); + endcase + end + // determine if the result underflows ??? -> fp + // - if the first 1 is shifted out of the result then the result underflows + // - can't underflow an integer to fp conversions + assign CvtResUf = ($signed(CvtCe) < $signed({{`NE-$clog2(`NF){1'b1}}, ResNegNF}))&~XZero&~IntToFp; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/divconv.sv b/pipelined/src/fpu/divconv.sv deleted file mode 100755 index 8cc98cd01..000000000 --- a/pipelined/src/fpu/divconv.sv +++ /dev/null @@ -1,126 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 9/28/2021 -// -// Purpose: Main convergence routine for floating point divider/square root unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module divconv ( - input logic [52:0] d, n, - input logic [2:0] sel_muxa, sel_muxb, - input logic sel_muxr, - input logic load_rega, load_regb, load_regc, load_regd, - input logic load_regr, load_regs, - input logic P, - input logic op_type, - input logic exp_odd, - input logic reset, - input logic clk, - - output logic [59:0] q1, qp1, qm1, - output logic [59:0] q0, qp0, qm0, - output logic [59:0] rega_out, regb_out, regc_out, regd_out, - output logic [119:0] regr_out -); - - logic [59:0] muxa_out, muxb_out; - logic [10:0] ia_div, ia_sqrt; - logic [59:0] ia_out; - logic [119:0] mul_out; - logic [59:0] q_out1, qm_out1, qp_out1; - logic [59:0] q_out0, qm_out0, qp_out0; - logic [59:0] mcand, mplier, mcand_q; - logic [59:0] twocmp_out; - logic [60:0] three; - logic [119:0] constant, constant2; - logic [59:0] q_const, qp_const, qm_const; - logic [59:0] d2, n2; - logic muxr_out; - logic cout1, cout2, cout3, cout4, cout5, cout6, cout7; - - // Check if exponent is odd for sqrt - // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {1'b0, d, 6'h0} : {d, 7'h0}; - assign n2 = op_type ? d2 : {n, 7'h0}; - - // IA div/sqrt - sbtm_div ia1 (d[52:41], ia_div); - sbtm_sqrt ia2 (d2[59:48], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; - - // Choose IA or iteration - mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); - - // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); - // Select Mcand, Remainder/Q'' - mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); - // Select mcand - remainder should always choose q1 [1,2) because - // adjustment of N in the from XX.FFFFFFF - mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); - mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); - // Q*D - N (reversed but changed in rounder.v to account for sign reversal) - // Add ulp for subtraction in remainder - mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); - - // Constant for Q'' - mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); - mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); - mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); - - // CPA (from CSA)/Remainder addition/subtraction - assign {cout1, mul_out} = (mcand*mplier) + constant + {119'b0, muxr_out}; - - // Assuming [1,2) - q1 - assign {cout2, q_out1} = regb_out + q_const; - assign {cout3, qp_out1} = regb_out + qp_const; - assign {cout4, qm_out1} = regb_out + qm_const + 1'b1; - // Assuming [0.5,1) - q0 - assign {cout5, q_out0} = {regb_out[58:0], 1'b0} + q_const; - assign {cout6, qp_out0} = {regb_out[58:0], 1'b0} + qp_const; - assign {cout7, qm_out0} = {regb_out[58:0], 1'b0} + qm_const + 1'b1; - - // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[118], mul_out[118], ~mul_out[117:59]}; - mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type, twocmp_out); - - // regs - flopenr #(60) regc (clk, reset, load_regc, twocmp_out, regc_out); - flopenr #(60) regb (clk, reset, load_regb, mul_out[118:59], regb_out); - flopenr #(60) rega (clk, reset, load_rega, mul_out[118:59], rega_out); - flopenr #(60) regd (clk, reset, load_regd, mul_out[118:59], regd_out); - flopenr #(120) regr (clk, reset, load_regr, mul_out, regr_out); - // Assuming [1,2) - flopenr #(60) rege (clk, reset, load_regs, {q_out1[59:35], (q_out1[34:6] & {29{~P}}), 6'h0}, q1); - flopenr #(60) regf (clk, reset, load_regs, {qm_out1[59:35], (qm_out1[34:6] & {29{~P}}), 6'h0}, qm1); - flopenr #(60) regg (clk, reset, load_regs, {qp_out1[59:35], (qp_out1[34:6] & {29{~P}}), 6'h0}, qp1); - // Assuming [0,1) - flopenr #(60) regh (clk, reset, load_regs, {q_out0[59:35], (q_out0[34:6] & {29{~P}}), 6'h0}, q0); - flopenr #(60) regj (clk, reset, load_regs, {qm_out0[59:35], (qm_out0[34:6] & {29{~P}}), 6'h0}, qm0); - flopenr #(60) regk (clk, reset, load_regs, {qp_out0[59:35], (qp_out0[34:6] & {29{~P}}), 6'h0}, qp0); - -endmodule // divconv diff --git a/pipelined/src/fpu/divconv_pipe.sv b/pipelined/src/fpu/divconv_pipe.sv deleted file mode 100755 index 3562ad3d5..000000000 --- a/pipelined/src/fpu/divconv_pipe.sv +++ /dev/null @@ -1,198 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Convergence unit for pipelined floating point divider/square root top unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module divconv_pipe (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out, - regr_out, d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk, - load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, load_regp, - P, op_type, exp_odd); - - input logic [52:0] d, n; - input logic [2:0] sel_muxa, sel_muxb; - input logic sel_muxr; - input logic load_rega, load_regb, load_regc, load_regd; - input logic load_regr, load_regs; - input logic load_regp; - input logic P; - input logic op_type; - input logic exp_odd; - input logic reset; - input logic clk; - - output logic [59:0] q1, qp1, qm1; - output logic [59:0] q0, qp0, qm0; - output logic [59:0] rega_out, regb_out, regc_out, regd_out; - output logic [119:0] regr_out; - - supply1 vdd; - supply0 vss; - - logic [59:0] muxa_out, muxb_out; - logic muxr_out; - logic [10:0] ia_div, ia_sqrt; - logic [59:0] ia_out; - logic [119:0] mul_out; - logic [59:0] q_out1, qm_out1, qp_out1; - logic [59:0] q_out0, qm_out0, qp_out0; - logic [59:0] mcand, mplier, mcand_q; - logic [59:0] twocmp_out; - logic [60:0] three; - logic [119:0] Carry, Carry2; - logic [119:0] Sum, Sum2; - logic [119:0] constant, constant2; - logic [59:0] q_const, qp_const, qm_const; - logic [59:0] d2, n2; - logic [11:0] d3; - - // Check if exponent is odd for sqrt - // If exp_odd=1 and sqrt, then M/2 and use ia_addr=0 as IA - assign d2 = (exp_odd&op_type) ? {vss, d, 6'h0} : {d, 7'h0}; - assign n2 = op_type ? d2 : {n, 7'h0}; - - // IA div/sqrt - sbtm_div ia1 (d[52:41], ia_div); - sbtm_sqrt ia2 (d2[59:48], ia_sqrt); - assign ia_out = op_type ? {ia_sqrt, {49{1'b0}}} : {ia_div, {49{1'b0}}}; - - // Choose IA or iteration - mux6 #(60) mx1 (d2, ia_out, rega_out, regc_out, regd_out, regb_out, sel_muxb, muxb_out); - mux5 #(60) mx2 (regc_out, n2, ia_out, regb_out, regd_out, sel_muxa, muxa_out); - - // Deal with remainder if [0.5, 1) instead of [1, 2) - mux2 #(120) mx3a ({~n, {67{1'b1}}}, {{1'b1}, ~n, {66{1'b1}}}, q1[59], constant2); - // Select Mcand, Remainder/Q'' - mux2 #(120) mx3 (120'h0, constant2, sel_muxr, constant); - // Select mcand - remainder should always choose q1 [1,2) because - // adjustment of N in the from XX.FFFFFFF - mux2 #(60) mx4 (q0, q1, q1[59], mcand_q); - mux2 #(60) mx5 (muxb_out, mcand_q, sel_muxr&op_type, mplier); - mux2 #(60) mx6 (muxa_out, mcand_q, sel_muxr, mcand); - // R4 Booth TDM multiplier (carry/save) - redundantmul #(60) bigmul(.a(mcand), .b(mplier), .out0(Sum), .out1(Carry)); - // Q*D - N (reversed but changed in rounder.v to account for sign reversal) - csa #(120) csa1 (Sum, Carry, constant, Sum2, Carry2); - // Add ulp for subtraction in remainder - mux2 #(1) mx7 (1'b0, 1'b1, sel_muxr, muxr_out); - - // Constant for Q'' - mux2 #(60) mx8 ({60'h0000_0000_0000_020}, {60'h0000_0040_0000_000}, P, q_const); - mux2 #(60) mx9 ({60'h0000_0000_0000_0A0}, {60'h0000_0140_0000_000}, P, qp_const); - mux2 #(60) mxA ({60'hFFFF_FFFF_FFFF_F9F}, {60'hFFFF_FF3F_FFFF_FFF}, P, qm_const); - - logic [119:0] Sum_pipe; - logic [119:0] Carry_pipe; - logic muxr_pipe; - logic rega_pipe; - logic regb_pipe; - logic regc_pipe; - logic regd_pipe; - logic regs_pipe; - logic regs_pipe2; - logic regr_pipe; - logic P_pipe; - logic op_type_pipe; - logic [59:0] q_const_pipe; - logic [59:0] qm_const_pipe; - logic [59:0] qp_const_pipe; - logic [59:0] q_const_pipe2; - logic [59:0] qm_const_pipe2; - logic [59:0] qp_const_pipe2; - - // Stage 1 - flopenr #(120) regp1 (clk, reset, load_regp, Sum2, Sum_pipe); - flopenr #(120) regp2 (clk, reset, load_regp, Carry2, Carry_pipe); - flopenr #(1) regp3 (clk, reset, load_regp, muxr_out, muxr_pipe); - - flopenr #(1) regp4 (clk, reset, load_regp, load_rega, rega_pipe); - flopenr #(1) regp5 (clk, reset, load_regp, load_regb, regb_pipe); - flopenr #(1) regp6 (clk, reset, load_regp, load_regc, regc_pipe); - flopenr #(1) regp7 (clk, reset, load_regp, load_regd, regd_pipe); - flopenr #(1) regp8 (clk, reset, load_regp, load_regs, regs_pipe); - flopenr #(1) regp9 (clk, reset, load_regp, load_regr, regr_pipe); - flopenr #(1) regpA (clk, reset, load_regp, P, P_pipe); - flopenr #(1) regpB (clk, reset, load_regp, op_type, op_type_pipe); - flopenr #(60) regpC (clk, reset, load_regp, q_const, q_const_pipe); - flopenr #(60) regpD (clk, reset, load_regp, qp_const, qp_const_pipe); - flopenr #(60) regpE (clk, reset, load_regp, qm_const, qm_const_pipe); - - // CPA (from CSA)/Remainder addition/subtraction - assign mul_out = Sum_pipe + Carry_pipe + {119'h0, muxr_pipe}; - // One's complement instead of two's complement (for hw efficiency) - assign three = {~mul_out[118] , mul_out[118], ~mul_out[117:59]}; - mux2 #(60) mxTC (~mul_out[118:59], three[60:1], op_type_pipe, twocmp_out); - - // Stage 2 - flopenr #(60) regc (clk, reset, regc_pipe, twocmp_out, regc_out); - flopenr #(60) regb (clk, reset, regb_pipe, mul_out[118:59], regb_out); - flopenr #(60) rega (clk, reset, rega_pipe, mul_out[118:59], rega_out); - flopenr #(60) regd (clk, reset, regd_pipe, mul_out[118:59], regd_out); - flopenr #(120) regr (clk, reset, regr_pipe, mul_out, regr_out); - flopenr #(1) regl (clk, reset, regs_pipe, regs_pipe, regs_pipe2); - flopenr #(60) regm (clk, reset, regs_pipe, q_const_pipe, q_const_pipe2); - flopenr #(60) regn (clk, reset, regs_pipe, qp_const_pipe, qp_const_pipe2); - flopenr #(60) rego (clk, reset, regs_pipe, qm_const_pipe, qm_const_pipe2); - - // Assuming [1,2) - q1 - assign q_out1 = regb_out + q_const; - assign qp_out1 = regb_out + qp_const; - assign qm_out1 = regb_out + qm_const + 1'b1; - // Assuming [0.5,1) - q0 - assign q_out0 = {regb_out[58:0], 1'b0} + q_const; - assign qp_out0 = {regb_out[58:0], 1'b0} + qp_const; - assign qm_out0 = {regb_out[58:0], 1'b0} + qm_const + 1'b1; - - // Stage 3 - // Assuming [1,2) - flopenr #(60) rege (clk, reset, regs_pipe2, {q_out1[59:35], (q_out1[34:6] & {29{~P_pipe}}), 6'h0}, q1); - flopenr #(60) regf (clk, reset, regs_pipe2, {qm_out1[59:35], (qm_out1[34:6] & {29{~P_pipe}}), 6'h0}, qm1); - flopenr #(60) regg (clk, reset, regs_pipe2, {qp_out1[59:35], (qp_out1[34:6] & {29{~P_pipe}}), 6'h0}, qp1); - // Assuming [0,1) - flopenr #(60) regh (clk, reset, regs_pipe2, {q_out0[59:35], (q_out0[34:6] & {29{~P_pipe}}), 6'h0}, q0); - flopenr #(60) regj (clk, reset, regs_pipe2, {qm_out0[59:35], (qm_out0[34:6] & {29{~P_pipe}}), 6'h0}, qm0); - flopenr #(60) regk (clk, reset, regs_pipe2, {qp_out0[59:35], (qp_out0[34:6] & {29{~P_pipe}}), 6'h0}, qp0); - -endmodule // divconv - -// *** rewrote behaviorally dh 5 Jan 2021 for speed -module csa #(parameter WIDTH=8) ( - input logic [WIDTH-1:0] a, b, c, - output logic [WIDTH-1:0] sum, carry); - - assign sum = a ^ b ^ c; - assign carry = (a & (b | c)) | (b & c); -/* - logic [WIDTH:0] carry_temp; - genvar i; - for (i=0;i> NF+1 Exp = DivQe+NF+1 + // .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1 + // .0000xxxxxxxxxxx... >> 1 Exp = 1 + // Left shift amount = DivQe+NF+1-1 + assign DivDenormShift = (`NE+2)'(`NF)+DivQe; + // if the result is normalized + // 00000000x.xxxxxx... Exp = DivQe + // .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1 + // 00000000.xxxxxxx... << NF Exp = DivQe+1 + // 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards) + // 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after) + // inital Left shift amount = NF + // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit + assign NormShift = (`NE+2)'(`NF); + // if the shift amount is negitive then dont shift (keep sticky bit) + // need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES) + assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}}; + + assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}}; + +endmodule diff --git a/pipelined/src/fpu/divsqrt.sv b/pipelined/src/fpu/divsqrt.sv new file mode 100644 index 000000000..a1b19394a --- /dev/null +++ b/pipelined/src/fpu/divsqrt.sv @@ -0,0 +1,70 @@ +/////////////////////////////////////////// +// srt.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module divsqrt( + input logic clk, + input logic reset, + input logic [`FMTBITS-1:0] FmtE, + input logic XsE, + input logic [`NF:0] XmE, YmE, + input logic [`NE-1:0] XeE, YeE, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic DivStartE, + input logic StallM, + input logic StallE, + input logic SqrtE, SqrtM, + output logic DivSM, + output logic DivBusy, + output logic DivDone, + output logic [`NE+1:0] QeM, + output logic [`DURLEN-1:0] EarlyTermShiftM, + output logic [`DIVb-(`RADIX/4):0] QmM +// output logic [`XLEN-1:0] RemM, +); + + logic [`DIVb+3:0] NextWSN, NextWCN; + logic [`DIVb+3:0] WS, WC; + logic [`DIVb+3:0] StickyWSA; + logic [`DIVb:0] X; + logic [`DIVN-2:0] Dpreproc; + logic [`DURLEN-1:0] Dur; + logic NegSticky; + + srtpreproc srtpreproc(.clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), .Sqrt(SqrtE), .Dur, .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc); + + srtfsm srtfsm(.reset, .XsE, .SqrtE, .NextWSN, .NextWCN, .WS, .WC, .Dur, .DivBusy, .clk, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .DivSE(DivSM), .XNaNE, .YNaNE, + .StickyWSA, .XInfE, .YInfE, .NegSticky(NegSticky), .EarlyTermShiftE(EarlyTermShiftM)); + srt srt(.clk, .SqrtE, .SqrtM, .X,.Dpreproc, .NegSticky, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, + .StickyWSA, .DivBusy, .Qm(QmM)); +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/exception.sv b/pipelined/src/fpu/exception.sv deleted file mode 100755 index bccfa01f4..000000000 --- a/pipelined/src/fpu/exception.sv +++ /dev/null @@ -1,83 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. - -module exception ( - - input logic [2:0] op_type, // Function opcode - input logic XSgnE, YSgnE, - // input logic [52:0] XManE, YManE, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - output logic [3:0] Ztype, // Indicates type of result (Z) - output logic Invalid, // Invalid operation exception - output logic Denorm, // Denormalized logic - output logic Sub // The effective operation is subtraction -); - wire ZQNaN; // '1' if result Z is a quiet NaN - wire ZPInf; // '1' if result Z positive infnity - wire ZNInf; // '1' if result Z negative infnity - wire add_sub; // '1' if operation is add or subtract - wire converts; // See if there are any converts - - - - // Is this instruction a convert - assign converts = op_type[1]; - - - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite and the "effective operation" is - // subtraction). - assign add_sub = ~op_type[1]; - assign Invalid = (XSNaNE | YSNaNE | (add_sub & XInfE & YInfE & (XSgnE^YSgnE^op_type[0]))) & ~converts; - - // The Denorm flag is set if (A is denormlized and the operation is not integer - // conversion ) or (if B is normalized and the operation is addition or subtraction). - assign Denorm = XDenormE | YDenormE & add_sub; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN and the operation uses B). - assign ZQNaN = Invalid | XNaNE | (YNaNE & add_sub); - - // The result is +Inf if ((A is +Inf) or (B is -Inf and the operation is - // subtraction) or (B is +Inf and the operation is addition)) and (the - // result is not a quiet NaN). - assign ZPInf = (XInfE&XSgnE | add_sub&YInfE&(~YSgnE^op_type[0]))&~ZQNaN; - - // The result is -Inf if ((A is -Inf) or (B is +Inf and the operation is - // subtraction) or (B is -Inf and the operation is addition)) and the - // result is not a quiet NaN. - assign ZNInf = (XInfE&~XSgnE | add_sub&YInfE&(YSgnE^op_type[0]))&~ZQNaN; - - // Set the type of the result as follows: - // (needs optimization - got lazy or was late) - // Ztype Result - // 0000 Normal - // 0001 Quiet NaN - // 0010 Negative Infinity - // 0011 Positive Infinity - // 0100 +Bzero and +Azero (and vice-versa) - // 0101 +Bzero and -Azero (and vice-versa) - // 1000 Convert SP to DP (and vice-versa) - - assign Ztype[0] = (ZQNaN | ZPInf) | - ((XZeroE & YZeroE & (XSgnE^YSgnE^op_type[0])) - & ~converts); - assign Ztype[1] = (ZNInf | ZPInf) | - (((XZeroE & YZeroE & XSgnE & YSgnE & ~op_type[0]) | - (XZeroE & YZeroE & XSgnE & ~YSgnE & op_type[0])) - & ~converts); - assign Ztype[2] = ((XZeroE & YZeroE & ~op_type[1]) - & ~converts); - assign Ztype[3] = (op_type[1] & ~op_type[0]); - - // Determine if the effective operation is subtraction - assign Sub = add_sub & (XSgnE^YSgnE^op_type[0]); - -endmodule // exception - diff --git a/pipelined/src/fpu/exception_div.sv b/pipelined/src/fpu/exception_div.sv deleted file mode 100755 index 3e701d2fb..000000000 --- a/pipelined/src/fpu/exception_div.sv +++ /dev/null @@ -1,82 +0,0 @@ -// Exception logic for the floating point adder. Note: We may -// actually want to move to where the result is computed. -module exception_div ( - - input logic [63:0] A, // 1st input operand (op1) - input logic [63:0] B, // 2nd input operand (op2) - input logic op_type, // Determine operation - output logic [2:0] Ztype, // Indicates type of result (Z) - output logic Invalid // Invalid operation exception -); - - logic AzeroM; // '1' if the mantissa of A is zero - logic BzeroM; // '1' if the mantissa of B is zero - logic AzeroE; // '1' if the exponent of A is zero - logic BzeroE; // '1' if the exponent of B is zero - logic AonesE; // '1' if the exponent of A is all ones - logic BonesE; // '1' if the exponent of B is all ones - logic AInf; // '1' if A is infinite - logic BInf; // '1' if B is infinite - logic AZero; // '1' if A is 0 - logic BZero; // '1' if B is 0 - logic ANaN; // '1' if A is a not-a-number - logic BNaN; // '1' if B is a not-a-number - logic ASNaN; // '1' if A is a signalling not-a-number - logic BSNaN; // '1' if B is a signalling not-a-number - logic ZSNaN; // '1' if result Z is a quiet NaN - logic ZInf; // '1' if result Z is an infnity - logic Zero; // '1' if result is zero - logic NegSqrt; // '1' if sqrt and operand is negative - - //***take this module out and add more registers or just recalculate it all - // Determine if mantissas are all zeros - assign AzeroM = (A[51:0] == 52'h0); - assign BzeroM = (B[51:0] == 52'h0); - - // Determine if exponents are all ones or all zeros - assign AonesE = A[62]&A[61]&A[60]&A[59]&A[58]&A[57]&A[56]&A[55]&A[54]&A[53]&A[52]; - assign BonesE = B[62]&B[61]&B[60]&B[59]&B[58]&B[57]&B[56]&B[55]&B[54]&B[53]&B[52]; - assign AzeroE = ~(A[62]|A[61]|A[60]|A[59]|A[58]|A[57]|A[56]|A[55]|A[54]|A[53]|A[52]); - assign BzeroE = ~(B[62]|B[61]|B[60]|B[59]|B[58]|B[57]|B[56]|B[55]|B[54]|B[53]|B[52]); - - // Determine special cases. Note: Zero is not really a special case. - assign AInf = AonesE & AzeroM; - assign BInf = BonesE & BzeroM; - assign ANaN = AonesE & ~AzeroM; - assign BNaN = BonesE & ~BzeroM; - assign ASNaN = ANaN & A[50]; - assign BSNaN = ANaN & A[50]; - assign AZero = AzeroE & AzeroM; - assign BZero = BzeroE & BzeroE; - - // Is NaN if operand is negative and its a sqrt - assign NegSqrt = (A[63] & op_type & ~AZero); - - // An "Invalid Operation" exception occurs if (A or B is a signalling NaN) - // or (A and B are both Infinite) - assign Invalid = ASNaN | BSNaN | (((AInf & BInf) | (AZero & BZero))&~op_type) | - NegSqrt; - - // The result is a quiet NaN if (an "Invalid Operation" exception occurs) - // or (A is a NaN) or (B is a NaN). - assign ZSNaN = Invalid | ANaN | BNaN; - - // The result is zero - assign Zero = (AZero | BInf)&~op_type | AZero&op_type; - - // The result is +Inf if ((A is Inf) or (B is 0)) and (the - // result is not a quiet NaN). - assign ZInf = (AInf | BZero)&~ZSNaN&~op_type | AInf&op_type&~ZSNaN; - - // Set the type of the result as follows: - // Ztype Result - // 000 Normal - // 010 Infinity - // 011 Zero - // 110 Div by 0 - // 111 SNaN - assign Ztype[2] = (ZSNaN); - assign Ztype[1] = (ZSNaN) | (Zero) | (ZInf); - assign Ztype[0] = (ZSNaN) | (Zero); - -endmodule // exception diff --git a/pipelined/src/fpu/faddcvt.sv b/pipelined/src/fpu/faddcvt.sv deleted file mode 100755 index e5dddb7e9..000000000 --- a/pipelined/src/fpu/faddcvt.sv +++ /dev/null @@ -1,426 +0,0 @@ -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and convert SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller exponent, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put sum onto output. -// - -module faddcvt( - input logic clk, - input logic reset, - input logic FlushM, // flush the memory stage - input logic StallM, // stall the memory stage - input logic [63:0] FSrcXE, // 1st input operand (A) - input logic [63:0] FSrcYE, // 2nd input operand (B) - input logic [2:0] FOpCtrlE, FOpCtrlM, // Function opcode - input logic FmtE, FmtM, // Result Precision (0 for double, 1 for single) - input logic [2:0] FrmM, // Rounding mode - specify values - input logic XSgnE, YSgnE, - input logic [52:0] XManE, YManE, - input logic [10:0] XExpE, YExpE, - input logic XSgnM, YSgnM, - input logic [52:0] XManM, YManM, - input logic [10:0] XExpM, YExpM, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XNormM, YNormM, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - output logic [63:0] FAddResM, // Result of operation - output logic [4:0] FAddFlgM); // IEEE exception flags - - logic [63:0] AddSumE, AddSumM; - logic [63:0] AddSumTcE, AddSumTcM; - logic [3:0] AddSelInvE, AddSelInvM; - logic [10:0] AddExpPostSumE,AddExpPostSumM; - logic AddCorrSignE, AddCorrSignM; - logic AddOpANormE, AddOpANormM; - logic AddOpBNormE, AddOpBNormM; - logic AddInvalidE, AddInvalidM; - logic AddDenormInE, AddDenormInM; - logic AddSwapE, AddSwapM; - logic AddSignAE, AddSignAM; - logic [11:0] AddExp1DenormE, AddExp2DenormE, AddExp1DenormM, AddExp2DenormM; - logic [10:0] AddExponentE, AddExponentM; - - - fpuaddcvt1 fpadd1 (.FOpCtrlE, .FmtE, .AddExponentE, - .AddExpPostSumE, .AddExp1DenormE, .AddExp2DenormE, .AddSumE, .AddSumTcE, .AddSelInvE, - .XSgnE, .YSgnE,.XManE, .YManE, .XExpE, .YExpE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, - .AddCorrSignE, .AddSignAE, .AddOpANormE, .AddOpBNormE, .AddInvalidE, - .AddDenormInE, .AddSwapE); - - // E/M pipeline registers - flopenrc #(64) EMRegAdd1(clk, reset, FlushM, ~StallM, AddSumE, AddSumM); - flopenrc #(64) EMRegAdd2(clk, reset, FlushM, ~StallM, AddSumTcE, AddSumTcM); - flopenrc #(11) EMRegAdd3(clk, reset, FlushM, ~StallM, AddExpPostSumE, AddExpPostSumM); - flopenrc #(12) EMRegAdd6(clk, reset, FlushM, ~StallM, AddExp1DenormE, AddExp1DenormM); - flopenrc #(12) EMRegAdd7(clk, reset, FlushM, ~StallM, AddExp2DenormE, AddExp2DenormM); - flopenrc #(11) EMRegAdd8(clk, reset, FlushM, ~StallM, AddExponentE, AddExponentM); - flopenrc #(11) EMRegAdd9(clk, reset, FlushM, ~StallM, - {AddSelInvE, AddCorrSignE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddSwapE, AddSignAE}, - {AddSelInvM, AddCorrSignM, AddOpANormM, AddOpBNormM, AddInvalidM, AddDenormInM, AddSwapM, AddSignAM}); - - - fpuaddcvt2 fpadd2 (.FrmM, .FOpCtrlM, .FmtM, .AddSumM, .AddSumTcM, .XNormM, .YNormM, - .AddExp1DenormM, .AddExp2DenormM, .AddExponentM, .AddExpPostSumM, .AddSelInvM, .XSgnM, .YSgnM, .XManM, .YManM, .XExpM, .YExpM, - .AddOpANormM, .AddOpBNormM, .AddInvalidM, .AddDenormInM, - .AddSignAM, .AddCorrSignM, .AddSwapM, .FAddResM, .FAddFlgM); -endmodule - -module fpuaddcvt1 ( - input logic [2:0] FOpCtrlE, // Function opcode - input logic FmtE, // Result Precision (1 for double, 0 for single) - input logic XSgnE, YSgnE, - input logic [10:0] XExpE, YExpE, - input logic [52:0] XManE, YManE, - input logic XDenormE, YDenormE, - input logic XNormE, YNormE, - input logic XZeroE, YZeroE, - input logic XInfE, YInfE, - input logic XNaNE, YNaNE, - input logic XSNaNE, YSNaNE, - - output logic [10:0] AddExponentE, - output logic [10:0] AddExpPostSumE, - output logic [11:0] AddExp1DenormE, AddExp2DenormE,//KEP used to be [10:0] - output logic [63:0] AddSumE, AddSumTcE, - output logic [3:0] AddSelInvE, - output logic AddCorrSignE, - output logic AddSignAE, - output logic AddOpANormE, AddOpBNormE, - output logic AddInvalidE, - output logic AddDenormInE, - output logic AddSwapE - ); - - logic [5:0] ZP_mantissaA; - logic [5:0] ZP_mantissaB; - wire ZV_mantissaA; - wire ZV_mantissaB; - - wire P; - assign P = ~(FmtE^FOpCtrlE[1]); - - wire [63:0] IntValue; - wire [11:0] exp1, exp2; - wire [11:0] exp_diff1, exp_diff2; - wire [11:0] exp_shift; - wire [51:0] mantissaA; - wire [56:0] mantissaA1; - wire [63:0] mantissaA3; - wire [51:0] mantissaB; - wire [56:0] mantissaB1, mantissaB2; - wire [63:0] mantissaB3; - wire exp_gt63; - wire Sticky_out; - wire sub; - wire zeroB; - wire [5:0] align_shift; - - // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input Flags. The "AddSelInvE" is used in - // the third pipeline stage to select the result. Also, AddOp1NormE - // and AddOp2NormE are one if FSrcXE and FSrcYE are not zero or denormalized. - // sub is one if the effective operation is subtaction. - - exception exc1 (.Ztype(AddSelInvE), .Invalid(AddInvalidE), .Denorm(AddDenormInE), .Sub(sub), - .XSgnE, .YSgnE, .XDenormE, .YDenormE, .XNormE, .YNormE, .XZeroE, .YZeroE, .XInfE, .YInfE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, - .op_type(FOpCtrlE)); - - // Perform Exponent Subtraction (used for alignment). For performance - // both exponent subtractions are performed in parallel. This was - // changed to a behavior level to allow the tools to try to optimize - // the two parallel additions. The input values are zero-extended to 12 - // bits prior to performing the addition. - - assign exp1 = {1'b0, XExpE}; - assign exp2 = {1'b0, YExpE}; - assign exp_diff1 = exp1 - exp2; - assign exp_diff2 = AddDenormInE ? ({YSgnE, YExpE} - {XSgnE, XExpE}): exp2 - exp1; - - // The second operand (B) should be set to zero, if FOpCtrlE does not - // specify addition or subtraction - assign zeroB = FOpCtrlE[1]; - - // Swapped operands if zeroB is not one and exp1 < exp2. - // Swapping causes exp2 to be used for the result exponent. - // Only the exponent of the larger operand is used to determine - // the final result. - assign AddSwapE = exp_diff1[11] & ~zeroB; - assign AddExponentE = AddSwapE ? YExpE : XExpE; - assign AddExpPostSumE = AddSwapE ? YExpE : XExpE; - assign mantissaA = AddSwapE ? YManE[51:0] : XManE[51:0]; - assign mantissaB = AddSwapE ? XManE[51:0] : YManE[51:0]; - assign AddSignAE = AddSwapE ? YSgnE : XSgnE; - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - // modified to 52 bits to detect leading zeroes on denormalized mantissas - // lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA); - // lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB); - logic [8:0] i; - logic [8:0] j; - always_comb begin - i = 0; - while (~mantissaA[52-i] & $unsigned(i) <= $unsigned(52)) i = i+1; // search for leading one - ZP_mantissaA = i; - end - always_comb begin - j = 0; - while (~mantissaB[52-j] & $unsigned(j) <= $unsigned(52)) j = j+1; // search for leading one - ZP_mantissaB = j; - end - - // Denormalized exponents created by subtracting the leading zeroes from the original exponents - assign AddExp1DenormE = AddSwapE ? (exp1 - {6'b0, ZP_mantissaB}) : (exp1 - {6'b0, ZP_mantissaA}); //KEP extended ZP_mantissa - assign AddExp2DenormE = AddSwapE ? (exp2 - {6'b0, ZP_mantissaA}) : (exp2 - {6'b0, ZP_mantissaB}); - - // Determine the alignment shift and limit it to 63. If any bit from - // exp_shift[6] to exp_shift[11] is one, then shift is set to all ones. - assign exp_shift = AddSwapE ? exp_diff2 : exp_diff1; - assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9] - | exp_shift[8] | exp_shift[7] | exp_shift[6]; - assign align_shift = exp_shift[5:0] | {6{exp_gt63}}; //KEP used to be all of exp_shift - - // Unpack the 52-bit mantissas to 57-bit numbers of the form. - // 001.M[51]M[50] ... M[1]M[0]00 - // Unless the number has an exponent of zero, in which case it - // is unpacked as - // 000.00 ... 00 - // This effectively flushes denormalized values to zero. - // The three bits of to the left of the binary point prevent overflow - // and loss of sign information. The two bits to the right of the - // original mantissa form the "guard" and "round" bits that are used - // to round the result. - assign AddOpANormE = AddSwapE ? YNormE : XNormE; - assign AddOpBNormE = AddSwapE ? XNormE : YNormE; - assign mantissaA1 = {2'h0, AddOpANormE, mantissaA[51:0]&{52{AddOpANormE}}, 2'h0}; - assign mantissaB1 = {2'h0, AddOpBNormE, mantissaB[51:0]&{52{AddOpBNormE}}, 2'h0}; - - // Perform mantissa alignment using a 57-bit barrel shifter - // If any of the bits shifted out are one, Sticky_out is set. - // The size of the barrel shifter could be reduced by two bits - // by not adding the leading two zeros until after the shift. - barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift); - - // Place either the sign-extened 32-bit value or the original 64-bit value - // into IntValue (to be used for integer to floating point conversion) - // assign IntValue [31:0] = FSrcXE[31:0]; - // assign IntValue [63:32] = FOpCtrlE[0] ? {32{FSrcXE[31]}} : FSrcXE[63:32]; - - // If doing an integer to floating point conversion, mantissaA3 is set to - // IntVal and the prenomalized exponent is set to 1084. Otherwise, - // mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero, - // and the exponent value is left unchanged. - // Under denormalized cases, the exponent before the rounder is set to 1 - // if the normal shift value is 11. - assign mantissaA3 = AddDenormInE ? ({12'h0, mantissaA}) : {mantissaA1, 7'h0}; - - // Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to - // 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six - // zeros. - assign mantissaB3[63:7] = AddDenormInE ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}}; - assign mantissaB3[6] = AddDenormInE ? mantissaB[6] : Sticky_out & ~zeroB; - assign mantissaB3[5:0] = AddDenormInE ? mantissaB[5:0] : 6'h0; - - // The sign of the result needs to be corrected if the true - // operation is subtraction and the input operands were swapped. - assign AddCorrSignE = ~FOpCtrlE[1]&FOpCtrlE[0]&AddSwapE; - - // 64-bit Mantissa Adder/Subtractor - cla64 add1 (AddSumE, mantissaA3, mantissaB3, sub); //***adder - - // 64-bit Mantissa Subtractor - to get the two's complement of the - // result when the sign from the adder/subtractor is negative. - cla_sub64 sub1 (AddSumTcE, mantissaB3, mantissaA3); //***adder - - // Finds normal underflow result to determine whether to round final exponent down - //***KEP used to be (AddSumE == 16'h0) I am unsure what it's supposed to be - // assign AddNormOvflowE = (AddDenormInE & (AddSumE == 64'h0) & (AddOpANormE | AddOpBNormE) & ~FOpCtrlE[0]) ? 1'b1 : (AddSumE[63] ? AddSumTcE[52] : AddSumE[52]); - -endmodule // fpadd - - -// -// File name : fpadd -// Title : Floating-Point Adder/Subtractor -// project : FPU -// Library : fpadd -// Author(s) : James E. Stine, Jr., Brett Mathis -// Purpose : definition of main unit to floating-point add/sub -// notes : -// -// Copyright Oklahoma State University -// Copyright AFRL -// -// Basic and Denormalized Operations -// -// Step 1: Load operands, set flags, and AddConvertM SP to DP -// Step 2: Check for special inputs ( +/- Infinity, NaN) -// Step 3: Compare exponents. Swap the operands of exp1 < exp2 -// or of (exp1 = exp2 AND mnt1 < mnt2) -// Step 4: Shift the mantissa corresponding to the smaller AddExponentM, -// and extend precision by three bits to the right. -// Step 5: Add or subtract the mantissas. -// Step 6: Normalize the result.// -// Shift left until normalized. Normalized when the value to the -// left of the binrary point is 1. -// Step 7: Round the result.// -// Step 8: Put AddSumM onto output. -// - - -module fpuaddcvt2 ( - input logic [2:0] FrmM, // Rounding mode - specify values - input logic [2:0] FOpCtrlM, // Function opcode - input logic FmtM, // Result Precision (0 for double, 1 for single) - input logic [63:0] AddSumM, AddSumTcM, - input logic [11:0] AddExp1DenormM, AddExp2DenormM, - input logic [10:0] AddExponentM, AddExpPostSumM, - input logic [3:0] AddSelInvM, - input logic XSgnM, YSgnM, - input logic [52:0] XManM, YManM, - input logic [10:0] XExpM, YExpM, - input logic XNormM, YNormM, - input logic AddOpANormM, AddOpBNormM, - input logic AddInvalidM, - input logic AddDenormInM, - input logic AddSignAM, - input logic AddCorrSignM, - input logic AddSwapM, - - output logic [63:0] FAddResM, // Result of operation - output logic [4:0] FAddFlgM // IEEE exception flags -); - wire AddDenormM; // AddDenormM on input or output - - wire P; - assign P = ~(FmtM^FOpCtrlM[1]); - - wire [10:0] exp_pre; - wire [63:0] Result; - wire [63:0] sum_norm, sum_norm_w_bypass; - wire [5:0] norm_shift, norm_shift_denorm; - wire exp_valid; - wire DenormIO; - wire [4:0] FlagsIn; - wire Sticky_out; - wire sign_corr; - wire zeroB; - wire mantissa_comp; - wire mantissa_comp_sum; - wire mantissa_comp_sum_tc; - wire Float1_sum_comp; - wire Float2_sum_comp; - wire Float1_sum_tc_comp; - wire Float2_sum_tc_comp; - wire normal_underflow; - wire [63:0] sum_corr; - logic AddNormOvflowM; - - - logic AddOvEnM; // Overflow trap enabled - logic AddUnEnM; // Underflow trap enabled - - assign AddOvEnM = 1'b1; - assign AddUnEnM = 1'b1; - //AddExponentM value pre-rounding with considerations for denormalized - //cases/conversion cases - assign exp_pre = AddDenormInM ? - ((norm_shift == 6'b001011) ? 11'b00000000001 : (AddSwapM ? AddExp2DenormM[10:0] : AddExp1DenormM[10:0])) - : AddExponentM; - - - // Finds normal underflow result to determine whether to round final AddExponentM down - // Comparison between each float and the resulting AddSumM of the primary cla adder/subtractor and cla subtractor - assign Float1_sum_comp = ~(XManM[51:0] > AddSumM[51:0]); - assign Float2_sum_comp = ~(YManM[51:0] > AddSumM[51:0]); - assign Float1_sum_tc_comp = ~(XManM[51:0] > AddSumTcM[51:0]); - assign Float2_sum_tc_comp = ~(YManM[51:0] > AddSumTcM[51:0]); - - // Determines the correct Float value to compare based on AddSwapM result - assign mantissa_comp_sum = AddSwapM ? Float2_sum_comp : Float1_sum_comp; - assign mantissa_comp_sum_tc = AddSwapM ? Float2_sum_tc_comp : Float1_sum_tc_comp; - - // Determines the correct comparison result based on operation and sign of resulting AddSumM - assign mantissa_comp = (FOpCtrlM[0] ^ AddSumM[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum; - - // If the signs are different and both operands aren't denormalized - // the normal underflow bit is needed and therefore updated. - assign normal_underflow = ((XSgnM ^ YSgnM) & (AddOpANormM | AddOpBNormM)) ? mantissa_comp : 1'b0; - - // Determine the correct sign of the result - assign sign_corr = (AddCorrSignM ^ AddSignAM) ^ AddSumM[63]; - - // If the AddSumM is negative, use its two complement instead. - // This value has to be 64-bits to correctly handle the - // case 10...00 - assign sum_corr = (AddDenormInM & (AddOpANormM | AddOpBNormM) & ( ( (XSgnM ~^ YSgnM) & FOpCtrlM[0] ) | ((XSgnM ^ YSgnM) & ~FOpCtrlM[0]) )) - ? (AddSumM[63] ? AddSumM : AddSumTcM) : (AddSumM[63] ? AddSumTcM : AddSumM); - - // Finds normal underflow result to determine whether to round final AddExponentM down - //KEP used to be (AddSumM == 16'h0) not sure what it is supposed to be - assign AddNormOvflowM = (AddDenormInM & (AddSumM == 64'h0) & (AddOpANormM | AddOpBNormM) & ~FOpCtrlM[0]) ? 1'b1 : (AddSumM[63] ? AddSumTcM[52] : AddSumM[52]); - - // Leading-Zero Detector. Determine the size of the shift needed for - // normalization. If sum_corrected is all zeros, the exp_valid is - // zero; otherwise, it is one. - lz64 lzd1 (norm_shift, exp_valid, sum_corr); - - assign norm_shift_denorm = (AddDenormInM & ( (~AddOpANormM & ~AddOpBNormM) | normal_underflow)) ? (6'h00) : (norm_shift); - - // Barell shifter used for normalization. It takes as inputs the - // the corrected AddSumM and the amount by which the AddSumM should - // be right shifted. It outputs the normalized AddSumM. - barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm); - - assign sum_norm_w_bypass = sum_norm; - - // Round the mantissa to a 52-bit value, with the leading one - // removed. If the result is a single precision number, the actual - // mantissa is in the upper 23 bits and the lower 29 bits are zero. - // At this point, normalization has already been performed, so we know - // exactly where the rounding point is. The rounding units also - // handles special cases and set the exception flags. - - // Changed DenormIO -> AddDenormM and FlagsIn -> FAddFlgM in order to - // help in processor reservation station detection of load/stores. In - // other words, the processor would like to know ahead of time that - // if the result is an exception then don't load or store. - rounder round1 (.Result, .DenormIO, .Flags(FlagsIn), .rm(FrmM), .P, .OvEn(AddOvEnM), .UnEn(AddUnEnM), .exp_valid, - .sel_inv(AddSelInvM), .Invalid(AddInvalidM), .DenormIn(AddDenormInM), .Asign(sign_corr), .Aexp(exp_pre), .norm_shift, .A(sum_norm_w_bypass), - .exponent_postsum(AddExpPostSumM), .A_Norm(XNormM), .B_Norm(YNormM), .exp_A_unmodified({XSgnM, XExpM}), .exp_B_unmodified({YSgnM, YExpM}), - .normal_overflow(AddNormOvflowM), .normal_underflow, .swap(AddSwapM), .op_type(FOpCtrlM), .sum(AddSumM)); - - // Store the final result and the exception flags in registers. - assign FAddResM = Result; - assign {AddDenormM, FAddFlgM} = {DenormIO, FlagsIn}; - -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fclassify.sv b/pipelined/src/fpu/fclassify.sv index dd6165ca1..6aaec00a4 100644 --- a/pipelined/src/fpu/fclassify.sv +++ b/pipelined/src/fpu/fclassify.sv @@ -1,30 +1,57 @@ - +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: classify unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" module fclassify ( - input logic XSgnE, // sign bit - input logic XNaNE, // is NaN - input logic XSNaNE, // is signaling NaN - input logic XNormE, // is normal - input logic XDenormE, // is denormal - input logic XZeroE, // is zero - input logic XInfE, // is infinity - output logic [63:0] ClassResE // classify result - ); + input logic Xs, // sign bit + input logic XNaN, // is NaN + input logic XSNaN, // is signaling NaN + input logic XDenorm,// is denormal + input logic XZero, // is zero + input logic XInf, // is infinity + output logic [`XLEN-1:0] ClassRes// classify result +); logic PInf, PZero, PNorm, PDenorm; logic NInf, NZero, NNorm, NDenorm; - + logic XNorm; // determine the sub categories - assign PInf = ~XSgnE&XInfE; - assign NInf = XSgnE&XInfE; - assign PNorm = ~XSgnE&XNormE; - assign NNorm = XSgnE&XNormE; - assign PDenorm = ~XSgnE&XDenormE; - assign NDenorm = XSgnE&XDenormE; - assign PZero = ~XSgnE&XZeroE; - assign NZero = XSgnE&XZeroE; + assign XNorm= ~(XNaN | XInf| XDenorm| XZero); + assign PInf = ~Xs&XInf; + assign NInf = Xs&XInf; + assign PNorm = ~Xs&XNorm; + assign NNorm = Xs&XNorm; + assign PDenorm = ~Xs&XDenorm; + assign NDenorm = Xs&XDenorm; + assign PZero = ~Xs&XZero; + assign NZero = Xs&XZero; // determine sub category and combine into the result // bit 0 - -Inf @@ -37,6 +64,6 @@ module fclassify ( // bit 7 - +Inf // bit 8 - signaling NaN // bit 9 - quiet NaN - assign ClassResE = {{54{1'b0}}, XNaNE&~XSNaNE, XSNaNE, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf}; + assign ClassRes = {{`XLEN-10{1'b0}}, XNaN&~XSNaN, XSNaN, PInf, PNorm, PDenorm, PZero, NZero, NDenorm, NNorm, NInf}; endmodule diff --git a/pipelined/src/fpu/fcmp.sv b/pipelined/src/fpu/fcmp.sv index 94b75d7e1..48ff536f6 100755 --- a/pipelined/src/fpu/fcmp.sv +++ b/pipelined/src/fpu/fcmp.sv @@ -1,43 +1,69 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Comparison unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + `include "wally-config.vh" -// FOpCtrlE values -// 111 min +// OpCtrl values +// 110 min // 101 max // 010 equal // 001 less than // 011 less than or equal - module fcmp ( - input logic FmtE, // precision 1 = double 0 = single - input logic [2:0] FOpCtrlE, // see above table - input logic XSgnE, YSgnE, // input signs - input logic [`NE-1:0] XExpE, YExpE, // input exponents - input logic [`NF:0] XManE, YManE, // input mantissa - input logic XZeroE, YZeroE, // is zero - input logic XNaNE, YNaNE, // is NaN - input logic XSNaNE, YSNaNE, // is signaling NaN - input logic [`FLEN-1:0] FSrcXE, FSrcYE, // original, non-converted to double, inputs - output logic CmpNVE, // invalid flag - output logic [`FLEN-1:0] CmpResE // compare resilt + input logic [`FMTBITS-1:0] Fmt, // format of fp number + input logic [2:0] OpCtrl, // see above table + input logic Xs, Ys, // input signs + input logic [`NE-1:0] Xe, Ye, // input exponents + input logic [`NF:0] Xm, Ym, // input mantissa + input logic XZero, YZero, // is zero + input logic XNaN, YNaN, // is NaN + input logic XSNaN, YSNaN, // is signaling NaN + input logic [`FLEN-1:0] X, Y, // original inputs (before unpacker) + output logic CmpNV, // invalid flag + output logic [`FLEN-1:0] CmpFpRes, // compare floating-point result + output logic [`XLEN-1:0] CmpIntRes // compare integer result ); - logic LTabs, LT, EQ; // is X < or > or = Y - logic BothZeroE, EitherNaNE, EitherSNaNE; + logic LTabs, LT, EQ; // is X < or > or = Y + logic [`FLEN-1:0] NaNRes; // NaN result + logic BothZero; // are both inputs zero + logic EitherNaN, EitherSNaN; // are either input a (signaling) NaN - assign LTabs= {1'b0, XExpE, XManE} < {1'b0, YExpE, YManE}; // unsigned comparison, treating FP as integers - assign LT = (XSgnE & ~YSgnE) | (XSgnE & YSgnE & ~LTabs & ~EQ) | (~XSgnE & ~YSgnE & LTabs); - // assign LT = {~XSgnE, XExpE, XManE[`NF-1:0]} < {~YSgnE, YExpE, YManE[`NF-1:0]}; // *** James look at whether we can simplify to this, but it fails regression + assign LTabs= {1'b0, Xe, Xm} < {1'b0, Ye, Ym}; // unsigned comparison, treating FP as integers + assign LT = (Xs & ~Ys) | (Xs & Ys & ~LTabs & ~EQ) | (~Xs & ~Ys & LTabs); // signed comparison + assign EQ = (X == Y); - //assign LT = $signed({XSgnE, XExpE, XManE[`NF-1:0]}) < $signed({YSgnE, YExpE, YManE[`NF-1:0]}); - //assign LT = XInt < YInt; -// assign LT = XSgnE^YSgnE ? XSgnE : XExpE==YExpE ? ((XManE Y + else // MIN + if(XNaN) + if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN + else CmpFpRes = Y; // X = NaN Y != NaN + else + if(YNaN) CmpFpRes = X; // X != NaN Y = NaN + else // X,Y != NaN + if(LT) CmpFpRes = X; // X < Y + else CmpFpRes = Y; // X > Y + // LT/LE/EQ // - -0 = 0 // - inf = inf and -inf = -inf // - return 0 if comparison with NaN (unordered) - - logic [`FLEN-1:0] QNaN; - // fmin/fmax of two NaNs returns a quiet NaN of the appropriate size - // for IEEE, return the payload of X - // for RISC-V, return the canonical NaN - if(`IEEE754) assign QNaN = FmtE ? {XSgnE, XExpE, 1'b1, XManE[`NF-2:0]} : {{32{1'b1}}, XSgnE, XExpE[7:0], 1'b1, XManE[50:29]}; - else assign QNaN = FmtE ? {1'b0, XExpE, 1'b1, 51'b0} : {{32{1'b1}}, 1'b0, XExpE[7:0], 1'b1, 22'b0}; - - // when one input is a NaN -output the non-NaN - always_comb begin - case (FOpCtrlE[2:0]) - 3'b111: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Min - : YNaNE ? FSrcXE : LT ? FSrcXE : FSrcYE; - 3'b101: CmpResE = XNaNE ? YNaNE ? QNaN : FSrcYE // Max - : YNaNE ? FSrcXE : LT ? FSrcYE : FSrcXE; - 3'b010: CmpResE = {63'b0, (EQ|BothZeroE) & ~EitherNaNE}; // Equal - 3'b001: CmpResE = {63'b0, LT & ~BothZeroE & ~EitherNaNE}; // Less than - 3'b011: CmpResE = {63'b0, (LT|EQ|BothZeroE) & ~EitherNaNE}; // Less than or equal - default: CmpResE = 64'b0; - endcase - end - + assign CmpIntRes = {(`XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN}; endmodule diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 153b97ef7..934aba2cd 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -1,111 +1,155 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: control unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" module fctrl ( + input logic clk, + input logic reset, + input logic StallE, StallM, StallW, // stall signals + input logic FlushE, FlushM, FlushW, // flush signals + input logic [31:0] InstrD, input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision input logic [6:0] OpD, // bits 6:0 of instruction input logic [4:0] Rs2D, // bits 24:20 of instruction input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode input logic [2:0] FRM_REGW, // rounding mode from CSR input logic [1:0] STATUS_FS, // is FPU enabled? - output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction - output logic FRegWriteD, // FP register write enable - output logic FDivStartD, // Start division or squareroot - output logic [1:0] FResultSelD, // select result to be written to fp register - output logic [2:0] FOpCtrlD, // chooses which opperation to do - specifics shown at bottom of module and in each unit - output logic [2:0] FResSelD, // select one of the results done in the memory stage - output logic [1:0] FIntResSelD, // select the result that will be written to the integer register - output logic FmtD, // precision - single-0 double-1 - output logic [2:0] FrmD, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - output logic FWriteIntD // is the result written to the integer register + input logic FDivBusyE, // is the divider busy + output logic IllegalFPUInstrD, IllegalFPUInstrM, // Is the instruction an illegal fpu instruction + output logic FRegWriteM, FRegWriteW, // FP register write enable + output logic [2:0] FrmM, // FP rounding mode + output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format + output logic DivStartE, // Start division or squareroot + output logic XEnE, YEnE, ZEnE, + output logic YEnForwardE, ZEnForwardE, + output logic FWriteIntE, FWriteIntM, // Write to integer register + output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component + output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage + output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit + output logic [4:0] Adr1E, Adr2E, Adr3E // adresses of each input ); - `define FCTRLW 14 + `define FCTRLW 11 logic [`FCTRLW-1:0] ControlsD; + logic IllegalFPUInstrE; + logic FRegWriteD; // FP register write enable + logic DivStartD; // integer register write enable + logic FWriteIntD; // integer register write enable + logic FRegWriteE; // FP register write enable + logic [2:0] OpCtrlD; // Select which opperation to do in each component + logic [1:0] PostProcSelD; // select result in the post processing unit + logic [1:0] FResSelD; // Select one of the results that finish in the memory stage + logic [2:0] FrmD, FrmE; // FP rounding mode + logic [`FMTBITS-1:0] FmtD; // FP format + //*** will putting x for don't cares reduce area in synthisis??? // FPU Instruction Decoder always_comb if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled - ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; + ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; else case(OpD) - // FRegWrite_FWriteInt_FResultSel_FOpCtrl_FResSel_FIntResSel_FDivStart_IllegalFPUInstr + // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr 7'b0000111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b1_0_00_000_000_00_0_0; // flw - 3'b011: ControlsD = `FCTRLW'b1_0_00_001_000_00_0_0; // fld - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // flw + 3'b011: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0; // fld + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b0100111: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_0_00_010_000_00_0_0; // fsw - 3'b011: ControlsD = `FCTRLW'b0_0_00_011_000_00_0_0; // fsd - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsw + 3'b011: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0; // fsd + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase - 7'b1000011: ControlsD = `FCTRLW'b1_0_01_000_000_00_0_0; // fmadd - 7'b1000111: ControlsD = `FCTRLW'b1_0_01_001_000_00_0_0; // fmsub - 7'b1001011: ControlsD = `FCTRLW'b1_0_01_010_000_00_0_0; // fnmsub - 7'b1001111: ControlsD = `FCTRLW'b1_0_01_011_000_00_0_0; // fnmadd + 7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0; // fmadd + 7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0; // fmsub + 7'b1001011: ControlsD = `FCTRLW'b1_0_01_10_010_0_0; // fnmsub + 7'b1001111: ControlsD = `FCTRLW'b1_0_01_10_011_0_0; // fnmadd 7'b1010011: casez(Funct7D) - 7'b00000??: ControlsD = `FCTRLW'b1_0_01_110_000_00_0_0; // fadd - 7'b00001??: ControlsD = `FCTRLW'b1_0_01_111_000_00_0_0; // fsub - 7'b00010??: ControlsD = `FCTRLW'b1_0_01_100_000_00_0_0; // fmul - 7'b00011??: ControlsD = `FCTRLW'b1_0_10_000_000_00_1_0; // fdiv - 7'b01011??: ControlsD = `FCTRLW'b1_0_10_001_000_00_1_0; // fsqrt + 7'b00000??: ControlsD = `FCTRLW'b1_0_01_10_110_0_0; // fadd + 7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0; // fsub + 7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0; // fmul + 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0; // fdiv + 7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0; // fsqrt 7'b00100??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_11_000_001_00_0_0; // fsgnj - 3'b001: ControlsD = `FCTRLW'b1_0_11_001_001_00_0_0; // fsgnjn - 3'b010: ControlsD = `FCTRLW'b1_0_11_010_001_00_0_0; // fsgnjx - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0; // fsgnj + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0; // fsgnjn + 3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0; // fsgnjx + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b00101??: case(Funct3D) - 3'b000: ControlsD = `FCTRLW'b1_0_11_111_010_00_0_0; // fmin - 3'b001: ControlsD = `FCTRLW'b1_0_11_101_010_00_0_0; // fmax - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0; // fmin + 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0; // fmax + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase 7'b10100??: case(Funct3D) - 3'b010: ControlsD = `FCTRLW'b0_1_11_010_010_00_0_0; // feq - 3'b001: ControlsD = `FCTRLW'b0_1_11_001_010_00_0_0; // flt - 3'b000: ControlsD = `FCTRLW'b0_1_11_011_010_00_0_0; // fle - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0; // feq + 3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0; // flt + 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0; // fle + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx__0_1; // non-implemented instruction endcase - 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_11_000_000_10_0_0; // fclass - else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_100_000_01_0_0; // fmv.x.w - else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_101_000_01_0_0; // fmv.x.d - else ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0; // fclass + else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.w to int reg + else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0; // fmv.x.d to int reg + else ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction 7'b1101000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_11_000_011_00_0_0; // fcvt.s.w - 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.s.wu - 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.s.l - 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.s.lu - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.s.w w->s + 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.s.wu wu->s + 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.s.l l->s + 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.s.lu lu->s endcase 7'b1100000: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.s - 2'b01: ControlsD = `FCTRLW'b0_1_11_011_011_11_0_0; // fcvt.wu.s - 2'b10: ControlsD = `FCTRLW'b0_1_11_101_011_11_0_0; // fcvt.l.s - 2'b11: ControlsD = `FCTRLW'b0_1_11_111_011_11_0_0; // fcvt.lu.s - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.s s->w + 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.s s->wu + 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.s s->l + 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.s s->lu endcase - 7'b1111000: ControlsD = `FCTRLW'b1_0_11_000_000_00_0_0; // fmv.w.x - 7'b010000?: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.s.d + 7'b1111000: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.w.x to fp reg + 7'b0100000: ControlsD = `FCTRLW'b1_0_01_00_000_0_0; // fcvt.s.d 7'b1101001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b1_0_11_000_011_00_0_0; // fcvt.d.w - 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.d.wu - 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.d.l - 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.d.lu - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b1_0_01_00_101_0_0; // fcvt.d.w w->d + 2'b01: ControlsD = `FCTRLW'b1_0_01_00_100_0_0; // fcvt.d.wu wu->d + 2'b10: ControlsD = `FCTRLW'b1_0_01_00_111_0_0; // fcvt.d.l l->d + 2'b11: ControlsD = `FCTRLW'b1_0_01_00_110_0_0; // fcvt.d.lu lu->d endcase 7'b1100001: case(Rs2D[1:0]) - 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.d - 2'b01: ControlsD = `FCTRLW'b0_1_11_011_011_11_0_0; // fcvt.wu.d - 2'b10: ControlsD = `FCTRLW'b0_1_11_101_011_11_0_0; // fcvt.l.d - 2'b11: ControlsD = `FCTRLW'b0_1_11_111_011_11_0_0; // fcvt.lu.d - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + 2'b00: ControlsD = `FCTRLW'b0_1_01_00_001_0_0; // fcvt.w.d d->w + 2'b01: ControlsD = `FCTRLW'b0_1_01_00_000_0_0; // fcvt.wu.d d->wu + 2'b10: ControlsD = `FCTRLW'b0_1_01_00_011_0_0; // fcvt.l.d d->l + 2'b11: ControlsD = `FCTRLW'b0_1_01_00_010_0_0; // fcvt.lu.d d->lu endcase - 7'b1111001: ControlsD = `FCTRLW'b1_0_11_001_000_00_0_0; // fmv.d.x - //7'b0100001: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.d.s - default: ControlsD = `FCTRLW'b0_0_00_000_100_00_0_1; // non-implemented instruction + 7'b1111001: ControlsD = `FCTRLW'b1_0_00_xx_011_0_0; // fmv.d.x to fp reg + 7'b0100001: ControlsD = `FCTRLW'b1_0_01_00_001_0_0; // fcvt.d.s + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase - default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_xx_0xx_0_1; // non-implemented instruction endcase // unswizzle control bits - assign {FRegWriteD, FWriteIntD, FResultSelD, FOpCtrlD, FResSelD, FIntResSelD, FDivStartD, IllegalFPUInstrD} = ControlsD; + assign {FRegWriteD, FWriteIntD, FResSelD, PostProcSelD, OpCtrlD, DivStartD, IllegalFPUInstrD} = ControlsD; // rounding modes: // 000 - round to nearest, ties to even @@ -119,77 +163,99 @@ module fctrl ( // Precision // 0-single // 1-double - assign FmtD = FResultSelD == 2'b00 ? Funct3D[0] : FResSelD == 3'b100 | OpD[6:1] == 6'b010000 ? ~Funct7D[0] : Funct7D[0]; - - // FResultSel: - // 000 - ReadRes - load - // 001 - FMARes - FMA and multiply - // 010 - FAddRes - add and fp to fp - // 011 - FDivRes - divide and squareroot - // 100 - FRes - anything that is written to the fp register and is ready in the memory stage - // FResSel: - // 00 - SrcA - move to fp register - // 01 - SgnRes - sign injection - // 10 - CmpRes - min/max - // 11 - CvtRes - convert to fp - // FIntResSel: - // 00 - CmpRes - less than, equal, or less than or equal - // 01 - FSrcX - move to int register - // 10 - ClassRes - classify - // 11 - CvtRes - convert to signed/unsigned int + if (`FPSIZES == 1) + assign FmtD = 0; + else if (`FPSIZES == 2)begin + logic [1:0] FmtTmp; + assign FmtTmp = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : (~OpD[6]&(&OpD[2:0])) ? {~Funct3D[1], ~(Funct3D[1]^Funct3D[0])} : Funct7D[1:0]; + assign FmtD = (`FMT == FmtTmp); + end + else if (`FPSIZES == 3|`FPSIZES == 4) + assign FmtD = ((Funct7D[6:3] == 4'b0100)&OpD[4]) ? Rs2D[1:0] : Funct7D[1:0]; - // OpCtrl values: - // div/sqrt - // fdiv = ???0 - // fsqrt = ???1 - - // cmp - // fmin = ?111 - // fmax = ?101 - // feq = ?010 - // flt = ?001 - // fle = ?011 - // {?, is min or max, is eq or le, is lt or le} - - //fma/mult - // fmadd = ?000 - // fmsub = ?001 - // fnmsub = ?010 -(a*b)+c - // fnmadd = ?011 -(a*b)-c - // fmul = ?100 - // {?, is mul, negate product, negate addend} - - // sgn inj - // fsgnj = ??00 - // fsgnjn = ??01 - // fsgnjx = ??10 - - // add/sub/cnvt - // fadd = 0000 - // fsub = 0001 - // fcvt.s.d = 0111 - // fcvt.d.s = 0111 - // Fmt controls the output for fp -> fp - // convert - // fcvt.w.s = 0010 - // fcvt.wu.s = 0110 - // fcvt.s.w = 0001 - // fcvt.s.wu = 0101 - // fcvt.l.s = 1010 - // fcvt.lu.s = 1110 - // fcvt.s.l = 1001 - // fcvt.s.lu = 1101 - // fcvt.w.d = 0010 - // fcvt.wu.d = 0110 - // fcvt.d.w = 0001 - // fcvt.d.wu = 0101 - // fcvt.l.d = 1010 - // fcvt.lu.d = 1110 - // fcvt.d.l = 1001 - // fcvt.d.lu = 1101 - // {long, unsigned, to int, from int} + +// enables: +// X - all except int->fp, store, load, mv int->fp +// Y - all except cvt, mv, load, class, sqrt +// Z - fma ops only +// load/store mv int->fp cvt int->fp + assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2])); +// load/class mv cvt + assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0])))); + assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]); + assign YEnForwardE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0])))); + assign ZEnForwardE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&~OpCtrlE[2]; + +// Final Res Sel: +// fp int +// 00 other cmp +// 01 postproc cvt +// 10 store class +// 11 mv + +// post processing Sel: +// 00 cvt +// 01 div +// 10 fma + +// Other Sel: +// Ctrl signal = {OpCtrl[2], &FOpctrl[1:0]} +// 000 - sign 00 +// 001 - negate sign 00 +// 010 - xor sign 00 +// 011 - mv to fp 01 +// 110 - min 10 +// 101 - max 10 + +// OpCtrl: +// Fma: {not multiply-add?, negate prod?, negate Z?} +// 000 - fmadd +// 001 - fmsub +// 010 - fnmsub +// 011 - fnmadd +// 100 - mul +// 110 - add +// 111 - sub +// Div: +// 0 - div +// 1 - sqrt +// Cvt Int: {Int to Fp?, 64 bit int?, signed int?} +// Cvt Fp: output format +// 10 - to half +// 00 - to single +// 01 - to double +// 11 - to quad +// Cmp: {equal?, less than?} +// 010 - eq +// 001 - lt +// 011 - le +// 110 - min +// 101 - max +// Sgn: +// 00 - sign +// 01 - negate sign +// 10 - xor sign + // D/E pipleine register + flopenrc #(12+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, + {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD}, + {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE}); + flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, + {Adr1E, Adr2E, Adr3E}); + flopenrc #(1) DEDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, DivStartD, DivStartE); + if(`FLEN>`XLEN) + flopenrc #(1) DEIllegalReg(clk, reset, FlushE, ~StallE, IllegalFPUInstrD, IllegalFPUInstrE); + // E/M pipleine register + flopenrc #(12+int'(`FMTBITS)) EMCtrlReg (clk, reset, FlushM, ~StallM, + {FRegWriteE, FResSelE, PostProcSelE, FrmE, FmtE, OpCtrlE, FWriteIntE}, + {FRegWriteM, FResSelM, PostProcSelM, FrmM, FmtM, OpCtrlM, FWriteIntM}); + if(`FLEN>`XLEN) + flopenrc #(1) EMIllegalReg(clk, reset, FlushM, ~StallM, IllegalFPUInstrE, IllegalFPUInstrM); + // M/W pipleine register + flopenrc #(3) MWCtrlReg(clk, reset, FlushW, ~StallW, + {FRegWriteM, FResSelM}, + {FRegWriteW, FResSelW}); endmodule diff --git a/pipelined/src/fpu/fcvt.sv b/pipelined/src/fpu/fcvt.sv new file mode 100644 index 000000000..d2967887f --- /dev/null +++ b/pipelined/src/fpu/fcvt.sv @@ -0,0 +1,235 @@ + +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Floating point conversions of configurable size +// +// Int component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR Int PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fcvt ( + input logic Xs, // input's sign + input logic [`NE-1:0] Xe, // input's exponent + input logic [`NF:0] Xm, // input's fraction + input logic [`XLEN-1:0] Int, // integer input - from IEU + input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic XZero, // is the input zero + input logic XDenorm, // is the input denormalized + input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) + output logic [`NE:0] Ce, // the calculated expoent + output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by + output logic ResDenormUf,// does the result underflow or is denormalized + output logic Cs, // the result's sign + output logic IntZero, // is the integer zero? + output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) + ); + + // OpCtrls: + // fp->fp conversions: {0, output precision} - only one of the operations writes to the int register + // half - 10 + // single - 00 + // double - 01 + // quad - 11 + // int<->fp conversions: {is int->fp?, is the integer 64-bit?, is the integer signed?} + // bit 2 bit 1 bit 0 + // for example: signed long -> single floating point has the OpCode 101 + + + + logic [`FMTBITS-1:0] OutFmt; // format of the output + logic [`XLEN-1:0] PosInt; // the positive integer input + logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size + logic [`NE-2:0] NewBias; // the bias of the final result + logic [`NE-1:0] OldExp; // the old exponent + logic Signed; // is the opperation with a signed integer? + logic Int64; // is the integer 64 bits? + logic IntToFp; // is the opperation an int->fp conversion? + logic [`CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder) + logic [`LOGCVTLEN-1:0] LeadingZeros; // output from the LZC + + + // seperate OpCtrl for code readability + assign Signed = OpCtrl[0]; + assign Int64 = OpCtrl[1]; + assign IntToFp = OpCtrl[2]; + + // choose the ouptut format depending on the opperation + // - fp -> fp: OpCtrl contains the percision of the output + // - int -> fp: Fmt contains the percision of the output + if (`FPSIZES == 2) + assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == `FMT); + else if (`FPSIZES == 3 | `FPSIZES == 4) + assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0]; + + + /////////////////////////////////////////////////////////////////////////// + // negation + /////////////////////////////////////////////////////////////////////////// + // 1) negate the input if the input is a negitive singed integer + // 2) trim the input to the proper size (kill the 32 most significant zeroes if needed) + + assign PosInt = Cs ? -Int : Int; + assign TrimInt = {{`XLEN-32{Int64}}, {32{1'b1}}} & PosInt; + assign IntZero = ~|TrimInt; + + /////////////////////////////////////////////////////////////////////////// + // lzc + /////////////////////////////////////////////////////////////////////////// + + // choose the input to the leading zero counter i.e. priority encoder + // int -> fp : | positive integer | 00000... (if needed) | + // fp -> fp : | fraction | 00000... (if needed) | + assign LzcInFull = IntToFp ? {TrimInt, {`CVTLEN-`XLEN+1{1'b0}}} : + {Xm, {`CVTLEN-`NF{1'b0}}}; + assign LzcIn = LzcInFull[`CVTLEN-1:0]; + + lzc #(`CVTLEN+1) lzc (.num(LzcInFull), .ZeroCnt(LeadingZeros)); + + /////////////////////////////////////////////////////////////////////////// + // shifter + /////////////////////////////////////////////////////////////////////////// + + // kill the shift if it's negitive + // select the amount to shift by + // fp -> int: + // - shift left by CalcExp - essentially shifting until the unbiased exponent = 0 + // - don't shift if supposed to shift right (underflowed or denorm input) + // denormalized/undeflowed result fp -> fp: + // - shift left by NF-1+CalcExp - to shift till the biased expoenent is 0 + // ??? -> fp: + // - shift left by LeadingZeros - to shift till the result is normalized + // - only shift fp -> fp if the intital value is denormalized + // - this is a problem because the input to the lzc was the fraction rather than the mantissa + // - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true? + always_comb + if(ToInt) ShiftAmt = Ce[`LOGCVTLEN-1:0]&{`LOGCVTLEN{~Ce[`NE]}}; + else if (ResDenormUf&~IntToFp) ShiftAmt = (`LOGCVTLEN)'(`NF-1)+Ce[`LOGCVTLEN-1:0]; + else ShiftAmt = LeadingZeros; + + /////////////////////////////////////////////////////////////////////////// + // exp calculations + /////////////////////////////////////////////////////////////////////////// + + + // *** possible optimizaations: + // - if subtracting exp by bias only the msb needs a full adder, the rest can be HA - dunno how to implement this for synth + // - Smaller exp -> Larger Exp can be calculated with: *** can use in Other units??? FMA??? insert this thing in later + // Exp if in range: {~Exp[SNE-1], Exp[SNE-2:0]} + // Exp in range if: Exp[SNE-1] = 1 & Exp[LNE-2:SNE] = 1111... & Exp[LNE-1] = 0 | Exp[SNE-1] = 0 & Exp[LNE-2:SNE] = 000... & Exp[LNE-1] = 1 + // i.e.: &Exp[LNE-2:SNE-1] xor Exp[LNE-1] + // Too big if: Exp[LNE-1] = 1 + // Too small if: none of the above + + // Select the bias of the output + // fp -> int : select 1 + // ??? -> fp : pick the new bias depending on the output format + if (`FPSIZES == 1) begin + assign NewBias = ToInt ? (`NE-1)'(1) : (`NE-1)'(`BIAS); + + end else if (`FPSIZES == 2) begin + logic [`NE-2:0] NewBiasToFp; + assign NewBiasToFp = OutFmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; + + end else if (`FPSIZES == 3) begin + logic [`NE-2:0] NewBiasToFp; + always_comb + case (OutFmt) + `FMT: NewBiasToFp = (`NE-1)'(`BIAS); + `FMT1: NewBiasToFp = (`NE-1)'(`BIAS1); + `FMT2: NewBiasToFp = (`NE-1)'(`BIAS2); + default: NewBiasToFp = {`NE-1{1'bx}}; + endcase + assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; + + end else if (`FPSIZES == 4) begin + logic [`NE-2:0] NewBiasToFp; + always_comb + case (OutFmt) + 2'h3: NewBiasToFp = (`NE-1)'(`Q_BIAS); + 2'h1: NewBiasToFp = (`NE-1)'(`D_BIAS); + 2'h0: NewBiasToFp = (`NE-1)'(`S_BIAS); + 2'h2: NewBiasToFp = (`NE-1)'(`H_BIAS); + endcase + assign NewBias = ToInt ? (`NE-1)'(1) : NewBiasToFp; + end + // select the old exponent + // int -> fp : largest bias + XLEN + // fp -> ??? : XExp + assign OldExp = IntToFp ? (`NE)'(`BIAS)+(`NE)'(`XLEN-1) : Xe; + + // calculate CalcExp + // fp -> fp : + // - XExp - Largest bias + new bias - (LeadingZeros+1) + // only do ^ if the input was denormalized + // - convert the expoenent to the final preciaion (Exp - oldBias + newBias) + // - correct the expoent when there is a normalization shift ( + LeadingZeros+1) + // fp -> int : XExp - Largest Bias + 1 - (LeadingZeros+1) + // | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp + // process: + // - start + // | `XLEN zeros | Mantissa | 0's if nessisary | + // + // - shift left 1 (1) + // | `XLEN-1 zeros |bit| frac | 0's if nessisary | + // . <- binary point + // + // - shift left till unbiased exponent is 0 (XExp - Largest Bias) + // | 0's | Mantissa | 0's if nessisary | + // | keep | + // + // - if the input is denormalized then we dont shift... so the "- LeadingZeros" is just leftovers from other options + // int -> fp : largest bias + XLEN - Largest bias + new bias - LeadingZeros = XLEN + NewBias - LeadingZeros + // Process: + // - shifted right by XLEN (XLEN) + // - shift left to normilize (-LeadingZeros) + // - newBias to make the biased exponent + // oldexp - biasold +newbias - LeadingZeros&(XDenorm|IntToFp) + assign Ce = {1'b0, OldExp} - (`NE+1)'(`BIAS) + {2'b0, NewBias} - {{`NE-`LOGCVTLEN+1{1'b0}}, (LeadingZeros&{`LOGCVTLEN{XDenorm|IntToFp}})}; + // find if the result is dnormal or underflows + // - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0) + // - can't underflow an integer to Fp conversion + assign ResDenormUf = (~|Ce | Ce[`NE])&~XZero&~IntToFp; + + + /////////////////////////////////////////////////////////////////////////// + // sign + /////////////////////////////////////////////////////////////////////////// + + // determine the sign of the result + // - if int -> fp + // - if 64-bit : check the msb of the 64-bit integer input and if it's signed + // - if 32-bit : check the msb of the 32-bit integer input and if it's signed + // - otherwise: the floating point input's sign + always_comb + if(IntToFp) + if(Int64) Cs = Int[`XLEN-1]&Signed; + else Cs = Int[31]&Signed; + else Cs = Xs; + +endmodule + diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv deleted file mode 100644 index fb8e1ad9a..000000000 --- a/pipelined/src/fpu/fcvtfp.sv +++ /dev/null @@ -1,190 +0,0 @@ - -`include "wally-config.vh" -module cvtfp ( - input logic [10:0] XExpE, // input's exponent - input logic [52:0] XManE, // input's mantissa - input logic XSgnE, // input's sign - input logic XZeroE, // is the input zero - input logic XDenormE, // is the input denormalized - input logic XInfE, // is the input infinity - input logic XNaNE, // is the input a NaN - input logic XSNaNE, // is the input a signaling NaN - input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtE, // the input's precision (1 = double 0 = single) - output logic [63:0] CvtFpResE, // the fp to fp conversion's result - output logic [4:0] CvtFpFlgE); // the fp to fp conversion's flags - - logic [12:0] DSExp; // double to single precision exponent - logic Denorm; // is the double to single precision result denormalized - logic Shift; // do you shift the double precision exponent (if single precision result is denormalized) - logic [51:0] SDFrac; // single to double precision fraction - logic [25:0] DSFrac; // double to single precision fraction - logic [77:0] DSFracShifted; // single precision fraction shifted for double precision - logic Sticky, UfSticky, Guard, Round, LSBFrac, UfGuard, UfRound, UfLSBFrac; // rounding bits - logic CalcPlus1, UfCalcPlus1, Plus1, UfPlus1; // do you add one to the result - logic [12:0] DSExpFull; // full double to single exponent - logic [22:0] DSResFrac; // final double to single fraction - logic [7:0] DSResExp; // final double to single exponent - logic [10:0] SDExp; // final single to double precision exponent - logic Overflow, Underflow, Inexact; // flags - logic [31:0] DSRes; // double to single precision result - - - // add support for all formats - // consider reordering code blocks so upconverting is in one region of the file - // and downconverting is in the other region. - - /////////////////////////////////////////////////////////////////////////////// - // LZC: Leading Zero Counter - /////////////////////////////////////////////////////////////////////////////// - - // *** consider sharing this with fcvtint - // *** emphasize parallel structure between the two - // *** add a priorityencoder module to generic (similar to priorityonehot) and use it - - // LZC - find the first 1 in the input's mantissa - logic [8:0] i,NormCnt; - always_comb begin - i = 0; - while (~XManE[52-i] & i <= 52) i = i+1; // search for leading one - NormCnt = i; - end - - - /////////////////////////////////////////////////////////////////////////////// - // Expoents - /////////////////////////////////////////////////////////////////////////////// - - // convert the single precion exponent to single precision. - // - subtract the double precision exponent (1023) and add the - // single precsision exponent (127) - // - if the input is zero then kill the exponent - - assign DSExp = ({2'b0,XExpE}-13'd1023+13'd127)&{13{~XZeroE}}; - - // is the converted double to single precision exponent in the denormalized range - assign Denorm = $signed(DSExp) <= 0 & $signed(DSExp) > $signed(-(13'd23)); - - - // caluculate the final single to double precsion exponent - // - subtract the single precision bias (127) and add the double - // precision bias (127) - // - if the result is zero or denormalized, kill the exponent - assign SDExp = XExpE-({2'b0,NormCnt&{9{~XZeroE}}})+({11{XDenormE}}&1024-127); //*** seems ineffecient - - - - /////////////////////////////////////////////////////////////////////////////// - // Fraction - /////////////////////////////////////////////////////////////////////////////// - - - // normalize the single precision fraction for double precsion - // - needed for denormal single precsion values - assign SDFrac = XManE[51:0] << NormCnt; - - // check if the double precision mantissa needs to be shifted - // - the mantissa needs to be shifted if the single precision result is denormal - assign Shift = Denorm | (($signed(DSExp) > $signed(-(13'd25))) & DSExp[12]); - // shift the mantissa - assign DSFracShifted = {XManE, 25'b0} >> ((-DSExp+1)&{13{Shift}}); //***might be some optimization here - assign DSFrac = DSFracShifted[76:51]; - - - - /////////////////////////////////////////////////////////////////////////////// - // Rounder - /////////////////////////////////////////////////////////////////////////////// - - // used to determine underflow flag - assign UfSticky = |DSFracShifted[50:0]; - assign UfGuard = DSFrac[1]; - assign UfRound = DSFrac[0]; - assign UfLSBFrac = DSFrac[2]; - - - assign Sticky = UfSticky | UfRound; - assign Guard = DSFrac[2]; - assign Round = DSFrac[1]; - assign LSBFrac = DSFrac[3]; - - - always_comb begin // ***remove guard bit - // Determine if you add 1 - case (FrmE) - 3'b000: CalcPlus1 = Guard & (Round | (Sticky) | (~Round&~Sticky&LSBFrac));//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = XSgnE;//round down - 3'b011: CalcPlus1 = ~XSgnE;//round up - 3'b100: CalcPlus1 = (Guard & (Round | (Sticky) | (~Round&~Sticky)));//round to nearest max magnitude - default: CalcPlus1 = 1'bx; - endcase - // Determine if you add 1 (for underflow flag) - case (FrmE) - 3'b000: UfCalcPlus1 = UfGuard & (UfRound | UfSticky | (~UfRound&~UfSticky&UfLSBFrac));//round to nearest even - 3'b001: UfCalcPlus1 = 0;//round to zero - 3'b010: UfCalcPlus1 = XSgnE;//round down - 3'b011: UfCalcPlus1 = ~XSgnE;//round up - 3'b100: UfCalcPlus1 = (UfGuard & (UfRound | UfSticky | (~UfRound&~UfSticky)));//round to nearest max magnitude - default: UfCalcPlus1 = 1'bx; - endcase - - end - - // if an answer is exact don't round - assign Plus1 = CalcPlus1 & (Sticky | UfGuard | Guard | Round); - assign UfPlus1 = UfCalcPlus1 & (Sticky | UfGuard); - - - - // round the double to single precision result - assign {DSExpFull, DSResFrac} = {DSExp&{13{~Denorm}}, DSFrac[25:3]} + {35'b0,Plus1}; - assign DSResExp = DSExpFull[7:0]; - - - /////////////////////////////////////////////////////////////////////////////// - // Flags - /////////////////////////////////////////////////////////////////////////////// - - // calculate the flags - // - overflow, underflow and inexact can only be set by the double to single precision opperation - // - don't set underflow or overflow if the input is NaN or Infinity - // - don't set the inexact flag if the input is NaN - assign Overflow = $signed(DSExpFull) >= $signed({5'b0, {8{1'b1}}}) & ~(XNaNE|XInfE); - assign Underflow = (($signed(DSExpFull) <= 0) & ((Sticky|Guard|Round) | (XManE[52]&~|DSFrac) | (|DSFrac&~Denorm)) | ((DSExpFull == 1) & Denorm & ~(UfPlus1&UfLSBFrac))) & ~(XNaNE|XInfE); - assign Inexact = (Sticky|Guard|Round|Underflow|Overflow) &~(XNaNE); - - // pack the flags together and choose the result based on the opperation - assign CvtFpFlgE = FmtE ? {XSNaNE, 1'b0, Overflow, Underflow, Inexact} : {XSNaNE, 4'b0}; - - - - /////////////////////////////////////////////////////////////////////////////// - // Result Selection - /////////////////////////////////////////////////////////////////////////////// - - if(`IEEE754) begin - // select the double to single precision result - assign DSRes = XNaNE ? {XSgnE, {8{1'b1}}, 1'b1, XManE[50:29]} : - Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : - Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : - {XSgnE, 8'hff, 23'b0} : - {XSgnE, DSResExp, DSResFrac}; - - // select the final result based on the opperation - //*** in al units before putting into : ? put in a seperate signal - assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]}; - end else begin - // select the double to single precision result - assign DSRes = XNaNE ? {1'b0, {8{1'b1}}, 1'b1, 22'b0} : - Underflow & ~Denorm ? {XSgnE, 30'b0, CalcPlus1&(|FrmE[1:0]|Shift)} : - Overflow | XInfE ? ((FrmE[1:0]==2'b01) | (FrmE[1:0]==2'b10&~XSgnE) | (FrmE[1:0]==2'b11&XSgnE)) & ~XInfE ? {XSgnE, 8'hfe, {23{1'b1}}} : - {XSgnE, 8'hff, 23'b0} : - {XSgnE, DSResExp, DSResFrac}; - - // select the final result based on the opperation - assign CvtFpResE = FmtE ? {{32{1'b1}},DSRes} : {XSgnE&~XNaNE, SDExp, SDFrac[51]|XNaNE, SDFrac[50:0]&{51{~XNaNE}}}; - end -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv deleted file mode 100644 index 6a6686993..000000000 --- a/pipelined/src/fpu/fcvtint.sv +++ /dev/null @@ -1,190 +0,0 @@ - -`include "wally-config.vh" -// `include "../../config/rv64icfd/wally-config.vh" -// `define XLEN 64 -module fcvt ( - input logic XSgnE, // X's sign - input logic [10:0] XExpE, // X's exponent - input logic [52:0] XManE, // X's fraction - input logic XZeroE, // is X zero - input logic XNaNE, // is X NaN - input logic XInfE, // is X infinity - input logic XDenormE, // is X denormalized - input logic [`XLEN-1:0] ForwardedSrcAE, // integer input - input logic [2:0] FOpCtrlE, // chooses which instruction is done (full list below) - input logic [2:0] FrmE, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic FmtE, // precision 1 = double 0 = single - output logic [63:0] CvtResE, // convert final result - output logic [4:0] CvtFlgE); // convert flags {invalid, divide by zero, overflow, underflow, inexact} - - logic ResSgn; // FP result's sign - logic [10:0] ResExp,TmpExp; // FP result's exponent - logic [51:0] ResFrac; // FP result's fraction - logic [6:0] LZResP; // lz output - logic [7:0] Bits; // how many bits are in the integer result - logic [7:0] SubBits; // subtract these bits from the exponent (FP result) - logic [64+51:0] ShiftedManTmp; // Shifted mantissa - logic [64+51:0] ShiftVal; // value being shifted (to int - XMan, to FP - |integer input|) - logic [64+1:0] ShiftedMan; // shifted mantissa truncated - logic [64:0] RoundedTmp; // full size rounded result - in case of overfow - logic [63:0] Rounded; // rounded result - logic [12:0] ExpVal; // unbiased X exponent - logic [12:0] ShiftCnt; // how much is the mantissa shifted - logic [64-1:0] IntIn; // trimed integer input - logic [64-1:0] PosInt; // absolute value of the integer input - logic [63:0] CvtIntRes; // interger result from the fp -> int instructions - logic [63:0] CvtFPRes; // floating point result from the int -> fp instructions - logic Of, Uf; // did the integer result underflow or overflow - logic Guard, Round, LSB, Sticky; // bits used to determine rounding - logic Plus1,CalcPlus1; // do you add one for rounding - logic SgnRes; // sign of the floating point result - logic Res64, In64; // is the result or input 64 bits - logic RoundMSB; // most significant bit of the fraction - logic RoundSgn; // sign of the rounded result - logic Invalid, Inexact; // flags - - // FOpCtrlE: - // fcvt.w.s = 001 - // fcvt.wu.s = 011 - // fcvt.s.w = 000 - // fcvt.s.wu = 010 - // fcvt.l.s = 101 - // fcvt.lu.s = 111 - // fcvt.s.l = 100 - // fcvt.s.lu = 110 - // fcvt.w.d = 001 - // fcvt.wu.d = 011 - // fcvt.d.w = 000 - // fcvt.d.wu = 010 - // fcvt.l.d = 101 - // fcvt.lu.d = 111 - // fcvt.d.l = 100 - // fcvt.d.lu = 110 - // {long, unsigned, to int} - - // *** revisit this module, explain in more depth - // should the int to fp and fp to int paths be separated? - // add support for all formats - - // calculate signals based off the input and output's size - assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]); - assign In64 = (~FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&FOpCtrlE[0]); - assign SubBits = In64 ? 8'd64 : 8'd32; - assign Bits = Res64 ? 8'd64 : 8'd32; - - // calulate the unbiased exponent - assign ExpVal = {1'b0,XExpE} - {1'b0, (11)'(`BIAS)} + {12'b0, XDenormE}; - -//////////////////////////////////////////////////////// - - // position the input in the most significant bits - assign IntIn = FOpCtrlE[2] ? {ForwardedSrcAE, {64-`XLEN{1'b0}}} : {ForwardedSrcAE[31:0], 32'b0}; - // make the integer positive - assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn; - // determine the integer's sign - assign ResSgn = ~FOpCtrlE[1]&IntIn[64-1]; - - // Leading one detector - logic [8:0] i; - always_comb begin - i = 0; - while (~PosInt[64-1-i] & i < `XLEN) i = i+1; // search for leading one - LZResP = i[5:0]+1; // compute shift count - end - - // if no one was found set to zero otherwise calculate the exponent - assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {4'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {4'b0, LZResP}; - - - - -//////////////////////////////////////////// - - - // select the shift value and amount based on operation (to fp or int) - assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {6'b0, LZResP}; - assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0}; - - // if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds) - // if the shift is negitive add a bit for sticky bit calculation - // otherwise shift left - assign ShiftedManTmp = &ShiftCnt ? {{64{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; - - // truncate the shifted mantissa - assign ShiftedMan = ShiftedManTmp[64+51:50]; - - // calculate sticky bit - // - take into account the possible right shift from before - // - the sticky bit calculation covers three diffrent sizes depending on the opperation - assign Sticky = |ShiftedManTmp[49:0] | &ShiftCnt&XManE[0] | (~FOpCtrlE[0]&|ShiftedManTmp[62:50]) | (~FOpCtrlE[0]&~FmtE&|ShiftedManTmp[91:63]); - - - // determine guard, round, and least significant bit of the result - assign Guard = FOpCtrlE[0] ? ShiftedMan[1] : FmtE ? ShiftedMan[13] : ShiftedMan[42]; - assign Round = FOpCtrlE[0] ? ShiftedMan[0] : FmtE ? ShiftedMan[12] : ShiftedMan[41]; - assign LSB = FOpCtrlE[0] ? ShiftedMan[2] : FmtE ? ShiftedMan[14] : ShiftedMan[43]; - - always_comb begin//*** remove guard bit - // Determine if you add 1 - case (FrmE) - 3'b000: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky&LSB));//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = (XSgnE&FOpCtrlE[0]) | (ResSgn&~FOpCtrlE[0]);//round down - 3'b011: CalcPlus1 = (~XSgnE&FOpCtrlE[0]) | (~ResSgn&~FOpCtrlE[0]);//round up - 3'b100: CalcPlus1 = Guard & (Round | Sticky | (~Round&~Sticky));//round to nearest max magnitude - default: CalcPlus1 = 1'bx; - endcase - end - - // dont tound if the result is exact - assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZeroE&FOpCtrlE[0]); - - // round the shifted mantissa - assign RoundedTmp = ShiftedMan[64+1:2] + {64'b0, Plus1}; - assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + {62'b0, Plus1} : {{TmpExp, ShiftedMan[64+1:43]} + {33'b0,Plus1}, 29'b0} ; - - // fit the rounded result into the appropriate size and take the 2's complement if needed - assign Rounded = Res64 ? XSgnE&FOpCtrlE[0] ? -RoundedTmp[63:0] : RoundedTmp[63:0] : - XSgnE ? {{32{1'b1}}, -RoundedTmp[31:0]} : {32'b0, RoundedTmp[31:0]}; - - // extract the MSB and Sign for later use (will be used to determine underflow and overflow) - assign RoundMSB = Res64 ? RoundedTmp[64] : RoundedTmp[32]; - assign RoundSgn = Res64 ? Rounded[63] : Rounded[31]; - - - // check if the result overflows - assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==({{5{Bits[7]}}, Bits}-1))) | (~XSgnE&XInfE) | XNaNE; - - // check if the result underflows (this calculation changes if the result is signed or unsigned) - assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; - - // calculate the result's sign - assign SgnRes = ~FOpCtrlE[2] & FOpCtrlE[0]; - - // select the integer result - assign CvtIntRes = Of ? FOpCtrlE[1] ? {64{1'b1}} : SgnRes ? {33'b0, {31{1'b1}}}: {1'b0, {63{1'b1}}} : - Uf ? FOpCtrlE[1] ? {63'b0, Plus1&~XSgnE} : SgnRes ? {{33{1'b1}}, 31'b0} : {1'b1, 63'b0} : - |RoundedTmp ? Rounded[64-1:0] : 64'b0; - - // select the floating point result - assign CvtFPRes = FmtE ? {ResSgn, ResExp, ResFrac} : {{32{1'b1}}, ResSgn, ResExp[7:0], ResFrac[51:29]}; - - // select the result - assign CvtResE = FOpCtrlE[0] ? CvtIntRes : CvtFPRes; - - // calculate the flags - // - only set invalid flag for out-of-range vales - // - set inexact if in representable range and not exact - - if(`IEEE754) begin // checks before rounding - assign Invalid = (Of | Uf)&FOpCtrlE[0]; - assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&(XSgnE|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); - assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; - end else begin // RISC-V checks if the result is in range after rounding - assign Invalid = (Of | Uf)&FOpCtrlE[0]; - assign Inexact = (Guard|Round|Sticky)&~(&FOpCtrlE[1:0]&((XSgnE&~(ShiftCnt[12]&~Plus1))|Of))&~((Of|Uf)&~FOpCtrlE[1]&FOpCtrlE[0]); - assign CvtFlgE = {Invalid&~Inexact, 3'b0, Inexact}; - end -endmodule // fpadd - - diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index b80c814fd..690e04ebb 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -31,47 +31,51 @@ `include "wally-config.vh" module fhazard( - input logic [4:0] Adr1E, Adr2E, Adr3E, // read data adresses - input logic FRegWriteM, FRegWriteW, // is the fp register being written to - input logic [4:0] RdM, RdW, // the adress being written to - input logic [1:0] FResultSelM, // the result being selected + input logic [4:0] Adr1E, Adr2E, Adr3E, // read data adresses + input logic FRegWriteM, FRegWriteW, // is the fp register being written to + input logic [4:0] RdM, RdW, // the adress being written to + input logic [1:0] FResSelM, // the result being selected + input logic XEnE, YEnE, ZEnE, output logic FStallD, // stall the decode stage - output logic [1:0] FForwardXE, FForwardYE, FForwardZE // select a forwarded value + output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value ); always_comb begin // set defaults - FForwardXE = 2'b00; // choose FRD1E - FForwardYE = 2'b00; // choose FRD2E - FForwardZE = 2'b00; // choose FRD3E + ForwardXE = 2'b00; // choose FRD1E + ForwardYE = 2'b00; // choose FRD2E + ForwardZE = 2'b00; // choose FRD3E FStallD = 0; // if the needed value is in the memory stage - input 1 - if ((Adr1E == RdM) & FRegWriteM) - // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 2'b11) FForwardXE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall - // if the needed value is in the writeback stage - else if ((Adr1E == RdW) & FRegWriteW) FForwardXE = 2'b01; // choose FPUResult64W + if(XEnE) + if ((Adr1E == RdM) & FRegWriteM) + // if the result will be FResM (can be taken from the memory stage) + if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM + else FStallD = 1; // otherwise stall + // if the needed value is in the writeback stage + else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W // if the needed value is in the memory stage - input 2 - if ((Adr2E == RdM) & FRegWriteM) - // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 2'b11) FForwardYE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall - // if the needed value is in the writeback stage - else if ((Adr2E == RdW) & FRegWriteW) FForwardYE = 2'b01; // choose FPUResult64W + if(YEnE) + if ((Adr2E == RdM) & FRegWriteM) + // if the result will be FResM (can be taken from the memory stage) + if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM + else FStallD = 1; // otherwise stall + // if the needed value is in the writeback stage + else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W // if the needed value is in the memory stage - input 3 - if ((Adr3E == RdM) & FRegWriteM) - // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 2'b11) FForwardZE = 2'b10; // choose FResM - else FStallD = 1; // otherwise stall - // if the needed value is in the writeback stage - else if ((Adr3E == RdW) & FRegWriteW) FForwardZE = 2'b01; // choose FPUResult64W + if(ZEnE) + if ((Adr3E == RdM) & FRegWriteM) + // if the result will be FResM (can be taken from the memory stage) + if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM + else FStallD = 1; // otherwise stall + // if the needed value is in the writeback stage + else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W end diff --git a/pipelined/src/fpu/flags.sv b/pipelined/src/fpu/flags.sv new file mode 100644 index 000000000..67fdb4935 --- /dev/null +++ b/pipelined/src/fpu/flags.sv @@ -0,0 +1,176 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Post-Processing flag calculation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module flags( + input logic Xs, + input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs + input logic XInf, YInf, ZInf, // inputs are infinity + input logic Plus1, + input logic InfIn, // is a Inf input being used + input logic NaNIn, // is a NaN input being used + input logic [`FMTBITS-1:0] OutFmt, // output format + input logic XZero, YZero, // inputs are zero + input logic Sqrt, // Sqrt? + input logic ToInt, // convert to integer + input logic IntToFp, // convert integer to floating point + input logic Int64, // convert to 64 bit integer + input logic Signed, // convert to a signed integer + input logic [`NE:0] CvtCe, // the calculated expoent - Cvt + input logic CvtOp, // conversion opperation? + input logic DivOp, // conversion opperation? + input logic FmaOp, // Fma opperation? + input logic [`NE+1:0] FullRe, // Re with bits to determine sign and overflow + input logic [`NE+1:0] Me, // exponent of the normalized sum + input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits + input logic FmaAs, FmaPs, // the product and modified Z signs + input logic R, UfL, S, UfPlus1, // bits used to determine rounding + output logic DivByZero, + output logic IntInvalid, Invalid, Overflow, // flags used to select the res + output logic [4:0] PostProcFlg // flags +); + logic SigNaN; // is an input a signaling NaN + logic Inexact; // inexact flag + logic FpInexact; // floating point inexact flag + logic IntInexact; // integer inexact flag + logic FmaInvalid; // integer invalid flag + logic DivInvalid; // integer invalid flag + logic Underflow; // Underflow flag + logic ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent + logic ShiftGtIntSz; // is the shift greater than the the integer size (use Re to account for possible roundning "shift") + + /////////////////////////////////////////////////////////////////////////////// + // Flags + /////////////////////////////////////////////////////////////////////////////// + + + + if (`FPSIZES == 1) begin + assign ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE]; + assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64)); + + end else if (`FPSIZES == 2) begin + assign ResExpGteMax = OutFmt ? &FullRe[`NE-1:0] | FullRe[`NE] : &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]); + + assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64)); + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: ResExpGteMax = &FullRe[`NE-1:0] | FullRe[`NE]; + `FMT1: ResExpGteMax = &FullRe[`NE1-1:0] | (|FullRe[`NE:`NE1]); + `FMT2: ResExpGteMax = &FullRe[`NE2-1:0] | (|FullRe[`NE:`NE2]); + default: ResExpGteMax = 1'bx; + endcase + assign ShiftGtIntSz = (|FullRe[`NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64)); + + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + `Q_FMT: ResExpGteMax = &FullRe[`Q_NE-1:0] | FullRe[`Q_NE]; + `D_FMT: ResExpGteMax = &FullRe[`D_NE-1:0] | (|FullRe[`Q_NE:`D_NE]); + `S_FMT: ResExpGteMax = &FullRe[`S_NE-1:0] | (|FullRe[`Q_NE:`S_NE]); + `H_FMT: ResExpGteMax = &FullRe[`H_NE-1:0] | (|FullRe[`Q_NE:`H_NE]); + endcase + // a left shift of intlen+1 is still in range but any more than that is an overflow + // inital: | 64 0's | XLEN | + // | 64 0's | XLEN | << 64 + // | XLEN | 00000... | + // 65 = ...0 0 0 0 0 1 0 0 0 0 0 1 + // | or | | or | + // 33 = ...0 0 0 0 0 0 1 0 0 0 0 1 + // | or | | or | + // larger or equal if: + // - any of the bits after the most significan 1 is one + // - the most signifcant in 65 or 33 is still a one in the number and + // one of the later bits is one + assign ShiftGtIntSz = (|FullRe[`Q_NE:7]|(FullRe[6]&~Int64)) | ((|FullRe[4:0]|(FullRe[5]&Int64))&((FullRe[5]&~Int64) | FullRe[6]&Int64)); + end + + // if the result is greater than or equal to the max exponent(not taking into account sign) + // | and the exponent isn't negitive + // | | if the input isnt infinity or NaN + // | | | + assign Overflow = ResExpGteMax & ~FullRe[`NE+1]&~(InfIn|NaNIn|DivByZero); + + // detecting tininess after rounding + // the exponent is negitive + // | the result is denormalized + // | | the result is normal and rounded from a denorm + // | | | and if given an unbounded exponent the result does not round + // | | | | and if the result is not exact + // | | | | | and if the input isnt infinity or NaN + // | | | | | | + assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&UfL)))&(R|S))&~(InfIn|NaNIn|DivByZero|Invalid); + + // Set Inexact flag if the res is diffrent from what would be outputed given infinite precision + // - Don't set the underflow flag if an underflowed res isn't outputed + assign FpInexact = (S|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid); + + // if the res is too small to be represented and not 0 + // | and if the res is not invalid (outside the integer bounds) + // | | + assign IntInexact = ((CvtCe[`NE]&~XZero)|S|R)&~IntInvalid; + + // select the inexact flag to output + assign Inexact = ToInt ? IntInexact : FpInexact; + + // Set Invalid flag for following cases: + // 1) any input is a signaling NaN + // 2) Inf - Inf (unless x or y is NaN) + // 3) 0 * Inf + + // if the input is NaN or infinity + // | if the integer res overflows (out of range) + // | | if the input was negitive but ouputing to a unsigned number + // | | | the res doesn't round to zero + // | | | | or the res rounds up out of bounds + // | | | | and the res didn't underflow + // | | | | | + assign IntInvalid = NaNIn|InfIn|(ShiftGtIntSz&~FullRe[`NE+1])|((Xs&~Signed)&(~((CvtCe[`NE]|(~|CvtCe))&~Plus1)))|(CvtNegResMsbs[1]^CvtNegResMsbs[0]); + // | + // or when the positive res rounds up out of range + assign SigNaN = (XSNaN&~(IntToFp&CvtOp)) | (YSNaN&~CvtOp) | (ZSNaN&FmaOp); + assign FmaInvalid = ((XInf | YInf) & ZInf & (FmaPs ^ FmaAs) & ~NaNIn) | (XZero & YInf) | (YZero & XInf); + assign DivInvalid = ((XInf & YInf) | (XZero & YZero))&~Sqrt | (Xs&Sqrt&~NaNIn&~XZero); + + assign Invalid = SigNaN | (FmaInvalid&FmaOp) | (DivInvalid&DivOp); + + // if dividing by zero and not 0/0 + // - don't set flag if an input is NaN or Inf(IEEE says has to be a finite numerator) + assign DivByZero = YZero&DivOp&~Sqrt&~(XZero|NaNIn|InfIn); + + // Combine flags + // - to integer results do not set the underflow or overflow flags + assign PostProcFlg = {Invalid|(IntInvalid&CvtOp&ToInt), DivByZero, Overflow&~(ToInt&CvtOp), Underflow&~(ToInt&CvtOp), Inexact}; + +endmodule + + + + diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index db8ecaf2f..d12f497eb 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // -// Written: Katherine Parry, David Harris -// Modified: 6/23/2021 +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: // // Purpose: Floating point multiply-accumulate of configurable size // @@ -30,97 +30,29 @@ `include "wally-config.vh" module fma( - input logic clk, - input logic reset, - input logic FlushM, // flush the memory stage - input logic StallM, // stall memory stage - input logic [`FPSIZES/3:0] FmtE, FmtM, // precision 1 = double 0 = single - input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic XSgnE, YSgnE, ZSgnE, // input signs - execute stage - input logic [`NE-1:0] XExpE, YExpE, ZExpE, // input exponents - execute stage - input logic [`NF:0] XManE, YManE, ZManE, // input mantissa - execute stage - input logic XSgnM, YSgnM, // input signs - memory stage - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - memory stage - input logic [`NF:0] XManM, YManM, ZManM, // input mantissa - memory stage - input logic XDenormE, YDenormE, ZDenormE, // is denorm - input logic XZeroE, YZeroE, ZZeroE, // is zero - execute stage - input logic XNaNM, YNaNM, ZNaNM, // is NaN - input logic XSNaNM, YSNaNM, ZSNaNM, // is signaling NaN - input logic XZeroM, YZeroM, ZZeroM, // is zero - memory stage - input logic XInfM, YInfM, ZInfM, // is infinity - output logic [`FLEN-1:0] FMAResM, // FMA result - output logic [4:0] FMAFlgM); // FMA flags - - //fma/mult/add - // fmadd = 000 - // fmsub = 001 - // fnmsub = 010 -(a*b)+c - // fnmadd = 011 -(a*b)-c - // fmul = 100 - // fadd = 110 - // fsub = 111 - - // signals transfered between pipeline stages - logic [3*`NF+5:0] SumE, SumM; - logic [`NE+1:0] ProdExpE, ProdExpM; - logic AddendStickyE, AddendStickyM; - logic KillProdE, KillProdM; - logic InvZE, InvZM; - logic NegSumE, NegSumM; - logic ZSgnEffE, ZSgnEffM; - logic PSgnE, PSgnM; - logic [$clog2(3*`NF+7)-1:0] NormCntE, NormCntM; - logic Mult; - - fma1 fma1 (.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, - .FOpCtrlE, .FmtE, .SumE, .NegSumE, .InvZE, .NormCntE, .ZSgnEffE, .PSgnE, - .ProdExpE, .AddendStickyE, .KillProdE); - - // E/M pipeline registers - flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SumE, SumM); - flopenrc #(13) EMRegFma3(clk, reset, FlushM, ~StallM, ProdExpE, ProdExpM); - flopenrc #($clog2(3*`NF+7)+7) EMRegFma4(clk, reset, FlushM, ~StallM, - {AddendStickyE, KillProdE, InvZE, NormCntE, NegSumE, ZSgnEffE, PSgnE, FOpCtrlE[2]&~FOpCtrlE[1]&~FOpCtrlE[0]}, - {AddendStickyM, KillProdM, InvZM, NormCntM, NegSumM, ZSgnEffM, PSgnM, Mult}); - - fma2 fma2(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, - .FrmM, .FmtM, .ProdExpM, .AddendStickyM, .KillProdM, .SumM, .NegSumM, .InvZM, .NormCntM, .ZSgnEffM, .PSgnM, - .XZeroM, .YZeroM, .ZZeroM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .XSNaNM, .YSNaNM, .ZSNaNM, .Mult, - .FMAResM, .FMAFlgM); - -endmodule - - - //*** in al units before putting into : ? put in a seperate signal - -module fma1( - input logic XSgnE, YSgnE, ZSgnE, // input's signs - input logic [`NE-1:0] XExpE, YExpE, ZExpE, // biased exponents in B(NE.0) format - input logic [`NF:0] XManE, YManE, ZManE, // fractions in U(0.NF) format - input logic XDenormE, YDenormE, ZDenormE, // is the input denormal - input logic XZeroE, YZeroE, ZZeroE, // is the input zero - input logic [2:0] FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) - input logic [`FPSIZES/3:0] FmtE, // precision 1 = double 0 = single - output logic [`NE+1:0] ProdExpE, // X exponent + Y exponent - bias in B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign - output logic AddendStickyE, // sticky bit that is calculated during alignment - output logic KillProdE, // set the product to zero before addition if the product is too small to matter - output logic [3*`NF+5:0] SumE, // the positive sum - output logic NegSumE, // was the sum negitive - output logic InvZE, // intert Z - output logic ZSgnEffE, // the modified Z sign - output logic PSgnE, // the product's sign - output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift cnt + input logic Xs, Ys, Zs, // input's signs + input logic [`NE-1:0] Xe, Ye, Ze, // input's biased exponents in B(NE.0) format + input logic [`NF:0] Xm, Ym, Zm, // input's significands in U(0.NF) format + input logic XZero, YZero, ZZero, // is the input zero + input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) + input logic [`FMTBITS-1:0] Fmt, // format of the result single double half or quad + output logic [`NE+1:0] Pe, // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign + output logic ZmSticky, // sticky bit that is calculated during alignment + output logic KillProd, // set the product to zero before addition if the product is too small to matter + output logic [3*`NF+5:0] Sm, // the positive sum's significand + output logic NegSum, // was the sum negitive + output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) + output logic As, // the aligned addend's sign (modified Z sign for other opperations) + output logic Ps, // the product's sign + output logic Ss, // the sum's sign + output logic [`NE+1:0] Se, + output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count ); - logic [`NE-1:0] Denorm; // value of a denormaized number based on precision - logic [2*`NF+1:0] ProdManE; // 1.X frac * 1.Y frac in U(2.2Nf) format - logic [3*`NF+5:0] AlignedAddendE; // Z aligned for addition in U(NF+5.2NF+1) - logic [3*`NF+6:0] AlignedAddendInv; // aligned addend possibly inverted - logic [2*`NF+1:0] ProdManKilled; // the product's mantissa possibly killed - logic [3*`NF+6:0] PreSum, NegPreSum; // positive and negitve versions of the sum - logic [`NE-1:0] XExpVal, YExpVal; // exponent value after taking into accound denormals + logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format + logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1) + logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted + logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed /////////////////////////////////////////////////////////////////////////////// // Calculate the product // - When multipliying two fp numbers, add the exponents @@ -131,1190 +63,29 @@ module fma1( // calculate the product's exponent - expadd expadd(.FmtE, .XExpE, .YExpE, .XZeroE, .YZeroE, .XDenormE, .YDenormE, .XExpVal, .YExpVal, - .Denorm, .ProdExpE); + fmaexpadd expadd(.Fmt, .Xe, .Ye, .XZero, .YZero, .Pe); // multiplication of the mantissa's - mult mult(.XManE, .YManE, .ProdManE); + fmamult mult(.Xm, .Ym, .Pm); /////////////////////////////////////////////////////////////////////////////// // Alignment shifter /////////////////////////////////////////////////////////////////////////////// - - align align(.ZExpE, .ZManE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .ProdExpE, .Denorm, .XExpVal, .YExpVal, - .AlignedAddendE, .AddendStickyE, .KillProdE); - // calculate the signs and take the opperation into account - sign sign(.FOpCtrlE, .XSgnE, .YSgnE, .ZSgnE, .PSgnE, .ZSgnEffE); + fmasign sign(.OpCtrl, .Xs, .Ys, .Zs, .Ps, .As, .InvA); + + fmaalign align(.Ze, .Zm, .XZero, .YZero, .ZZero, .Xe, .Ye, + .Am, .ZmSticky, .KillProd); + + // /////////////////////////////////////////////////////////////////////////////// // // Addition/LZA // /////////////////////////////////////////////////////////////////////////////// - add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE); - - loa loa(.A(AlignedAddendInv+{(3*`NF+6)'(0),InvZE}), .P(ProdManKilled), .NormCntE); - - // Choose the positive sum and accompanying LZA result. - assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0]; - + fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); + fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule -module expadd( - input logic [`FPSIZES/3:0] FmtE, // precision - input logic [`NE-1:0] XExpE, YExpE, // input exponents - input logic XDenormE, YDenormE, // are the inputs denormalized - input logic XZeroE, YZeroE, // are the inputs zero - output logic [`NE-1:0] XExpVal, YExpVal, // Exponent value after taking into account denormals - output logic [`NE-1:0] Denorm, // value of denormalized exponent - output logic [`NE+1:0] ProdExpE // product's exponent B^(1023)NE+2 -); - - - // denormalized numbers have diffrent values depending on which precison it is. - // FLEN - 1 - // Other - BIAS - other bias + 1 - - if (`FPSIZES == 1) begin - assign Denorm = 1; - - end else if (`FPSIZES == 2) begin - assign Denorm = FmtE ? (`NE)'(1) : (`NE)'(`BIAS)-(`NE)'(`BIAS1)+(`NE)'(1); - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtE) - `FMT: Denorm = 1; - `FMT1: Denorm = `BIAS-`BIAS1+1; - `FMT2: Denorm = `BIAS-`BIAS2+1; - default: Denorm = 1'bx; - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtE) - 2'h3: Denorm = 1; - 2'h1: Denorm = `BIAS-`D_BIAS+1; - 2'h0: Denorm = `BIAS-`S_BIAS+1; - 2'h2: Denorm = `BIAS-`H_BIAS+1; - endcase - end - - end - - // pick denormalized value or exponent - assign XExpVal = XDenormE ? Denorm : XExpE; - assign YExpVal = YDenormE ? Denorm : YExpE; - // kill the exponent if the product is zero - either X or Y is 0 - assign ProdExpE = ({2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, (`NE)'(`BIAS)})&{`NE+2{~(XZeroE|YZeroE)}}; - -endmodule - - - - - -module mult( - input logic [`NF:0] XManE, YManE, - output logic [2*`NF+1:0] ProdManE -); - assign ProdManE = XManE * YManE; -endmodule - - - - - - - - -module sign( - input logic [2:0] FOpCtrlE, // precision - input logic XSgnE, YSgnE, ZSgnE, // are the inputs denormalized - output logic PSgnE, // the product's sign - takes opperation into account - output logic ZSgnEffE // Z sign used in fma - takes opperation into account -); - - // Calculate the product's sign - // Negate product's sign if FNMADD or FNMSUB - - // flip is negation opperation - assign PSgnE = XSgnE ^ YSgnE ^ (FOpCtrlE[1]&~FOpCtrlE[2]); - // flip if subtraction - assign ZSgnEffE = ZSgnE^FOpCtrlE[0]; - -endmodule - - - - - - - - -module align( - input logic [`NE-1:0] ZExpE, // biased exponents in B(NE.0) format - input logic [`NF:0] ZManE, // fractions in U(0.NF) format] - input logic ZDenormE, // is the input denormal - input logic XZeroE, YZeroE, ZZeroE, // is the input zero - input logic [`NE-1:0] XExpVal, YExpVal, // Exponent value after taking into account denormals - input logic [`NE+1:0] ProdExpE, // the product's exponent - input logic [`NE-1:0] Denorm, // the biased value of a denormalized number - output logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1) - output logic AddendStickyE, // Sticky bit calculated from the aliged addend - output logic KillProdE // should the product be set to zero -); - - logic [`NE+1:0] AlignCnt; // how far to shift the addend to align with the product in Q(NE+2.0) format - logic [4*`NF+5:0] ZManShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1) - logic [4*`NF+5:0] ZManPreShifted; // input to the alignment shifter U(NF+5.3NF+1) - logic [`NE-1:0] ZExpVal; // Exponent value after taking into account denormals - - /////////////////////////////////////////////////////////////////////////////// - // Alignment shifter - /////////////////////////////////////////////////////////////////////////////// - - // determine the shift count for alignment - // - negitive means Z is larger, so shift Z left - // - positive means the product is larger, so shift Z right - // - Denormal numbers have a diffrent exponent value depending on the precision - assign ZExpVal = ZDenormE ? Denorm : ZExpE; - // assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3); - assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, (`NE)'(`BIAS)} + `NF+3 - {2'b0, ZExpVal}; - - // Defualt Addition without shifting - // | 54'b0 | 106'b(product) | 2'b0 | - // | addnend | - - // the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...) - assign ZManPreShifted = {ZManE,(3*`NF+5)'(0)}; - always_comb - begin - - // If the product is too small to effect the sum, kill the product - - // | 54'b0 | 106'b(product) | 2'b0 | - // | addnend | - if ($signed(AlignCnt) < $signed((`NE+2)'(0))) begin - KillProdE = 1; - ZManShifted = ZManPreShifted; - AddendStickyE = ~(XZeroE|YZeroE); - - // If the Addend is shifted right - // | 54'b0 | 106'b(product) | 2'b0 | - // | addnend | - end else if ($signed(AlignCnt)<=$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5))) begin - KillProdE = 0; - ZManShifted = ZManPreShifted >> AlignCnt; - AddendStickyE = |(ZManShifted[`NF-1:0]); - - // If the addend is too small to effect the addition - // - The addend has to shift two past the end of the addend to be considered too small - // - The 2 extra bits are needed for rounding - - // | 54'b0 | 106'b(product) | 2'b0 | - // | addnend | - end else begin - KillProdE = 0; - ZManShifted = 0; - AddendStickyE = ~ZZeroE; - - end - end - - assign AlignedAddendE = ZManShifted[4*`NF+5:`NF]; - -endmodule - - - - - - - -module add( - input logic [3*`NF+5:0] AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1) - input logic [2*`NF+1:0] ProdManE, // the product's mantissa - input logic PSgnE, ZSgnEffE,// the product and modified Z signs - input logic KillProdE, // should the product be set to 0 - input logic XZeroE, YZeroE, // is the input zero - output logic [3*`NF+6:0] AlignedAddendInv, // aligned addend possibly inverted - output logic [2*`NF+1:0] ProdManKilled, // the product's mantissa possibly killed - output logic NegSumE, // was the sum negitive - output logic InvZE, // do you invert Z - output logic [3*`NF+6:0] PreSum, NegPreSum// possibly negitive sum -); - - /////////////////////////////////////////////////////////////////////////////// - // Addition - /////////////////////////////////////////////////////////////////////////////// - - // Negate Z when doing one of the following opperations: - // -prod + Z - // prod - Z - assign InvZE = ZSgnEffE ^ PSgnE; - - // Choose an inverted or non-inverted addend - the one has to be added now for the LZA - assign AlignedAddendInv = InvZE ? {1'b1, ~AlignedAddendE} : {1'b0, AlignedAddendE}; - // Kill the product if the product is too small to effect the addition (determined in fma1.sv) - assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}}; - - - - // Do the addition - // - calculate a positive and negitive sum in parallel - assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE}; - assign NegPreSum = XZeroE|YZeroE|KillProdE ? {1'b0, AlignedAddendE} : {1'b0, AlignedAddendE} + {{`NF+3{1'b1}}, ~ProdManKilled, 2'b0} + {(3*`NF+7)'(4)}; - - // Is the sum negitive - assign NegSumE = PreSum[3*`NF+6]; - -endmodule - - -module loa( //https://ieeexplore.ieee.org/abstract/document/930098 - input logic [3*`NF+6:0] A, // addend - input logic [2*`NF+1:0] P, // product - output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift count for the positive result - ); - - logic [3*`NF+6:0] T; - logic [3*`NF+6:0] G; - logic [3*`NF+6:0] Z; - logic [3*`NF+6:0] f; - - assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4]; - assign G[3*`NF+6:2*`NF+4] = 0; - assign Z[3*`NF+6:2*`NF+4] = ~A[3*`NF+6:2*`NF+4]; - assign T[2*`NF+3:2] = A[2*`NF+3:2]^P; - assign G[2*`NF+3:2] = A[2*`NF+3:2]&P; - assign Z[2*`NF+3:2] = ~A[2*`NF+3:2]&~P; - assign T[1:0] = A[1:0]; - assign G[1:0] = 0; - assign Z[1:0] = ~A[1:0]; - - - // Apply function to determine Leading pattern - // - note: the paper linked above uses the numbering system where 0 is the most significant bit - //f[n] = ~T[n]&T[n-1] note: n is the MSB - //f[i] = (T[i+1]&(G[i]&~Z[i-1] | Z[i]&~G[i-1])) | (~T[i+1]&(Z[i]&~Z[i-1] | G[i]&~G[i-1])) - assign f[3*`NF+6] = ~T[3*`NF+6]&T[3*`NF+5]; - assign f[3*`NF+5:0] = (T[3*`NF+6:1]&(G[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | Z[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1})) | (~T[3*`NF+6:1]&(Z[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | G[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1})); - - - - lzc lzc(.f, .NormCntE); - -endmodule - -module lzc( - input logic [3*`NF+6:0] f, - output logic [$clog2(3*`NF+7)-1:0] NormCntE // normalization shift -); - - logic [$clog2(3*`NF+7)-1:0] i; - always_comb begin - i = 0; - while (~f[3*`NF+6-i] & $unsigned(i) <= $unsigned($clog2(3*`NF+7)'(3)*($clog2(3*`NF+7))'(`NF)+($clog2(3*`NF+7))'(6))) i = i+1; // search for leading one - NormCntE = i; - end -endmodule - - - - - - - - -module fma2( - - input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - input logic [`NF:0] XManM, YManM, ZManM, // input mantissas - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single - input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias - input logic AddendStickyM, // sticky bit that is calculated during alignment - input logic KillProdM, // set the product to zero before addition if the product is too small to matter - input logic XZeroM, YZeroM, ZZeroM, // inputs are zero - input logic XInfM, YInfM, ZInfM, // inputs are infinity - input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN - input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs - input logic [3*`NF+5:0] SumM, // the positive sum - input logic NegSumM, // was the sum negitive - input logic InvZM, // do you invert Z - input logic ZSgnEffM, // the modified Z sign - depends on instruction - input logic PSgnM, // the product's sign - input logic Mult, // multiply opperation - input logic [$clog2(3*`NF+7)-1:0] NormCntM, // the normalization shift count - output logic [`FLEN-1:0] FMAResM, // FMA final result - output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact} - - - - logic [`NF-1:0] ResultFrac; // Result fraction - logic [`NE-1:0] ResultExp; // Result exponent - logic ResultSgn, ResultSgnTmp; // Result sign - logic [`NE+1:0] SumExp; // exponent of the normalized sum - logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow - logic [`NF+2:0] NormSum; // normalized sum - logic NormSumSticky; // sticky bit calulated from the normalized sum - logic SumZero; // is the sum zero - logic ResultDenorm; // is the result denormalized - logic Sticky, UfSticky; // Sticky bit - logic CalcPlus1; // do you add or subtract one for rounding - logic UfPlus1; // do you add one (for determining underflow flag) - logic Invalid,Underflow,Overflow; // flags - logic Guard, Round; // bits needed to determine rounding - logic UfLSBNormSum; // bits needed to determine rounding for underflow flag - logic [`FLEN:0] RoundAdd; // how much to add to the result - - - - - - /////////////////////////////////////////////////////////////////////////////// - // Normalization - /////////////////////////////////////////////////////////////////////////////// - - normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM, - .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm); - - - - - /////////////////////////////////////////////////////////////////////////////// - // Rounding - /////////////////////////////////////////////////////////////////////////////// - - // round to nearest even - // round to zero - // round to -infinity - // round to infinity - // round to nearest max magnitude - - fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgnTmp, .SumExp, - .CalcPlus1, .UfPlus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .RoundAdd, .UfLSBNormSum); - - - - - - /////////////////////////////////////////////////////////////////////////////// - // Sign calculation - /////////////////////////////////////////////////////////////////////////////// - - - resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .Mult, .ResultSgnTmp, .ResultSgn); - - - - - /////////////////////////////////////////////////////////////////////////////// - // Flags - /////////////////////////////////////////////////////////////////////////////// - - fmaflags fmaflags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .XZeroM, .YZeroM, - .XNaNM, .YNaNM, .ZNaNM, .FullResultExp, .SumExp, .ZSgnEffM, .PSgnM, .Round, .Guard, .UfLSBNormSum, .Sticky, .UfPlus1, - .FmtM, .Invalid, .Overflow, .Underflow, .FMAFlgM); - - - - - /////////////////////////////////////////////////////////////////////////////// - // Select the result - /////////////////////////////////////////////////////////////////////////////// - - resultselect resultselect(.XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, - .FrmM, .FmtM, .AddendStickyM, .KillProdM, .XInfM, .YInfM, .ZInfM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, - .ZSgnEffM, .PSgnM, .ResultSgn, .CalcPlus1, .Invalid, .Overflow, .Underflow, - .ResultDenorm, .ResultExp, .ResultFrac, .FMAResM); - -// *** use NF where needed - -endmodule - -module resultsign( - input logic [2:0] FrmM, - input logic PSgnM, ZSgnEffM, - input logic Underflow, - input logic InvZM, - input logic NegSumM, - input logic SumZero, - input logic Mult, - output logic ResultSgnTmp, - output logic ResultSgn -); - - logic ZeroSgn; - // logic ResultSgnTmp; - - // Determine the sign if the sum is zero - // if cancelation then 0 unless round to -infinity - // if multiply then Psgn - // otherwise psign - assign ZeroSgn = (PSgnM^ZSgnEffM)&~Underflow&~Mult ? FrmM[1:0] == 2'b10 : PSgnM; - - // is the result negitive - // if p - z is the Sum negitive - // if -p + z is the Sum positive - // if -p - z then the Sum is negitive - assign ResultSgnTmp = InvZM&(ZSgnEffM)&NegSumM | InvZM&PSgnM&~NegSumM | ((ZSgnEffM)&PSgnM); - assign ResultSgn = SumZero ? ZeroSgn : ResultSgnTmp; - -endmodule - - -module normalize( - input logic [3*`NF+5:0] SumM, // the positive sum - input logic [`NE-1:0] ZExpM, // exponent of Z - input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias - input logic [$clog2(3*`NF+7)-1:0] NormCntM, // normalization shift count - input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single - input logic KillProdM, // is the product set to zero - input logic AddendStickyM, // the sticky bit caclulated from the aligned addend - input logic NegSumM, // was the sum negitive - output logic [`NF+2:0] NormSum, // normalized sum - output logic SumZero, // is the sum zero - output logic NormSumSticky, UfSticky, // sticky bits - output logic [`NE+1:0] SumExp, // exponent of the normalized sum - output logic ResultDenorm // is the result denormalized -); - logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results - logic [$clog2(3*`NF+7)-1:0] DenormShift; // right shift if the result is denormalized //***change this later - logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction - logic [3*`NF+8:0] SumShifted; // the shifted sum before LZA correction - logic [`NE+1:0] SumExpTmpTmp; // the exponent of the normalized sum with the `FLEN bias - logic PreResultDenorm; // is the result denormalized - calculated before LZA corection - logic LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction - - /////////////////////////////////////////////////////////////////////////////// - // Normalization - /////////////////////////////////////////////////////////////////////////////// - - // Determine if the sum is zero - assign SumZero = ~(|SumM); - - // calculate the sum's exponent - assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); - - //convert the sum's exponent into the propper percision - if (`FPSIZES == 1) begin - assign SumExpTmp = SumExpTmpTmp; - - end else if (`FPSIZES == 2) begin - assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-(`NE+2)'(`BIAS)+(`NE+2)'(`BIAS1))&{`NE+2{|SumExpTmpTmp}}; - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtM) - `FMT: SumExpTmp = SumExpTmpTmp; - `FMT1: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS1)&{`NE+2{|SumExpTmpTmp}}; - `FMT2: SumExpTmp = (SumExpTmpTmp-`BIAS+`BIAS2)&{`NE+2{|SumExpTmpTmp}}; - default: SumExpTmp = `NE+2'bx; - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtM) - 2'h3: SumExpTmp = SumExpTmpTmp; - 2'h1: SumExpTmp = (SumExpTmpTmp-`BIAS+`D_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h0: SumExpTmp = (SumExpTmpTmp-`BIAS+`S_BIAS)&{`NE+2{|SumExpTmpTmp}}; - 2'h2: SumExpTmp = (SumExpTmpTmp-`BIAS+`H_BIAS)&{`NE+2{|SumExpTmpTmp}}; - endcase - end - - end - - // determine if the result is denormalized - - if (`FPSIZES == 1) begin - logic Sum0LEZ, Sum0GEFL; - assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; - assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); - assign PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; - - end else if (`FPSIZES == 2) begin - logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; - assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; - assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); - assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)); - assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF1+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)) | ~|SumExpTmpTmp; - assign PreResultDenorm = (FmtM ? Sum0LEZ : Sum1LEZ) & (FmtM ? Sum0GEFL : Sum1GEFL) & ~SumZero; - - end else if (`FPSIZES == 3) begin - logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; - assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; - assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF)-(`NE+2)'(2)); - assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)); - assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF1+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS1)) | ~|SumExpTmpTmp; - assign Sum2LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`BIAS2)); - assign Sum2GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF2+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`BIAS2)) | ~|SumExpTmpTmp; - always_comb begin - case (FmtM) - `FMT: PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; - `FMT1: PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; - `FMT2: PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; - default: PreResultDenorm = 1'bx; - endcase - end - - end else if (`FPSIZES == 4) begin - logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL; - assign Sum0LEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp; - assign Sum0GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`NF )-(`NE+2)'(2)); - assign Sum1LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`D_BIAS)); - assign Sum1GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`D_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`D_BIAS)) | ~|SumExpTmpTmp; - assign Sum2LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`S_BIAS)); - assign Sum2GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`S_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`S_BIAS)) | ~|SumExpTmpTmp; - assign Sum3LEZ = $signed(SumExpTmpTmp) <= $signed( (`NE+2)'(`BIAS)-(`NE+2)'(`H_BIAS)); - assign Sum3GEFL = $signed(SumExpTmpTmp) >= $signed(-(`NE+2)'(`H_NF+2)+(`NE+2)'(`BIAS)-(`NE+2)'(`H_BIAS)) | ~|SumExpTmpTmp; - always_comb begin - case (FmtM) - 2'h3: PreResultDenorm = Sum0LEZ & Sum0GEFL & ~SumZero; - 2'h1: PreResultDenorm = Sum1LEZ & Sum1GEFL & ~SumZero; - 2'h0: PreResultDenorm = Sum2LEZ & Sum2GEFL & ~SumZero; - 2'h2: PreResultDenorm = Sum3LEZ & Sum3GEFL & ~SumZero; - endcase - end - - end - - // 010. when should be 001. - // - shift left one - // - add one from exp - // - if kill prod dont add to exp - - // Determine if the result is denormal - // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero; - - // Determine the shift needed for denormal results - // - if not denorm add 1 to shift out the leading 1 - assign DenormShift = PreResultDenorm ? SumExpTmp[$clog2(3*`NF+7)-1:0] : 1; - // Normalize the sum - assign SumShifted = {3'b0, SumM} << NormCntM+DenormShift; - // LZA correction - assign LZAPlus1 = SumShifted[3*`NF+7]; - assign LZAPlus2 = SumShifted[3*`NF+8]; - // the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone - assign CorrSumShifted = LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0]; - assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3]; - - // Calculate the sticky bit - if (`FPSIZES == 1) begin - assign NormSumSticky = |CorrSumShifted[2*`NF+2:0]; - - end else if (`FPSIZES == 2) begin - // 3*NF+5 - NF1 - 3 - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&~FmtM); - - end else if (`FPSIZES == 3) begin - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`NF1:2*`NF+3]&((FmtM==`FMT1)|(FmtM==`FMT2))) | - (|CorrSumShifted[3*`NF+2-`NF2:3*`NF+3-`NF1]&(FmtM==`FMT2)); - - end else if (`FPSIZES == 4) begin - assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | - (|CorrSumShifted[3*`NF+2-`D_NF:2*`NF+3]&((FmtM==1)|(FmtM==0)|(FmtM==2))) | - (|CorrSumShifted[3*`NF+2-`S_NF:3*`NF+3-`D_NF]&((FmtM==0)|(FmtM==2))) | - (|CorrSumShifted[3*`NF+2-`H_NF:3*`NF+3-`S_NF]&(FmtM==2)); - - end - - assign UfSticky = AddendStickyM | NormSumSticky; - - // Determine sum's exponent - // if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2 - assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~ResultDenorm&PreResultDenorm&~KillProdM}+{12'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}) & {`NE+2{~(SumZero|ResultDenorm)}}; - // recalculate if the result is denormalized - assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; - -endmodule - -module fmaround( - input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single - input logic [2:0] FrmM, // rounding mode - input logic UfSticky, // sticky bit for underlow calculation - input logic [`NF+2:0] NormSum, // normalized sum - input logic AddendStickyM, // addend's sticky bit - input logic NormSumSticky, // normalized sum's sticky bit - input logic ZZeroM, // is Z zero - input logic InvZM, // invert Z - input logic [`NE+1:0] SumExp, // exponent of the normalized sum - input logic ResultSgnTmp, // the result's sign - output logic CalcPlus1, UfPlus1, // do you add or subtract on from the result - output logic [`NE+1:0] FullResultExp, // ResultExp with bits to determine sign and overflow - output logic [`NF-1:0] ResultFrac, // Result fraction - output logic [`NE-1:0] ResultExp, // Result exponent - output logic Sticky, // sticky bit - output logic [`FLEN:0] RoundAdd, // how much to add to the result - output logic Round, Guard, UfLSBNormSum // bits needed to calculate rounding -); - logic LSBNormSum; // bit used for rounding - least significant bit of the normalized sum - logic SubBySmallNum, UfSubBySmallNum; // was there supposed to be a subtraction by a small number - logic UfGuard; // guard bit used to caluculate underflow - logic UfCalcPlus1, CalcMinus1, Plus1, Minus1; // do you add or subtract on from the result - logic [`NF-1:0] NormSumTruncated; // the normalized sum trimed to fit the mantissa - logic UfRound; - - /////////////////////////////////////////////////////////////////////////////// - // Rounding - /////////////////////////////////////////////////////////////////////////////// - - // round to nearest even - // {Guard, Round, Sticky} - // 0xx - do nothing - // 100 - tie - Plus1 if result is odd (LSBNormSum = 1) - // - don't add 1 if a small number was supposed to be subtracted - // 101 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number) - // 110/111 - Plus1 - - // round to zero - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0 - - // round to -infinity - // - Plus1 if negative unless a small number was supposed to be subtracted from a result with guard and round bits of 0 - // - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0 - - // round to infinity - // - Plus1 if positive unless a small number was supposed to be subtracted from a result with guard and round bits of 0 - // - subtract 1 if a small number was supposed to be subtracted from a negative result with guard and round bits of 0 - - // round to nearest max magnitude - // {Guard, Round, Sticky} - // 0xx - do nothing - // 100 - tie - Plus1 - // - don't add 1 if a small number was supposed to be subtracted - // 101 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number) - // 110/111 - Plus1 - - if (`FPSIZES == 1) begin - // determine guard, round, and least significant bit of the result - assign Guard = NormSum[2]; - assign Round = NormSum[1]; - assign LSBNormSum = NormSum[3]; - - // used to determine underflow flag - assign UfGuard = NormSum[1]; - assign UfRound = NormSum[0]; - assign UfLSBNormSum = NormSum[2]; - - // determine sticky - assign Sticky = UfSticky | NormSum[0]; - - end else if (`FPSIZES == 2) begin - // \/-------------NF---------------, - // | NF1 | 3 | | - // '-------NF1------^ - - // determine guard, round, and least significant bit of the result - assign Guard = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; - assign Round = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; - assign LSBNormSum = FmtM ? NormSum[3] : NormSum[`NF-`NF1+3]; - - // used to determine underflow flag - assign UfGuard = FmtM ? NormSum[1] : NormSum[`NF-`NF1+1]; - assign UfRound = FmtM ? NormSum[0] : NormSum[`NF-`NF1]; - assign UfLSBNormSum = FmtM ? NormSum[2] : NormSum[`NF-`NF1+2]; - - // determine sticky - assign Sticky = UfSticky | (FmtM ? NormSum[0] : NormSum[`NF-`NF1]); - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtM) - `FMT: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[2]; - Round = NormSum[1]; - LSBNormSum = NormSum[3]; - // used to determine underflow flag - UfGuard = NormSum[1]; - UfRound = NormSum[0]; - UfLSBNormSum = NormSum[2]; - // determine sticky - Sticky = UfSticky | NormSum[0]; - end - `FMT1: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`NF1+2]; - Round = NormSum[`NF-`NF1+1]; - LSBNormSum = NormSum[`NF-`NF1+3]; - // used to determine underflow flag - UfGuard = NormSum[`NF-`NF1+1]; - UfRound = NormSum[`NF-`NF1]; - UfLSBNormSum = NormSum[`NF-`NF1+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`NF1]; - end - `FMT2: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`NF2+2]; - Round = NormSum[`NF-`NF2+1]; - LSBNormSum = NormSum[`NF-`NF2+3]; - // used to determine underflow flag - UfGuard = NormSum[`NF-`NF2+1]; - UfRound = NormSum[`NF-`NF2]; - UfLSBNormSum = NormSum[`NF-`NF2+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`NF2]; - end - default: begin - Guard = 1'bx; - Round = 1'bx; - LSBNormSum = 1'bx; - UfGuard = 1'bx; - UfRound = 1'bx; - UfLSBNormSum = 1'bx; - Sticky = 1'bx; - end - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtM) - 2'h3: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[2]; - Round = NormSum[1]; - LSBNormSum = NormSum[3]; - // used to determine underflow flag - UfGuard = NormSum[1]; - UfRound = NormSum[0]; - UfLSBNormSum = NormSum[2]; - // determine sticky - Sticky = UfSticky | NormSum[0]; - end - 2'h1: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`D_NF+2]; - Round = NormSum[`NF-`D_NF+1]; - LSBNormSum = NormSum[`NF-`D_NF+3]; - // used to determine underflow flag - UfGuard = NormSum[`NF-`D_NF+1]; - UfRound = NormSum[`NF-`D_NF]; - UfLSBNormSum = NormSum[`NF-`D_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`D_NF]; - end - 2'h0: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`S_NF+2]; - Round = NormSum[`NF-`S_NF+1]; - LSBNormSum = NormSum[`NF-`S_NF+3]; - // used to determine underflow flag - UfGuard = NormSum[`NF-`S_NF+1]; - UfRound = NormSum[`NF-`S_NF]; - UfLSBNormSum = NormSum[`NF-`S_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`S_NF]; - end - 2'h2: begin - // determine guard, round, and least significant bit of the result - Guard = NormSum[`NF-`H_NF+2]; - Round = NormSum[`NF-`H_NF+1]; - LSBNormSum = NormSum[`NF-`H_NF+3]; - // used to determine underflow flag - UfGuard = NormSum[`NF-`H_NF+1]; - UfRound = NormSum[`NF-`H_NF]; - UfLSBNormSum = NormSum[`NF-`H_NF+2]; - // determine sticky - Sticky = UfSticky | NormSum[`NF-`H_NF]; - end - endcase - end - - end - - - // Deterimine if a small number was supposed to be subtrated - assign SubBySmallNum = AddendStickyM & InvZM & ~(NormSumSticky|UfRound) & ~ZZeroM; //***here - assign UfSubBySmallNum = AddendStickyM & InvZM & ~(NormSumSticky) & ~ZZeroM; //***here - - always_comb begin - // Determine if you add 1 - case (FrmM) - 3'b000: CalcPlus1 = Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&LSBNormSum&~SubBySmallNum));//round to nearest even - 3'b001: CalcPlus1 = 0;//round to zero - 3'b010: CalcPlus1 = ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round down - 3'b011: CalcPlus1 = ~ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round up - 3'b100: CalcPlus1 = (Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&~SubBySmallNum)));//round to nearest max magnitude - default: CalcPlus1 = 1'bx; - endcase - // Determine if you add 1 (for underflow flag) - case (FrmM) - 3'b000: UfCalcPlus1 = UfGuard & (UfRound | (UfSticky&UfRound|~UfSubBySmallNum) | (~Sticky&UfLSBNormSum&~UfSubBySmallNum));//round to nearest even - 3'b001: UfCalcPlus1 = 0;//round to zero - 3'b010: UfCalcPlus1 = ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round down - 3'b011: UfCalcPlus1 = ~ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round up - 3'b100: UfCalcPlus1 = (UfGuard & (UfRound | (UfSticky&~(~UfRound&UfSubBySmallNum)) | (~Sticky&~UfSubBySmallNum)));//round to nearest max magnitude - default: UfCalcPlus1 = 1'bx; - endcase - // Determine if you subtract 1 - case (FrmM) - 3'b000: CalcMinus1 = 0;//round to nearest even - 3'b001: CalcMinus1 = SubBySmallNum & ~Guard & ~Round;//round to zero - 3'b010: CalcMinus1 = ~ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round down - 3'b011: CalcMinus1 = ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round up - 3'b100: CalcMinus1 = 0;//round to nearest max magnitude - default: CalcMinus1 = 1'bx; - endcase - - end - - // If an answer is exact don't round - assign Plus1 = CalcPlus1 & (Sticky | Guard | Round); - assign UfPlus1 = UfCalcPlus1 & (Sticky | UfGuard);//UfRound is part of sticky - assign Minus1 = CalcMinus1 & (Sticky | Guard | Round); - - // Compute rounded result - if (`FPSIZES == 1) begin - assign RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{`FLEN{1'b0}}, Plus1}; - - end else if (`FPSIZES == 2) begin - // \/FLEN+1 - // | NE+2 | NF | - // '-NE+2-^----NF1----^ - // `FLEN+1-`NE-2-`NF1 = FLEN-1-NE-NF1 - assign RoundAdd = FmtM ? Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1} : - Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtM) - `FMT: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; - `FMT1: RoundAdd = Minus1 ? {{`NE+2+`NF1{1'b1}}, (`FLEN-1-`NE-`NF1)'(0)} : {(`NE+1+`NF1)'(0), Plus1, (`FLEN-1-`NE-`NF1)'(0)}; - `FMT2: RoundAdd = Minus1 ? {{`NE+2+`NF2{1'b1}}, (`FLEN-1-`NE-`NF2)'(0)} : {(`NE+1+`NF2)'(0), Plus1, (`FLEN-1-`NE-`NF2)'(0)}; - default: RoundAdd = (`FLEN+1)'(0); - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtM) - 2'h3: RoundAdd = Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1}; - 2'h1: RoundAdd = Minus1 ? {{`NE+2+`D_NF{1'b1}}, (`FLEN-1-`NE-`D_NF)'(0)} : {(`NE+1+`D_NF)'(0), Plus1, (`FLEN-1-`NE-`D_NF)'(0)}; - 2'h0: RoundAdd = Minus1 ? {{`NE+2+`S_NF{1'b1}}, (`FLEN-1-`NE-`S_NF)'(0)} : {(`NE+1+`S_NF)'(0), Plus1, (`FLEN-1-`NE-`S_NF)'(0)}; - 2'h2: RoundAdd = Minus1 ? {{`NE+2+`H_NF{1'b1}}, (`FLEN-1-`NE-`H_NF)'(0)} : {(`NE+1+`H_NF)'(0), Plus1, (`FLEN-1-`NE-`H_NF)'(0)}; - endcase - end - - end - - assign NormSumTruncated = NormSum[`NF+2:3]; - assign {FullResultExp, ResultFrac} = {SumExp, NormSumTruncated} + RoundAdd; - assign ResultExp = FullResultExp[`NE-1:0]; - - -endmodule - -module fmaflags( - input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs - input logic XInfM, YInfM, ZInfM, // inputs are infinity - input logic XZeroM, YZeroM, // inputs are zero - input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN - input logic [`NE+1:0] FullResultExp, // ResultExp with bits to determine sign and overflow - input logic [`NE+1:0] SumExp, // exponent of the normalized sum - input logic ZSgnEffM, PSgnM, // the product and modified Z signs - input logic Round, Guard, UfLSBNormSum, Sticky, UfPlus1, // bits used to determine rounding - input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single - output logic Invalid, Overflow, Underflow, // flags used to select the result - output logic [4:0] FMAFlgM // FMA flags -); - logic SigNaN; // is an input a signaling NaN - logic GtMaxExp; // is exponent greater than the maximum - logic UnderflowFlag, Inexact; // flags - - /////////////////////////////////////////////////////////////////////////////// - // Flags - /////////////////////////////////////////////////////////////////////////////// - - - - // Set Invalid flag for following cases: - // 1) any input is a signaling NaN - // 2) Inf - Inf (unless x or y is NaN) - // 3) 0 * Inf - - assign SigNaN = XSNaNM | YSNaNM | ZSNaNM; - assign Invalid = SigNaN | ((XInfM | YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM); - - // Set Overflow flag if the number is too big to be represented - // - Don't set the overflow flag if an overflowed result isn't outputed - if (`FPSIZES == 1) begin - assign GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; - - end else if (`FPSIZES == 2) begin - assign GtMaxExp = FmtM ? &FullResultExp[`NE-1:0] | FullResultExp[`NE] : &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtM) - `FMT: GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; - `FMT1: GtMaxExp = &FullResultExp[`NE1-1:0] | FullResultExp[`NE1]; - `FMT2: GtMaxExp = &FullResultExp[`NE2-1:0] | FullResultExp[`NE2]; - default: GtMaxExp = 1'bx; - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtM) - 2'h3: GtMaxExp = &FullResultExp[`NE-1:0] | FullResultExp[`NE]; - 2'h1: GtMaxExp = &FullResultExp[`D_NE-1:0] | FullResultExp[`D_NE]; - 2'h0: GtMaxExp = &FullResultExp[`S_NE-1:0] | FullResultExp[`S_NE]; - 2'h2: GtMaxExp = &FullResultExp[`H_NE-1:0] | FullResultExp[`H_NE]; - endcase - end - - end - assign Overflow = GtMaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); - - // Set Underflow flag if the number is too small to be represented in normal numbers - // - Don't set the underflow flag if the result is exact - - assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); - assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); - // Set Inexact flag if the result is diffrent from what would be outputed given infinite precision - // - Don't set the underflow flag if an underflowed result isn't outputed - assign Inexact = (Sticky|Overflow|Guard|Round|Underflow)&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM); - - // Combine flags - // - FMA can't set the Divide by zero flag - // - Don't set the underflow flag if the result was rounded up to a normal number - assign FMAFlgM = {Invalid, 1'b0, Overflow, UnderflowFlag, Inexact}; - -endmodule - - -module resultselect( - input logic XSgnM, YSgnM, // input signs - input logic [`NE-1:0] XExpM, YExpM, ZExpM, // input exponents - input logic [`NF:0] XManM, YManM, ZManM, // input mantissas - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic [`FPSIZES/3:0] FmtM, // precision 1 = double 0 = single - input logic AddendStickyM, // sticky bit that is calculated during alignment - input logic KillProdM, // set the product to zero before addition if the product is too small to matter - input logic XInfM, YInfM, ZInfM, // inputs are infinity - input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN - input logic ZSgnEffM, // the modified Z sign - depends on instruction - input logic PSgnM, // the product's sign - input logic ResultSgn, // the result's sign - input logic CalcPlus1, // rounding bits - input logic [`FLEN:0] RoundAdd, // how much to add to the result - input logic Invalid, Overflow, Underflow, // flags - input logic ResultDenorm, // is the result denormalized - input logic [`NE-1:0] ResultExp, // Result exponent - input logic [`NF-1:0] ResultFrac, // Result fraction - output logic [`FLEN-1:0] FMAResM // FMA final result -); - logic InfSgn; - logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InfResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult, NormResult; // possible results - assign InfSgn = ZInfM ? ZSgnEffM : PSgnM; - if (`FPSIZES == 1) begin - if(`IEEE754) begin - assign XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; - assign YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; - assign ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - assign InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end else begin - assign XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end - assign OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - assign KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; - assign UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; - assign InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; - assign NormResult = {ResultSgn, ResultExp, ResultFrac}; - - end else if (`FPSIZES == 2) begin //will the format conversion in killprod work in other conversions? - if(`IEEE754) begin - assign XNaNResult = FmtM ? {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; - assign YNaNResult = FmtM ? {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; - assign ZNaNResult = FmtM ? {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; - end else begin - assign XNaNResult = FmtM ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; - end - - assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} : - ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : - {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; - assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - assign InfResult = FmtM ? {InfSgn, {`NE{1'b1}}, (`NF)'(0)} : {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - assign NormResult = FmtM ? {ResultSgn, ResultExp, ResultFrac} : {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; - - end else if (`FPSIZES == 3) begin - always_comb begin - case (FmtM) - `FMT: begin - if(`IEEE754) begin - XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; - YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; - ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end else begin - XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end - - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; - UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; - InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; - NormResult = {ResultSgn, ResultExp, ResultFrac}; - end - `FMT1: begin - if(`IEEE754) begin - XNaNResult = {{`FLEN-`LEN1{1'b1}}, XSgnM, {`NE1{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF1]}; - YNaNResult = {{`FLEN-`LEN1{1'b1}}, YSgnM, {`NE1{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF1]}; - ZNaNResult = {{`FLEN-`LEN1{1'b1}}, ZSgnEffM, {`NE1{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF1]}; - InvalidResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; - end else begin - XNaNResult = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; - end - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : - {{`FLEN-`LEN1{1'b1}}, ResultSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - KillProdResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE1-2:0], ZManM[`NF-1:`NF-`NF1]} + (RoundAdd[`NF-`NF1+`LEN1-2:`NF-`NF1]&{`LEN1-1{AddendStickyM}})}; - UnderflowResult = {{`FLEN-`LEN1{1'b1}}, {ResultSgn, (`LEN1-1)'(0)} + {(`LEN1-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - InfResult = {{`FLEN-`LEN1{1'b1}}, InfSgn, {`NE1{1'b1}}, (`NF1)'(0)}; - NormResult = {{`FLEN-`LEN1{1'b1}}, ResultSgn, ResultExp[`NE1-1:0], ResultFrac[`NF-1:`NF-`NF1]}; - end - `FMT2: begin - if(`IEEE754) begin - XNaNResult = {{`FLEN-`LEN2{1'b1}}, XSgnM, {`NE2{1'b1}}, 1'b1, XManM[`NF-2:`NF-`NF2]}; - YNaNResult = {{`FLEN-`LEN2{1'b1}}, YSgnM, {`NE2{1'b1}}, 1'b1, YManM[`NF-2:`NF-`NF2]}; - ZNaNResult = {{`FLEN-`LEN2{1'b1}}, ZSgnEffM, {`NE2{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`NF2]}; - InvalidResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; - end else begin - XNaNResult = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; - end - - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : - {{`FLEN-`LEN2{1'b1}}, ResultSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - KillProdResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`NF2]} + (RoundAdd[`NF-`NF2+`LEN2-2:`NF-`NF2]&{`LEN2-1{AddendStickyM}})}; - UnderflowResult = {{`FLEN-`LEN2{1'b1}}, {ResultSgn, (`LEN2-1)'(0)} + {(`LEN2-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - InfResult = {{`FLEN-`LEN2{1'b1}}, InfSgn, {`NE2{1'b1}}, (`NF2)'(0)}; - NormResult = {{`FLEN-`LEN2{1'b1}}, ResultSgn, ResultExp[`NE2-1:0], ResultFrac[`NF-1:`NF-`NF2]}; - end - default: begin - if(`IEEE754) begin - XNaNResult = (`FLEN)'(0); - YNaNResult = (`FLEN)'(0); - ZNaNResult = (`FLEN)'(0); - InvalidResult = (`FLEN)'(0); - end else begin - XNaNResult = (`FLEN)'(0); - end - OverflowResult = (`FLEN)'(0); - KillProdResult = (`FLEN)'(0); - UnderflowResult = (`FLEN)'(0); - InfResult = (`FLEN)'(0); - NormResult = (`FLEN)'(0); - end - endcase - end - - end else if (`FPSIZES == 4) begin - always_comb begin - case (FmtM) - 2'h3: begin - if(`IEEE754) begin - XNaNResult = {XSgnM, {`NE{1'b1}}, 1'b1, XManM[`NF-2:0]}; - YNaNResult = {YSgnM, {`NE{1'b1}}, 1'b1, YManM[`NF-2:0]}; - ZNaNResult = {ZSgnEffM, {`NE{1'b1}}, 1'b1, ZManM[`NF-2:0]}; - InvalidResult = {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end else begin - XNaNResult = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; - end - - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : - {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}}; - KillProdResult = {ResultSgn, {ZExpM, ZManM[`NF-1:0]} + (RoundAdd[`FLEN-2:0]&{`FLEN-1{AddendStickyM}})}; - UnderflowResult = {ResultSgn, {`FLEN-1{1'b0}}} + {(`FLEN-1)'(0),(CalcPlus1&(AddendStickyM|FrmM[1]))}; - InfResult = {InfSgn, {`NE{1'b1}}, (`NF)'(0)}; - NormResult = {ResultSgn, ResultExp, ResultFrac}; - end - 2'h1: begin - if(`IEEE754) begin - XNaNResult = {{`FLEN-`D_LEN{1'b1}}, XSgnM, {`D_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`D_NF]}; - YNaNResult = {{`FLEN-`D_LEN{1'b1}}, YSgnM, {`D_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`D_NF]}; - ZNaNResult = {{`FLEN-`D_LEN{1'b1}}, ZSgnEffM, {`D_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`D_NF]}; - InvalidResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; - end else begin - XNaNResult = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; - end - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : - {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - KillProdResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`D_NE-2:0], ZManM[`NF-1:`NF-`D_NF]} + (RoundAdd[`NF-`D_NF+`D_LEN-2:`NF-`D_NF]&{`D_LEN-1{AddendStickyM}})}; - UnderflowResult = {{`FLEN-`D_LEN{1'b1}}, {ResultSgn, (`D_LEN-1)'(0)} + {(`D_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - InfResult = {{`FLEN-`D_LEN{1'b1}}, InfSgn, {`D_NE{1'b1}}, (`D_NF)'(0)}; - NormResult = {{`FLEN-`D_LEN{1'b1}}, ResultSgn, ResultExp[`D_NE-1:0], ResultFrac[`NF-1:`NF-`D_NF]}; - end - 2'h0: begin - if(`IEEE754) begin - XNaNResult = {{`FLEN-`S_LEN{1'b1}}, XSgnM, {`S_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`S_NF]}; - YNaNResult = {{`FLEN-`S_LEN{1'b1}}, YSgnM, {`S_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`S_NF]}; - ZNaNResult = {{`FLEN-`S_LEN{1'b1}}, ZSgnEffM, {`S_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`S_NF]}; - InvalidResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; - end else begin - XNaNResult = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; - end - - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : - {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - KillProdResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`NE2-2:0], ZManM[`NF-1:`NF-`S_NF]} + (RoundAdd[`NF-`S_NF+`S_LEN-2:`NF-`S_NF]&{`S_LEN-1{AddendStickyM}})}; - UnderflowResult = {{`FLEN-`S_LEN{1'b1}}, {ResultSgn, (`S_LEN-1)'(0)} + {(`S_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - InfResult = {{`FLEN-`S_LEN{1'b1}}, InfSgn, {`S_NE{1'b1}}, (`S_NF)'(0)}; - NormResult = {{`FLEN-`S_LEN{1'b1}}, ResultSgn, ResultExp[`S_NE-1:0], ResultFrac[`NF-1:`NF-`S_NF]}; - end - 2'h2: begin - if(`IEEE754) begin - XNaNResult = {{`FLEN-`H_LEN{1'b1}}, XSgnM, {`H_NE{1'b1}}, 1'b1, XManM[`NF-2:`NF-`H_NF]}; - YNaNResult = {{`FLEN-`H_LEN{1'b1}}, YSgnM, {`H_NE{1'b1}}, 1'b1, YManM[`NF-2:`NF-`H_NF]}; - ZNaNResult = {{`FLEN-`H_LEN{1'b1}}, ZSgnEffM, {`H_NE{1'b1}}, 1'b1, ZManM[`NF-2:`NF-`H_NF]}; - InvalidResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; - end else begin - XNaNResult = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; - end - - OverflowResult = ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : - {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - - KillProdResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, {ZExpM[`NE-1], ZExpM[`H_NE-2:0], ZManM[`NF-1:`NF-`H_NF]} + (RoundAdd[`NF-`H_NF+`H_LEN-2:`NF-`H_NF]&{`H_LEN-1{AddendStickyM}})}; - UnderflowResult = {{`FLEN-`H_LEN{1'b1}}, {ResultSgn, (`H_LEN-1)'(0)} + {(`H_LEN-1)'(0), (CalcPlus1&(AddendStickyM|FrmM[1]))}}; - InfResult = {{`FLEN-`H_LEN{1'b1}}, InfSgn, {`H_NE{1'b1}}, (`H_NF)'(0)}; - NormResult = {{`FLEN-`H_LEN{1'b1}}, ResultSgn, ResultExp[`H_NE-1:0], ResultFrac[`NF-1:`NF-`H_NF]}; - end - endcase - end - - end - if(`IEEE754) begin - assign FMAResM = XNaNM ? XNaNResult : - YNaNM ? YNaNResult : - ZNaNM ? ZNaNResult : - Invalid ? InvalidResult : - XInfM|YInfM|ZInfM ? InfResult : - KillProdM ? KillProdResult : - Overflow ? OverflowResult : - Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult : - NormResult; - end else begin - assign FMAResM = XNaNM|YNaNM|ZNaNM|Invalid ? XNaNResult : - XInfM|YInfM|ZInfM ? InfResult : - KillProdM ? KillProdResult : - Overflow ? OverflowResult : - Underflow & ~ResultDenorm & (ResultExp!=1) ? UnderflowResult : - NormResult; - end - -endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fmaadd.sv b/pipelined/src/fpu/fmaadd.sv new file mode 100644 index 000000000..af7b15bf4 --- /dev/null +++ b/pipelined/src/fpu/fmaadd.sv @@ -0,0 +1,75 @@ +/////////////////////////////////////////// +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: FMA significand adder +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fmaadd( + input logic [3*`NF+5:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1) + input logic [2*`NF+1:0] Pm, // the product's mantissa + input logic Ps, As,// the product sign and the alligend addeded's sign (Modified Z sign for other opperations) + input logic InvA, // invert the aligned addend + input logic KillProd, // should the product be set to 0 + input logic ZmSticky, + input logic [`NE-1:0] Ze, + input logic [`NE+1:0] Pe, + output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted + output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed + output logic NegSum, // was the sum negitive + output logic Ss, + output logic [`NE+1:0] Se, + output logic [3*`NF+5:0] Sm // the positive sum +); + logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum + + /////////////////////////////////////////////////////////////////////////////// + // Addition + /////////////////////////////////////////////////////////////////////////////// + + // Choose an inverted or non-inverted addend. Put carry into adder/LZA for addition + assign AmInv = InvA ? ~Am : Am; + // Kill the product if the product is too small to effect the addition (determined in fma1.sv) + assign PmKilled = KillProd ? '0 : Pm; + // Do the addition + // - calculate a positive and negitive sum in parallel + // Zsticky Psticky + // PreSum -1 = don't add 1 +1 = add 2 + // NegPreSum +1 = add 2 -1 = don't add 1 + // for NegPreSum the product is set to -1 whenever the product is killed, therefore add 1, 2 or 0 + assign {NegSum, PreSum} = {{`NF+3{1'b0}}, PmKilled, 1'b0, InvA&ZmSticky&KillProd} + {InvA, AmInv} + {{3*`NF+6{1'b0}}, InvA&~((ZmSticky&~KillProd))}; + assign NegPreSum = Am + {{`NF+2{1'b1}}, ~PmKilled, 2'b11} + {(3*`NF+4)'(0), ZmSticky&~KillProd, ~(ZmSticky)}; + + // Choose the positive sum and accompanying LZA result. + assign Sm = NegSum ? NegPreSum : PreSum; + // is the result negitive + // if p - z is the Sum negitive + // if -p + z is the Sum positive + // if -p - z then the Sum is negitive + assign Ss = NegSum^Ps; + assign Se = KillProd ? {2'b0, Ze} : Pe; +endmodule diff --git a/pipelined/src/fpu/fmaalign.sv b/pipelined/src/fpu/fmaalign.sv new file mode 100644 index 000000000..f7c849993 --- /dev/null +++ b/pipelined/src/fpu/fmaalign.sv @@ -0,0 +1,101 @@ + +/////////////////////////////////////////// +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: FMA alginment shift +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fmaalign( + input logic [`NE-1:0] Xe, Ye, Ze, // biased exponents in B(NE.0) format + input logic [`NF:0] Zm, // significand in U(0.NF) format] + input logic XZero, YZero, ZZero, // is the input zero + output logic [3*`NF+5:0] Am, // addend aligned for addition in U(NF+5.2NF+1) + output logic ZmSticky, // Sticky bit calculated from the aliged addend + output logic KillProd // should the product be set to zero +); + + logic [`NE+1:0] ACnt; // how far to shift the addend to align with the product in Q(NE+2.0) format + logic [4*`NF+5:0] ZmShifted; // output of the alignment shifter including sticky bits U(NF+5.3NF+1) + logic [4*`NF+5:0] ZmPreshifted; // input to the alignment shifter U(NF+5.3NF+1) + logic KillZ; + + /////////////////////////////////////////////////////////////////////////////// + // Alignment shifter + /////////////////////////////////////////////////////////////////////////////// + + // determine the shift count for alignment + // - negitive means Z is larger, so shift Z left + // - positive means the product is larger, so shift Z right + // This could have been done using Pe, but ACnt is on the critical path so we replicate logic for speed + assign ACnt = {2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)} + (`NE+2)'(`NF+3) - {2'b0, Ze}; + + // Defualt Addition without shifting + // | 54'b0 | 106'b(product) | 2'b0 | + // | addnend | + + // the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...) + assign ZmPreshifted = {Zm,(3*`NF+5)'(0)}; + + assign KillProd = (ACnt[`NE+1]&~ZZero)|XZero|YZero; + assign KillZ = $signed(ACnt)>$signed((`NE+2)'(3)*(`NE+2)'(`NF)+(`NE+2)'(5)); + + always_comb + begin + + // If the product is too small to effect the sum, kill the product + + // | 54'b0 | 106'b(product) | 2'b0 | + // | addnend | + if (KillProd) begin + ZmShifted = {(`NF+3)'(0), Zm, (2*`NF+2)'(0)}; + ZmSticky = ~(XZero|YZero); + + // If the addend is too small to effect the addition + // - The addend has to shift two past the end of the addend to be considered too small + // - The 2 extra bits are needed for rounding + + // | 54'b0 | 106'b(product) | 2'b0 | + // | addnend | + end else if (KillZ) begin + ZmShifted = 0; + ZmSticky = ~ZZero; + + // If the Addend is shifted right + // | 54'b0 | 106'b(product) | 2'b0 | + // | addnend | + end else begin + ZmShifted = ZmPreshifted >> ACnt; + ZmSticky = |(ZmShifted[`NF-1:0]); + + end + end + + assign Am = ZmShifted[4*`NF+5:`NF]; + +endmodule + diff --git a/pipelined/src/fpu/sbtm_sqrt.sv b/pipelined/src/fpu/fmaexpadd.sv similarity index 61% rename from pipelined/src/fpu/sbtm_sqrt.sv rename to pipelined/src/fpu/fmaexpadd.sv index bc15a82f2..d39dfadde 100644 --- a/pipelined/src/fpu/sbtm_sqrt.sv +++ b/pipelined/src/fpu/fmaexpadd.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // -// Written: James Stine -// Modified: 8/1/2018 +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: // -// Purpose: Bipartite Lookup for sqrt part of fpdivsqrt +// Purpose: FMA exponent addition // // A component of the Wally configurable RISC-V project. // @@ -27,42 +27,19 @@ // OR OTHER DEALINGS IN THE SOFTWARE. //////////////////////////////////////////////////////////////////////////////////////////////// -module sbtm_sqrt (input logic [11:0] a, output logic [10:0] y); - - // bit partitions - logic [4:0] x0; - logic [2:0] x1; - logic [3:0] x2; - logic [2:0] x2_1cmp; - // mem outputs - logic [13:0] y0; - logic [5:0] y1; - // input to CPA - logic [14:0] op1; - logic [14:0] op2; - logic [14:0] p; - logic cout; - - assign x0 = a[11:7]; - assign x1 = a[6:4]; - assign x2 = a[3:0]; - - sbtm_a2 mem1 ({x0, x1}, y0); - assign op1 = {y0, 1'b0}; - - // 1s cmp per sbtm/stam - assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; - sbtm_a3 mem2 ({x0, x2_1cmp}, y1); - // 1s cmp per sbtm/stam - assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} : - {8'b0, y1, 1'b1}; - - // CPA - assign {cout, p} = op1 + op2; - assign y = p[14:4]; - -endmodule // sbtm2 +`include "wally-config.vh" +module fmaexpadd( + input logic [`FMTBITS-1:0] Fmt, // format of the output: single double half quad + input logic [`NE-1:0] Xe, Ye, // input's exponents + input logic XZero, YZero, // are the inputs zero + output logic [`NE+1:0] Pe // product's exponent B^(1023)NE+2 +); + logic PZero; + // kill the exponent if the product is zero - either X or Y is 0 + assign PZero = XZero | YZero; + assign Pe = PZero ? '0 : ({2'b0, Xe} + {2'b0, Ye} - {2'b0, (`NE)'(`BIAS)}); +endmodule diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv new file mode 100644 index 000000000..8e92a5dc4 --- /dev/null +++ b/pipelined/src/fpu/fmalza.sv @@ -0,0 +1,60 @@ +/////////////////////////////////////////// +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: Leading Zero Anticipator +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fmalza #(WIDTH) ( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] + input logic [WIDTH-1:0] A, // addend + input logic [2*`NF+3:0] Pm, // product + input logic Cin, // carry in + input logic sub, + output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result + ); + + logic [WIDTH:0] F; + logic [WIDTH-1:0] B, P, G, K; + logic [WIDTH-1:0] Pp1, Gm1, Km1; + + assign B = {{(`NF+2){1'b0}}, Pm}; // Zero extend product + + assign P = A^B; + assign G = A&B; + assign K= ~A&~B; + + assign Pp1 = {sub, P[WIDTH-1:1]}; + assign Gm1 = {G[WIDTH-2:0], Cin}; + assign Km1 = {K[WIDTH-2:0], ~Cin}; + + // Apply function to determine Leading pattern + // - note: the paper linked above uses the numbering system where 0 is the most significant bit + assign F[WIDTH] = ~sub&P[WIDTH-1]; + assign F[WIDTH-1:0] = (Pp1&(G&~Km1 | K&~Gm1)) | (~Pp1&(K&~Km1 | G&~Gm1)); + + lzc #(WIDTH+1) lzc (.num(F), .ZeroCnt(SCnt)); +endmodule diff --git a/pipelined/src/fpu/fmamult.sv b/pipelined/src/fpu/fmamult.sv new file mode 100644 index 000000000..1e1b0981e --- /dev/null +++ b/pipelined/src/fpu/fmamult.sv @@ -0,0 +1,38 @@ +/////////////////////////////////////////// +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: FMA Significand Multiplier +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fmamult( + input logic [`NF:0] Xm, Ym, + output logic [2*`NF+1:0] Pm +); + assign Pm = Xm * Ym; +endmodule + diff --git a/pipelined/src/fpu/fmashiftcalc.sv b/pipelined/src/fpu/fmashiftcalc.sv new file mode 100644 index 000000000..a1c0a276c --- /dev/null +++ b/pipelined/src/fpu/fmashiftcalc.sv @@ -0,0 +1,158 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Fma shift calculation +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module fmashiftcalc( + input logic [3*`NF+5:0] FmaSm, // the positive sum + input logic [`NE-1:0] Ze, // exponent of Z + input logic [`NE+1:0] FmaPe, // X exponent + Y exponent - bias + input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count + input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single + input logic FmaKillProd, // is the product set to zero + input logic [`NE+1:0] FmaSe, + output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results + output logic FmaSZero, // is the result denormalized - calculated before LZA corection + output logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection + output logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt, // normalization shift count + output logic [3*`NF+7:0] FmaShiftIn // is the sum zero +); + logic [`NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the `FLEN bias + logic [`NE+1:0] BiasCorr; + + /////////////////////////////////////////////////////////////////////////////// + // Normalization + /////////////////////////////////////////////////////////////////////////////// + //*** insert bias-bias simplification in fcvt.sv/phone pictures + // Determine if the sum is zero + assign FmaSZero = ~(|FmaSm); + // calculate the sum's exponent + assign PreNormSumExp = FmaSe + {{`NE+2-$unsigned($clog2(3*`NF+7)){1'b1}}, ~FmaSCnt} + (`NE+2)'(`NF+4); + + //convert the sum's exponent into the proper percision + if (`FPSIZES == 1) begin + assign NormSumExp = PreNormSumExp; + + end else if (`FPSIZES == 2) begin + assign BiasCorr = Fmt ? (`NE+2)'(0) : (`NE+2)'(`BIAS1-`BIAS); + assign NormSumExp = PreNormSumExp+BiasCorr; + + end else if (`FPSIZES == 3) begin + always_comb begin + case (Fmt) + `FMT: BiasCorr = '0; + `FMT1: BiasCorr = (`NE+2)'(`BIAS1-`BIAS); + `FMT2: BiasCorr = (`NE+2)'(`BIAS2-`BIAS); + default: BiasCorr = 'x; + endcase + end + assign NormSumExp = PreNormSumExp+BiasCorr; + + end else if (`FPSIZES == 4) begin + always_comb begin + case (Fmt) + 2'h3: BiasCorr = '0; + 2'h1: BiasCorr = (`NE+2)'(`D_BIAS-`Q_BIAS); + 2'h0: BiasCorr = (`NE+2)'(`S_BIAS-`Q_BIAS); + 2'h2: BiasCorr = (`NE+2)'(`H_BIAS-`Q_BIAS); + endcase + end + assign NormSumExp = PreNormSumExp+BiasCorr; + + end + + // determine if the result is denormalized + + if (`FPSIZES == 1) begin + logic Sum0LEZ, Sum0GEFL; + assign Sum0LEZ = PreNormSumExp[`NE+1] | ~|PreNormSumExp; + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2)); + assign FmaPreResultDenorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; + + end else if (`FPSIZES == 2) begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; + assign Sum0LEZ = PreNormSumExp[`NE+1] | ~|PreNormSumExp; + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2)); + assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1)); + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp; + assign FmaPreResultDenorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero; + + end else if (`FPSIZES == 3) begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; + assign Sum0LEZ = PreNormSumExp[`NE+1] | ~|PreNormSumExp; + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2)); + assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS1)); + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF1-2+`BIAS-`BIAS1)) | ~|PreNormSumExp; + assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`BIAS2)); + assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF2-2+`BIAS-`BIAS2)) | ~|PreNormSumExp; + always_comb begin + case (Fmt) + `FMT: FmaPreResultDenorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; + `FMT1: FmaPreResultDenorm = Sum1LEZ & Sum1GEFL & ~FmaSZero; + `FMT2: FmaPreResultDenorm = Sum2LEZ & Sum2GEFL & ~FmaSZero; + default: FmaPreResultDenorm = 1'bx; + endcase + end + + end else if (`FPSIZES == 4) begin + logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL; + assign Sum0LEZ = PreNormSumExp[`NE+1] | ~|PreNormSumExp; + assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`NF-2)); + assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`D_BIAS)); + assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`D_NF-2+`BIAS-`D_BIAS)) | ~|PreNormSumExp; + assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`S_BIAS)); + assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`S_NF-2+`BIAS-`S_BIAS)) | ~|PreNormSumExp; + assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((`NE+2)'(`BIAS-`H_BIAS)); + assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((`NE+2)'(-`H_NF-2+`BIAS-`H_BIAS)) | ~|PreNormSumExp; + always_comb begin + case (Fmt) + 2'h3: FmaPreResultDenorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; + 2'h1: FmaPreResultDenorm = Sum1LEZ & Sum1GEFL & ~FmaSZero; + 2'h0: FmaPreResultDenorm = Sum2LEZ & Sum2GEFL & ~FmaSZero; + 2'h2: FmaPreResultDenorm = Sum3LEZ & Sum3GEFL & ~FmaSZero; + endcase + end + + end + + // 010. when should be 001. + // - shift left one + // - add one from exp + // - if kill prod dont add to exp + + // Determine if the result is denormal + // assign FmaPreResultDenorm = $signed(NormSumExp)<=0 & ($signed(NormSumExp)>=$signed(-FracLen)) & ~FmaSZero; + + // set and calculate the shift input and amount + // - shift once if killing a product and the result is denormalized + assign FmaShiftIn = {2'b0, FmaSm}; + if (`FPSIZES == 1) + assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+7)-1:0]+($clog2(3*`NF+7))'(`NF+3): FmaSCnt+1; + else + assign FmaShiftAmt = FmaPreResultDenorm ? FmaSe[$clog2(3*`NF+7)-1:0]+($clog2(3*`NF+7))'(`NF+3)+BiasCorr[$clog2(3*`NF+7)-1:0]: FmaSCnt+1; +endmodule diff --git a/pipelined/src/fpu/fmasign.sv b/pipelined/src/fpu/fmasign.sv new file mode 100644 index 000000000..936eea211 --- /dev/null +++ b/pipelined/src/fpu/fmasign.sv @@ -0,0 +1,49 @@ +/////////////////////////////////////////// +// +// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu +// Modified: +// +// Purpose: FMA Sign Logic +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fmasign( + input logic [2:0] OpCtrl, // opperation contol + input logic Xs, Ys, Zs, // sign of the inputs + output logic Ps, // the product's sign - takes opperation into account + output logic As, // aligned addend sign used in fma - takes opperation into account + output logic InvA // Effective subtraction: invert addend +); + + // Calculate the product's sign + // Negate product's sign if FNMADD or FNMSUB + + // flip is negation opperation + assign Ps = Xs ^ Ys ^ (OpCtrl[1]&~OpCtrl[2]); + // flip addend sign for subtraction + assign As = Zs^OpCtrl[0]; + // Effective subtraction when product and addend have opposite signs + assign InvA = As ^ Ps; +endmodule diff --git a/pipelined/src/fpu/fpdiv.sv b/pipelined/src/fpu/fpdiv.sv deleted file mode 100755 index 127a7686c..000000000 --- a/pipelined/src/fpu/fpdiv.sv +++ /dev/null @@ -1,132 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Floating point divider/square root top unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// `timescale 1ps/1ps -module fpdiv ( - input logic clk, - input logic reset, - input logic start, - input logic [63:0] op1, - input logic [63:0] op2, - input logic [1:0] rm, - input logic op_type, - input logic P, - input logic OvEn, - input logic UnEn, - input logic XNaNQ, - input logic YNaNQ, - input logic XZeroQ, - input logic YZeroQ, - input logic XInfQ, - input logic YInfQ, - - output logic done, - output logic FDivBusyE, - output logic [63:0] AS_Result, - output logic [4:0] Flags); - - logic [63:0] Float1; - logic [63:0] Float2; - - logic [12:0] exp1, exp2, expF; - logic [12:0] exp_diff, bias; - logic [13:0] exp_sqrt; - logic [63:0] Result; - logic [52:0] mantissaA; - logic [52:0] mantissaB; - - logic [2:0] sel_inv; - logic Invalid; - logic [4:0] FlagsIn; - logic signResult; - - logic [59:0] q1, qm1, qp1, q0, qm0, qp0; - logic [59:0] rega_out, regb_out, regc_out, regd_out; - logic [119:0] regr_out; - logic [2:0] sel_muxa, sel_muxb; - logic sel_muxr; - logic load_rega, load_regb, load_regc, load_regd, load_regr; - - logic load_regs; - logic exp_cout1, exp_cout2; - logic exp_odd, open; - - // op_type : fdiv=0, fsqrt=1 - assign Float1 = op1; - assign Float2 = op_type ? op1 : op2; - - // Exception detection - exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid); - - // Determine Sign/Mantissa - assign signResult = (Float1[63]^Float2[63]); - assign mantissaA = {1'b1, Float1[51:0]}; - assign mantissaB = {1'b1, Float2[51:0]}; - // Perform Exponent Subtraction - expA - expB + Bias - assign exp1 = {2'b0, Float1[62:52]}; - assign exp2 = {2'b0, Float2[62:52]}; - assign bias = {3'h0, 10'h3FF}; - // Divide exponent - assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias}; - - // Sqrt exponent (check if exponent is odd) - assign exp_odd = Float1[52] ? 1'b0 : 1'b1; - assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd}; - // Choose correct exponent - assign expF = op_type ? exp_sqrt[13:1] : exp_diff; - - // Main Goldschmidt/Division Routine - divconv goldy (.q1, .qm1, .qp1, .q0, .qm0, .qp0, .rega_out, .regb_out, .regc_out, .regd_out, - .regr_out, .d(mantissaB), .n(mantissaA), .sel_muxa, .sel_muxb, .sel_muxr, - .reset, .clk, .load_rega, .load_regb, .load_regc, .load_regd, - .load_regr, .load_regs, .P, .op_type, .exp_odd); - - // FSM : control divider - fsm_fpdiv control (.clk, .reset, .start, .op_type, - .done, .load_rega, .load_regb, .load_regc, .load_regd, - .load_regr, .load_regs, .sel_muxa, .sel_muxb, .sel_muxr, - .divBusy(FDivBusyE)); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. The rounding units also handles special cases and - // set the exception flags. - rounder_div round1 (.rm, .P, .OvEn, .UnEn, .exp_diff(expF), - .sel_inv, .Invalid, .SignR(signResult), - .Float1(op1), .Float2(op2), - .XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ, - .XInfQ, .YInfQ, .op_type, - .q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out, - .Result, .Flags(FlagsIn)); - - // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, done, Result, AS_Result); - flopenr #(5) regc (clk, reset, done, FlagsIn, Flags); - -endmodule // fpadd - diff --git a/pipelined/src/fpu/fpdiv_pipe.sv b/pipelined/src/fpu/fpdiv_pipe.sv deleted file mode 100755 index 8e4bd2399..000000000 --- a/pipelined/src/fpu/fpdiv_pipe.sv +++ /dev/null @@ -1,170 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Floating point divider/square root top unit pipelined version (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module fpdiv_pipe ( - input logic clk, - input logic reset, - input logic start, - input logic [63:0] op1, - input logic [63:0] op2, - input logic [1:0] rm, - input logic op_type, - input logic P, - input logic OvEn, - input logic UnEn, - input logic XNaNQ, - input logic YNaNQ, - input logic XZeroQ, - input logic YZeroQ, - input logic XInfQ, - input logic YInfQ, - - output logic done, - output logic FDivBusyE, - output logic load_preload, - output logic [63:0] AS_Result, - output logic [4:0] Flags); - - supply1 vdd; - supply0 vss; - - logic [63:0] Float1; - logic [63:0] Float2; - logic [63:0] IntValue; - - logic [12:0] exp1, exp2, expF; - logic [14:0] exp_pre_diff; - logic [12:0] exp_diff, bias; - logic [13:0] exp_sqrt; - - logic [63:0] Result; - logic [52:0] mantissaA; - logic [52:0] mantissaB; - - logic [2:0] sel_inv; - logic Invalid; - logic [4:0] FlagsIn; - logic exp_gt63; - logic Sticky_out; - logic signResult, sign_corr; - logic corr_sign; - logic zeroB; - logic convert; - logic swap; - logic sub; - - logic [59:0] q1, qm1, qp1, q0, qm0, qp0; - logic [59:0] rega_out, regb_out, regc_out, regd_out; - logic [119:0] regr_out; - logic [2:0] sel_muxa, sel_muxb; - logic sel_muxr; - logic load_rega, load_regb, load_regc, load_regd, load_regr; - logic load_regp, load_regs; - - logic exp_odd, exp_odd1; - logic start1; - logic P1; - logic op_type1; - logic [12:0] expF1; - logic [52:0] mantissaA1; - logic [52:0] mantissaB1; - logic [2:0] sel_inv1; - logic signResult1; - logic Invalid1; - - // op_type : fdiv=0, fsqrt=1 - assign Float1 = op1; - assign Float2 = op_type ? op1 : op2; - - // Exception detection - exception_div exc1 (.A(Float1), .B(Float2), .op_type, .Ztype(sel_inv), .Invalid); - - // Determine Sign/Mantissa - assign signResult = ((Float1[63]^Float2[63])&~op_type); - assign mantissaA = {vdd, Float1[51:0]}; - assign mantissaB = {vdd, Float2[51:0]}; - - // Perform Exponent Subtraction - expA - expB + Bias - assign exp1 = {2'b0, Float1[62:52]}; - assign exp2 = {2'b0, Float2[62:52]}; - // bias : DP = 2^{11-1}-1 = 1023 - assign bias = {3'h0, 10'h3FF}; - // Divide exponent - assign exp_pre_diff = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias}; - assign exp_diff = exp_pre_diff[12:0]; - - // Sqrt exponent (check if exponent is odd) - assign exp_odd = Float1[52] ? 1'b0 : 1'b1; - assign exp_sqrt = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd}; - // Choose correct exponent - assign expF = op_type ? exp_sqrt[13:1] : exp_diff; - - flopenr #(1) rega (clk, reset, 1'b1, exp_odd, exp_odd1); - flopenr #(1) regb (clk, reset, 1'b1, P, P1); - flopenr #(1) regc (clk, reset, 1'b1, op_type, op_type1); - flopenr #(13) regd (clk, reset, 1'b1, expF, expF1); - flopenr #(53) rege (clk, reset, 1'b1, mantissaA, mantissaA1); - flopenr #(53) regf (clk, reset, 1'b1, mantissaB, mantissaB1); - flopenr #(1) regg (clk, reset, 1'b1, start, start1); - flopenr #(3) regh (clk, reset, 1'b1, sel_inv, sel_inv1); - flopenr #(1) regj (clk, reset, 1'b1, signResult, signResult1); - flopenr #(1) regk (clk, reset, 1'b1, Invalid, Invalid1); - - // Main Goldschmidt/Division Routine - divconv_pipe goldy (.q1, .qm1, .qp1, .q0, .qm0, .qp0, - .rega_out, .regb_out, .regc_out, .regd_out, - .regr_out, .d(mantissaB1), .n(mantissaA1), - .sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk, - .load_rega, .load_regb, .load_regc, .load_regd, - .load_regr, .load_regs, .load_regp, - .P(P), .op_type(op_type1), .exp_odd(exp_odd1)); - - // FSM : control divider - fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P), - .done, .load_rega, .load_regb, .load_regc, .load_regd, - .load_regr, .load_regs, .load_regp, .load_preload, - .sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE)); - - // Round the mantissa to a 52-bit value, with the leading one - // removed. The rounding units also handles special cases and - // set the exception flags. - rounder_div round1 (.rm, .P(P), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1), - .sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1), - .Float1(op1), .Float2(op2), - .XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ, - .XInfQ, .YInfQ, .op_type(op_type1), - .q1, .qm1, .qp1, .q0, .qm0, .qp0, .regr_out, - .Result, .Flags(FlagsIn)); - - // Store the final result and the exception flags in registers. - flopenr #(64) regl (clk, reset, done, Result, AS_Result); - flopenr #(5) regn (clk, reset, done, FlagsIn, Flags); - -endmodule // fpdiv_pipe - diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 0fc9e8635..3e5485acb 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// // -// Written: Katherine Parry, James Stine, Brett Mathis +// Written: me@KatherineParry.com, James Stine, Brett Mathis // Modified: 6/23/2021 // // Purpose: FPU @@ -30,32 +30,31 @@ `include "wally-config.vh" module fpu ( - input logic clk, - input logic reset, - input logic [2:0] FRM_REGW, // Rounding mode from CSR - input logic [31:0] InstrD, // instruction from IFU - input logic [`XLEN-1:0] ReadDataW,// Read data from memory - input logic [`XLEN-1:0] ForwardedSrcAE, // Integer input being processed (from IEU) - input logic StallE, StallM, StallW, // stall signals from HZU - input logic FlushE, FlushM, FlushW, // flush signals from HZU - input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) - input logic [1:0] STATUS_FS, // Is floating-point enabled? - output logic FRegWriteM, // FP register write enable - output logic FStallD, // Stall the decode stage - output logic FWriteIntE, // integer register write enables - output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory - output logic [`XLEN-1:0] FIntResM, // data to be written to integer register - output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) - output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction + input logic clk, + input logic reset, + input logic [2:0] FRM_REGW, // Rounding mode (from CSR) + input logic [31:0] InstrD, // instruction (from IFU) + input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) + input logic [`XLEN-1:0] ForwardedSrcAE, // Integer input (from IEU) + input logic StallE, StallM, StallW, // stall signals (from HZU) + input logic FlushE, FlushM, FlushW, // flush signals (from HZU) + input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) + input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) + output logic FRegWriteM, // FP register write enable (to privileged unit) + output logic FpLoadStoreM, // Fp load instruction? (to LSU) + output logic FStore2, // store two words into memory (to LSU) + output logic FStallD, // Stall the decode stage (To HZU) + output logic FWriteIntE, // integer register write enable (to IEU) + output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory (to IEU) - only used if `XLEN >`FLEN + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to IEU) - only used if `XLEN <`FLEN + output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) + output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) + output logic [1:0] FResSelW, // final result selection (to IEU) + output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) + output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to privileged unit) output logic [4:0] SetFflagsM // FPU flags (to privileged unit) ); - //*** make everything FLEN at some point - //*** add the 128 bit support to the if statement when needed - //*** make new tests for fp using testfloat that include flag checking and all rounding modes - //*** what is the format for 16-bit - finding conflicting info online can't find anything specified in spec - //*** only fma/mul and fp <-> int convert flags have been tested. test the others. - // FPU specifics: // - uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s @@ -63,81 +62,112 @@ module fpu ( // - sets the underflow after rounding // control signals - logic FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable - logic [2:0] FrmD, FrmE, FrmM; // FP rounding mode - logic FmtD, FmtE, FmtM, FmtW; // FP precision 0-single 1-double - logic FDivStartD, FDivStartE; // Start division or squareroot - logic FWriteIntD; // Write to integer register - logic [1:0] FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals - logic [1:0] FResultSelD, FResultSelE; // Select the result written to FP register - logic [1:0] FResultSelM, FResultSelW; // Select the result written to FP register - logic [2:0] FOpCtrlD, FOpCtrlE; // Select which opperation to do in each component - logic [2:0] FResSelD, FResSelE; // Select one of the results that finish in the memory stage - logic [1:0] FIntResSelD, FIntResSelE; // Select the result written to the integer resister - logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input + logic FRegWriteW; // FP register write enable + logic [2:0] FrmM; // FP rounding mode + logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double + logic DivStartE; // Start division or squareroot + logic FWriteIntM; // Write to integer register + logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals + logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component + logic [1:0] FResSelE, FResSelM; // Select one of the results that finish in the memory stage + logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit + logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input + logic IllegalFPUInstrM; + logic XEnE, YEnE, ZEnE; + logic YEnForwardE, ZEnForwardE; // regfile signals - logic [63:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage - logic [63:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage - logic [63:0] FSrcXE; // Input 1 to the various units (after forwarding) - logic [63:0] FPreSrcYE, FSrcYE; // Input 2 to the various units (after forwarding) - logic [63:0] FPreSrcZE, FSrcZE; // Input 3 to the various units (after forwarding) + logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage + logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage + logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding) + logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding) + logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding) + logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding) // unpacking signals - logic XSgnE, YSgnE, ZSgnE; // input's sign - execute stage - logic XSgnM, YSgnM; // input's sign - memory stage - logic [10:0] XExpE, YExpE, ZExpE; // input's exponent - execute stage - logic [10:0] XExpM, YExpM, ZExpM; // input's exponent - memory stage - logic [52:0] XManE, YManE, ZManE; // input's fraction - execute stage - logic [52:0] XManM, YManM, ZManM; // input's fraction - memory stage - logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage - logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage - logic XNaNQ, YNaNQ; // is the input a NaN - divide - logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage - logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage - logic XDenormE, YDenormE, ZDenormE; // is the input denormalized - logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage - logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage - logic XZeroQ, YZeroQ; // is the input zero - divide - logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage - logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage - logic XInfQ, YInfQ; // is the input infinity - divide - logic XExpMaxE; // is the exponent all ones (max value) - logic XNormE; // is normal - logic FmtQ; - logic FOpCtrlQ; + logic XsE, YsE, ZsE; // input's sign - execute stage + logic XsM, YsM; // input's sign - memory stage + logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage + logic [`NE-1:0] ZeM; // input's exponent - memory stage + logic [`NF:0] XmE, YmE, ZmE; // input's fraction - execute stage + logic [`NF:0] XmM, YmM, ZmM; // input's fraction - memory stage + logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage + logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage + logic XNaNQ, YNaNQ; // is the input a NaN - divide + logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage + logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage + logic XDenormE, ZDenormE, ZDenormM; // is the input denormalized + logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage + logic XZeroM, YZeroM, ZZeroM; // is the input zero - memory stage + logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage + logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage + logic XExpMaxE; // is the exponent all ones (max value) + + // Fma Signals + logic [3*`NF+5:0] SmE, SmM; + logic [`NE+1:0] PeE, PeM; + logic ZmStickyE, ZmStickyM; + logic [`NE+1:0] SeE,SeM; + logic KillProdE, KillProdM; + logic InvAE, InvAM; + logic NegSumE, NegSumM; + logic AsE, AsM; + logic PsE, PsM; + logic SsE, SsM; + logic [$clog2(3*`NF+7)-1:0] SCntE, SCntM; + + // Cvt Signals + logic [`NE:0] CeE, CeM; // the calculated expoent + logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by + logic CvtResDenormUfE, CvtResDenormUfM;// does the result underflow or is denormalized + logic CsE, CsM; // the result's sign + logic IntZeroE, IntZeroM; // is the integer zero? + logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) + + //divide signals + logic [`DIVb-(`RADIX/4):0] QmM; + logic [`NE+1:0] QeE, QeM; + logic DivSE, DivSM; + logic DivDoneM; + logic [`DURLEN-1:0] EarlyTermShiftM; // result and flag signals - logic [63:0] FDivResM, FDivResW; // divide/squareroot result - logic [4:0] FDivFlgM; // divide/squareroot flags - logic [63:0] FMAResM, FMAResW; // FMA/multiply result - logic [4:0] FMAFlgM; // FMA/multiply result - logic [63:0] ReadResW; // read result (load instruction) - logic [63:0] CvtFpResE; // add/FP -> FP convert result - logic [4:0] CvtFpFlgE; // add/FP -> FP convert flags - logic [63:0] CvtResE; // FP <-> int convert result - logic [4:0] CvtFlgE; // FP <-> int convert flags //*** trim this - logic [63:0] ClassResE; // classify result - logic [63:0] CmpResE; // compare result - logic CmpNVE; // compare invalid flag (Not Valid) - logic [63:0] SgnResE; // sign injection result - logic [63:0] FResE, FResM, FResW; // selected result that is ready in the memory stage - logic [4:0] FFlgE, FFlgM; // selected flag that is ready in the memory stage - logic [`XLEN-1:0] FIntResE; - logic [63:0] FPUResultW; // final FP result being written to the FP register + logic [`XLEN-1:0] ClassResE; // classify result + logic [`XLEN-1:0] FIntResE; // classify result + logic [`FLEN-1:0] FpResM, FpResW; // classify result + logic [`FLEN-1:0] PostProcResM; // classify result + logic [4:0] PostProcFlgM; // classify result + logic [`XLEN-1:0] FCvtIntResM; + logic [`FLEN-1:0] CmpFpResE; // compare result + logic [`XLEN-1:0] CmpIntResE; // compare result + logic CmpNVE; // compare invalid flag (Not Valid) + logic [`FLEN-1:0] SgnResE; // sign injection result + logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage + logic PreNVE, PreNVM; // selected flag that is ready in the memory stage + logic [`FLEN-1:0] FPUResultW; // final FP result being written to the FP register // other signals - logic FDivSqrtDoneE; // is divide done - logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit - logic load_preload; // enable for FF on fpdivsqrt - logic [63:0] AlignedSrcAE; // align SrcA to the floating point format - logic [63:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed + logic [`FLEN-1:0] AlignedSrcAE; // align SrcA to the floating point format + logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed + logic [`FLEN-1:0] BoxedOneE; // Zero value for Z for multiplication, with NaN boxing if needed // DECODE STAGE + ////////////////////////////////////////////////////////////////////////////////////////// + // ||||||||||| + // ||| ||| + // ||| ||| + // ||| ||| + // ||| ||| + // ||| ||| + // ||||||||||| + ////////////////////////////////////////////////////////////////////////////////////////// + // calculate FP control signals - fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW, .STATUS_FS, - .IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD, - .FIntResSelD, .FmtD, .FrmD, .FWriteIntD); + fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .InstrD, + .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE, + .reset, .clk, .IllegalFPUInstrD, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, .YEnForwardE, .ZEnForwardE, + .DivStartE, .FWriteIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE, + .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .Adr1E, .Adr2E, .Adr3E); // FP register file fregfile fregfile (.clk, .reset, .we4(FRegWriteW), @@ -146,146 +176,239 @@ module fpu ( .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); // D/E pipeline registers - flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E); - flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E); - flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E); - flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, - {Adr1E, Adr2E, Adr3E}); - flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE, - {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD}, - {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE}); + flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E); + flopenrc #(`FLEN) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E); + flopenrc #(`FLEN) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E); // EXECUTION STAGE + + ////////////////////////////////////////////////////////////////////////////////////////// + // |||||||||||| + // ||| + // ||| + // ||||||||| + // ||| + // ||| + // |||||||||||| + ////////////////////////////////////////////////////////////////////////////////////////// + // Hazard unit for FPU // - determines if any forwarding or stalls are needed - fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM, - .FStallD, .FForwardXE, .FForwardYE, .FForwardZE); + fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM, + .XEnE, .YEnE(YEnForwardE), .ZEnE(ZEnForwardE), .FStallD, .ForwardXE, .ForwardYE, .ForwardZE); // forwarding muxs - mux3 #(64) fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE); - mux3 #(64) fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE); - mux3 #(64) fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE); - mux3 #(64) fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, - {2'b0, {10{1'b1}}, 52'b0}, - {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, - FSrcYE); // Force Z to be 0 for multiply instructions + mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE); + mux3 #(`FLEN) fyemux (FRD2E, FPUResultW, PreFpResM, ForwardYE, PreYE); + mux3 #(`FLEN) fzemux (FRD3E, FPUResultW, PreFpResM, ForwardZE, PreZE); + + + generate + if(`FPSIZES == 1) assign BoxedOneE = {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}; + else if(`FPSIZES == 2) + mux2 #(`FLEN) fonemux ({{`FLEN-`LEN1{1'b1}}, 2'b0, {`NE1-1{1'b1}}, (`NF1)'(0)}, {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes + else if(`FPSIZES == 3 | `FPSIZES == 4) + mux4 #(`FLEN) fonemux ({{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}, + {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}, + {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}, + {2'b0, {`NE-1{1'b1}}, (`NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes + endgenerate + + + mux2 #(`FLEN) fyaddmux (PreYE, BoxedOneE, OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10), YE); // Force Z to be 0 for multiply instructions + // Force Z to be 0 for multiply instructions - mux2 #(64) fmulzeromux (64'hFFFFFFFF00000000, 64'b0, FmtE, BoxedZeroE); // NaN boxing for 32-bit zero - mux3 #(64) fzmulmux (FPreSrcZE, BoxedZeroE, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE); - + generate + if(`FPSIZES == 1) assign BoxedZeroE = 0; + else if(`FPSIZES == 2) + mux2 #(`FLEN) fmulzeromux ({{`FLEN-`LEN1{1'b1}}, {`LEN1{1'b0}}}, (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes + else if(`FPSIZES == 3 | `FPSIZES == 4) + mux4 #(`FLEN) fmulzeromux ({{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}, + {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}, + {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}, + (`FLEN)'(0), FmtE, BoxedZeroE); // NaN boxing zeroes + endgenerate + + mux3 #(`FLEN) fzmulmux (PreZE, BoxedZeroE, PreYE, {OpCtrlE[2]&OpCtrlE[1], OpCtrlE[2]&~OpCtrlE[1]}, ZE); + // unpack unit // - splits FP inputs into their various parts // - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity) - unpack unpack (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FmtE, - .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); + unpack unpack (.X(XE), .Y(YE), .Z(ZE), .Fmt(FmtE), .Xs(XsE), .Ys(YsE), .Zs(ZsE), + .Xe(XeE), .Ye(YeE), .Ze(ZeE), .Xm(XmE), .Ym(YmE), .Zm(ZmE), .YEn(YEnE), + .XNaN(XNaNE), .YNaN(YNaNE), .ZNaN(ZNaNE), .XSNaN(XSNaNE), .XEn(XEnE), + .YSNaN(YSNaNE), .ZSNaN(ZSNaNE), .XDenorm(XDenormE), .ZDenorm(ZDenormE), + .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .XInf(XInfE), .YInf(YInfE), + .ZEn(ZEnE), .ZInf(ZInfE), .XExpMax(XExpMaxE)); + + // fused multiply add + // - fadd/fsub + // - fmul + // - fmadd/fnmadd/fmsub/fnmsub + fma fma (.Xs(XsE), .Ys(YsE), .Zs(ZsE), + .Xe(XeE), .Ye(YeE), .Ze(ZeE), + .Xm(XmE), .Ym(YmE), .Zm(ZmE), + .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), + .OpCtrl(OpCtrlE), .Fmt(FmtE), + .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), + .Sm(SmE), .Pe(PeE), + .NegSum(NegSumE), .InvA(InvAE), .SCnt(SCntE), + .ZmSticky(ZmStickyE), .KillProd(KillProdE)); - // FMA - // - two stage FMA - // - execute stage - multiplication and addend shifting - // - memory stage - addition and rounding - // - handles FMA and multiply instructions - fma fma (.clk, .reset, .FlushM, .StallM, - .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, - .XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, - .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, - .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM, - .FOpCtrlE, - .FmtE, .FmtM, .FrmM, - .FMAFlgM, .FMAResM); - - // fpdivsqrt using Goldschmidt's iteration - flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E), - .clear(FDivSqrtDoneE), .en(load_preload), - .reset(reset), .clk(clk)); - flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E), - .clear(FDivSqrtDoneE), .en(load_preload), - .reset(reset), .clk(clk)); - flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}), - .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}), - .clear(FDivSqrtDoneE), .en(load_preload), - .reset(reset), .clk(clk)); - fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), - .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1), - .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload, - .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM)); - - // convert from signle to double and vice versa - cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE); - - // compare unit - // - computation is done in one stage - // - writes to FP file durring min/max instructions - // - other comparisons write a 1 or 0 to the integer register - fcmp fcmp (.FmtE, .FOpCtrlE, .XSgnE, .YSgnE, .XExpE, .YExpE, .XManE, .YManE, - .XZeroE, .YZeroE, .XNaNE, .YNaNE, .XSNaNE, .YSNaNE, .FSrcXE, .FSrcYE, .CmpNVE, .CmpResE); - - // sign injection unit - fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE, - .SgnResE); + // divide and squareroot + // - fdiv + // - fsqrt + // *** add other opperations + divsqrt divsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), + .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE, + .StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal + .EarlyTermShiftM, .QmM, .DivDone(DivDoneM)); + // compare + // - fmin/fmax + // - flt/fle/feq + fcmp fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE), + .Xm(XmE), .Ym(YmE), .XZero(XZeroE), .YZero(YZeroE), .XNaN(XNaNE), .YNaN(YNaNE), + .XSNaN(XSNaNE), .YSNaN(YSNaNE), .X(XE), .Y(YE), .CmpNV(CmpNVE), + .CmpFpRes(CmpFpResE), .CmpIntRes(CmpIntResE)); + // sign injection + // - fsgnj/fsgnjx/fsgnjn + fsgninj fsgninj(.OpCtrl(OpCtrlE[1:0]), .Xs(XsE), .Ys(YsE), .X(XE), .Fmt(FmtE), .SgnRes(SgnResE)); // classify - fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, - .XSNaNE, .ClassResE); + // - fclass + fclassify fclassify (.Xs(XsE), .XDenorm(XDenormE), .XZero(XZeroE), .XNaN(XNaNE), + .XInf(XInfE), .XSNaN(XSNaNE), .ClassRes(ClassResE)); - // Convert - fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE, - .CvtResE, .CvtFlgE); + // convert + // - fcvt.*.* + fcvt fcvt (.Xs(XsE), .Xe(XeE), .Xm(XmE), .Int(ForwardedSrcAE), .OpCtrl(OpCtrlE), + .ToInt(FWriteIntE), .XZero(XZeroE), .XDenorm(XDenormE), .Fmt(FmtE), .Ce(CeE), + .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CsE), .IntZero(IntZeroE), + .LzcIn(CvtLzcInE)); // data to be stored in memory - to IEU // - FP uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - assign FWriteDataE = FSrcYE[`XLEN-1:0]; + + if(`LLEN==`XLEN) + assign FWriteDataE = {{`XLEN-`FLEN{1'b1}}, YE}; + else begin + logic [`FLEN-1:0] WriteDataE; + if(`FPSIZES == 1) assign WriteDataE = YE; + else if(`FPSIZES == 2) assign WriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}}; + else + always_comb + case(FmtE) + `Q_FMT: WriteDataE = YE; + `D_FMT: WriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}}; + `S_FMT: WriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}}; + `H_FMT: WriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}}; + endcase + flopenrc #(`FLEN) EMWriteDataReg (clk, reset, FlushM, ~StallM, WriteDataE, FWriteDataM); + end - // Align SrcA to MSB when single precicion - mux2 #(64) SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); + // NaN Block SrcA + generate + if(`FPSIZES == 1) assign AlignedSrcAE = {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}; + else if(`FPSIZES == 2) + mux2 #(`FLEN) SrcAMux ({{`FLEN-`LEN1{1'b1}}, ForwardedSrcAE[`LEN1-1:0]}, {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); + else if(`FPSIZES == 3 | `FPSIZES == 4) + mux4 #(`FLEN) SrcAMux ({{`FLEN-`S_LEN{1'b1}}, ForwardedSrcAE[`S_LEN-1:0]}, + {{`FLEN-`D_LEN{1'b1}}, ForwardedSrcAE[`D_LEN-1:0]}, + {{`FLEN-`H_LEN{1'b1}}, ForwardedSrcAE[`H_LEN-1:0]}, + {{`FLEN-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes + endgenerate // select a result that may be written to the FP register - mux5 #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE); - mux5 #(5) FFlgMux(5'b0, 5'b0, {CmpNVE, 4'b0}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE); + mux3 #(`FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE); + assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE); // select the result that may be written to the integer register - to IEU - mux4 #(`XLEN) IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], - CvtResE[`XLEN-1:0], FIntResSelE, FIntResE); + + logic [`FLEN-1:0] SgnExtXE; + generate + if(`FPSIZES == 1) + assign SgnExtXE = XE; + else if(`FPSIZES == 2) + mux2 #(`FLEN) sgnextmux ({{`FLEN-`LEN1{XsE}}, XE[`LEN1-1:0]}, XE, FmtE, SgnExtXE); + else if(`FPSIZES == 3 | `FPSIZES == 4) + mux4 #(`FLEN) fmulzeromux ({{`FLEN-`H_LEN{XsE}}, XE[`H_LEN-1:0]}, + {{`FLEN-`S_LEN{XsE}}, XE[`S_LEN-1:0]}, + {{`FLEN-`D_LEN{XsE}}, XE[`D_LEN-1:0]}, + XE, FmtE, SgnExtXE); // NaN boxing zeroes + endgenerate + if (`FLEN>`XLEN) + assign IntSrcXE = SgnExtXE[`XLEN-1:0]; + else + assign IntSrcXE = {{`XLEN-`FLEN{XsE}}, SgnExtXE}; + + mux3 #(`XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE); + // *** DH 5/25/22: CvtRes will move to mem stage. Premux in execute to save area, then make sure stalls are ok + // *** make sure the fpu matches the chapter diagram // E/M pipe registers - // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM); - flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM}); - flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM}); - flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM}); - flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, - {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE}, - {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM}); - flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); - flopenrc #(5) EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM); - flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM); - flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM, - {FRegWriteE, FResultSelE, FrmE, FmtE}, - {FRegWriteM, FResultSelM, FrmM, FmtM}); + // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, XE, FSrcXM); + flopenrc #(`NF+2) EMFpReg2 (clk, reset, FlushM, ~StallM, {XsE,XmE}, {XsM,XmM}); + flopenrc #(`NF+2) EMFpReg3 (clk, reset, FlushM, ~StallM, {YsE,YmE}, {YsM,YmM}); + flopenrc #(`FLEN) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZeE,ZmE}, {ZeM,ZmM}); + flopenrc #(`XLEN) EMFpReg6 (clk, reset, FlushM, ~StallM, FIntResE, FIntResM); + flopenrc #(`FLEN) EMFpReg7 (clk, reset, FlushM, ~StallM, PreFpResE, PreFpResM); + flopenrc #(13) EMFpReg5 (clk, reset, FlushM, ~StallM, + {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE, ZDenormE}, + {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM}); + flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM); + flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM); + flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM); + flopenrc #($clog2(3*`NF+7)+9+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, + {ZmStickyE, KillProdE, InvAE, SCntE, NegSumE, AsE, PsE, SsE, SeE}, + {ZmStickyM, KillProdM, InvAM, SCntM, NegSumM, AsM, PsM, SsM, SeM}); + flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, + {CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE}, + {CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM}); // BEGIN MEMORY STAGE + ////////////////////////////////////////////////////////////////////////////////////////// + // ||| ||| + // |||||| |||||| + // ||| ||| ||| ||| + // ||| ||||| ||| + // ||| ||| ||| + // ||| ||| + // ||| ||| + ////////////////////////////////////////////////////////////////////////////////////////// + + assign FpLoadStoreM = FResSelM[1]; + + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .DivEarlyTermShift(EarlyTermShiftM), + .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), + .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM), + .FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), + .CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM), + .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM)); + // FPU flag selection - to privileged - mux4 #(5) FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM); + mux2 #(5) FPUFlgMux ({PreNVM&~FResSelM[1], 4'b0}, PostProcFlgM, ~FResSelM[1]&FResSelM[0], SetFflagsM); + mux2 #(`FLEN) FPUResMux (PreFpResM, PostProcResM, FResSelM[0], FpResM); // M/W pipe registers - flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); - flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); - flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW); - flopenrc #(4) MWCtrlReg(clk, reset, FlushW, ~StallW, - {FRegWriteM, FResultSelM, FmtM}, - {FRegWriteW, FResultSelW, FmtW}); + flopenrc #(`FLEN) MWRegFp(clk, reset, FlushW, ~StallW, FpResM, FpResW); + flopenrc #(`XLEN) MWRegInt(clk, reset, FlushW, ~StallW, FCvtIntResM, FCvtIntResW); // BEGIN WRITEBACK STAGE - // put ReadData into NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - // - for load instruction - mux2 #(64) ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW); + ////////////////////////////////////////////////////////////////////////////////////////// + // ||| ||| + // ||| ||| + // ||| ||| ||| + // ||| ||||| ||| + // ||| ||| ||| ||| + // |||||| |||||| + // ||| ||| + ////////////////////////////////////////////////////////////////////////////////////////// // select the result to be written to the FP register - mux4 #(64) FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW); + mux2 #(`FLEN) FPUResultMux (FpResW, ReadDataW, FResSelW[1], FPUResultW); + endmodule // fpu diff --git a/pipelined/src/fpu/fpudivsqrtrecur.sv b/pipelined/src/fpu/fpudivsqrtrecur.sv deleted file mode 100644 index 62a441367..000000000 --- a/pipelined/src/fpu/fpudivsqrtrecur.sv +++ /dev/null @@ -1,74 +0,0 @@ -/////////////////////////////////////////// -// -// Written: David Harris -// Modified: 11 September 2021 -// -// Purpose: Recurrence-based SRT Division and Square Root -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module fpudivsqrtrecur ( - input logic clk, - input logic reset, - input logic FlushM, // flush the memory stage - input logic StallM, // stall memory stage - input logic FDivSqrtStart, // start a computation - input logic FmtE, // precision 1 = double 0 = single - input logic FDivE, FSqrtE, - input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude - input logic XSgnE, YSgnE, // input signs - execute stage - input logic [`NE-1:0] XExpE, YExpE, // input exponents - execute stage - input logic [`NF:0] XManE, YManE, // input mantissa - execute stage - input logic XDenormE, YDenormE, // is denorm - input logic XZeroE, YZeroE, // is zero - execute stage - input logic XNaNE, YNaNE, // is NaN - input logic XSNaNE, YSNaNE, // is signaling NaN - input logic XInfE, YInfE, ZInfE, // is infinity - input logic [10:0] BiasE, // bias (max exponent/2) ***parameterize in unpacking unit - output logic FDviSqrtBusy, FDivSqrtDone, //currently occpied, or done with operation - output logic [`FLEN-1:0] FDivSqrtResM, // result - output logic [4:0] FDivSqrtFlgM // flags - ); - - logic FDivSqrtResSgn; - logic [`FLEN-1:0] FDivSqrtRecurRes; - - // Radix-2 SRT Division and Square Root - - // Special Cases - // *** shift to handle denorms in hardware - - assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs - - always_comb begin - if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one - else if (FDivE & YZeroE | XInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(1), (`NF)'(0)}; // infinity - else if (FDivE & YInfE) FDivSqrtResM = {FDivSqrtResSgn, (`NE)'(0), (`NF)'(0)}; // zero - else FDivSqrtResM = FDivSqrtRecurRes; - end - - // *** handle early termination in the special cases - // *** handle signaling NANs -endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fpudivsqrtrecurcore.sv b/pipelined/src/fpu/fpudivsqrtrecurcore.sv deleted file mode 100644 index b13ef0da2..000000000 --- a/pipelined/src/fpu/fpudivsqrtrecurcore.sv +++ /dev/null @@ -1,105 +0,0 @@ -/////////////////////////////////////////// -// -// Written: David Harris -// Modified: 11 September 2021 -// -// Purpose: Recurrence-based SRT Division and Square Root -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -// Bit counts: -// Inputs are originally normalized floating point numbers with NF fractional bits and a leading 1 integer bit -// x is right shifted by up to 2 to be in the range of 1/4 <= x < 1/2 for divide, 1/4 <= x < 1 for sqrt -// Hence, x now has NF+2 fractional bits and 0 integer bits -// d is right shifted by 1 to be in the range of 1/2 <= d < 1. It thus has NF+1 fractional bits and 0 integer bits -// q is eventually in the range of 1/4 < q < 1 and hence needs NF+2 bits to keep NF bits when normalized, plus some*** more bits for rounding -// The partial - -/* -module fpudivsqrtrecurcore ( - input logic clk, - input logic reset, - input logic start, // start a computation - input logic busy, // computation running - input logic fmt, // precision 1 = double 0 = single - input logic [`NF+1:0] x, // in range 1/4 <= x < 1/2 for divide, 1/4 <=x < 1 for sqrt - input logic [`NF+1:0] din, // in range 1/2 <= d < 1 for divide - input logic FDiv, FSqrt, // *** not yet used - output logic [`FLEN-1:0] FDivSqrtRecurRes // result - ); - - assign FDivSqrtRecurRes = 0; - - logic [***] d, ws, wsout, wsnext, wc, wcout, wcnext; - logic [1:0] q; // 00 = 0, 01 = 1, 10 = -1 - - // Radix-2 SRT Division - - // registers for divisor and partial remainder - flopen #(NF+1) dreg(clk, start, din, d); - mux2 #(NF+1) wsmux(wsout, x, start, wsnext); - flopen #(NF+1) wsreg(clk, busy, wsnext, ws); - mux2 #(NF+1) wcmux(wcout, 0, start, wcnext); - flopen #(NF+1) wcreg(clk, busy, wcnext, wc); - - // quotient selection - qsel qsel(ws[***4bits], wc[***], q); - - // partial remainder update - always_comb begin // select -d * q to add to partial remainder - if (q[1]) dq = d; - else if (q[0]) dq = ~d; - else dq = 0; - end - csa #(***) csa(ws, wc, dq, q[1], wsout, wcout); - - -endmodule -*/ - -/* -module csa #(parameter N=4) ( - input logic [N-1:0] sin, cin, ain, - input logic carry, - output logic [N-1:0] sum, cout -); - - logic [N-1:0] c; - - assign c = {cin[N-2:0], carry}; // shift carries left and inject optional 1 into lsb - assign sum = sin ^ ain ^ c; - assign cout = sin & ain | sin & c | ain & c; -endmodule -*/ - -module qsel( // radix 2 SRT division quotient selection - input logic [3:0] wc, ws, - output logic [1:0] q -); - -endmodule - - - diff --git a/pipelined/src/fpu/fregfile.sv b/pipelined/src/fpu/fregfile.sv index 2d54038de..00c89ff56 100644 --- a/pipelined/src/fpu/fregfile.sv +++ b/pipelined/src/fpu/fregfile.sv @@ -33,10 +33,10 @@ module fregfile ( input logic clk, reset, input logic we4, input logic [4:0] a1, a2, a3, a4, - input logic [63:0] wd4, - output logic [63:0] rd1, rd2, rd3); + input logic [`FLEN-1:0] wd4, + output logic [`FLEN-1:0] rd1, rd2, rd3); - logic [63:0] rf[31:0]; + logic [`FLEN-1:0] rf[31:0]; integer i; // three ported register file diff --git a/pipelined/src/fpu/fsgn.sv b/pipelined/src/fpu/fsgn.sv deleted file mode 100755 index efe6ece34..000000000 --- a/pipelined/src/fpu/fsgn.sv +++ /dev/null @@ -1,30 +0,0 @@ -//performs the fsgnj/fsgnjn/fsgnjx RISCV instructions - -module fsgn ( - input logic XSgnE, YSgnE, // X and Y sign bits - input logic [63:0] FSrcXE, // X - input logic XExpMaxE, // max possible exponent (all ones) - input logic FmtE, // precision 1 = double 0 = single - input logic [1:0] SgnOpCodeE, // operation control - output logic [63:0] SgnResE // result - ); - - logic ResSgn; - - //op code designation: - // - //00 - fsgnj - directly copy over sign value of FSrcYE - //01 - fsgnjn - negate sign value of FSrcYE - //10 - fsgnjx - XOR sign values of FSrcXE & FSrcYE - // - - // calculate the result's sign - assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]); - - // format final result based on precision - // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]}; - - -endmodule diff --git a/pipelined/src/fpu/fsgninj.sv b/pipelined/src/fpu/fsgninj.sv new file mode 100755 index 000000000..a5b7e7742 --- /dev/null +++ b/pipelined/src/fpu/fsgninj.sv @@ -0,0 +1,84 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 6/23/2021 +// +// Purpose: FPU Sign Injection instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module fsgninj ( + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result +); + + logic ResSgn; + + // OpCtrl: + // 00 - fsgnj - directly copy over sign value of Y + // 01 - fsgnjn - negate sign value of Y + // 10 - fsgnjx - XOR sign values of X and Y + + // calculate the result's sign + assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys; + + // format final result based on precision + // - uses NaN-blocking format + // - if there are any unsused bits the most significant bits are filled with 1s + + if (`FPSIZES == 1) + assign SgnRes = {ResSgn, X[`FLEN-2:0]}; + + else if (`FPSIZES == 2) + assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; + + else if (`FPSIZES == 3) begin + logic [2:0] SgnBits; + always_comb + case (Fmt) + `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT2: SgnBits = {2'b11, ResSgn}; + default: SgnBits = {3{1'bx}}; + endcase + assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; + + + end else if (`FPSIZES == 4) begin + logic [3:0] SgnBits; + always_comb + case (Fmt) + `Q_FMT: SgnBits = {ResSgn, X[`D_LEN-1], X[`S_LEN-1], X[`H_LEN-1]}; + `D_FMT: SgnBits = {1'b1, ResSgn, X[`S_LEN-1], X[`H_LEN-1]}; + `S_FMT: SgnBits = {2'b11, ResSgn, X[`H_LEN-1]}; + `H_FMT: SgnBits = {3'b111, ResSgn}; + endcase + assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]}; + end + +endmodule diff --git a/pipelined/src/fpu/fsm_fpdiv.sv b/pipelined/src/fpu/fsm_fpdiv.sv deleted file mode 100755 index 37e6fe2ed..000000000 --- a/pipelined/src/fpu/fsm_fpdiv.sv +++ /dev/null @@ -1,537 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 9/28/2021 -// -// Purpose: FSM for floating point divider/square root unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module fsm_fpdiv ( - input logic clk, - input logic reset, - input logic start, - input logic op_type, - output logic done, - output logic load_rega, - output logic load_regb, - output logic load_regc, - output logic load_regd, - output logic load_regr, - output logic load_regs, - output logic [2:0] sel_muxa, - output logic [2:0] sel_muxb, - output logic sel_muxr, - output logic divBusy - ); - - typedef enum logic [4:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, - S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, - S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, - S30} statetype; - - statetype current_state, next_state; - - always @(posedge clk) - begin - if (reset == 1'b1) - current_state = S0; - else - current_state = next_state; - end - - always_comb - begin - case(current_state) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - else if (start==1'b1 & op_type==1'b0) - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S1; - end // if (start==1'b1 & op_type==1'b0) - else if (start==1'b1 & op_type==1'b1) - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S13; - end - else - begin - done = 1'b0; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - end // case: S0 - S1: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S2; - end - S2: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S3; - end - S3: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S4; - end - S4: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S5; - end - S5: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; // add - next_state = S6; - end - S6: // iteration 3 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S8; - end - S7: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S8; - end // case: S7 - S8: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S9; - end - S9: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - next_state = S10; - end - S10: // done - begin - done = 1'b1; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S11; - end // case: S10 - S11: // done - begin - done = 1'b0; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - S13: // start of sqrt path - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S14; - end - S14: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - next_state = S15; - end - S15: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S16; - end - S16: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S17; - end - S17: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S18; - end - S18: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S19; - end - S19: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S20; - end - S20: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S21; - end - S21: // iteration 3 - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S22; - end - S22: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S23; - end - S23: - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S24; - end - S24: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S25; - end - S25: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - next_state = S26; - end - S26: // done - begin - done = 1'b1; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S27; - end // case: S26 - S27: // done - begin - done = 1'b0; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - default: - begin - done = 1'b0; - divBusy = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - endcase // case(current_state) - end // always @ (current_state or X) - -endmodule // fsm diff --git a/pipelined/src/fpu/fsm_fpdiv_pipe.sv b/pipelined/src/fpu/fsm_fpdiv_pipe.sv deleted file mode 100755 index 33d270b89..000000000 --- a/pipelined/src/fpu/fsm_fpdiv_pipe.sv +++ /dev/null @@ -1,1330 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 9/28/2021 -// -// Purpose: FSM for floating point divider/square root unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module fsm_fpdiv_pipe ( - input logic clk, - input logic reset, - input logic start, - input logic op_type, - input logic P, - output logic done, - output logic load_preload, - output logic load_rega, - output logic load_regb, - output logic load_regc, - output logic load_regd, - output logic load_regr, - output logic load_regs, - output logic load_regp, - output logic [2:0] sel_muxa, - output logic [2:0] sel_muxb, - output logic sel_muxr, - output logic divBusy - ); - - // div64 : S1-S14 (14 cycles) - // sqrt64 : S15-S35 (21 cycles) - // div32: S36-S47 (12 cycles) - // sqrt32 : S48-S64 (17 cycles) - typedef enum logic [6:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, - S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, - S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, - S30, S31, S32, S33, S34, S35, S36, S37, S38, S39, - S40, S41, S42, S43, S44, S45, S46, S47, S48, S49, - S50, S51, S52, S53, S54, S55, S56, S57, S58, S59, - S60, S61, S62, S63, S64, S65, S66} statetype; - - statetype current_state, next_state; - - always @(posedge clk) - begin - if (reset == 1'b1) - current_state <= S0; - else - current_state <= next_state; - end - - always @(*) - begin - case(current_state) - S0: // iteration 0 - begin - if (start==1'b0) - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end // if (start==1'b0) - else - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b1; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S66; - end - end // case: S0 - S66: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S65; - end // if (start==1'b0) - S65: - begin - if (op_type==1'b0 & P==1'b0) - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S1; - end - else if (op_type==1'b0 & P==1'b1) - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S36; - end - else if (op_type==1'b1 & P==1'b0) - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S15; - end - else if (op_type==1'b1 & P==1'b1) - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S48; - end - else - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - end // case: S0 - // div64 - S1: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S2; - end // case: S1 - S2: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S3; - end - S3: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S4; - end - S4: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S5; - end - S5: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; // add - next_state = S6; - end - S6: // iteration 3 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S7; - end - S7: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S8; - end // case: S7 - S8: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S9; - end // case: S7 - S9: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S10; - end // case: S9 - S10: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - next_state = S11; - end - S11: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - next_state = S12; - end // case: S11 - S12: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S13; - end - S13: - begin - done = 1'b1; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S14; - end - S14: - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - // sqrt64 - S15: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S16; - end - S16: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - next_state = S17; - end - S17: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S18; - end - S18: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S19; - end - S19: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S20; - end - S20: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S21; - end - S21: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S22; - end - S22: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S23; - end // case: S18 - S23: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S24; - end - S24: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S25; - end - S25: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S26; - end - S26: // iteration 3 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S27; - end // case: S21 - S27: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S28; - end - S28: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S29; - end - S29: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S30; - end // case: S23 - S30: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S31; - end - S31: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - next_state = S32; - end // case: S25 - S32: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - next_state = S33; - end - S33: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S34; - end - S34: // done - begin - done = 1'b1; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S35; - end - S35: - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - // div32 - S36: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b001; - sel_muxb = 3'b001; - sel_muxr = 1'b0; - next_state = S37; - end // case: S1 - S37: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S38; - end - S38: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S39; - end - S39: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S40; - end - S40: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S41; - end - S41: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S42; - end - S42: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S43; - end // case: S9 - S43: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - next_state = S44; - end - S44: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b1; - next_state = S45; - end // case: S11 - S45: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S46; - end - S46: // done - begin - done = 1'b1; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S47; - end - S47: - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - // sqrt32 - S48: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S49; - end - S49: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b001; - sel_muxb = 3'b100; - sel_muxr = 1'b0; - next_state = S50; - end - S50: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b010; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S51; - end - S51: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S52; - end - S52: // iteration 1 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S53; - end - S53: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S54; - end - S54: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S55; - end - S55: // iteration 2 - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b1; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S56; - end // case: S18 - S56: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S57; - end - S57: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b1; - load_regb = 1'b0; - load_regc = 1'b1; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b100; - sel_muxb = 3'b010; - sel_muxr = 1'b0; - next_state = S58; - end - S58: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b1; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b011; - sel_muxr = 1'b0; - next_state = S59; - end - S59: // q,qm,qp - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b1; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S60; - end - S60: // rem - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - next_state = S61; - end // case: S25 - S61: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b1; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b011; - sel_muxb = 3'b110; - sel_muxr = 1'b1; - next_state = S62; - end // case: S34 - S62: - begin - done = 1'b0; - divBusy = 1'b1; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S63; - end - S63: // done - begin - done = 1'b1; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b1; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S64; - end // case: S34 - S64: - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - default: - begin - done = 1'b0; - divBusy = 1'b0; - load_preload = 1'b0; - load_rega = 1'b0; - load_regb = 1'b0; - load_regc = 1'b0; - load_regd = 1'b0; - load_regr = 1'b0; - load_regs = 1'b0; - load_regp = 1'b0; - sel_muxa = 3'b000; - sel_muxb = 3'b000; - sel_muxr = 1'b0; - next_state = S0; - end - endcase // case(current_state) - end // always @ (current_state or X) - -endmodule // fsm diff --git a/pipelined/src/fpu/lzd_denorm.sv b/pipelined/src/fpu/lzd_denorm.sv deleted file mode 100755 index a91b0920e..000000000 --- a/pipelined/src/fpu/lzd_denorm.sv +++ /dev/null @@ -1,171 +0,0 @@ -// module lz2 (P, V, B0, B1); - -// input B0; -// input B1; - -// output P; -// output V; - -// assign V = B0 | B1; -// assign P = B0 & ~B1; - -// endmodule // lz2 - -// Note: This module is not made out of two lz2's - why not? (MJS) - -// module lz4 (ZP, ZV, B0, B1, V0, V1); - -// input B0; -// input B1; -// input V0; -// input V1; - -// output [1:0] ZP; -// output ZV; - -// assign ZP[0] = V0 ? B0 : B1; -// assign ZP[1] = ~V0; -// assign ZV = V0 | V1; - -// endmodule // lz4 - -// // Note: This module is not made out of two lz4's - why not? (MJS) - -// module lz8 (ZP, ZV, B); - -// input [7:0] B; - -// wire s1p0; -// wire s1v0; -// wire s1p1; -// wire s1v1; -// wire s2p0; -// wire s2v0; -// wire s2p1; -// wire s2v1; -// wire [1:0] ZPa; -// wire [1:0] ZPb; -// wire ZVa; -// wire ZVb; - -// output [2:0] ZP; -// output ZV; - -// lz2 l1(s1p0, s1v0, B[2], B[3]); -// lz2 l2(s1p1, s1v1, B[0], B[1]); -// lz4 l3(ZPa, ZVa, s1p0, s1p1, s1v0, s1v1); - -// lz2 l4(s2p0, s2v0, B[6], B[7]); -// lz2 l5(s2p1, s2v1, B[4], B[5]); -// lz4 l6(ZPb, ZVb, s2p0, s2p1, s2v0, s2v1); - -// assign ZP[1:0] = ZVb ? ZPb : ZPa; -// assign ZP[2] = ~ZVb; -// assign ZV = ZVa | ZVb; - -// endmodule // lz8 - -// module lz16 (ZP, ZV, B); - -// input [15:0] B; - -// wire [2:0] ZPa; -// wire [2:0] ZPb; -// wire ZVa; -// wire ZVb; - -// output [3:0] ZP; -// output ZV; - -// lz8 l1(ZPa, ZVa, B[7:0]); -// lz8 l2(ZPb, ZVb, B[15:8]); - -// assign ZP[2:0] = ZVb ? ZPb : ZPa; -// assign ZP[3] = ~ZVb; -// assign ZV = ZVa | ZVb; - -// endmodule // lz16 - -// module lz32 (ZP, ZV, B); - -// input [31:0] B; - -// wire [3:0] ZPa; -// wire [3:0] ZPb; -// wire ZVa; -// wire ZVb; - -// output [4:0] ZP; -// output ZV; - -// lz16 l1(ZPa, ZVa, B[15:0]); -// lz16 l2(ZPb, ZVb, B[31:16]); - -// assign ZP[3:0] = ZVb ? ZPb : ZPa; -// assign ZP[4] = ~ZVb; -// assign ZV = ZVa | ZVb; - -// endmodule // lz32 - -// // This module returns the number of leading zeros ZP in the 64-bit -// // number B. If there are no ones in B, then ZP and ZV are both 0. - -// module lz64 (ZP, ZV, B); - -// input [63:0] B; - -// wire [4:0] ZPa; -// wire [4:0] ZPb; -// wire ZVa; -// wire ZVb; - -// output [5:0] ZP; -// output ZV; - -// lz32 l1(ZPa, ZVa, B[31:0]); -// lz32 l2(ZPb, ZVb, B[63:32]); - -// assign ZV = ZVa | ZVb; -// assign ZP[4:0] = (ZVb ? ZPb : ZPa) & {5{ZV}}; -// assign ZP[5] = ~ZVb & ZV; - -// endmodule // lz64 - -// This module returns the number of leading zeros ZP in the 52-bit -// number B. If there are no ones in B, then ZP and ZV are both 0. - -module lz52 (ZP, ZV, B); - - input [51:0] B; - - wire [4:0] ZP_32; - wire [3:0] ZP_16; - wire [1:0] ZP_4; - wire ZV_32; - wire ZV_16; - wire ZV_4; - - wire ZP_2_1; - wire ZP_2_2; - wire ZV_2_1; - wire ZV_2_2; - - output [5:0] ZP; - output ZV; - - lz32 l1 (ZP_32, ZV_32, B[51:20]); - lz16 l2 (ZP_16, ZV_16, B[19:4]); - - lz2 l3_1 (ZP_2_1, ZV_2_1, B[3], B[2]); - lz2 l3_2 (ZP_2_2, ZV_2_2, B[1], B[0]); - lz4 l3_final (ZP_4, ZV_4, ZP_2_1, ZP_2_2, ZV_2_1, ZV_2_2); - - assign ZV = ZV_32 | ZV_16 | ZV_4; - assign ZP[5] = ~ZV_32; - assign ZP[4] = ZV_32 ? ZP_32[4] : ~ZV_16; - assign ZP[3:2] = ZV_32 ? ZP_32[3:2] : (ZV_16 ? ZP_16[3:2] : 2'b0); - assign ZP[1:0] = ZV_32 ? ZP_32[1:0] : (ZV_16 ? ZP_16[1:0] : ZP_4); - -endmodule // lz52 - - diff --git a/pipelined/src/fpu/negateintres.sv b/pipelined/src/fpu/negateintres.sv new file mode 100644 index 000000000..7a696b379 --- /dev/null +++ b/pipelined/src/fpu/negateintres.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Negate integer result +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module negateintres( + input logic Xs, + input logic [`NORMSHIFTSZ-1:0] Shifted, + input logic Signed, + input logic Int64, + input logic Plus1, + output logic [1:0] CvtNegResMsbs, + output logic [`XLEN+1:0] CvtNegRes +); + + + // round and negate the positive res if needed + assign CvtNegRes = Xs ? -({2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}) : {2'b0, Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`XLEN]}+{{`XLEN+1{1'b0}}, Plus1}; + + always_comb + if(Signed) + if(Int64) CvtNegResMsbs = CvtNegRes[`XLEN:`XLEN-1]; + else CvtNegResMsbs = CvtNegRes[32:31]; + else + if(Int64) CvtNegResMsbs = CvtNegRes[`XLEN+1:`XLEN]; + else CvtNegResMsbs = CvtNegRes[33:32]; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/normshift.sv b/pipelined/src/fpu/normshift.sv new file mode 100644 index 000000000..f382eed37 --- /dev/null +++ b/pipelined/src/fpu/normshift.sv @@ -0,0 +1,74 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: normalization shifter +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + + + // convert shift + // fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp + // process: + // - start - CalcExp = 1 + XExp - Largest Bias + // | `XLEN zeros | Mantissa | 0's if nessisary | + // + // - shift left 1 (1) + // | `XLEN-1 zeros |bit| frac | 0's if nessisary | + // . <- binary point + // + // - shift left till unbiased exponent is 0 (XExp - Largest Bias) + // | 0's | Mantissa | 0's if nessisary | + // | keep | + // + // fp -> fp: + // - if result is denormalized or underflowed: + // | `NF-1 zeros | Mantissa | 0's if nessisary | << NF+CalcExp-1 + // process: + // - start + // | mantissa | 0's | + // + // - shift right by NF-1 (NF-1) + // | `NF-1 zeros | mantissa | 0's | + // + // - shift left by CalcExp = XExp - Largest bias + new bias + // | 0's | mantissa | 0's | + // | keep | + // + // - if the input is denormalized: + // | lzcIn | 0's if nessisary | << ZeroCnt+1 + // - plus 1 to shift out the first 1 + // + // int -> fp: | lzcIn | 0's if nessisary | << ZeroCnt+1 + // - plus 1 to shift out the first 1 + +module normshift( + input logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt, // normalization shift count + input logic [`NORMSHIFTSZ-1:0] ShiftIn, // is the sum zero + output logic [`NORMSHIFTSZ-1:0] Shifted // is the sum zero +); + assign Shifted = ShiftIn << ShiftAmt; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/otfc.sv b/pipelined/src/fpu/otfc.sv new file mode 100644 index 000000000..b2d1310ff --- /dev/null +++ b/pipelined/src/fpu/otfc.sv @@ -0,0 +1,177 @@ +/////////////////////////////////////////// +// otfc.sv +// +// Written: me@KatherineParry.com, cturek@hmc.edu +// Modified:7/14/2022 +// +// Purpose: On the fly conversion +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module otfc2 ( + input logic qp, qz, + input logic [`DIVb:0] Q, QM, + output logic [`DIVb:0] QNext, QMNext +); + // The on-the-fly converter transfers the quotient + // bits to the quotient as they come. + // Use this otfc for division only. + logic [`DIVb-1:0] QR, QMR; + + assign QR = Q[`DIVb-1:0]; + assign QMR = QM[`DIVb-1:0]; // Shifted Q and QM + + always_comb begin + if (qp) begin + QNext = {QR, 1'b1}; + QMNext = {QR, 1'b0}; + end else if (qz) begin + QNext = {QR, 1'b0}; + QMNext = {QMR, 1'b1}; + end else begin // If qp and qz are not true, then qn is + QNext = {QMR, 1'b1}; + QMNext = {QMR, 1'b0}; + end + end + +endmodule + +/////////////////////////////// +// Square Root OTFC, Radix 2 // +/////////////////////////////// +module sotfc2( + input logic sp, sz, + input logic [`DIVb-1:0] C, + input logic [`DIVb:0] S, SM, + output logic [`DIVb:0] SNext, SMNext +); + // The on-the-fly converter transfers the square root + // bits to the quotient as they come. + // Use this otfc for division and square root. + logic [`DIVb:0] CExt; + + assign CExt = {1'b1, C}; + + always_comb begin + if (sp) begin + SNext = S | (CExt & ~(CExt << 1)); + SMNext = S; + end else if (sz) begin + SNext = S; + SMNext = SM | (CExt & ~(CExt << 1)); + end else begin // If sp and sz are not true, then sn is + SNext = SM | (CExt & ~(CExt << 1)); + SMNext = SM; + end + end + +endmodule + +module otfc4 ( + input logic [3:0] q, + input logic [`DIVb:0] Q, QM, + output logic [`DIVb:0] QNext, QMNext +); + + // The on-the-fly converter transfers the quotient + // bits to the quotient as they come. + // + // This code follows the psuedocode presented in the + // floating point chapter of the book. Right now, + // it is written for Radix-4 division. + // + // QM is Q-1. It allows us to write negative bits + // without using a costly CPA. + + // QR and QMR are the shifted versions of Q and QM. + // They are treated as [N-1:r] size signals, and + // discard the r most significant bits of Q and QM. + logic [`DIVb-2:0] QR, QMR; + + // shift Q (quotent) and QM (quotent-1) + // if q = 2 Q = {Q, 10} QM = {Q, 01} + // else if q = 1 Q = {Q, 01} QM = {Q, 00} + // else if q = 0 Q = {Q, 00} QM = {QM, 11} + // else if q = -1 Q = {QM, 11} QM = {QM, 10} + // else if q = -2 Q = {QM, 10} QM = {QM, 01} + + assign QR = Q[`DIVb-2:0]; + assign QMR = QM[`DIVb-2:0]; // Shifted Q and QM + always_comb begin + if (q[3]) begin // +2 + QNext = {QR, 2'b10}; + QMNext = {QR, 2'b01}; + end else if (q[2]) begin // +1 + QNext = {QR, 2'b01}; + QMNext = {QR, 2'b00}; + end else if (q[1]) begin // -1 + QNext = {QMR, 2'b11}; + QMNext = {QMR, 2'b10}; + end else if (q[0]) begin // -2 + QNext = {QMR, 2'b10}; + QMNext = {QMR, 2'b01}; + end else begin // 0 + QNext = {QR, 2'b00}; + QMNext = {QMR, 2'b11}; + end + end + // Final Qmeint is in the range [.5, 2) + +endmodule + +/////////////////////////////// +// Square Root OTFC, Radix 4 // +/////////////////////////////// +module sotfc4( + input logic [3:0] s, + input logic Sqrt, + input logic [`DIVb+3:0] S, SM, + input logic [`DIVb+3:0] C, + output logic [`DIVb+3:0] SNext, SMNext +); + // The on-the-fly converter transfers the square root + // bits to the quotient as they come. + // Use this otfc for division and square root. + + always_comb begin + if (s[3]) begin + SNext = S | ((C << 1)&~(C << 2)); + SMNext = S | (C&~(C << 1)); + end else if (s[2]) begin + SNext = S | (C&~(C << 1)); + SMNext = S; + end else if (s[1]) begin + SNext = SM | (C&~(C << 2)); + SMNext = SM | ((C << 1)&~(C << 2)); + end else if (s[0]) begin + SNext = SM | ((C << 1)&~(C << 2)); + SMNext = SM | (C&~(C << 1)); + end else begin // If sp and sn are not true, then sz is + SNext = S; + SMNext = SM | (C & ~(C << 2)); + end + end + +endmodule diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv new file mode 100644 index 000000000..f96101443 --- /dev/null +++ b/pipelined/src/fpu/postprocess.sv @@ -0,0 +1,237 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Post-Processing +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module postprocess ( + // general signals + input logic Xs, Ys, // input signs + input logic [`NE-1:0] Ze, // input exponents + input logic [`NF:0] Xm, Ym, Zm, // input mantissas + input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single + input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic XZero, YZero, ZZero, // inputs are zero + input logic XInf, YInf, ZInf, // inputs are infinity + input logic XNaN, YNaN, ZNaN, // inputs are NaN + input logic XSNaN, YSNaN, ZSNaN, // inputs are signaling NaNs + input logic ZDenorm, // is the original precision denormalized + input logic [1:0] PostProcSel, // select result to be written to fp register + //fma signals + input logic FmaAs, // the modified Z sign - depends on instruction + input logic FmaPs, // the product's sign + input logic [`NE+1:0] FmaSe, + input logic [`NE+1:0] FmaPe, // Product exponent + input logic [3*`NF+5:0] FmaSm, // the positive sum + input logic FmaZmS, // sticky bit that is calculated during alignment + input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter + input logic FmaNegSum, // was the sum negitive + input logic FmaInvA, // do you invert Z + input logic FmaSs, + input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count + //divide signals + input logic [`DURLEN-1:0] DivEarlyTermShift, + input logic DivS, + input logic DivDone, + input logic [`NE+1:0] DivQe, + input logic [`DIVb-(`RADIX/4):0] DivQm, + // conversion signals + input logic CvtCs, // the result's sign + input logic [`NE:0] CvtCe, // the calculated expoent + input logic CvtResDenormUf, + input logic [`LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by + input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic [`CVTLEN-1:0] CvtLzcIn, // input to the Leading Zero Counter (priority encoder) + input logic IntZero, // is the input zero + // final results + output logic [`FLEN-1:0] PostProcRes, // FMA final result + output logic [4:0] PostProcFlg, + output logic [`XLEN-1:0] FCvtIntRes // the int conversion result + ); + + // general signals + logic Ws; + logic [`NF-1:0] Rf; // Result fraction + logic [`NE-1:0] Re; // Result exponent + logic Ms; + logic [`NE+1:0] Me; + logic [`CORRSHIFTSZ-1:0] Mf; // corectly shifted fraction + logic [`NE+1:0] FullRe; // Re with bits to determine sign and overflow + logic S; // S bit + logic UfPlus1; // do you add one (for determining underflow flag) + logic R; // bits needed to determine rounding + logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count + logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero + logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result + logic Plus1; // add one to the final result? + logic IntInvalid, Overflow, Invalid; // flags + logic UfL; + logic [`FMTBITS-1:0] OutFmt; + // fma signals + logic [`NE+1:0] FmaMe; // exponent of the normalized sum + logic FmaSZero; // is the sum zero + logic [3*`NF+7:0] FmaShiftIn; // shift input + logic [`NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account denormal or zero results + logic FmaPreResultDenorm; // is the result denormalized - calculated before LZA corection + logic [$clog2(3*`NF+7)-1:0] FmaShiftAmt; // normalization shift count + // division singals + logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt; + logic [`NORMSHIFTSZ-1:0] DivShiftIn; + logic [`NE+1:0] Qe; + logic DivByZero; + logic DivResDenorm; + logic [`NE+1:0] DivDenormShift; + // conversion signals + logic [`CVTLEN+`NF:0] CvtShiftIn; // number to be shifted + logic [1:0] CvtNegResMsbs; + logic [`XLEN+1:0] CvtNegRes; + logic CvtResUf; + // readability signals + logic Mult; // multiply opperation + logic Int64; // is the integer 64 bits? + logic Signed; // is the opperation with a signed integer? + logic IntToFp; // is the opperation an int->fp conversion? + logic CvtOp; + logic FmaOp; + logic DivOp; + logic InfIn; + logic NaNIn; + logic Sqrt; + + // signals to help readability + assign Signed = OpCtrl[0]; + assign Int64 = OpCtrl[1]; + assign IntToFp = OpCtrl[2]; + assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0]; + assign CvtOp = (PostProcSel == 2'b00); + assign FmaOp = (PostProcSel == 2'b10); + assign DivOp = (PostProcSel == 2'b01)&DivDone; + assign Sqrt = OpCtrl[0]; + + // is there an input of infinity or NaN being used + assign InfIn = XInf|YInf|ZInf; + assign NaNIn = XNaN|YNaN|ZNaN; + + // choose the ouptut format depending on the opperation + // - fp -> fp: OpCtrl contains the percision of the output + // - otherwise: Fmt contains the percision of the output + if (`FPSIZES == 2) + assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == `FMT); + else if (`FPSIZES == 3 | `FPSIZES == 4) + assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; + + /////////////////////////////////////////////////////////////////////////////// + // Normalization + /////////////////////////////////////////////////////////////////////////////// + + cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn, + .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); + fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe, + .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); + divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn); + + always_comb + case(PostProcSel) + 2'b10: begin // fma + ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(3*`NF+7){1'b0}}, FmaShiftAmt}; + ShiftIn = {FmaShiftIn, {`NORMSHIFTSZ-(3*`NF+8){1'b0}}}; + end + 2'b00: begin // cvt + ShiftAmt = {{$clog2(`NORMSHIFTSZ)-$clog2(`CVTLEN+1){1'b0}}, CvtShiftAmt}; + ShiftIn = {CvtShiftIn, {`NORMSHIFTSZ-`CVTLEN-`NF-1{1'b0}}}; + end + 2'b01: begin //div + if(DivDone) begin + ShiftAmt = DivShiftAmt; + ShiftIn = DivShiftIn; + end else begin + ShiftAmt = '0; + ShiftIn = '0; + end + end + default: begin + ShiftAmt = {$clog2(`NORMSHIFTSZ){1'bx}}; + ShiftIn = {`NORMSHIFTSZ{1'bx}}; + end + endcase + + normshift normshift (.ShiftIn, .ShiftAmt, .Shifted); + + shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultDenorm, .NormSumExp, + .DivResDenorm, .DivDenormShift, .DivOp, .DivQe, + .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf); + + /////////////////////////////////////////////////////////////////////////////// + // Rounding + /////////////////////////////////////////////////////////////////////////////// + + // round to nearest even + // round to zero + // round to -infinity + // round to infinity + // round to nearest max magnitude + + + roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum, + .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms); + + round round(.OutFmt, .Frm, .S, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe, + .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf, + .DivS, .DivDone, + .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .R, .UfL, .Me); + + /////////////////////////////////////////////////////////////////////////////// + // Sign calculation + /////////////////////////////////////////////////////////////////////////////// + + resultsign resultsign(.Frm, .FmaPs, .FmaAs, .FmaMe, .R, .S, + .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Ws); + + /////////////////////////////////////////////////////////////////////////////// + // Flags + /////////////////////////////////////////////////////////////////////////////// + + flags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero, + .Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe, + .NaNIn, .FmaAs, .FmaPs, .R, .IntInvalid, .DivByZero, + .UfL, .S, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1, + .Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg); + + /////////////////////////////////////////////////////////////////////////////// + // Select the result + /////////////////////////////////////////////////////////////////////////////// + + negateintres negateintres(.Xs, .Shifted, .Signed, .Int64, .Plus1, .CvtNegResMsbs, .CvtNegRes); + specialcase specialcase(.Xs, .Xm, .Ym, .Zm, .XZero, .IntInvalid, + .IntZero, .Frm, .OutFmt, .XNaN, .YNaN, .ZNaN, .CvtResUf, + .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .CvtNegRes, + .XInf, .YInf, .DivOp, + .DivByZero, .FullRe, .CvtCe, .Ws, .Re, .Rf, .PostProcRes, .FCvtIntRes); + +endmodule diff --git a/pipelined/src/fpu/qsel.sv b/pipelined/src/fpu/qsel.sv new file mode 100644 index 000000000..e9350da26 --- /dev/null +++ b/pipelined/src/fpu/qsel.sv @@ -0,0 +1,198 @@ +/////////////////////////////////////////// +// srt.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module qsel2 ( // *** eventually just change to 4 bits + input logic [3:0] ps, pc, + output logic qp, qz//, qn +); + + logic [3:0] p, g; + logic magnitude, sign, cout; + + // The quotient selection logic is presented for simplicity, not + // for efficiency. You can probably optimize your logic to + // select the proper divisor with less delay. + + // Qmient equations from EE371 lecture notes 13-20 + assign p = ps ^ pc; + assign g = ps & pc; + + assign magnitude = ~(&p[2:0]); + assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); + assign sign = p[3] ^ cout; +/* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) & + (ps[52]^pc[52])); + assign #1 sign = (ps[55]^pc[55])^ + (ps[54] & pc[54] | ((ps[54]^pc[54]) & + (ps[53]&pc[53] | ((ps[53]^pc[53]) & + (ps[52]&pc[52]))))); */ + + // Produce quotient = +1, 0, or -1 + assign qp = magnitude & ~sign; + assign qz = ~magnitude; +// assign #1 qn = magnitude & sign; +endmodule + +//////////////////////////////////// +// Adder Input Generation, Radix 2 // +//////////////////////////////////// +module fgen2 ( + input logic sp, sz, + input logic [`DIVb-1:0] C, + input logic [`DIVb:0] S, SM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] FP, FN, FZ; + logic [`DIVb+3:0] SExt, SMExt, CExt; + + assign SExt = {3'b0, S}; + assign SMExt = {3'b0, SM}; + assign CExt = {4'hf, C}; + + // Generate for both positive and negative bits + assign FP = ~(SExt << 1) & CExt; + assign FN = (SMExt << 1) | (CExt & ~(CExt << 2)); + assign FZ = '0; + + // Choose which adder input will be used + + always_comb + if (sp) F = FP; + else if (sz) F = FZ; + else F = FN; + +endmodule + +module qsel4 ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] WS, WC, + input logic Sqrt, + output logic [3:0] q +); + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] Dmsbs; + assign PreWmsbs = WC[`DIVb+3:`DIVb-4] + WS[`DIVb+3:`DIVb-4]; + assign Wmsbs = PreWmsbs[7:1]; + assign Dmsbs = D[`DIVN-2:`DIVN-4];//|{3{D[`DIVN-2]&Sqrt}}; + // D = 0001.xxx... + // Dmsbs = | | + // W = xxxx.xxx... + // Wmsbs = | | + + logic [3:0] QSel4[1023:0]; + + always_comb begin + integer d, w, i, w2; + for(d=0; d<8; d++) + for(w=0; w<128; w++)begin + i = d*128+w; + w2 = w-128*(w>=64); // convert to two's complement + case(d) + 0: if($signed(w2)>=$signed(12)) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-4) QSel4[i] = 4'b0000; + else if(w2>=-13) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 1: if(w2>=14) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-5) QSel4[i] = 4'b0000; // was -6 + else if(~Sqrt&(w2>=-15)) QSel4[i] = 4'b0010; // divide case + else if( Sqrt&(w2>=-14)) QSel4[i] = 4'b0010; // sqrt case + else QSel4[i] = 4'b0001; + 2: if(w2>=15) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; + else if(w2>=-16) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 3: if(w2>=16) QSel4[i] = 4'b1000; + else if(w2>=4) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; + else if(w2>=-17) QSel4[i] = 4'b0010; // was -18 + else QSel4[i] = 4'b0001; + 4: if(w2>=18) QSel4[i] = 4'b1000; + else if(w2>=6) QSel4[i] = 4'b0100; + else if(w2>=-6) QSel4[i] = 4'b0000; // was -8 + else if(~Sqrt&(w2>=-20)) QSel4[i] = 4'b0010; // divide case + else if( Sqrt&(w2>=-18)) QSel4[i] = 4'b0010; // sqrt case + else QSel4[i] = 4'b0001; + 5: if(w2>=20) QSel4[i] = 4'b1000; + else if(w2>=6) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-20) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 6: if(w2>=20) QSel4[i] = 4'b1000; + else if(w2>=8) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-22) QSel4[i] = 4'b0010; + else QSel4[i] = 4'b0001; + 7: if(w2>=22) QSel4[i] = 4'b1000; // was 24 + else if(w2>=8) QSel4[i] = 4'b0100; + else if(w2>=-8) QSel4[i] = 4'b0000; + else if(w2>=-23) QSel4[i] = 4'b0010; // was -24 + else QSel4[i] = 4'b0001; + endcase + end + end + assign q = QSel4[{Dmsbs,Wmsbs}]; + +endmodule + +//////////////////////////////////// +// Adder Input Generation, Radix 4 // +//////////////////////////////////// +module fgen4 ( + input logic [3:0] s, + input logic [`DIVb+3:0] C, S, SM, + output logic [`DIVb+3:0] F +); + logic [`DIVb+3:0] F2, F1, F0, FN1, FN2; + + // Generate for both positive and negative bits + assign F2 = (~S << 2) & (C << 2); + assign F1 = ~(S << 1) & C; + assign F0 = '0; + assign FN1 = (SM << 1) | (C & ~(C << 3)); + assign FN2 = (SM << 2) | ((C << 2)&~(C << 4)); + + // Choose which adder input will be used + + always_comb + if (s[3]) F = F2; + else if (s[2]) F = F1; + else if (s[1]) F = FN1; + else if (s[0]) F = FN2; + else F = F0; + + // assign F = sp ? FP : (sn ? FN : FZ); + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/redundantmul.sv b/pipelined/src/fpu/redundantmul.sv deleted file mode 100644 index c1bd8f25a..000000000 --- a/pipelined/src/fpu/redundantmul.sv +++ /dev/null @@ -1,58 +0,0 @@ -/////////////////////////////////////////// -// redundantmul.sv -// -// Written: David_Harris@hmc.edu and ssanghai@hm.edu 10/11/2021 -// Modified: -// -// Purpose: multiplier with output in redundant carry-sum form -// This can be faster than a mutiplier that requires a final adder to obtain the nonredundant answer. -// The module has several implementations controlled by the DESIGN_COMPILER flag. -// When DESIGN_COMPILER = 1, use the Synopsys DesignWare DW02_multp block. This will give highest quality results -// but doesn't work in simulation or when using different tools -// When DESIGN_COMPILER = 2, use the Wally mult_cs block with Radix 2 Booth encoding and a Wallace Tree -// This simulates and synthesizes, but quality of results ae lower than DesignWare -// Otherwise, just use a nonredundant multiplier and set one word to 0. This is best for FPGAs, which have -// block multipliers, and also simulates fastest. -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module redundantmul #(parameter WIDTH =8)( - input logic [WIDTH-1:0] a,b, - output logic [2*WIDTH-1:0] out0, out1); - - if (`DESIGN_COMPILER == 1) begin:mul - logic [2*WIDTH-1+2:0] tmp_out0; - logic [2*WIDTH-1+2:0] tmp_out1; - - DW02_multp #(WIDTH, WIDTH, 2*WIDTH+2) mul(.a, .b, .tc(1'b0), .out0(tmp_out0), .out1(tmp_out1)); - assign out0 = tmp_out0[2*WIDTH-1:0]; - assign out1 = tmp_out1[2*WIDTH-1:0]; - end else begin:mul // force a nonredunant multipler. This will simulate properly and also is appropriate for FPGAs. - assign out0 = a * b; - assign out1 = 0; - end -endmodule - - diff --git a/pipelined/src/fpu/resultsign.sv b/pipelined/src/fpu/resultsign.sv new file mode 100644 index 000000000..c2912ece7 --- /dev/null +++ b/pipelined/src/fpu/resultsign.sv @@ -0,0 +1,76 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: calculating the result's sign +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module resultsign( + input logic [2:0] Frm, + input logic FmaPs, FmaAs, + input logic ZInf, + input logic InfIn, + input logic FmaOp, + input logic [`NE+1:0] FmaMe, + input logic FmaSZero, + input logic Mult, + input logic R, + input logic S, + input logic Ms, + output logic Ws +); + + logic Zeros; + logic Infs; + + // The IEEE754-2019 standard specifies: + // - the sign of an exact zero sum (with operands of diffrent signs) should be positive unless rounding toward negitive infinity + // - when the exact result of an FMA opperation is non-zero, but is zero due to rounding, use the sign of the exact result + // - if x = +0 or -0 then x+x=x and x-(-x)=x + // - the sign of a product is the exclisive or or the opperand's signs + // Zero sign will only be selected if: + // - P=Z and a cancelation occurs - exact zero + // - Z is zero and P is zero - exact zero + // - P is killed and Z is zero - Psgn + // - Z is killed and P is zero - impossible + // Zero sign calculation: + // - if a multiply opperation is done, then use the products sign(Ps) + // - if the zero sum is not exactly zero i.e. R|S use the sign of the exact result (which is the product's sign) + // - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign + assign Zeros = (FmaPs^FmaAs)&~(R|S)&~Mult ? Frm[1:0] == 2'b10 : FmaPs; + + + // is the result negitive + // if p - z is the Sum negitive + // if -p + z is the Sum positive + // if -p - z then the Sum is negitive + assign Infs = ZInf ? FmaAs : FmaPs; + always_comb + if(InfIn&FmaOp) Ws = Infs; + else if(FmaSZero&FmaOp) Ws = Zeros; + else Ws = Ms; + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/round.sv new file mode 100644 index 000000000..0943413bd --- /dev/null +++ b/pipelined/src/fpu/round.sv @@ -0,0 +1,314 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Rounder +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" +// what position is XLEN in? +// options: +// 1: XLEN > NF > NF1 +// 2: NF > XLEN > NF1 +// 3: NF > NF1 > XLEN +// single and double will always be smaller than XLEN +`define XLENPOS ((`XLEN>`NF) ? 1 : (`XLEN>`NF1) ? 2 : 3) + +module round( + input logic [`FMTBITS-1:0] OutFmt, // precision 1 = double 0 = single + input logic [2:0] Frm, // rounding mode + input logic FmaOp, + input logic DivOp, + input logic CvtOp, + input logic ToInt, + input logic DivDone, + input logic [1:0] PostProcSel, + input logic CvtResDenormUf, + input logic CvtResUf, + input logic [`CORRSHIFTSZ-1:0] Mf, + input logic FmaZmS, // addend's sticky bit + input logic [`NE+1:0] FmaMe, // exponent of the normalized sum + input logic Ms, // the result's sign + input logic [`NE:0] CvtCe, // the calculated expoent + input logic [`NE+1:0] Qe, // the calculated expoent + input logic DivS, // sticky bit + output logic UfPlus1, // do you add or subtract on from the result + output logic [`NE+1:0] FullRe, // Re with bits to determine sign and overflow + output logic [`NF-1:0] Rf, // Result fraction + output logic [`NE-1:0] Re, // Result exponent + output logic S, // sticky bit + output logic [`NE+1:0] Me, + output logic Plus1, + output logic R, UfL // bits needed to calculate rounding +); + logic L; // bit used for rounding - least significant bit of the normalized sum + logic UfCalcPlus1; + logic NormS; // normalized sum's sticky bit + logic UfS; // sticky bit for underlow calculation + logic [`NF-1:0] RoundFrac; + logic FpRes, IntRes; + logic UfR; + logic FpRound, FpLSBRes, FpUfRound; + logic CalcPlus1, FpPlus1; + logic [`FLEN:0] RoundAdd; // how much to add to the result + + /////////////////////////////////////////////////////////////////////////////// + // Rounding + /////////////////////////////////////////////////////////////////////////////// + + // round to nearest even + // {R, S} + // 0x - do nothing + // 10 - tie - Plus1 if result is odd (LSBNormSum = 1) + // - don't add 1 if a small number was supposed to be subtracted + // 11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number) + // - plus 1 otherwise + + // round to zero - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0 + + // round to -infinity + // - Plus1 if negative unless a small number was supposed to be subtracted from a result with guard and round bits of 0 + // - subtract 1 if a small number was supposed to be subtracted from a positive result with guard and round bits of 0 + + // round to infinity + // - Plus1 if positive unless a small number was supposed to be subtracted from a result with guard and round bits of 0 + // - subtract 1 if a small number was supposed to be subtracted from a negative result with guard and round bits of 0 + + // round to nearest max magnitude + // {Guard, R, S} + // 0x - do nothing + // 10 - tie - Plus1 + // - don't add 1 if a small number was supposed to be subtracted + // 11 - do nothing if a small number was supposed to subtracted (the sticky bit was set by the small number) + // - Plus 1 otherwise + + assign IntRes = CvtOp & ToInt; + assign FpRes = ~IntRes; + + // sticky bit calculation + if (`FPSIZES == 1) begin + + // 1: XLEN > NF + // | XLEN | + // | NF |1|1| + // ^ ^ if floating point result + // ^ if not an FMA result + if (`XLENPOS == 1)assign NormS = (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:0]); + // 2: NF > XLEN + if (`XLENPOS == 2)assign NormS = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&IntRes) | + (|Mf[`CORRSHIFTSZ-`NF-2:0]); + + end else if (`FPSIZES == 2) begin + // XLEN is either 64 or 32 + // so half and single are always smaller then XLEN + + // 1: XLEN > NF > NF1 + if (`XLENPOS == 1) assign NormS = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~OutFmt) | + (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:0]); + // 2: NF > XLEN > NF1 + if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~OutFmt) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~OutFmt)) | + (|Mf[`CORRSHIFTSZ-`NF-2:0]); + // 3: NF > NF1 > XLEN + if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&IntRes) | + (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~OutFmt|IntRes)) | + (|Mf[`CORRSHIFTSZ-`NF-2:0]); + + end else if (`FPSIZES == 3) begin + // 1: XLEN > NF > NF1 + if (`XLENPOS == 1) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) | + (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&FpRes&~(OutFmt==`FMT)) | + (|Mf[`CORRSHIFTSZ-`NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:0]); + // 2: NF > XLEN > NF1 + if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`NF1-1]&FpRes&(OutFmt==`FMT1)) | + (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`FMT)) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF-1]&(IntRes|~(OutFmt==`FMT))) | + (|Mf[`CORRSHIFTSZ-`NF-2:0]); + // 3: NF > NF1 > XLEN + if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`NF2-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&(OutFmt==`FMT1)) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`NF1-1]&((OutFmt==`FMT1)|IntRes)) | + (|Mf[`CORRSHIFTSZ-`NF1-2:`CORRSHIFTSZ-`NF-1]&(~(OutFmt==`FMT)|IntRes)) | + (|Mf[`CORRSHIFTSZ-`NF-2:0]); + + end else if (`FPSIZES == 4) begin + // Quad precision will always be greater than XLEN + // 2: NF > XLEN > NF1 + if (`XLENPOS == 2) assign NormS = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) | + (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`D_NF-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) | + (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&~(OutFmt==`Q_FMT)) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) | + (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]); + // 3: NF > NF1 > XLEN + // The extra XLEN bit will be ored later when caculating the final sticky bit - the ufplus1 not needed for integer + if (`XLENPOS == 3) assign NormS = (|Mf[`CORRSHIFTSZ-`H_NF-2:`CORRSHIFTSZ-`S_NF-1]&FpRes&(OutFmt==`H_FMT)) | + (|Mf[`CORRSHIFTSZ-`S_NF-2:`CORRSHIFTSZ-`XLEN-1]&FpRes&((OutFmt==`S_FMT)|(OutFmt==`H_FMT))) | + (|Mf[`CORRSHIFTSZ-`XLEN-2:`CORRSHIFTSZ-`D_NF-1]&((OutFmt==`S_FMT)|(OutFmt==`H_FMT)|IntRes)) | + (|Mf[`CORRSHIFTSZ-`D_NF-2:`CORRSHIFTSZ-`Q_NF-1]&(~(OutFmt==`Q_FMT)|IntRes)) | + (|Mf[`CORRSHIFTSZ-`Q_NF-2:0]); + + end + + + + // only add the Addend sticky if doing an FMA opperation + // - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits) + assign UfS = FmaZmS&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp; + + // determine round and LSB of the rounded value + // - underflow round bit is used to determint the underflow flag + if (`FPSIZES == 1) begin + assign FpRound = Mf[`CORRSHIFTSZ-`NF-1]; + assign FpLSBRes = Mf[`CORRSHIFTSZ-`NF]; + assign FpUfRound = Mf[`CORRSHIFTSZ-`NF-2]; + + end else if (`FPSIZES == 2) begin + assign FpRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-1] : Mf[`CORRSHIFTSZ-`NF1-1]; + assign FpLSBRes = OutFmt ? Mf[`CORRSHIFTSZ-`NF] : Mf[`CORRSHIFTSZ-`NF1]; + assign FpUfRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-2] : Mf[`CORRSHIFTSZ-`NF1-2]; + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: begin + FpRound = Mf[`CORRSHIFTSZ-`NF-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`NF]; + FpUfRound = Mf[`CORRSHIFTSZ-`NF-2]; + end + `FMT1: begin + FpRound = Mf[`CORRSHIFTSZ-`NF1-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`NF1]; + FpUfRound = Mf[`CORRSHIFTSZ-`NF1-2]; + end + `FMT2: begin + FpRound = Mf[`CORRSHIFTSZ-`NF2-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`NF2]; + FpUfRound = Mf[`CORRSHIFTSZ-`NF2-2]; + end + default: begin + FpRound = 1'bx; + FpLSBRes = 1'bx; + FpUfRound = 1'bx; + end + endcase + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: begin + FpRound = Mf[`CORRSHIFTSZ-`Q_NF-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`Q_NF]; + FpUfRound = Mf[`CORRSHIFTSZ-`Q_NF-2]; + end + 2'h1: begin + FpRound = Mf[`CORRSHIFTSZ-`D_NF-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`D_NF]; + FpUfRound = Mf[`CORRSHIFTSZ-`D_NF-2]; + end + 2'h0: begin + FpRound = Mf[`CORRSHIFTSZ-`S_NF-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`S_NF]; + FpUfRound = Mf[`CORRSHIFTSZ-`S_NF-2]; + end + 2'h2: begin + FpRound = Mf[`CORRSHIFTSZ-`H_NF-1]; + FpLSBRes = Mf[`CORRSHIFTSZ-`H_NF]; + FpUfRound = Mf[`CORRSHIFTSZ-`H_NF-2]; + end + endcase + end + + assign R = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-1] : FpRound; + assign L = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN] : FpLSBRes; + assign UfR = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-2] : FpUfRound; + + // used to determine underflow flag + assign UfL = FpRound; + // determine sticky + assign S = UfS | UfR; + + + always_comb begin + // Determine if you add 1 + case (Frm) + 3'b000: CalcPlus1 = R & (S| L);//round to nearest even + 3'b001: CalcPlus1 = 0;//round to zero + 3'b010: CalcPlus1 = Ms;//round down + 3'b011: CalcPlus1 = ~Ms;//round up + 3'b100: CalcPlus1 = R;//round to nearest max magnitude + default: CalcPlus1 = 1'bx; + endcase + // Determine if you add 1 (for underflow flag) + case (Frm) + 3'b000: UfCalcPlus1 = UfR & (UfS| UfL);//round to nearest even + 3'b001: UfCalcPlus1 = 0;//round to zero + 3'b010: UfCalcPlus1 = Ms;//round down + 3'b011: UfCalcPlus1 = ~Ms;//round up + 3'b100: UfCalcPlus1 = UfR;//round to nearest max magnitude + default: UfCalcPlus1 = 1'bx; + endcase + + end + + // If an answer is exact don't round + assign Plus1 = CalcPlus1 & (S | R); + assign FpPlus1 = Plus1&~(ToInt&CvtOp); + assign UfPlus1 = UfCalcPlus1 & S; // UfR is part of sticky + + // Compute rounded result + if (`FPSIZES == 1) begin + assign RoundAdd = {{`FLEN{1'b0}}, FpPlus1}; + + end else if (`FPSIZES == 2) begin + // \/FLEN+1 + // | NE+2 | NF | + // '-NE+2-^----NF1----^ + // `FLEN+1-`NE-2-`NF1 = FLEN-1-NE-NF1 + assign RoundAdd = {(`NE+1+`NF1)'(0), FpPlus1&~OutFmt, (`NF-`NF1-1)'(0), FpPlus1&OutFmt}; + + end else if (`FPSIZES == 3) begin + assign RoundAdd = {(`NE+1+`NF2)'(0), FpPlus1&(OutFmt==`FMT2), (`NF1-`NF2-1)'(0), FpPlus1&(OutFmt==`FMT1), (`NF-`NF1-1)'(0), FpPlus1&(OutFmt==`FMT)}; + + end else if (`FPSIZES == 4) + assign RoundAdd = {(`Q_NE+1+`H_NF)'(0), FpPlus1&(OutFmt==`H_FMT), (`S_NF-`H_NF-1)'(0), FpPlus1&(OutFmt==`S_FMT), (`D_NF-`S_NF-1)'(0), FpPlus1&(OutFmt==`D_FMT), (`Q_NF-`D_NF-1)'(0), FpPlus1&(OutFmt==`Q_FMT)}; + + // determine the result to be roundned + assign RoundFrac = Mf[`CORRSHIFTSZ-1:`CORRSHIFTSZ-`NF]; + + always_comb + case(PostProcSel) + 2'b10: Me = FmaMe; // fma + 2'b00: Me = {CvtCe[`NE], CvtCe}&{`NE+2{~CvtResDenormUf|CvtResUf}}; // cvt + 2'b01: Me = DivDone ? Qe : '0; // divide + default: Me = '0; + endcase + + // round the result + // - if the fraction overflows one should be added to the exponent + assign {FullRe, Rf} = {Me, RoundFrac} + RoundAdd; + assign Re = FullRe[`NE-1:0]; + + +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/rounder_denorm.sv b/pipelined/src/fpu/rounder_denorm.sv deleted file mode 100755 index 3c9a0e91f..000000000 --- a/pipelined/src/fpu/rounder_denorm.sv +++ /dev/null @@ -1,259 +0,0 @@ -// The rounder takes as input logics a 64-bit value to be rounded, A, the -// exponent of the value to be rounded, the sign of the final result, Sign, -// the precision of the results, P, and the two-bit rounding mode, rm. -// It produces a rounded 52-bit result, Z, the exponent of the rounded -// result, Z_exp, and a flag that indicates if the result was rounded, -// Inexact. The rounding mode has the following values. -// rm Modee -// 00 round-to-nearest-even -// 01 round-toward-zero -// 10 round-toward-plus infinity -// 11 round-toward-minus infinity -// The rounding algorithm determines if '1' should be added to the -// truncated signficant result, based on three significant bits -// (least (L), round (R) and sticky (S)), the rounding mode (rm) -// and the sign of the final result (Sign). Visually, L and R appear as -// xxxxxL,Rxxxxxxx -// where , denotes the rounding boundary. S is the logical OR of all the -// bits to the right of R. - -module rounder ( - input logic [2:0] rm, - input logic P, - input logic OvEn, - input logic UnEn, - input logic exp_valid, - input logic [3:0] sel_inv, - input logic Invalid, - input logic DenormIn, - input logic Asign, - input logic [10:0] Aexp, - input logic [5:0] norm_shift, - input logic [63:0] A, - input logic [10:0] exponent_postsum, - input logic A_Norm, - input logic B_Norm, - input logic [11:0] exp_A_unmodified, - input logic [11:0] exp_B_unmodified, - input logic normal_overflow, - input logic normal_underflow, - input logic swap, - input logic [2:0] op_type, - input logic [63:0] sum, - - output logic [63:0] Result, - output logic DenormIO, - output logic [4:0] Flags -); - - wire Rsign; - wire Sticky_out; - wire [51:0] ShiftMant; - wire [63:0] ShiftMant_64; - wire [10:0] Rexp; - wire [10:0] Rexp_denorm; - wire [11:0] Texp; //Parallelized for denorm exponent - wire [11:0] Texp_addone; //results - wire [11:0] Texp_subone; - wire [51:0] Rmant; - wire [51:0] Tmant; - wire Rzero; - wire VSS = 1'b0; - wire VDD = 1'b1; - wire [51:0] B; // Value used to add the "ones" - wire [11:0] B_12_overflow; // Value used to add one to exponent - wire [11:0] B_12_underflow; // Value used to subtract one from exponent - wire S_SP; // Single precision sticky bit - wire S_DP; // Double precision sticky bit - wire S; // Actual sticky bit - wire R; // Round bit - wire L; // Least significant bit - wire add_one; // '1' if one should be added - wire UnFlow_SP, UnFlow_DP, UnderFlow; - wire OvFlow_SP, OvFlow_DP, OverFlow; - wire Inexact; - wire Round_zero; - wire Infinite; - wire VeryLarge; - wire Largest; - wire Adj_exp; - wire Valid; - wire NaN; - wire Cout; - wire Cout_overflow; - wire Texp_l7z; - wire Texp_l7o; - - // Determine the sticky bits for double and single precision - assign S_DP= A[9]|A[8]|A[7]|A[6]|A[5]|A[4]|A[3]|A[2]|A[1]|A[0]; - assign S_SP = S_DP |A[38]|A[37]|A[36]|A[35]|A[34]|A[33]|A[32]|A[31]|A[30]| - A[29]|A[28]|A[27]|A[26]|A[25]|A[24]|A[23]|A[22]|A[21]|A[20]| - A[19]|A[18]|A[17]|A[16]|A[15]|A[14]|A[13]|A[12]|A[11]|A[10]; - - // Set the least (L), round (R), and sticky (S) bits based on - // the precision. - assign {L, R, S} = P ? {A[40],A[39],S_SP} : {A[11],A[10],S_DP}; - - // Add one if ((the rounding mode is round-to-nearest) and (R is one) and - // (S or L is one)) or ((the rounding mode is towards plus or minus - // infinity (rm[1] = 1)) and (the sign and rm[0] are the same) and - // (R or S is one)). - - assign add_one = ~rm[2] & ((~rm[1]&~rm[0]&R&(L|S)) | (rm[1]&(Asign^~rm[0])&(R|S))) | (rm[2] & R); - - // Add one using a 52-bit adder. The one is added to the LSB B[0] for - // double precision or to B[29] for single precision. - // This could be simplified by using a specialized adder. - // The current adder is actually 64-bits. The leading one - // for normalized results in not included in the addition. - assign B = {{22{VSS}}, add_one&P, {28{VSS}}, add_one&~P}; - assign B_12_overflow = {8'h0, 3'b0, normal_overflow}; - assign B_12_underflow = {8'h0, 3'b0, normal_underflow}; - - cla52 add1(Tmant, Cout, A[62:11], B); //***adder - - cla12 add1_exp(Texp_addone, Cout_overflow, Texp, B_12_overflow); //***adder - - cla_sub12 sub1_exp(Texp_subone, Texp, B_12_underflow); //***adder - - // Now that rounding is done, we compute the final exponent - // and test for special cases. - - // Compute the value of the exponent by subtracting the shift - // value from the previous exponent and then adding 2 + cout. - // If needed this could be optimized to used a specialized - // adder. - - assign Texp = DenormIn ? ({1'b0, exponent_postsum}) : ({VSS, Aexp} - {{6{VSS}}, norm_shift} +{{10{VSS}}, VDD, Cout}); - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o; - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11] is one) or Texp[10] to - // Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = Texp[11] | ~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = (~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z)); - - // Set the overflow and underflow flags. They should not be set if - // the input logic was infinite or NaN or the output logic of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = (~sel_inv[2]&~sel_inv[1]&~sel_inv[0]); - assign NaN = ~sel_inv[2]&~sel_inv[1]& sel_inv[0]; - assign UnderFlow = ((P & UnFlow_SP | UnFlow_DP)&Valid&exp_valid) | - (~Aexp[10]&Aexp[9]&Aexp[8]&Aexp[7]&~Aexp[6] - &~Aexp[5]&~Aexp[4]&~Aexp[3]&~Aexp[2] - &~Aexp[1]&~Aexp[0]&sel_inv[3]); - assign OverFlow = (P & OvFlow_SP | OvFlow_DP)&Valid&~UnderFlow&exp_valid; - - // The DenormIO is set if underflow has occurred or if their was a - // denormalized input logic. - assign DenormIO = DenormIn | UnderFlow; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (R|S|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {UnderFlow, VSS, OverFlow, Invalid, Inexact}; - - // Determine the final result. - - // The sign of the final result is one if the result is not zero and - // the sign of A is one, or if the result is zero and the the rounding - // mode is round-to-minus infinity. The final result is zero, if exp_valid - // is zero. If underflow occurs, then the result is set to zero. - // - // For Zero (goes equally for subtraction although - // signs may alter operands sign): - // -0 + -0 = -0 (always) - // +0 + +0 = +0 (always) - // -0 + +0 = +0 (for RN, RZ, RU) - // -0 + +0 = -0 (for RD) - assign Rzero = ~exp_valid | UnderFlow; - assign Rsign = DenormIn ? - ( ~(op_type[1] | op_type[0]) ? - ( (sum[63] & (A_Norm | B_Norm) & (exp_A_unmodified[11] ^ exp_B_unmodified[11])) ? - ~Asign : Asign) - : ( ((A_Norm ^ B_Norm) & (exp_A_unmodified[11] ~^ exp_B_unmodified[11])) ? - (normal_underflow ? ~Asign : Asign) : Asign) - ) - : ( ((Asign&exp_valid | - (sel_inv[2]&~sel_inv[1]&sel_inv[0]&rm[1]&rm[0] | - sel_inv[2]&sel_inv[1]&~sel_inv[0] | - ~exp_valid&rm[1]&rm[0]&~sel_inv[2] | - UnderFlow&rm[1]&rm[0])) & ~sel_inv[3]) | - (Asign & sel_inv[3]) ); - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~Asign&rm[0] | Asign&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | (~sel_inv[2] & sel_inv[1]); - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // The denormalized rounded exponent uses the overflow/underflow values - // computed in the fpadd component to round the exponent up or down - // Depending on the operation and the signs of the orignal operands, - // underflow may or may not be needed to round. - assign Rexp_denorm = DenormIn ? - ((~op_type[1] & op_type[0]) ? - ( ((A_Norm != B_Norm) & (exp_A_unmodified[11] == exp_B_unmodified[11])) ? - ( (normal_overflow == normal_underflow) ? Texp[10:0] : (normal_overflow ? Texp_addone[10:0] : Texp_subone[10:0]) ) - : ( normal_overflow ? Texp_addone[10:0] : Texp[10:0] ) ) - : ( ((A_Norm != B_Norm) & (exp_A_unmodified[11] != exp_B_unmodified[11])) ? - ( (normal_overflow == normal_underflow) ? Texp[10:0] : (normal_overflow ? Texp_addone[10:0] : Texp_subone[10:0]) ) - : ( normal_overflow ? Texp_addone[10:0] : Texp[10:0] ) ) - ) : - Rexp; //KEP used to be all of exp_A_unmodified - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - // If operation is denormalized, take the mantissa directly from - // its normalized value. - assign Rmant[51] = Largest | NaN | (Tmant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = {51{Largest}} | (Tmant[50:0]&{51{~Infinite&Valid&~Rzero}}); - - assign ShiftMant = A[51:0]; - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - - assign Result = DenormIn ? {Rsign, Rexp_denorm, ShiftMant} : (P ? {{32{1'b1}}, Rsign, Rexp[7:0], Rmant[51:29]} - : {Rsign, Rexp, Rmant}); - -endmodule // rounder - diff --git a/pipelined/src/fpu/rounder_div.sv b/pipelined/src/fpu/rounder_div.sv deleted file mode 100755 index 43045ee57..000000000 --- a/pipelined/src/fpu/rounder_div.sv +++ /dev/null @@ -1,212 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Floating point divider/square root rounder unit (Goldschmidt) -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module rounder_div ( - input logic [1:0] rm, - input logic P, - input logic OvEn, - input logic UnEn, - input logic [12:0] exp_diff, - input logic [2:0] sel_inv, - input logic Invalid, - input logic SignR, - input logic [63:0] Float1, - input logic [63:0] Float2, - input logic XNaNQ, - input logic YNaNQ, - input logic XZeroQ, - input logic YZeroQ, - input logic XInfQ, - input logic YInfQ, - input logic op_type, - input logic [59:0] q1, - input logic [59:0] qm1, - input logic [59:0] qp1, - input logic [59:0] q0, - input logic [59:0] qm0, - input logic [59:0] qp0, - input logic [119:0] regr_out, - - output logic [63:0] Result, - output logic [4:0] Flags - ); - - logic Rsign; - logic [10:0] Rexp; - logic [12:0] Texp; - logic [51:0] Rmant; - logic [59:0] Tmant; - logic [51:0] Smant; - logic Rzero; - logic Gdp, Gsp, G; - logic UnFlow_SP, UnFlow_DP, UnderFlow; - logic OvFlow_SP, OvFlow_DP, OverFlow; - logic Inexact; - logic Round_zero; - logic Infinite; - logic VeryLarge; - logic Largest; - logic Div0; - logic Adj_exp; - logic Valid; - logic NaN; - logic Texp_l7z; - logic Texp_l7o; - logic OvCon; - logic zero_rem; - logic [1:0] mux_mant; - logic sign_rem; - logic [59:0] q, qm, qp; - logic exp_ovf; - - logic [50:0] NaN_out; - logic NaN_Sign_out; - logic Sign_out; - - // Remainder = 0? - assign zero_rem = ~(|regr_out); - // Remainder Sign - assign sign_rem = ~regr_out[119]; - // choose correct Guard bit [1,2) or [0,1) - assign Gdp = q1[59] ? q1[6] : q0[6]; - assign Gsp = q1[59] ? q1[35] : q0[35]; - assign G = P ? Gsp : Gdp; - // Selection of Rounding (from logic/switching) - assign mux_mant[1] = (SignR&rm[1]&rm[0]&G) | (!SignR&rm[1]&!rm[0]&G) | - (!rm[1]&!rm[0]&G&!sign_rem) | - (SignR&rm[1]&rm[0]&!zero_rem&!sign_rem) | - (!SignR&rm[1]&!rm[0]&!zero_rem&!sign_rem); - assign mux_mant[0] = (!SignR&rm[0]&!G&!zero_rem&sign_rem) | - (!rm[1]&rm[0]&!G&!zero_rem&sign_rem) | - (SignR&rm[1]&!rm[0]&!G&!zero_rem&sign_rem); - - // Which Q? - mux2 #(60) mx1 (q0, q1, q1[59], q); - mux2 #(60) mx2 (qm0, qm1, q1[59], qm); - mux2 #(60) mx3 (qp0, qp1, q1[59], qp); - // Choose Q, Q+1, Q-1 - mux3 #(60) mx4 (q, qm, qp, mux_mant, Tmant); - assign Smant = Tmant[58:7]; - // Compute the value of the exponent - // exponent is modified if we choose: - // 1.) we choose any qm0, qp0, q0 (since we shift mant) - // 2.) we choose qp and we overflow (for RU) - assign exp_ovf = |{qp[58:36], (qp[35:7] & {29{~P}})}; - assign Texp = exp_diff - {{12{1'b0}}, ~q1[59]} + {{12{1'b0}}, mux_mant[1]&qp1[59]&~exp_ovf}; - - // Overflow only occurs for double precision, if Texp[10] to Texp[0] are - // all ones. To encourage sharing with single precision overflow detection, - // the lower 7 bits are tested separately. - assign Texp_l7o = Texp[6]&Texp[5]&Texp[4]&Texp[3]&Texp[2]&Texp[1]&Texp[0]; - assign OvFlow_DP = (~Texp[12]&Texp[11]) | (Texp[10]&Texp[9]&Texp[8]&Texp[7]&Texp_l7o); - - // Overflow occurs for single precision if (Texp[10] is one) and - // ((Texp[9] or Texp[8] or Texp[7]) is one) or (Texp[6] to Texp[0] - // are all ones. - assign OvFlow_SP = Texp[10]&(Texp[9]|Texp[8]|Texp[7]|Texp_l7o); - - // Underflow occurs for double precision if (Texp[11]/Texp[10] is one) or - // Texp[10] to Texp[0] are all zeros. - assign Texp_l7z = ~Texp[6]&~Texp[5]&~Texp[4]&~Texp[3]&~Texp[2]&~Texp[1]&~Texp[0]; - assign UnFlow_DP = (Texp[12]&Texp[11]) | ~Texp[11]&~Texp[10]&~Texp[9]&~Texp[8]&~Texp[7]&Texp_l7z; - - // Underflow occurs for single precision if (Texp[10] is zero) and - // (Texp[9] or Texp[8] or Texp[7]) is zero. - assign UnFlow_SP = ~Texp[10]&(~Texp[9]|~Texp[8]|~Texp[7]|Texp_l7z); - - // Set the overflow and underflow flags. They should not be set if - // the input was infinite or NaN or the output of the adder is zero. - // 00 = Valid - // 10 = NaN - assign Valid = ~sel_inv[2]&~sel_inv[1]&~sel_inv[0]; - assign NaN = sel_inv[2]&sel_inv[1]&sel_inv[0]; - assign UnderFlow = (P & UnFlow_SP | UnFlow_DP) & Valid; - assign OverFlow = (P & OvFlow_SP | OvFlow_DP) & Valid; - assign Div0 = YZeroQ&~XZeroQ&~op_type&~NaN; - - // The final result is Inexact if any rounding occurred ((i.e., R or S - // is one), or (if the result overflows ) or (if the result underflows and the - // underflow trap is not enabled)) and (value of the result was not previous set - // by an exception case). - assign Inexact = (G|~zero_rem|OverFlow|(UnderFlow&~UnEn))&Valid; - - // Set the IEEE Exception Flags: Inexact, Underflow, Overflow, Div_By_0, - // Invlalid. - assign Flags = {Inexact, UnderFlow, OverFlow, Div0, Invalid}; - - // Determine sign - assign Rzero = UnderFlow | (~sel_inv[2]&sel_inv[1]&sel_inv[0]); - assign Rsign = SignR; - - // The exponent of the final result is zero if the final result is - // zero or a denorm, all ones if the final result is NaN or Infinite - // or overflow occurred and the magnitude of the number is - // not rounded toward from zero, and all ones with an LSB of zero - // if overflow occurred and the magnitude of the number is - // rounded toward zero. If the result is single precision, - // Texp[7] shoud be inverted. When the Overflow trap is enabled (OvEn = 1) - // and overflow occurs and the operation is not conversion, bits 10 and 9 are - // inverted for double precision, and bits 7 and 6 are inverted for single precision. - assign Round_zero = ~rm[1]&rm[0] | ~SignR&rm[0] | SignR&rm[1]&~rm[0]; - assign VeryLarge = OverFlow & ~OvEn; - assign Infinite = (VeryLarge & ~Round_zero) | sel_inv[1]; - assign Largest = VeryLarge & Round_zero; - assign Adj_exp = OverFlow & OvEn; - assign Rexp[10:1] = ({10{~Valid}} | - {Texp[10]&~Adj_exp, Texp[9]&~Adj_exp, Texp[8], - (Texp[7]^P)&~(Adj_exp&P), Texp[6]&~(Adj_exp&P), Texp[5:1]} | - {10{VeryLarge}})&{10{~Rzero | NaN}}; - assign Rexp[0] = ({~Valid} | Texp[0] | Infinite)&(~Rzero | NaN)&~Largest; - - // If the result is zero or infinity, the mantissa is all zeros. - // If the result is NaN, the mantissa is 10...0 - // If the result the largest floating point number, the mantissa - // is all ones. Otherwise, the mantissa is not changed. - assign NaN_out = ~XNaNQ&YNaNQ ? Float2[50:0] : Float1[50:0]; - assign NaN_Sign_out = ~XNaNQ&YNaNQ ? Float2[63] : Float1[63]; - assign Sign_out = (XZeroQ&YZeroQ | XInfQ&YInfQ)&~op_type | Rsign&~XNaNQ&~YNaNQ | - NaN_Sign_out&(XNaNQ|YNaNQ); - // FIXME (jes) - Imperas gives sNaN a Sign=0 where x86 gives Sign=1 - // | Float1[63]&op_type; (logic to fix this but removed for now) - - assign Rmant[51] = Largest | NaN | (Smant[51]&~Infinite&~Rzero); - assign Rmant[50:0] = ({51{Largest}} | (Smant[50:0]&{51{~Infinite&Valid&~Rzero}}) | - (NaN_out&{51{NaN}}))&({51{~(op_type&Float1[63]&~XZeroQ)}}); - - // For single precision, the 8 least significant bits of the exponent - // and 23 most significant bits of the mantissa contain bits used - // for the final result. A double precision result is returned if - // overflow has occurred, the overflow trap is enabled, and a conversion - // is being performed. - assign OvCon = OverFlow & OvEn; - assign Result = (P&~OvCon) ? { {32{1'b1}}, Sign_out, Rexp[7:0], Rmant[51:29]} - : {Sign_out, Rexp, Rmant}; - -endmodule // rounder - diff --git a/pipelined/src/fpu/sbtm_div.sv b/pipelined/src/fpu/roundsign.sv similarity index 60% rename from pipelined/src/fpu/sbtm_div.sv rename to pipelined/src/fpu/roundsign.sv index 3daa5accb..62e882e65 100644 --- a/pipelined/src/fpu/sbtm_div.sv +++ b/pipelined/src/fpu/roundsign.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // -// Written: James Stine -// Modified: 8/1/2018 +// Written: me@KatherineParry.com +// Modified: 7/5/2022 // -// Purpose: Bipartite Lookup for divide portion of fpdivsqrt +// Purpose: Sign calculation ofr rounding // // A component of the Wally configurable RISC-V project. // @@ -26,37 +26,28 @@ // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE // OR OTHER DEALINGS IN THE SOFTWARE. //////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" -module sbtm_div (input logic [11:0] a, output logic [10:0] ia_out); +module roundsign( + input logic FmaPs, FmaAs, + input logic FmaInvA, + input logic Xs, + input logic Ys, + input logic FmaNegSum, + input logic Sqrt, + input logic FmaOp, + input logic DivOp, + input logic CvtOp, + input logic CvtCs, + input logic FmaSs, + output logic Ms +); - // bit partitions - logic [3:0] x0; - logic [2:0] x1; - logic [3:0] x2; - logic [2:0] x2_1cmp; - // mem outputs - logic [12:0] y0; - logic [4:0] y1; - // input to CPA - logic [14:0] op1; - logic [14:0] op2; - logic [14:0] p; - logic cout; + logic Qs; - assign x0 = a[10:7]; - assign x1 = a[6:4]; - assign x2 = a[3:0]; + assign Qs = Xs^(Ys&~Sqrt); - sbtm_a0 mem1 ({x0, x1}, y0); - // 1s cmp per sbtm/stam - assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0]; - sbtm_a1 mem2 ({x0, x2_1cmp}, y1); - assign op1 = {1'b0, y0, 1'b0}; - // 1s cmp per sbtm/stam - assign op2 = x2[3] ? {1'b1, {8{1'b1}}, ~y1, 1'b1} : - {1'b0, 8'b0, y1, 1'b1}; - // CPA - assign {cout, p} = op1 + op2; - assign ia_out = p[14:4]; + // Sign for rounding calulation + assign Ms = (FmaSs&FmaOp) | (CvtCs&CvtOp) | (Qs&DivOp); -endmodule // sbtm +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/sbtm_a0.sv b/pipelined/src/fpu/sbtm_a0.sv deleted file mode 100644 index f06350289..000000000 --- a/pipelined/src/fpu/sbtm_a0.sv +++ /dev/null @@ -1,170 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Bipartite Lookup -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module sbtm_a0 (input logic [6:0] a, - output logic [12:0] y); - - always_comb - case(a) - 7'b0000000: y = 13'b1111111100010; - 7'b0000001: y = 13'b1111110100011; - 7'b0000010: y = 13'b1111101100101; - 7'b0000011: y = 13'b1111100101000; - 7'b0000100: y = 13'b1111011101100; - 7'b0000101: y = 13'b1111010110000; - 7'b0000110: y = 13'b1111001110110; - 7'b0000111: y = 13'b1111000111100; - 7'b0001000: y = 13'b1111000000100; - 7'b0001001: y = 13'b1110111001100; - 7'b0001010: y = 13'b1110110010101; - 7'b0001011: y = 13'b1110101011110; - 7'b0001100: y = 13'b1110100101001; - 7'b0001101: y = 13'b1110011110100; - 7'b0001110: y = 13'b1110011000000; - 7'b0001111: y = 13'b1110010001101; - 7'b0010000: y = 13'b1110001011010; - 7'b0010001: y = 13'b1110000101000; - 7'b0010010: y = 13'b1101111110111; - 7'b0010011: y = 13'b1101111000110; - 7'b0010100: y = 13'b1101110010111; - 7'b0010101: y = 13'b1101101100111; - 7'b0010110: y = 13'b1101100111001; - 7'b0010111: y = 13'b1101100001011; - 7'b0011000: y = 13'b1101011011101; - 7'b0011001: y = 13'b1101010110001; - 7'b0011010: y = 13'b1101010000100; - 7'b0011011: y = 13'b1101001011001; - 7'b0011100: y = 13'b1101000101110; - 7'b0011101: y = 13'b1101000000011; - 7'b0011110: y = 13'b1100111011001; - 7'b0011111: y = 13'b1100110101111; - 7'b0100000: y = 13'b1100110000110; - 7'b0100001: y = 13'b1100101011110; - 7'b0100010: y = 13'b1100100110110; - 7'b0100011: y = 13'b1100100001111; - 7'b0100100: y = 13'b1100011101000; - 7'b0100101: y = 13'b1100011000001; - 7'b0100110: y = 13'b1100010011011; - 7'b0100111: y = 13'b1100001110101; - 7'b0101000: y = 13'b1100001010000; - 7'b0101001: y = 13'b1100000101011; - 7'b0101010: y = 13'b1100000000111; - 7'b0101011: y = 13'b1011111100011; - 7'b0101100: y = 13'b1011111000000; - 7'b0101101: y = 13'b1011110011101; - 7'b0101110: y = 13'b1011101111010; - 7'b0101111: y = 13'b1011101011000; - 7'b0110000: y = 13'b1011100110110; - 7'b0110001: y = 13'b1011100010101; - 7'b0110010: y = 13'b1011011110011; - 7'b0110011: y = 13'b1011011010011; - 7'b0110100: y = 13'b1011010110010; - 7'b0110101: y = 13'b1011010010010; - 7'b0110110: y = 13'b1011001110011; - 7'b0110111: y = 13'b1011001010011; - 7'b0111000: y = 13'b1011000110100; - 7'b0111001: y = 13'b1011000010110; - 7'b0111010: y = 13'b1010111110111; - 7'b0111011: y = 13'b1010111011001; - 7'b0111100: y = 13'b1010110111100; - 7'b0111101: y = 13'b1010110011110; - 7'b0111110: y = 13'b1010110000001; - 7'b0111111: y = 13'b1010101100100; - 7'b1000000: y = 13'b1010101001000; - 7'b1000001: y = 13'b1010100101100; - 7'b1000010: y = 13'b1010100010000; - 7'b1000011: y = 13'b1010011110100; - 7'b1000100: y = 13'b1010011011001; - 7'b1000101: y = 13'b1010010111110; - 7'b1000110: y = 13'b1010010100011; - 7'b1000111: y = 13'b1010010001001; - 7'b1001000: y = 13'b1010001101111; - 7'b1001001: y = 13'b1010001010101; - 7'b1001010: y = 13'b1010000111011; - 7'b1001011: y = 13'b1010000100001; - 7'b1001100: y = 13'b1010000001000; - 7'b1001101: y = 13'b1001111101111; - 7'b1001110: y = 13'b1001111010111; - 7'b1001111: y = 13'b1001110111110; - 7'b1010000: y = 13'b1001110100110; - 7'b1010001: y = 13'b1001110001110; - 7'b1010010: y = 13'b1001101110110; - 7'b1010011: y = 13'b1001101011111; - 7'b1010100: y = 13'b1001101000111; - 7'b1010101: y = 13'b1001100110000; - 7'b1010110: y = 13'b1001100011001; - 7'b1010111: y = 13'b1001100000010; - 7'b1011000: y = 13'b1001011101100; - 7'b1011001: y = 13'b1001011010110; - 7'b1011010: y = 13'b1001011000000; - 7'b1011011: y = 13'b1001010101010; - 7'b1011100: y = 13'b1001010010100; - 7'b1011101: y = 13'b1001001111111; - 7'b1011110: y = 13'b1001001101001; - 7'b1011111: y = 13'b1001001010100; - 7'b1100000: y = 13'b1001000111111; - 7'b1100001: y = 13'b1001000101011; - 7'b1100010: y = 13'b1001000010110; - 7'b1100011: y = 13'b1001000000010; - 7'b1100100: y = 13'b1000111101110; - 7'b1100101: y = 13'b1000111011010; - 7'b1100110: y = 13'b1000111000110; - 7'b1100111: y = 13'b1000110110010; - 7'b1101000: y = 13'b1000110011111; - 7'b1101001: y = 13'b1000110001011; - 7'b1101010: y = 13'b1000101111000; - 7'b1101011: y = 13'b1000101100101; - 7'b1101100: y = 13'b1000101010010; - 7'b1101101: y = 13'b1000101000000; - 7'b1101110: y = 13'b1000100101101; - 7'b1101111: y = 13'b1000100011011; - 7'b1110000: y = 13'b1000100001001; - 7'b1110001: y = 13'b1000011110110; - 7'b1110010: y = 13'b1000011100101; - 7'b1110011: y = 13'b1000011010011; - 7'b1110100: y = 13'b1000011000001; - 7'b1110101: y = 13'b1000010110000; - 7'b1110110: y = 13'b1000010011110; - 7'b1110111: y = 13'b1000010001101; - 7'b1111000: y = 13'b1000001111100; - 7'b1111001: y = 13'b1000001101011; - 7'b1111010: y = 13'b1000001011010; - 7'b1111011: y = 13'b1000001001010; - 7'b1111100: y = 13'b1000000111001; - 7'b1111101: y = 13'b1000000101001; - 7'b1111110: y = 13'b1000000011001; - 7'b1111111: y = 13'b1000000001001; - default: y = 13'bxxxxxxxxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - diff --git a/pipelined/src/fpu/sbtm_a1.sv b/pipelined/src/fpu/sbtm_a1.sv deleted file mode 100644 index 60505b2e9..000000000 --- a/pipelined/src/fpu/sbtm_a1.sv +++ /dev/null @@ -1,170 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Bipartite Lookup -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module sbtm_a1 (input logic [6:0] a, - output logic [4:0] y); - - always_comb - case(a) - 7'b0000000: y = 5'b11100; - 7'b0000001: y = 5'b11000; - 7'b0000010: y = 5'b10100; - 7'b0000011: y = 5'b10000; - 7'b0000100: y = 5'b01101; - 7'b0000101: y = 5'b01001; - 7'b0000110: y = 5'b00101; - 7'b0000111: y = 5'b00001; - 7'b0001000: y = 5'b11001; - 7'b0001001: y = 5'b10101; - 7'b0001010: y = 5'b10010; - 7'b0001011: y = 5'b01111; - 7'b0001100: y = 5'b01011; - 7'b0001101: y = 5'b01000; - 7'b0001110: y = 5'b00101; - 7'b0001111: y = 5'b00001; - 7'b0010000: y = 5'b10110; - 7'b0010001: y = 5'b10011; - 7'b0010010: y = 5'b10000; - 7'b0010011: y = 5'b01101; - 7'b0010100: y = 5'b01010; - 7'b0010101: y = 5'b00111; - 7'b0010110: y = 5'b00100; - 7'b0010111: y = 5'b00001; - 7'b0011000: y = 5'b10100; - 7'b0011001: y = 5'b10001; - 7'b0011010: y = 5'b01110; - 7'b0011011: y = 5'b01100; - 7'b0011100: y = 5'b01001; - 7'b0011101: y = 5'b00110; - 7'b0011110: y = 5'b00100; - 7'b0011111: y = 5'b00001; - 7'b0100000: y = 5'b10010; - 7'b0100001: y = 5'b01111; - 7'b0100010: y = 5'b01101; - 7'b0100011: y = 5'b01010; - 7'b0100100: y = 5'b01000; - 7'b0100101: y = 5'b00110; - 7'b0100110: y = 5'b00011; - 7'b0100111: y = 5'b00001; - 7'b0101000: y = 5'b10000; - 7'b0101001: y = 5'b01110; - 7'b0101010: y = 5'b01100; - 7'b0101011: y = 5'b01001; - 7'b0101100: y = 5'b00111; - 7'b0101101: y = 5'b00101; - 7'b0101110: y = 5'b00011; - 7'b0101111: y = 5'b00001; - 7'b0110000: y = 5'b01111; - 7'b0110001: y = 5'b01101; - 7'b0110010: y = 5'b01011; - 7'b0110011: y = 5'b01001; - 7'b0110100: y = 5'b00111; - 7'b0110101: y = 5'b00101; - 7'b0110110: y = 5'b00011; - 7'b0110111: y = 5'b00001; - 7'b0111000: y = 5'b01101; - 7'b0111001: y = 5'b01100; - 7'b0111010: y = 5'b01010; - 7'b0111011: y = 5'b01000; - 7'b0111100: y = 5'b00110; - 7'b0111101: y = 5'b00100; - 7'b0111110: y = 5'b00010; - 7'b0111111: y = 5'b00000; - 7'b1000000: y = 5'b01100; - 7'b1000001: y = 5'b01011; - 7'b1000010: y = 5'b01001; - 7'b1000011: y = 5'b00111; - 7'b1000100: y = 5'b00101; - 7'b1000101: y = 5'b00100; - 7'b1000110: y = 5'b00010; - 7'b1000111: y = 5'b00000; - 7'b1001000: y = 5'b01011; - 7'b1001001: y = 5'b01010; - 7'b1001010: y = 5'b01000; - 7'b1001011: y = 5'b00111; - 7'b1001100: y = 5'b00101; - 7'b1001101: y = 5'b00011; - 7'b1001110: y = 5'b00010; - 7'b1001111: y = 5'b00000; - 7'b1010000: y = 5'b01010; - 7'b1010001: y = 5'b01001; - 7'b1010010: y = 5'b01000; - 7'b1010011: y = 5'b00110; - 7'b1010100: y = 5'b00101; - 7'b1010101: y = 5'b00011; - 7'b1010110: y = 5'b00010; - 7'b1010111: y = 5'b00000; - 7'b1011000: y = 5'b01010; - 7'b1011001: y = 5'b01000; - 7'b1011010: y = 5'b00111; - 7'b1011011: y = 5'b00110; - 7'b1011100: y = 5'b00100; - 7'b1011101: y = 5'b00011; - 7'b1011110: y = 5'b00010; - 7'b1011111: y = 5'b00000; - 7'b1100000: y = 5'b01001; - 7'b1100001: y = 5'b01000; - 7'b1100010: y = 5'b00110; - 7'b1100011: y = 5'b00101; - 7'b1100100: y = 5'b00100; - 7'b1100101: y = 5'b00011; - 7'b1100110: y = 5'b00001; - 7'b1100111: y = 5'b00000; - 7'b1101000: y = 5'b01000; - 7'b1101001: y = 5'b00111; - 7'b1101010: y = 5'b00110; - 7'b1101011: y = 5'b00101; - 7'b1101100: y = 5'b00100; - 7'b1101101: y = 5'b00010; - 7'b1101110: y = 5'b00001; - 7'b1101111: y = 5'b00000; - 7'b1110000: y = 5'b01000; - 7'b1110001: y = 5'b00111; - 7'b1110010: y = 5'b00110; - 7'b1110011: y = 5'b00100; - 7'b1110100: y = 5'b00011; - 7'b1110101: y = 5'b00010; - 7'b1110110: y = 5'b00001; - 7'b1110111: y = 5'b00000; - 7'b1111000: y = 5'b00111; - 7'b1111001: y = 5'b00110; - 7'b1111010: y = 5'b00101; - 7'b1111011: y = 5'b00100; - 7'b1111100: y = 5'b00011; - 7'b1111101: y = 5'b00010; - 7'b1111110: y = 5'b00001; - 7'b1111111: y = 5'b00000; - default: y = 5'bxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - diff --git a/pipelined/src/fpu/sbtm_a2.sv b/pipelined/src/fpu/sbtm_a2.sv deleted file mode 100755 index c54a994ea..000000000 --- a/pipelined/src/fpu/sbtm_a2.sv +++ /dev/null @@ -1,234 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Bipartite Lookup -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module sbtm_a2 (input logic [7:0] a, - output logic [13:0] y); - - always_comb - case(a) - 8'b01000000: y = 14'b10110100010111; - 8'b01000001: y = 14'b10110010111111; - 8'b01000010: y = 14'b10110001101000; - 8'b01000011: y = 14'b10110000010011; - 8'b01000100: y = 14'b10101111000001; - 8'b01000101: y = 14'b10101101110000; - 8'b01000110: y = 14'b10101100100001; - 8'b01000111: y = 14'b10101011010011; - 8'b01001000: y = 14'b10101010000111; - 8'b01001001: y = 14'b10101000111101; - 8'b01001010: y = 14'b10100111110100; - 8'b01001011: y = 14'b10100110101101; - 8'b01001100: y = 14'b10100101100111; - 8'b01001101: y = 14'b10100100100010; - 8'b01001110: y = 14'b10100011011111; - 8'b01001111: y = 14'b10100010011101; - 8'b01010000: y = 14'b10100001011100; - 8'b01010001: y = 14'b10100000011100; - 8'b01010010: y = 14'b10011111011110; - 8'b01010011: y = 14'b10011110100001; - 8'b01010100: y = 14'b10011101100100; - 8'b01010101: y = 14'b10011100101001; - 8'b01010110: y = 14'b10011011101111; - 8'b01010111: y = 14'b10011010110110; - 8'b01011000: y = 14'b10011001111110; - 8'b01011001: y = 14'b10011001000110; - 8'b01011010: y = 14'b10011000010000; - 8'b01011011: y = 14'b10010111011011; - 8'b01011100: y = 14'b10010110100110; - 8'b01011101: y = 14'b10010101110011; - 8'b01011110: y = 14'b10010101000000; - 8'b01011111: y = 14'b10010100001110; - 8'b01100000: y = 14'b10010011011100; - 8'b01100001: y = 14'b10010010101100; - 8'b01100010: y = 14'b10010001111100; - 8'b01100011: y = 14'b10010001001101; - 8'b01100100: y = 14'b10010000011111; - 8'b01100101: y = 14'b10001111110001; - 8'b01100110: y = 14'b10001111000100; - 8'b01100111: y = 14'b10001110011000; - 8'b01101000: y = 14'b10001101101100; - 8'b01101001: y = 14'b10001101000001; - 8'b01101010: y = 14'b10001100010110; - 8'b01101011: y = 14'b10001011101100; - 8'b01101100: y = 14'b10001011000011; - 8'b01101101: y = 14'b10001010011010; - 8'b01101110: y = 14'b10001001110010; - 8'b01101111: y = 14'b10001001001010; - 8'b01110000: y = 14'b10001000100011; - 8'b01110001: y = 14'b10000111111101; - 8'b01110010: y = 14'b10000111010111; - 8'b01110011: y = 14'b10000110110001; - 8'b01110100: y = 14'b10000110001100; - 8'b01110101: y = 14'b10000101100111; - 8'b01110110: y = 14'b10000101000011; - 8'b01110111: y = 14'b10000100011111; - 8'b01111000: y = 14'b10000011111100; - 8'b01111001: y = 14'b10000011011001; - 8'b01111010: y = 14'b10000010110111; - 8'b01111011: y = 14'b10000010010101; - 8'b01111100: y = 14'b10000001110011; - 8'b01111101: y = 14'b10000001010010; - 8'b01111110: y = 14'b10000000110001; - 8'b01111111: y = 14'b10000000010001; - 8'b10000000: y = 14'b01111111110001; - 8'b10000001: y = 14'b01111111010001; - 8'b10000010: y = 14'b01111110110010; - 8'b10000011: y = 14'b01111110010011; - 8'b10000100: y = 14'b01111101110101; - 8'b10000101: y = 14'b01111101010110; - 8'b10000110: y = 14'b01111100111001; - 8'b10000111: y = 14'b01111100011011; - 8'b10001000: y = 14'b01111011111110; - 8'b10001001: y = 14'b01111011100001; - 8'b10001010: y = 14'b01111011000100; - 8'b10001011: y = 14'b01111010101000; - 8'b10001100: y = 14'b01111010001100; - 8'b10001101: y = 14'b01111001110000; - 8'b10001110: y = 14'b01111001010101; - 8'b10001111: y = 14'b01111000111010; - 8'b10010000: y = 14'b01111000011111; - 8'b10010001: y = 14'b01111000000100; - 8'b10010010: y = 14'b01110111101010; - 8'b10010011: y = 14'b01110111010000; - 8'b10010100: y = 14'b01110110110110; - 8'b10010101: y = 14'b01110110011101; - 8'b10010110: y = 14'b01110110000100; - 8'b10010111: y = 14'b01110101101011; - 8'b10011000: y = 14'b01110101010010; - 8'b10011001: y = 14'b01110100111001; - 8'b10011010: y = 14'b01110100100001; - 8'b10011011: y = 14'b01110100001001; - 8'b10011100: y = 14'b01110011110001; - 8'b10011101: y = 14'b01110011011010; - 8'b10011110: y = 14'b01110011000010; - 8'b10011111: y = 14'b01110010101011; - 8'b10100000: y = 14'b01110010010100; - 8'b10100001: y = 14'b01110001111110; - 8'b10100010: y = 14'b01110001100111; - 8'b10100011: y = 14'b01110001010001; - 8'b10100100: y = 14'b01110000111011; - 8'b10100101: y = 14'b01110000100101; - 8'b10100110: y = 14'b01110000001111; - 8'b10100111: y = 14'b01101111111010; - 8'b10101000: y = 14'b01101111100101; - 8'b10101001: y = 14'b01101111010000; - 8'b10101010: y = 14'b01101110111011; - 8'b10101011: y = 14'b01101110100110; - 8'b10101100: y = 14'b01101110010001; - 8'b10101101: y = 14'b01101101111101; - 8'b10101110: y = 14'b01101101101001; - 8'b10101111: y = 14'b01101101010101; - 8'b10110000: y = 14'b01101101000001; - 8'b10110001: y = 14'b01101100101101; - 8'b10110010: y = 14'b01101100011010; - 8'b10110011: y = 14'b01101100000110; - 8'b10110100: y = 14'b01101011110011; - 8'b10110101: y = 14'b01101011100000; - 8'b10110110: y = 14'b01101011001101; - 8'b10110111: y = 14'b01101010111010; - 8'b10111000: y = 14'b01101010101000; - 8'b10111001: y = 14'b01101010010101; - 8'b10111010: y = 14'b01101010000011; - 8'b10111011: y = 14'b01101001110001; - 8'b10111100: y = 14'b01101001011111; - 8'b10111101: y = 14'b01101001001101; - 8'b10111110: y = 14'b01101000111100; - 8'b10111111: y = 14'b01101000101010; - 8'b11000000: y = 14'b01101000011001; - 8'b11000001: y = 14'b01101000000111; - 8'b11000010: y = 14'b01100111110110; - 8'b11000011: y = 14'b01100111100101; - 8'b11000100: y = 14'b01100111010100; - 8'b11000101: y = 14'b01100111000011; - 8'b11000110: y = 14'b01100110110011; - 8'b11000111: y = 14'b01100110100010; - 8'b11001000: y = 14'b01100110010010; - 8'b11001001: y = 14'b01100110000010; - 8'b11001010: y = 14'b01100101110010; - 8'b11001011: y = 14'b01100101100001; - 8'b11001100: y = 14'b01100101010010; - 8'b11001101: y = 14'b01100101000010; - 8'b11001110: y = 14'b01100100110010; - 8'b11001111: y = 14'b01100100100011; - 8'b11010000: y = 14'b01100100010011; - 8'b11010001: y = 14'b01100100000100; - 8'b11010010: y = 14'b01100011110101; - 8'b11010011: y = 14'b01100011100101; - 8'b11010100: y = 14'b01100011010110; - 8'b11010101: y = 14'b01100011000111; - 8'b11010110: y = 14'b01100010111001; - 8'b11010111: y = 14'b01100010101010; - 8'b11011000: y = 14'b01100010011011; - 8'b11011001: y = 14'b01100010001101; - 8'b11011010: y = 14'b01100001111110; - 8'b11011011: y = 14'b01100001110000; - 8'b11011100: y = 14'b01100001100010; - 8'b11011101: y = 14'b01100001010100; - 8'b11011110: y = 14'b01100001000110; - 8'b11011111: y = 14'b01100000111000; - 8'b11100000: y = 14'b01100000101010; - 8'b11100001: y = 14'b01100000011100; - 8'b11100010: y = 14'b01100000001111; - 8'b11100011: y = 14'b01100000000001; - 8'b11100100: y = 14'b01011111110100; - 8'b11100101: y = 14'b01011111100110; - 8'b11100110: y = 14'b01011111011001; - 8'b11100111: y = 14'b01011111001100; - 8'b11101000: y = 14'b01011110111111; - 8'b11101001: y = 14'b01011110110010; - 8'b11101010: y = 14'b01011110100101; - 8'b11101011: y = 14'b01011110011000; - 8'b11101100: y = 14'b01011110001011; - 8'b11101101: y = 14'b01011101111110; - 8'b11101110: y = 14'b01011101110010; - 8'b11101111: y = 14'b01011101100101; - 8'b11110000: y = 14'b01011101011001; - 8'b11110001: y = 14'b01011101001100; - 8'b11110010: y = 14'b01011101000000; - 8'b11110011: y = 14'b01011100110100; - 8'b11110100: y = 14'b01011100101000; - 8'b11110101: y = 14'b01011100011100; - 8'b11110110: y = 14'b01011100010000; - 8'b11110111: y = 14'b01011100000100; - 8'b11111000: y = 14'b01011011111000; - 8'b11111001: y = 14'b01011011101100; - 8'b11111010: y = 14'b01011011100000; - 8'b11111011: y = 14'b01011011010101; - 8'b11111100: y = 14'b01011011001001; - 8'b11111101: y = 14'b01011010111101; - 8'b11111110: y = 14'b01011010110010; - 8'b11111111: y = 14'b01011010100111; - default: y = 14'bxxxxxxxxxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 - - - - diff --git a/pipelined/src/fpu/sbtm_a3.sv b/pipelined/src/fpu/sbtm_a3.sv deleted file mode 100755 index 0f3c6e647..000000000 --- a/pipelined/src/fpu/sbtm_a3.sv +++ /dev/null @@ -1,230 +0,0 @@ -/////////////////////////////////////////// -// -// Written: James Stine -// Modified: 8/1/2018 -// -// Purpose: Bipartite Lookup -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -module sbtm_a3 (input logic [7:0] a, - output logic [5:0] y); - - always_comb - case(a) - 8'b01000000: y = 6'b100110; - 8'b01000001: y = 6'b100001; - 8'b01000010: y = 6'b011100; - 8'b01000011: y = 6'b010111; - 8'b01000100: y = 6'b010010; - 8'b01000101: y = 6'b001100; - 8'b01000110: y = 6'b000111; - 8'b01000111: y = 6'b000010; - 8'b01001000: y = 6'b100000; - 8'b01001001: y = 6'b011100; - 8'b01001010: y = 6'b011000; - 8'b01001011: y = 6'b010011; - 8'b01001100: y = 6'b001111; - 8'b01001101: y = 6'b001010; - 8'b01001110: y = 6'b000110; - 8'b01001111: y = 6'b000010; - 8'b01010000: y = 6'b011100; - 8'b01010001: y = 6'b011000; - 8'b01010010: y = 6'b010100; - 8'b01010011: y = 6'b010000; - 8'b01010100: y = 6'b001101; - 8'b01010101: y = 6'b001001; - 8'b01010110: y = 6'b000101; - 8'b01010111: y = 6'b000001; - 8'b01011000: y = 6'b011000; - 8'b01011001: y = 6'b010101; - 8'b01011010: y = 6'b010010; - 8'b01011011: y = 6'b001110; - 8'b01011100: y = 6'b001011; - 8'b01011101: y = 6'b001000; - 8'b01011110: y = 6'b000100; - 8'b01011111: y = 6'b000001; - 8'b01100000: y = 6'b010101; - 8'b01100001: y = 6'b010010; - 8'b01100010: y = 6'b001111; - 8'b01100011: y = 6'b001101; - 8'b01100100: y = 6'b001010; - 8'b01100101: y = 6'b000111; - 8'b01100110: y = 6'b000100; - 8'b01100111: y = 6'b000001; - 8'b01101000: y = 6'b010011; - 8'b01101001: y = 6'b010000; - 8'b01101010: y = 6'b001110; - 8'b01101011: y = 6'b001011; - 8'b01101100: y = 6'b001001; - 8'b01101101: y = 6'b000110; - 8'b01101110: y = 6'b000011; - 8'b01101111: y = 6'b000001; - 8'b01110000: y = 6'b010001; - 8'b01110001: y = 6'b001111; - 8'b01110010: y = 6'b001100; - 8'b01110011: y = 6'b001010; - 8'b01110100: y = 6'b001000; - 8'b01110101: y = 6'b000101; - 8'b01110110: y = 6'b000011; - 8'b01110111: y = 6'b000001; - 8'b01111000: y = 6'b001111; - 8'b01111001: y = 6'b001101; - 8'b01111010: y = 6'b001011; - 8'b01111011: y = 6'b001001; - 8'b01111100: y = 6'b000111; - 8'b01111101: y = 6'b000101; - 8'b01111110: y = 6'b000011; - 8'b01111111: y = 6'b000001; - 8'b10000000: y = 6'b001110; - 8'b10000001: y = 6'b001100; - 8'b10000010: y = 6'b001010; - 8'b10000011: y = 6'b001000; - 8'b10000100: y = 6'b000110; - 8'b10000101: y = 6'b000100; - 8'b10000110: y = 6'b000010; - 8'b10000111: y = 6'b000000; - 8'b10001000: y = 6'b001101; - 8'b10001001: y = 6'b001011; - 8'b10001010: y = 6'b001001; - 8'b10001011: y = 6'b000111; - 8'b10001100: y = 6'b000110; - 8'b10001101: y = 6'b000100; - 8'b10001110: y = 6'b000010; - 8'b10001111: y = 6'b000000; - 8'b10010000: y = 6'b001100; - 8'b10010001: y = 6'b001010; - 8'b10010010: y = 6'b001000; - 8'b10010011: y = 6'b000111; - 8'b10010100: y = 6'b000101; - 8'b10010101: y = 6'b000100; - 8'b10010110: y = 6'b000010; - 8'b10010111: y = 6'b000000; - 8'b10011000: y = 6'b001011; - 8'b10011001: y = 6'b001001; - 8'b10011010: y = 6'b001000; - 8'b10011011: y = 6'b000110; - 8'b10011100: y = 6'b000101; - 8'b10011101: y = 6'b000011; - 8'b10011110: y = 6'b000010; - 8'b10011111: y = 6'b000000; - 8'b10100000: y = 6'b001010; - 8'b10100001: y = 6'b001000; - 8'b10100010: y = 6'b000111; - 8'b10100011: y = 6'b000110; - 8'b10100100: y = 6'b000100; - 8'b10100101: y = 6'b000011; - 8'b10100110: y = 6'b000010; - 8'b10100111: y = 6'b000000; - 8'b10101000: y = 6'b001001; - 8'b10101001: y = 6'b001000; - 8'b10101010: y = 6'b000111; - 8'b10101011: y = 6'b000101; - 8'b10101100: y = 6'b000100; - 8'b10101101: y = 6'b000011; - 8'b10101110: y = 6'b000001; - 8'b10101111: y = 6'b000000; - 8'b10110000: y = 6'b001000; - 8'b10110001: y = 6'b000111; - 8'b10110010: y = 6'b000110; - 8'b10110011: y = 6'b000101; - 8'b10110100: y = 6'b000100; - 8'b10110101: y = 6'b000010; - 8'b10110110: y = 6'b000001; - 8'b10110111: y = 6'b000000; - 8'b10111000: y = 6'b001000; - 8'b10111001: y = 6'b000111; - 8'b10111010: y = 6'b000110; - 8'b10111011: y = 6'b000101; - 8'b10111100: y = 6'b000011; - 8'b10111101: y = 6'b000010; - 8'b10111110: y = 6'b000001; - 8'b10111111: y = 6'b000000; - 8'b11000000: y = 6'b000111; - 8'b11000001: y = 6'b000110; - 8'b11000010: y = 6'b000101; - 8'b11000011: y = 6'b000100; - 8'b11000100: y = 6'b000011; - 8'b11000101: y = 6'b000010; - 8'b11000110: y = 6'b000001; - 8'b11000111: y = 6'b000000; - 8'b11001000: y = 6'b000111; - 8'b11001001: y = 6'b000110; - 8'b11001010: y = 6'b000101; - 8'b11001011: y = 6'b000100; - 8'b11001100: y = 6'b000011; - 8'b11001101: y = 6'b000010; - 8'b11001110: y = 6'b000001; - 8'b11001111: y = 6'b000000; - 8'b11010000: y = 6'b000111; - 8'b11010001: y = 6'b000110; - 8'b11010010: y = 6'b000101; - 8'b11010011: y = 6'b000100; - 8'b11010100: y = 6'b000011; - 8'b11010101: y = 6'b000010; - 8'b11010110: y = 6'b000001; - 8'b11010111: y = 6'b000000; - 8'b11011000: y = 6'b000110; - 8'b11011001: y = 6'b000101; - 8'b11011010: y = 6'b000100; - 8'b11011011: y = 6'b000011; - 8'b11011100: y = 6'b000011; - 8'b11011101: y = 6'b000010; - 8'b11011110: y = 6'b000001; - 8'b11011111: y = 6'b000000; - 8'b11100000: y = 6'b000110; - 8'b11100001: y = 6'b000101; - 8'b11100010: y = 6'b000100; - 8'b11100011: y = 6'b000011; - 8'b11100100: y = 6'b000010; - 8'b11100101: y = 6'b000010; - 8'b11100110: y = 6'b000001; - 8'b11100111: y = 6'b000000; - 8'b11101000: y = 6'b000101; - 8'b11101001: y = 6'b000101; - 8'b11101010: y = 6'b000100; - 8'b11101011: y = 6'b000011; - 8'b11101100: y = 6'b000010; - 8'b11101101: y = 6'b000001; - 8'b11101110: y = 6'b000001; - 8'b11101111: y = 6'b000000; - 8'b11110000: y = 6'b000101; - 8'b11110001: y = 6'b000100; - 8'b11110010: y = 6'b000100; - 8'b11110011: y = 6'b000011; - 8'b11110100: y = 6'b000010; - 8'b11110101: y = 6'b000001; - 8'b11110110: y = 6'b000001; - 8'b11110111: y = 6'b000000; - 8'b11111000: y = 6'b000101; - 8'b11111001: y = 6'b000100; - 8'b11111010: y = 6'b000011; - 8'b11111011: y = 6'b000011; - 8'b11111100: y = 6'b000010; - 8'b11111101: y = 6'b000001; - 8'b11111110: y = 6'b000001; - 8'b11111111: y = 6'b000000; - default: y = 6'bxxxxxx; - endcase // case (a) - -endmodule // sbtm_a0 diff --git a/pipelined/src/fpu/shiftcorrection.sv b/pipelined/src/fpu/shiftcorrection.sv new file mode 100644 index 000000000..4839ba29e --- /dev/null +++ b/pipelined/src/fpu/shiftcorrection.sv @@ -0,0 +1,70 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: shift correction +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module shiftcorrection( + input logic [`NORMSHIFTSZ-1:0] Shifted, // the shifted sum before LZA correction + input logic FmaOp, + input logic DivOp, + input logic DivResDenorm, + input logic [`NE+1:0] DivQe, + input logic [`NE+1:0] DivDenormShift, + input logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results + input logic FmaPreResultDenorm, // is the result denormalized - calculated before LZA corection + input logic FmaSZero, + output logic [`CORRSHIFTSZ-1:0] Mf, // the shifted sum before LZA correction + output logic [`NE+1:0] Qe, + output logic [`NE+1:0] FmaMe // exponent of the normalized sum +); + logic [3*`NF+5:0] CorrSumShifted; // the shifted sum after LZA correction + logic [`CORRSHIFTSZ-1:0] CorrQmShifted; + logic ResDenorm; // is the result denormalized + logic LZAPlus1; // add one or two to the sum's exponent due to LZA correction + + // LZA correction + assign LZAPlus1 = Shifted[`NORMSHIFTSZ-1]; + // the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone + assign CorrSumShifted = LZAPlus1 ? Shifted[`NORMSHIFTSZ-2:1] : Shifted[`NORMSHIFTSZ-3:0]; + // if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Denorm) + assign CorrQmShifted = (LZAPlus1|(DivQe==1&~LZAPlus1)) ? Shifted[`NORMSHIFTSZ-2:`NORMSHIFTSZ-`CORRSHIFTSZ-1] : Shifted[`NORMSHIFTSZ-3:`NORMSHIFTSZ-`CORRSHIFTSZ-2]; + // if the result of the divider was calculated to be denormalized, then the result was correctly normalized, so select the top shifted bits + always_comb + if(FmaOp) Mf = {CorrSumShifted, {`CORRSHIFTSZ-(3*`NF+6){1'b0}}}; + else if (DivOp&~DivResDenorm) Mf = CorrQmShifted; + else Mf = Shifted[`NORMSHIFTSZ-1:`NORMSHIFTSZ-`CORRSHIFTSZ]; + // Determine sum's exponent + // if plus1 If plus2 if said denorm but norm plus 1 if said denorm but norm plus 2 + assign FmaMe = (NormSumExp+{{`NE+1{1'b0}}, LZAPlus1} +{{`NE+1{1'b0}}, ~ResDenorm&FmaPreResultDenorm}) & {`NE+2{~(FmaSZero|ResDenorm)}}; + // recalculate if the result is denormalized + assign ResDenorm = FmaPreResultDenorm&~Shifted[`NORMSHIFTSZ-2]&~Shifted[`NORMSHIFTSZ-1]; + + // the quotent is in the range [.5,2) if there is no early termination + // if the quotent < 1 and not denormal then subtract 1 to account for the normalization shift + assign Qe = ((DivResDenorm)&~DivDenormShift[`NE+1]) ? (`NE+2)'(0) : DivQe - {(`NE+1)'(0), ~LZAPlus1}; +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/shifter_denorm.sv b/pipelined/src/fpu/shifter_denorm.sv deleted file mode 100755 index b354433f9..000000000 --- a/pipelined/src/fpu/shifter_denorm.sv +++ /dev/null @@ -1,164 +0,0 @@ - -// MJS - This module implements a 57-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand alignment. - -module mux21x57 (Z, A, B, Sel); - - input [56:0] A; - input [56:0] B; - input Sel; - - output [56:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x57 - -// MJS - This module implements a 64-bit 2-to-1 multiplexor, which is -// used in the barrel shifter for significand normalization. - -module mux21x64 (Z, A, B, Sel); - - input [63:0] A; - input [63:0] B; - input Sel; - - output [63:0] Z; - - assign Z = Sel ? B : A; - -endmodule // mux21x64 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 64-bit 2-to-1 muxes. The -// barrel shifter takes a 64-bit input A and shifts it left by up to -// 63-bits, as specified by Shift, to produce a 63-bit output Z. -// Bits to the right are filled with zeros. -// The 64 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bit shifts. - -module barrel_shifter_l64 (Z, A, Shift); - - input [63:0] A; - input [5:0] Shift; - - wire [63:0] stage1; - wire [63:0] stage2; - wire [63:0] stage3; - wire [63:0] stage4; - wire [63:0] stage5; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - - output [63:0] Z; - - mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]); - mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]); - mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]); - mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]); - mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]); - mux21x64 mx06(Z , stage5, {stage5[62:0], onezero}, Shift[0]); - -endmodule // barrel_shifter_l63 - -// The implementation of the barrel shifter was modified to use -// fewer gates. It is now implemented using six 57-bit 2-to-1 muxes. The -// barrel shifter takes a 57-bit input A and right shifts it by up to -// 63-bits, as specified by Shift, to produce a 57-bit output Z. -// It also computes a Sticky bit, which is set to -// one if any of the bits that were shifted out was one. -// Bits shifted into the left are filled with zeros. -// The 63 bit shift is implemented using 6 stages of shifts of 32 -// 16, 8, 4, 2, and 1 bits. - -module barrel_shifter_r57 (Z, Sticky, A, Shift); - - input [56:0] A; - input [5:0] Shift; - - output Sticky; - output [56:0] Z; - - wire [56:0] stage1; - wire [56:0] stage2; - wire [56:0] stage3; - wire [56:0] stage4; - wire [56:0] stage5; - wire [62:0] sixtythreezeros = 63'h0; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - wire [62:0] S; - - // Shift operations - mux21x57 mx01(stage1, A, {thirtytwozeros, A[56:32]}, Shift[5]); - mux21x57 mx02(stage2, stage1, {sixteenzeros, stage1[56:16]}, Shift[4]); - mux21x57 mx03(stage3, stage2, {eightzeros, stage2[56:8]}, Shift[3]); - mux21x57 mx04(stage4, stage3, {fourzeros, stage3[56:4]}, Shift[2]); - mux21x57 mx05(stage5, stage4, {twozeros, stage4[56:2]}, Shift[1]); - mux21x57 mx06(Z , stage5, {onezero, stage5[56:1]}, Shift[0]); - - // Sticky bit calculation. The Sticky bit is set to one if any of the - // bits that were shifter out were one - - assign S[31:0] = {32{Shift[5]}} & A[31:0]; - assign S[47:32] = {16{Shift[4]}} & stage1[15:0]; - assign S[55:48] = { 8{Shift[3]}} & stage2[7:0]; - assign S[59:56] = { 4{Shift[2]}} & stage3[3:0]; - assign S[61:60] = { 2{Shift[1]}} & stage4[1:0]; - assign S[62] = Shift[0] & stage5[0]; - assign Sticky = (S != sixtythreezeros); - -endmodule // barrel_shifter_r57 - -/* -module barrel_shifter_r64 (Z, Sticky, A, Shift); - - input [63:0] A; - input [5:0] Shift; - - output Sticky; - output [63:0] Z; - - wire [63:0] stage1; - wire [63:0] stage2; - wire [63:0] stage3; - wire [63:0] stage4; - wire [63:0] stage5; - wire [62:0] sixtythreezeros = 63'h0; - wire [31:0] thirtytwozeros = 32'h0; - wire [15:0] sixteenzeros = 16'h0; - wire [ 7:0] eightzeros = 8'h0; - wire [ 3:0] fourzeros = 4'h0; - wire [ 1:0] twozeros = 2'b00; - wire onezero = 1'b0; - wire [62:0] S; - - // Shift operations - mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]); - mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]); - mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]); - mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]); - mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]); - mux21x64 mx06(Z , stage5, {onezero, stage5[63:1]}, Shift[0]); - - // Sticky bit calculation. The Sticky bit is set to one if any of the - // bits that were shifter out were one - - assign S[31:0] = {32{Shift[5]}} & A[31:0]; - assign S[47:32] = {16{Shift[4]}} & stage1[15:0]; - assign S[55:48] = { 8{Shift[3]}} & stage2[7:0]; - assign S[59:56] = { 4{Shift[2]}} & stage3[3:0]; - assign S[61:60] = { 2{Shift[1]}} & stage4[1:0]; - assign S[62] = Shift[0] & stage5[0]; - assign Sticky = (S != sixtythreezeros); - -endmodule // barrel_shifter_r64 -*/ \ No newline at end of file diff --git a/pipelined/src/fpu/specialcase.sv b/pipelined/src/fpu/specialcase.sv new file mode 100644 index 000000000..41e75110f --- /dev/null +++ b/pipelined/src/fpu/specialcase.sv @@ -0,0 +1,307 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: special case selection +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module specialcase( + input logic Xs, // input signs + input logic [`NF:0] Xm, Ym, Zm, // input mantissas + input logic XNaN, YNaN, ZNaN, // inputs are NaN + input logic [2:0] Frm, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude + input logic [`FMTBITS-1:0] OutFmt, // output format + input logic InfIn, + input logic NaNIn, + input logic XInf, YInf, + input logic XZero, + input logic IntZero, + input logic IntToFp, + input logic Int64, + input logic Signed, + input logic CvtOp, + input logic DivOp, + input logic FmaOp, + input logic Plus1, + input logic DivByZero, + input logic [`NE:0] CvtCe, // the calculated expoent + input logic Ws, // the res's sign + input logic IntInvalid, Invalid, Overflow, // flags + input logic CvtResUf, + input logic [`NE-1:0] Re, // Res exponent + input logic [`NE+1:0] FullRe, // Res exponent + input logic [`NF-1:0] Rf, // Res fraction + input logic [`XLEN+1:0] CvtNegRes, // the negation of the result + output logic [`FLEN-1:0] PostProcRes, // final res + output logic [`XLEN-1:0] FCvtIntRes // final res +); + logic [`FLEN-1:0] XNaNRes, YNaNRes, ZNaNRes, InvalidRes, OfRes, UfRes, NormRes; // possible results + logic OfResMax; + logic [`XLEN-1:0] OfIntRes; // the overflow result for integer output + logic KillRes; + logic SelOfRes; + + + // does the overflow result output the maximum normalized floating point number + // output infinity if the input is infinity + assign OfResMax = (~InfIn|(IntToFp&CvtOp))&~DivByZero&((Frm[1:0]==2'b01) | (Frm[1:0]==2'b10&~Ws) | (Frm[1:0]==2'b11&Ws)); + + if (`FPSIZES == 1) begin + + //NaN res selection depending on standard + if(`IEEE754) begin + assign XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]}; + assign YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]}; + assign ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]}; + assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + assign InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + + assign OfRes = OfResMax ? {Ws, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Ws, {`NE{1'b1}}, {`NF{1'b0}}}; + assign UfRes = {Ws, {`FLEN-2{1'b0}}, Plus1&Frm[1]&~(DivOp&YInf)}; + assign NormRes = {Ws, Re, Rf}; + + end else if (`FPSIZES == 2) begin //will the format conversion in killprod work in other conversions? + if(`IEEE754) begin + assign XNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]}; + assign YNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]}; + assign ZNaNRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]}; + assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end else begin + assign InvalidRes = OutFmt ? {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end + + always_comb + if(OutFmt) + if(OfResMax) OfRes = {Ws, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}}; + else OfRes = {Ws, {`NE{1'b1}}, {`NF{1'b0}}}; + else + if(OfResMax) OfRes = {{`FLEN-`LEN1{1'b1}}, Ws, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}}; + else OfRes = {{`FLEN-`LEN1{1'b1}}, Ws, {`NE1{1'b1}}, (`NF1)'(0)}; + assign UfRes = OutFmt ? {Ws, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)} : {{`FLEN-`LEN1{1'b1}}, Ws, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + assign NormRes = OutFmt ? {Ws, Re, Rf} : {{`FLEN-`LEN1{1'b1}}, Ws, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]}; + + end else if (`FPSIZES == 3) begin + always_comb + case (OutFmt) + `FMT: begin + if(`IEEE754) begin + XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]}; + YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]}; + ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]}; + InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + + OfRes = OfResMax ? {Ws, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Ws, {`NE{1'b1}}, {`NF{1'b0}}}; + UfRes = {Ws, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {Ws, Re, Rf}; + end + `FMT1: begin + if(`IEEE754) begin + XNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF1]}; + YNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF1]}; + ZNaNRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF1]}; + InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end else begin + InvalidRes = {{`FLEN-`LEN1{1'b1}}, 1'b0, {`NE1{1'b1}}, 1'b1, (`NF1-1)'(0)}; + end + OfRes = OfResMax ? {{`FLEN-`LEN1{1'b1}}, Ws, {`NE1-1{1'b1}}, 1'b0, {`NF1{1'b1}}} : {{`FLEN-`LEN1{1'b1}}, Ws, {`NE1{1'b1}}, (`NF1)'(0)}; + UfRes = {{`FLEN-`LEN1{1'b1}}, Ws, (`LEN1-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {{`FLEN-`LEN1{1'b1}}, Ws, Re[`NE1-1:0], Rf[`NF-1:`NF-`NF1]}; + end + `FMT2: begin + if(`IEEE754) begin + XNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Xm[`NF-2:`NF-`NF2]}; + YNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Ym[`NF-2:`NF-`NF2]}; + ZNaNRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, Zm[`NF-2:`NF-`NF2]}; + InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + end else begin + InvalidRes = {{`FLEN-`LEN2{1'b1}}, 1'b0, {`NE2{1'b1}}, 1'b1, (`NF2-1)'(0)}; + end + + OfRes = OfResMax ? {{`FLEN-`LEN2{1'b1}}, Ws, {`NE2-1{1'b1}}, 1'b0, {`NF2{1'b1}}} : {{`FLEN-`LEN2{1'b1}}, Ws, {`NE2{1'b1}}, (`NF2)'(0)}; + UfRes = {{`FLEN-`LEN2{1'b1}}, Ws, (`LEN2-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {{`FLEN-`LEN2{1'b1}}, Ws, Re[`NE2-1:0], Rf[`NF-1:`NF-`NF2]}; + end + default: begin + if(`IEEE754) begin + XNaNRes = (`FLEN)'(0); + YNaNRes = (`FLEN)'(0); + ZNaNRes = (`FLEN)'(0); + InvalidRes = (`FLEN)'(0); + end else begin + InvalidRes = (`FLEN)'(0); + end + OfRes = (`FLEN)'(0); + UfRes = (`FLEN)'(0); + NormRes = (`FLEN)'(0); + end + endcase + + end else if (`FPSIZES == 4) begin + always_comb + case (OutFmt) + 2'h3: begin + if(`IEEE754) begin + XNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Xm[`NF-2:0]}; + YNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Ym[`NF-2:0]}; + ZNaNRes = {1'b0, {`NE{1'b1}}, 1'b1, Zm[`NF-2:0]}; + InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end else begin + InvalidRes = {1'b0, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}}; + end + + OfRes = OfResMax ? {Ws, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} : {Ws, {`NE{1'b1}}, {`NF{1'b0}}}; + UfRes = {Ws, (`FLEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {Ws, Re, Rf}; + end + 2'h1: begin + if(`IEEE754) begin + XNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`D_NF]}; + YNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`D_NF]}; + ZNaNRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`D_NF]}; + InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + end else begin + InvalidRes = {{`FLEN-`D_LEN{1'b1}}, 1'b0, {`D_NE{1'b1}}, 1'b1, (`D_NF-1)'(0)}; + end + OfRes = OfResMax ? {{`FLEN-`D_LEN{1'b1}}, Ws, {`D_NE-1{1'b1}}, 1'b0, {`D_NF{1'b1}}} : {{`FLEN-`D_LEN{1'b1}}, Ws, {`D_NE{1'b1}}, (`D_NF)'(0)}; + UfRes = {{`FLEN-`D_LEN{1'b1}}, Ws, (`D_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {{`FLEN-`D_LEN{1'b1}}, Ws, Re[`D_NE-1:0], Rf[`NF-1:`NF-`D_NF]}; + end + 2'h0: begin + if(`IEEE754) begin + XNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`S_NF]}; + YNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`S_NF]}; + ZNaNRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`S_NF]}; + InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + end else begin + InvalidRes = {{`FLEN-`S_LEN{1'b1}}, 1'b0, {`S_NE{1'b1}}, 1'b1, (`S_NF-1)'(0)}; + end + + OfRes = OfResMax ? {{`FLEN-`S_LEN{1'b1}}, Ws, {`S_NE-1{1'b1}}, 1'b0, {`S_NF{1'b1}}} : {{`FLEN-`S_LEN{1'b1}}, Ws, {`S_NE{1'b1}}, (`S_NF)'(0)}; + UfRes = {{`FLEN-`S_LEN{1'b1}}, Ws, (`S_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {{`FLEN-`S_LEN{1'b1}}, Ws, Re[`S_NE-1:0], Rf[`NF-1:`NF-`S_NF]}; + end + 2'h2: begin + if(`IEEE754) begin + XNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Xm[`NF-2:`NF-`H_NF]}; + YNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Ym[`NF-2:`NF-`H_NF]}; + ZNaNRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, Zm[`NF-2:`NF-`H_NF]}; + InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + end else begin + InvalidRes = {{`FLEN-`H_LEN{1'b1}}, 1'b0, {`H_NE{1'b1}}, 1'b1, (`H_NF-1)'(0)}; + end + + OfRes = OfResMax ? {{`FLEN-`H_LEN{1'b1}}, Ws, {`H_NE-1{1'b1}}, 1'b0, {`H_NF{1'b1}}} : {{`FLEN-`H_LEN{1'b1}}, Ws, {`H_NE{1'b1}}, (`H_NF)'(0)}; + // zero is exact fi dividing by infinity so don't add 1 + UfRes = {{`FLEN-`H_LEN{1'b1}}, Ws, (`H_LEN-2)'(0), Plus1&Frm[1]&~(DivOp&YInf)}; + NormRes = {{`FLEN-`H_LEN{1'b1}}, Ws, Re[`H_NE-1:0], Rf[`NF-1:`NF-`H_NF]}; + end + endcase + + end + + + + + + // determine if you shoould kill the res - Cvt + // - do so if the res underflows, is zero (the exp doesnt calculate correctly). or the integer input is 0 + // - dont set to zero if fp input is zero but not using the fp input + // - dont set to zero if int input is zero but not using the int input + assign KillRes = CvtOp ? (CvtResUf|(XZero&~IntToFp)|(IntZero&IntToFp)) : FullRe[`NE+1] | (((YInf&~XInf)|XZero)&DivOp);//Underflow & ~ResDenorm & (Re!=1); + assign SelOfRes = Overflow|DivByZero|(InfIn&~(YInf&DivOp)); + // output infinity with result sign if divide by zero + if(`IEEE754) + always_comb + if(XNaN&~(IntToFp&CvtOp)) PostProcRes = XNaNRes; + else if(YNaN&~CvtOp) PostProcRes = YNaNRes; + else if(ZNaN&FmaOp) PostProcRes = ZNaNRes; + else if(Invalid) PostProcRes = InvalidRes; + else if(SelOfRes) PostProcRes = OfRes; + else if(KillRes) PostProcRes = UfRes; + else PostProcRes = NormRes; + else + always_comb + if(NaNIn|Invalid) PostProcRes = InvalidRes; + else if(SelOfRes) PostProcRes = OfRes; + else if(KillRes) PostProcRes = UfRes; + else PostProcRes = NormRes; + + /////////////////////////////////////////////////////////////////////////////////////// + // + // ||||||||||| ||| ||| ||||||||||||| + // ||| |||||| ||| ||| + // ||| ||| ||| ||| ||| + // ||| ||| |||||| ||| + // ||||||||||| ||| ||| ||| + // + /////////////////////////////////////////////////////////////////////////////////////// + + // *** probably can optimize the negation + // select the overflow integer res + // - negitive infinity and out of range negitive input + // | int | long | + // signed | -2^31 | -2^63 | + // unsigned | 0 | 0 | + // + // - positive infinity and out of range positive input and NaNs + // | int | long | + // signed | 2^31-1 | 2^63-1 | + // unsigned | 2^32-1 | 2^64-1 | + // + // other: 32 bit unsinged res should be sign extended as if it were a signed number + always_comb + if(Signed) + if(Xs&~NaNIn) // signed negitive + if(Int64) OfIntRes = {1'b1, {`XLEN-1{1'b0}}}; + else OfIntRes = {{`XLEN-32{1'b1}}, 1'b1, {31{1'b0}}}; + else // signed positive + if(Int64) OfIntRes = {1'b0, {`XLEN-1{1'b1}}}; + else OfIntRes = {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}}; + else + if(Xs&~NaNIn) OfIntRes = {`XLEN{1'b0}}; // unsigned negitive + else OfIntRes = {`XLEN{1'b1}}; // unsigned positive + + + // select the integer output + // - if the input is invalid (out of bounds NaN or Inf) then output overflow res + // - if the input underflows + // - if rounding and signed opperation and negitive input, output -1 + // - otherwise output a rounded 0 + // - otherwise output the normal res (trmined and sign extended if nessisary) + always_comb + if(IntInvalid) FCvtIntRes = OfIntRes; + else if(CvtCe[`NE]) + if(Xs&Signed&Plus1) FCvtIntRes = {{`XLEN{1'b1}}}; + else FCvtIntRes = {{`XLEN-1{1'b0}}, Plus1}; + else if(Int64) FCvtIntRes = CvtNegRes[`XLEN-1:0]; + else FCvtIntRes = {{`XLEN-32{CvtNegRes[31]}}, CvtNegRes[31:0]}; +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/srt.sv b/pipelined/src/fpu/srt.sv new file mode 100644 index 000000000..524bb2cec --- /dev/null +++ b/pipelined/src/fpu/srt.sv @@ -0,0 +1,269 @@ +/////////////////////////////////////////// +// srt.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module srt( + input logic clk, + input logic DivStart, + input logic DivBusy, + input logic [`NE-1:0] Xe, Ye, + input logic XZeroE, YZeroE, + input logic SqrtE, + input logic SqrtM, + input logic [`DIVb:0] X, + input logic [`DIVN-2:0] Dpreproc, + input logic NegSticky, + output logic [`DIVb-(`RADIX/4):0] Qm, + output logic [`DIVb+3:0] NextWSN, NextWCN, + output logic [`DIVb+3:0] StickyWSA, + output logic [`DIVb+3:0] FirstWS, FirstWC +); + +//QLEN = 1.(number of bits created for division) +// N is NF+1 or XLEN +// WC/WS is dependent on D so 4.N-1 ie N+3 bits or N+2:0 + one more bit in fraction for possible sqrt right shift +// D is 1.N-1, but the msb is always 1 so 0.N-1 or N-1 bits or N-1:0 +// Dsel should match WC/WS so 4.N-1 ie N+3 bits or N+2:0 +// Q/QM/S/SM should be 1.b so b+1 bits or b:0 +// C needs to be the lenght of the final fraction 0.b so b or b-1:0 + /* verilator lint_off UNOPTFLAT */ + logic [`DIVb+3:0] WSA[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb+3:0] WCA[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb+3:0] WS[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb+3:0] WC[`DIVCOPIES-1:0]; // Q4.b + logic [`DIVb:0] Q[`DIVCOPIES-1:0]; // U1.b + logic [`DIVb:0] QM[`DIVCOPIES-1:0];// 1.b + logic [`DIVb:0] QNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] QMNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] S[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] SM[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] SNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb:0] SMNext[`DIVCOPIES-1:0];// U1.b + logic [`DIVb-1:0] C[`DIVCOPIES-1:0]; // 0.b + /* verilator lint_on UNOPTFLAT */ + logic [`DIVb+3:0] WSN, WCN; // Q4.N-1 + logic [`DIVN-2:0] D; // U0.N-1 + logic [`DIVb+3:0] DBar, D2, DBar2; // Q4.N-1 + logic [`DIVb:0] QMMux; + logic [`DIVb-1:0] NextC; + logic [`DIVb-1:0] CMux; + logic [`DIVb:0] SMux; + + // Top Muxes and Registers + // When start is asserted, the inputs are loaded into the divider. + // Otherwise, the divisor is retained and the partial remainder + // is fed back for the next iteration. + // - when the start signal is asserted X and 0 are loaded into WS and WC + // - otherwise load WSA into the flipflop + // - the assumed one is added to D since it's always normalized (and X/0 is a special case handeled by result selection) + // - XZeroE is used as the assumed one to avoid creating a sticky bit - all other numbers are normalized + if (`RADIX == 2) begin : nextw + assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+2:0], 1'b0}; + assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+2:0], 1'b0}; + assign NextC = {1'b1, C[`DIVCOPIES-1][`DIVb-1:1]}; + end else begin + assign NextWSN = {WSA[`DIVCOPIES-1][`DIVb+1:0], 2'b0}; + assign NextWCN = {WCA[`DIVCOPIES-1][`DIVb+1:0], 2'b0}; + assign NextC = {2'b11, C[`DIVCOPIES-1][`DIVb-1:2]}; + end + + + // mux2 #(`DIVb+4) wsmux(NextWSN, {3'b0, X}, DivStart, WSN); + mux2 #(`DIVb+4) wsmux(NextWSN, {{3{SqrtE&~XZeroE}}, X}, DivStart, WSN); + flopen #(`DIVb+4) wsflop(clk, DivStart|DivBusy, WSN, WS[0]); + mux2 #(`DIVb+4) wcmux(NextWCN, '0, DivStart, WCN); + flopen #(`DIVb+4) wcflop(clk, DivStart|DivBusy, WCN, WC[0]); + flopen #(`DIVN-1) dflop(clk, DivStart, Dpreproc, D); + mux2 #(`DIVb) Cmux(NextC, {1'b1, {(`DIVb-1){1'b0}}}, DivStart, CMux); + flopen #(`DIVb) cflop(clk, DivStart|DivBusy, CMux, C[0]); + + // Divisor Selections + // - choose the negitive version of what's being selected + // - D is only the fraction + assign DBar = {3'b111, 1'b0, ~D, {`DIVb-`DIVN+1{1'b1}}}; + if(`RADIX == 4) begin : d2 + assign DBar2 = {2'b11, 1'b0, ~D, {`DIVb+2-`DIVN{1'b1}}}; + assign D2 = {2'b0, 1'b1, D, {`DIVb+2-`DIVN{1'b0}}}; + end + + genvar i; + generate + for(i=0; $unsigned(i)<`DIVCOPIES; i++) begin : interations + divinteration divinteration(.D, .DBar, .D2, .DBar2, .SqrtM, + .WS(WS[i]), .WC(WC[i]), .WSA(WSA[i]), .WCA(WCA[i]), .Q(Q[i]), .QM(QM[i]), .QNext(QNext[i]), .QMNext(QMNext[i]), + .C(C[i]), .S(S[i]), .SM(SM[i]), .SNext(SNext[i]), .SMNext(SMNext[i])); + if(i<(`DIVCOPIES-1)) begin + if (`RADIX==2)begin + assign WS[i+1] = {WSA[i][`DIVb+2:0], 1'b0}; + assign WC[i+1] = {WCA[i][`DIVb+2:0], 1'b0}; + assign C[i+1] = {1'b1, C[i][`DIVb-1:1]}; + end else begin + assign WS[i+1] = {WSA[i][`DIVb+1:0], 2'b0}; + assign WC[i+1] = {WCA[i][`DIVb+1:0], 2'b0}; + assign C[i+1] = {2'b11, C[i][`DIVb-1:2]}; + end + assign Q[i+1] = QNext[i]; + assign QM[i+1] = QMNext[i]; + assign S[i+1] = SNext[i]; + assign SM[i+1] = SMNext[i]; + end + end + endgenerate + + + // if starting a new divison set Q to 0 and QM to -1 + mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux); + flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]); + flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]); + + flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]); + mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux); + flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); + // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted + always_comb + if(SqrtM) // sqrt ouputs in the range (1, .5] + if(NegSticky) Qm = {SM[0][`DIVb-1-(`RADIX/4):0], 1'b0}; + else Qm = {S[0][`DIVb-1-(`RADIX/4):0], 1'b0}; + else + if(NegSticky) Qm = QM[0][`DIVb-(`RADIX/4):0]; + else Qm = Q[0][`DIVb-(`RADIX/4):0]; + + assign FirstWS = WS[0]; + assign FirstWC = WC[0]; + + if(`RADIX==2) + if (`DIVCOPIES == 1) + assign StickyWSA = {WSA[0][`DIVb+2:0], 1'b0}; + else + assign StickyWSA = {WSA[1][`DIVb+2:0], 1'b0}; + + +endmodule + +//////////////// +// Submodules // +//////////////// + + /* verilator lint_off UNOPTFLAT */ +module divinteration ( + input logic [`DIVN-2:0] D, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] Q, QM, + input logic [`DIVb:0] S, SM, + input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb-1:0] C, + input logic SqrtM, + output logic [`DIVb:0] QNext, QMNext, + output logic [`DIVb:0] SNext, SMNext, + output logic [`DIVb+3:0] WSA, WCA +); + /* verilator lint_on UNOPTFLAT */ + + logic [`DIVb+3:0] Dsel; + logic [3:0] q; + logic qp, qz; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + + // Qmient Selection logic + // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) + // q encoding: + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 + if(`RADIX == 2) begin : qsel + qsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], qp, qz); + fgen2 fgen2(.sp(qp), .sz(qz), .C, .S, .SM, .F); + end else begin + qsel4 qsel4(.D, .WS, .WC, .Sqrt(SqrtM), .q); + // fgen4 fgen4(.s(q), .C, .S, .SM, .F); + end + + if(`RADIX == 2) begin : dsel + assign Dsel = {`DIVb+4{~qz}}&(qp ? DBar : {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}); + end else begin + always_comb + case (q) + 4'b1000: Dsel = DBar2; + 4'b0100: Dsel = DBar; + 4'b0000: Dsel = '0; + 4'b0010: Dsel = {3'b0, 1'b1, D, {`DIVb-`DIVN+1{1'b0}}}; + 4'b0001: Dsel = D2; + default: Dsel = 'x; + endcase + end + // Partial Product Generation + // WSA, WCA = WS + WC - qD + assign AddIn = SqrtM ? F : Dsel; + if (`RADIX == 2) begin : csa + csa #(`DIVb+4) csa(WS, WC, AddIn, qp&~SqrtM, WSA, WCA); + end else begin + csa #(`DIVb+4) csa(WS, WC, AddIn, |q[3:2]&~SqrtM, WSA, WCA); + end + + if (`RADIX == 2) begin : otfc + otfc2 otfc2(.qp, .qz, .Q, .QM, .QNext, .QMNext); + sotfc2 sotfc2(.sp(qp), .sz(qz), .C, .S, .SM, .SNext, .SMNext); + end else begin + otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext); + // sotfc4 sotfc4(.s(q), .SqrtM, .C, .S, .SM, .SNext, .SMNext); + end + +endmodule + + +///////// +// csa // +///////// +module csa #(parameter N=69) ( + input logic [N-1:0] in1, in2, in3, + input logic cin, + output logic [N-1:0] out1, out2 +); + + // This block adds in1, in2, in3, and cin to produce + // a result out1 / out2 in carry-save redundant form. + // cin is just added to the least significant bit and + // is Startuired to handle adding a negative divisor. + // Fortunately, the carry (out2) is shifted left by one + // bit, leaving room in the least significant bit to + // insert cin. + + assign out1 = in1 ^ in2 ^ in3; + assign out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) | + (in2[N-2:0] & in3[N-2:0]), cin}; +endmodule + + + + diff --git a/pipelined/src/fpu/srtfsm.sv b/pipelined/src/fpu/srtfsm.sv new file mode 100644 index 000000000..c00f1dbab --- /dev/null +++ b/pipelined/src/fpu/srtfsm.sv @@ -0,0 +1,95 @@ +/////////////////////////////////////////// +// srt.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module srtfsm( + input logic clk, + input logic reset, + input logic [`DIVb+3:0] NextWSN, NextWCN, WS, WC, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic DivStart, + input logic XsE, + input logic SqrtE, + input logic StallE, + input logic StallM, + input logic [`DIVb+3:0] StickyWSA, + input logic [`DURLEN-1:0] Dur, + output logic [`DURLEN-1:0] EarlyTermShiftE, + output logic DivSE, + output logic DivDone, + output logic NegSticky, + output logic DivBusy + ); + + typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; + statetype state; + + logic [`DURLEN-1:0] step; + logic WZero; + //logic [$clog2(`DIVLEN/2+3)-1:0] Dur; + logic [`DIVb+3:0] W; + + //flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur); + assign DivBusy = (state == BUSY); + assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0}); + // calculate sticky bit + // - there is a chance that a value is subtracted infinitly, resulting in an exact QM result + // this is only a problem on radix 2 (and pssibly maximally redundant 4) since minimally redundant + // radix-4 division can't create a QM that continually adds 0's + if (`RADIX == 2) + assign DivSE = |W&~(StickyWSA == WS); + else + assign DivSE = |W; + assign DivDone = (state == DONE); + assign W = WC+WS; + assign NegSticky = W[`DIVb+3]; + assign EarlyTermShiftE = step; + + always_ff @(posedge clk) begin + if (reset) begin + state <= #1 IDLE; + end else if (DivStart&~StallE) begin + step <= Dur; + if (XZeroE|(YZeroE&~SqrtE)|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE; + else state <= #1 BUSY; + end else if (state == BUSY) begin + if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin + state <= #1 DONE; + end + step <= step - 1; + end else if (state == DONE) begin + if (StallM) state <= #1 DONE; + else state <= #1 IDLE; + end + end +endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/srtpreproc.sv b/pipelined/src/fpu/srtpreproc.sv new file mode 100644 index 000000000..63b2b9779 --- /dev/null +++ b/pipelined/src/fpu/srtpreproc.sv @@ -0,0 +1,136 @@ +/////////////////////////////////////////// +// srt.sv +// +// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek +// Modified:13 January 2022 +// +// Purpose: Combined Divide and Square Root Floating Point and Integer Unit +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module srtpreproc ( + input logic clk, + input logic DivStart, + input logic [`NF:0] Xm, Ym, + input logic [`NE-1:0] Xe, Ye, + input logic [`FMTBITS-1:0] Fmt, + input logic Sqrt, + input logic XZero, + output logic [`NE+1:0] QeM, + output logic [`DIVb:0] X, + output logic [`DIVN-2:0] Dpreproc, + output logic [`DURLEN-1:0] Dur +); + // logic [`XLEN-1:0] PosA, PosB; + // logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY; + logic [`NF-1:0] PreprocA, PreprocX; + logic [`NF-1:0] PreprocB, PreprocY; + logic [`NF+1:0] SqrtX; + logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; + logic [`NE+1:0] Qe; + + // assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA; + // assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB; + // lzc #(`XLEN) lzcA (PosA, zeroCntA); + // lzc #(`XLEN) lzcB (PosB, zeroCntB); + + // ***can probably merge X LZC with conversion + // cout the number of leading zeros + lzc #(`NF+1) lzcX (Xm, XZeroCnt); + lzc #(`NF+1) lzcY (Ym, YZeroCnt); + + // assign ExtraA = {PosA, {`DIVLEN-`XLEN{1'b0}}}; + // assign ExtraB = {PosB, {`DIVLEN-`XLEN{1'b0}}}; + + // assign PreprocA = ExtraA << zeroCntA; + // assign PreprocB = ExtraB << (zeroCntB + 1); + assign PreprocX = Xm[`NF-1:0]<>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; - - // discard bottom 2 or 3 bits of address offset within word or doubleword - localparam adrlsb = (`XLEN==64) ? 3 : 2; - logic [31:adrlsb] adrmsbs; - assign adrmsbs = a[31:adrlsb]; - - always_ff @(posedge clk) - rd <= RAM[adrmsbs]; - - genvar index; - for(index = 0; index < `XLEN/8; index++) begin - always_ff @(posedge clk) begin - if (we & ByteMask[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index]; - end - end - -----/\----- EXCLUDED -----/\----- */ + memory(.clk, .we, .bwe(ByteMask), .addr(a[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(rd), .din(wd)); endmodule diff --git a/pipelined/src/generic/lzc.sv b/pipelined/src/generic/lzc.sv new file mode 100644 index 000000000..71aabbc61 --- /dev/null +++ b/pipelined/src/generic/lzc.sv @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Leading Zero Counter +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +//leading zero counter i.e. priority encoder +module lzc #(parameter WIDTH = 1) ( + input logic [WIDTH-1:0] num, + output logic [$clog2(WIDTH+1)-1:0] ZeroCnt +); +/* verilator lint_off CMPCONST */ +/* verilator lint_off WIDTH */ + + logic [31:0] i; + always_comb begin + i = 0; + while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one + ZeroCnt = i; + end +/* verilator lint_on WIDTH */ +/* verilator lint_on CMPCONST */ +endmodule diff --git a/pipelined/src/generic/priorityonehot.sv b/pipelined/src/generic/priorityonehot.sv index bf9d041be..e2c79cd6e 100644 --- a/pipelined/src/generic/priorityonehot.sv +++ b/pipelined/src/generic/priorityonehot.sv @@ -39,9 +39,11 @@ module priorityonehot #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y ); - logic [N-1:0] nolower; - // create thermometer code mask - prioritythermometer #(N) maskgen(.a({a[N-2:0], 1'b0}), .y(nolower)); - assign y = a & nolower; + genvar i; + assign y[0] = a[0]; + for (i=1; i`XLEN)) begin:fpmux + logic [`XLEN-1:0] IFCvtResultW; + mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); + assign WriteDataE = ForwardedSrcBE; + mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); + mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); + end else if (`F_SUPPORTED) begin:fpmux + logic [`XLEN-1:0] IFCvtResultW; mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(`XLEN) writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE); + mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, ~FResSelW[1]&FResSelW[0], IFCvtResultW); + mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); end else begin:fpmux assign IFResultM = IEUResultM; assign WriteDataE = ForwardedSrcBE; + mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); end // handle Store Conditional result if atomic extension supported diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index a10d1f92f..b47cd1d2d 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -50,7 +50,6 @@ module ieu ( // Memory stage interface input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU - output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU @@ -61,9 +60,11 @@ module ieu ( output logic InvalidateICacheM, FlushDCacheM, // Writeback stage - input logic [`XLEN-1:0] CSRReadValW, ReadDataM, MDUResultW, + input logic [`XLEN-1:0] CSRReadValW, MDUResultW, + input logic [1:0] FResSelW, + input logic [`XLEN-1:0] FCvtIntResW, output logic [4:0] RdW, - output logic [`XLEN-1:0] ReadDataW, + input logic [`XLEN-1:0] ReadDataW, // input logic [`XLEN-1:0] PCLinkW, output logic InstrValidM, // hazards @@ -72,12 +73,12 @@ module ieu ( output logic FPUStallD, LoadStallD, MDUStallD, CSRRdStallD, output logic PCSrcE, output logic CSRReadM, CSRWriteM, PrivilegedM, - output logic CSRWritePendingDEM, + output logic CSRWriteFencePendingDEM, output logic StoreStallD ); logic [2:0] ImmSrcD; - logic [2:0] FlagsE; + logic [1:0] FlagsE; logic [2:0] ALUControlE; logic ALUSrcAE, ALUSrcBE; logic [2:0] ResultSrcW; @@ -92,23 +93,24 @@ module ieu ( logic RegWriteM, RegWriteW; logic MemReadE, CSRReadE; logic JumpE; + logic BranchSignedE; controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .MDUE, .W64E, .JumpE, .StallM, .FlushM, .MemRWM, - .CSRReadM, .CSRWriteM, .PrivilegedM, .SCE, .AtomicE, .AtomicM, .Funct3M, + .Funct3E, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, - .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWritePendingDEM, .StoreStallD); + .StallW, .FlushW, .RegWriteW, .ResultSrcW, .CSRWriteFencePendingDEM, .StoreStallD); datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE, + .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .IllegalFPUInstrE, .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, - .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, - .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, - .CSRReadValW, .ReadDataM, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); + .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .FResSelW, + .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, + .CSRReadValW, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); forward fw( .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW, diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index de2ac72ab..2e306dc60 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -116,7 +116,7 @@ module bpred // this predictor will have two pieces of data, // 1) A direction (1 = Taken, 0 = Not Taken) - // 2) Any information which is necessary for the predictor to built it's next state. + // 2) Any information which is necessary for the predictor to build its next state. // For a 2 bit table this is the prediction count. assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index e8460def9..b4b160289 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -33,14 +33,18 @@ module ifu ( input logic clk, reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushF, FlushD, FlushE, FlushM, FlushW, + input logic StallF, StallD, StallE, StallM, + input logic FlushF, FlushD, FlushE, FlushM, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic IFUBusAck, +(* mark_debug = "true" *) input logic IFUBusInit, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUStallF, +(* mark_debug = "true" *) output logic [2:0] IFUBurstType, +(* mark_debug = "true" *) output logic [1:0] IFUTransType, +(* mark_debug = "true" *) output logic IFUTransComplete, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, // Execute output logic [`XLEN-1:0] PCLinkE, @@ -65,7 +69,6 @@ module ifu ( output logic InstrPageFaultF, output logic IllegalIEUInstrFaultD, output logic InstrMisalignedFaultM, - input logic ExceptionM, // mmu management input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PTE, @@ -73,7 +76,7 @@ module ifu ( input logic [`XLEN-1:0] SATP_REGW, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic [1:0] STATUS_MPP, - input logic ITLBWriteF, ITLBFlushF, + input logic ITLBWriteF, sfencevmaM, output logic ITLBMissF, InstrDAPageFaultF, input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], @@ -138,6 +141,18 @@ module ifu ( //////////////////////////////////////////////////////////////////////////////////////////////// if(`ZICSR_SUPPORTED == 1) begin : immu + /////////////////////////////////////////// + // sfence.vma causes TLB flushes + /////////////////////////////////////////// + // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction + // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. + // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and + // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush + // after a cycle AND pulse it for another cycle on any further back-to-back sfences. + logic StallMQ, TLBFlush; + flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); + assign TLBFlush = sfencevmaM & ~StallMQ; + mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1)) immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .DisableTranslation(1'b0), @@ -146,7 +161,7 @@ module ifu ( .PTE(PTE), .PageTypeWriteVal(PageType), .TLBWrite(ITLBWriteF), - .TLBFlush(ITLBFlushF), + .TLBFlush, .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(), @@ -170,11 +185,10 @@ module ifu ( logic [`XLEN-1:0] AllInstrRawF; assign InstrRawF = AllInstrRawF[31:0]; - if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM - dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill), + dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0), - .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), + .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), .BusCommittedM(), .DCacheStallM(ICacheStallF), .Cacheable(CacheableF), .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess)); @@ -182,18 +196,16 @@ module ifu ( if (`IBUS) begin : bus localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN; - localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] ReadDataLine; + localparam integer LOGBWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ICacheBusWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - logic [31:0] temp; logic SelUncachedAdr; - busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) + busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED) busdp(.clk, .reset, - .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(), - .LSUBusRead(IFUBusRead), .LSUBusSize(), + .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .LSUBusWriteCrit(), + .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .WordCount(), .DCacheFetchLine(ICacheFetchLine), @@ -210,7 +222,7 @@ module ifu ( if(CACHE_ENABLED) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) + .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM(TrapM), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), @@ -224,7 +236,7 @@ module ifu ( .Atomic('0), .FlushCache('0), .NextAdr(PCNextFSpill[11:0]), .PAdr(PCPF), - .CacheCommitted(), .InvalidateCacheM(InvalidateICacheM)); + .CacheCommitted(), .InvalidateCache(InvalidateICacheM)); end else begin : passthrough assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0; diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index a5dd06ac4..5a0753974 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -32,7 +32,7 @@ module atomic ( input logic clk, - input logic reset, FlushW, StallW, + input logic reset, StallW, input logic [`XLEN-1:0] ReadDataM, input logic [`XLEN-1:0] LSUWriteDataM, input logic [`PA_BITS-1:0] LSUPAdrM, @@ -52,7 +52,7 @@ module atomic ( .result(AMOResult)); mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM); assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; - lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, + lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, .SquashSCW, .LSURWM); endmodule diff --git a/pipelined/src/lsu/bigendianswap.sv b/pipelined/src/lsu/bigendianswap.sv index bf1a732ac..29c717edc 100644 --- a/pipelined/src/lsu/bigendianswap.sv +++ b/pipelined/src/lsu/bigendianswap.sv @@ -30,12 +30,32 @@ `include "wally-config.vh" -module bigendianswap ( +module bigendianswap #(parameter LEN=`XLEN) ( input logic BigEndianM, - input logic [`XLEN-1:0] a, - output logic [`XLEN-1:0] y); + input logic [LEN-1:0] a, + output logic [LEN-1:0] y); - if(`XLEN == 64) begin + if(LEN == 128) begin + always_comb + if (BigEndianM) begin // swap endianness + y[127:120] = a[7:0]; + y[119:112] = a[15:8]; + y[111:104] = a[23:16]; + y[103:96] = a[31:24]; + y[95:88] = a[39:32]; + y[87:80] = a[47:40]; + y[79:72] = a[55:48]; + y[71:64] = a[63:56]; + y[63:56] = a[71:64]; + y[55:48] = a[79:72]; + y[47:40] = a[87:80]; + y[39:32] = a[95:88]; + y[31:24] = a[103:96]; + y[23:16] = a[111:104]; + y[15:8] = a[119:112]; + y[7:0] = a[127:120]; + end else y = a; + end else if(LEN == 64) begin always_comb if (BigEndianM) begin // swap endianness y[63:56] = a[7:0]; diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index e80de5bde..5139efdc1 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -40,9 +40,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) // bus interface input logic [`XLEN-1:0] LSUBusHRDATA, input logic LSUBusAck, + input logic LSUBusInit, output logic LSUBusWrite, output logic LSUBusRead, - output logic [2:0] LSUBusSize, + output logic [2:0] LSUBusSize, + output logic [2:0] LSUBurstType, + output logic [1:0] LSUTransType, // For AHBLite + output logic LSUTransComplete, input logic [2:0] LSUFunct3M, output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [LOGWPL-1:0] WordCount, @@ -66,13 +70,15 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalLSUBusAdr; + logic [LOGWPL-1:0] WordCountDelayed; + // *** implement flops as an array if feasbile; DCacheBusWriteData might be a problem // *** better name than DCacheBusWriteData genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer logic [WORDSPERLINE-1:0] CaptureWord; - assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCount); + assign CaptureWord[index] = LSUBusAck & LSUBusRead & (index == WordCountDelayed); flopen #(`XLEN) fb(.clk, .en(CaptureWord[index]), .d(LSUBusHRDATA), .q(DCacheBusWriteData[(index+1)*`XLEN-1:index*`XLEN])); end @@ -83,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, - .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, - .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); + .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, + .LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index f3860c0d6..75c4d006b 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -41,6 +41,7 @@ module busfsm #(parameter integer WordCountThreshold, input logic DCacheFetchLine, input logic DCacheWriteLine, input logic LSUBusAck, + input logic LSUBusInit, // This might be better as LSUBusLock, or to send this using LSUBusAck. input logic CPUBusy, input logic CacheableM, @@ -48,10 +49,13 @@ module busfsm #(parameter integer WordCountThreshold, output logic LSUBusWrite, output logic LSUBusWriteCrit, output logic LSUBusRead, + output logic [2:0] LSUBurstType, + output logic LSUTransComplete, + output logic [1:0] LSUTransType, output logic DCacheBusAck, output logic BusCommittedM, output logic SelUncachedAdr, - output logic [LOGWPL-1:0] WordCount); + output logic [LOGWPL-1:0] WordCount, WordCountDelayed); @@ -61,7 +65,8 @@ module busfsm #(parameter integer WordCountThreshold, logic CntReset; logic WordCountFlag; logic [LOGWPL-1:0] NextWordCount; - logic UnCachedAccess; + logic UnCachedAccess, UnCachedRW; + logic [2:0] LocalBurstType; typedef enum logic [2:0] {STATE_BUS_READY, @@ -75,18 +80,27 @@ module busfsm #(parameter integer WordCountThreshold, (* mark_debug = "true" *) busstatetype BusCurrState, BusNextState; - + // Used to send address for address stage of AHB. flopenr #(LOGWPL) WordCountReg(.clk(clk), .reset(reset | CntReset), .en(CntEn), .d(NextWordCount), - .q(WordCount)); + .q(WordCount)); + + // Used to store data from data phase of AHB. + flopenr #(LOGWPL) + WordCountDelayedReg(.clk(clk), + .reset(reset | CntReset), + .en(CntEn), + .d(WordCount), + .q(WordCountDelayed)); assign NextWordCount = WordCount + 1'b1; - assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]); - assign CntEn = PreCntEn & LSUBusAck; + assign PreCntEn = (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); + assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); // Detect when we are waiting on the final access. + assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag & ~UnCachedRW; // Want to count when doing cache accesses and we aren't wrapping up. assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; @@ -112,22 +126,43 @@ module busfsm #(parameter integer WordCountThreshold, else BusNextState = STATE_BUS_READY; STATE_BUS_CPU_BUSY: if(CPUBusy) BusNextState = STATE_BUS_CPU_BUSY; else BusNextState = STATE_BUS_READY; - STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_FETCH; - STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) BusNextState = STATE_BUS_READY; - else BusNextState = STATE_BUS_WRITE; + STATE_BUS_FETCH: if (WordCountFlag & LSUBusAck) begin + if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + else BusNextState = STATE_BUS_READY; + end else BusNextState = STATE_BUS_FETCH; + STATE_BUS_WRITE: if(WordCountFlag & LSUBusAck) begin + if (DCacheFetchLine) BusNextState = STATE_BUS_FETCH; + else if (DCacheWriteLine) BusNextState = STATE_BUS_WRITE; + else BusNextState = STATE_BUS_READY; + end else BusNextState = STATE_BUS_WRITE; default: BusNextState = STATE_BUS_READY; endcase end + always_comb begin + case(WordCountThreshold) + 0: LocalBurstType = 3'b000; + 3: LocalBurstType = 3'b011; // INCR4 + 7: LocalBurstType = 3'b101; // INCR8 + 15: LocalBurstType = 3'b111; // INCR16 + default: LocalBurstType = 3'b001; // INCR without end. + endcase + end - assign CntReset = BusCurrState == STATE_BUS_READY; + // Would these be better as always_comb statements or muxes? + assign LSUBurstType = (UnCachedRW) ? 3'b0 : LocalBurstType; // Don't want to use burst when doing an Uncached Access. + assign LSUTransComplete = (UnCachedRW) ? LSUBusAck : WordCountFlag & LSUBusAck; + // Use SEQ if not doing first word, NONSEQ if doing the first read/write, and IDLE if finishing up. + assign LSUTransType = (|WordCount) & ~UnCachedRW ? 2'b11 : (LSUBusRead | LSUBusWrite) & (~LSUTransComplete) ? 2'b10 : 2'b00; + // Reset if we aren't initiating a transaction or if we are finishing a transaction. + assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine) | LSUTransComplete; + assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | (BusCurrState == STATE_BUS_UNCACHED_WRITE) | (BusCurrState == STATE_BUS_UNCACHED_READ) | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_WRITE); - assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE; assign UnCachedLSUBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[0] & ~IgnoreRequest) | (BusCurrState == STATE_BUS_UNCACHED_WRITE); assign LSUBusWrite = UnCachedLSUBusWrite | (BusCurrState == STATE_BUS_WRITE); @@ -139,6 +174,10 @@ module busfsm #(parameter integer WordCountThreshold, (BusCurrState == STATE_BUS_UNCACHED_READ); assign LSUBusRead = UnCachedLSUBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine); + + // Makes bus only do uncached reads/writes when we actually do uncached reads/writes. Needed because CacheableM is 0 when flushing cache. + assign UnCachedRW = UnCachedLSUBusWrite | UnCachedLSUBusRead; + assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LSUBusAck) | (BusCurrState == STATE_BUS_WRITE & WordCountFlag & LSUBusAck); assign BusCommittedM = BusCurrState != STATE_BUS_READY; diff --git a/pipelined/src/lsu/lrsc.sv b/pipelined/src/lsu/lrsc.sv index 66b2ac3d6..a99f6f838 100644 --- a/pipelined/src/lsu/lrsc.sv +++ b/pipelined/src/lsu/lrsc.sv @@ -34,7 +34,7 @@ module lrsc ( input logic clk, reset, - input logic FlushW, StallW, + input logic StallW, input logic MemReadM, input logic [1:0] PreLSURWM, output logic [1:0] LSURWM, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index eaad232df..08d217e17 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -51,11 +51,15 @@ module lsu ( input logic [`XLEN-1:0] IEUAdrE, (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, input logic [`XLEN-1:0] WriteDataE, - output logic [`XLEN-1:0] ReadDataM, + output logic [`LLEN-1:0] ReadDataW, // cpu privilege input logic [1:0] PrivilegeModeW, input logic BigEndianM, - input logic DTLBFlushM, + input logic sfencevmaM, + // fpu + input logic [`FLEN-1:0] FWriteDataM, + input logic FStore2, + input logic FpLoadStoreM, // faults output logic LoadPageFaultM, StoreAmoPageFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -66,9 +70,13 @@ module lsu ( (* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) input logic LSUBusAck, + (* mark_debug = "true" *) input logic LSUBusInit, (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [2:0] LSUBusSize, + (* mark_debug = "true" *) output logic [2:0] LSUBurstType, + (* mark_debug = "true" *) output logic [1:0] LSUTransType, + (* mark_debug = "true" *) output logic LSUTransComplete, // page table walker input logic [`XLEN-1:0] SATP_REGW, // from csr input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, @@ -93,7 +101,7 @@ module lsu ( logic [6:0] LSUFunct7M; logic [1:0] LSUAtomicM; (* mark_debug = "true" *) logic [`XLEN+1:0] PreLSUPAdrM; - logic [11:0] PreLSUAdrE, LSUAdrE; + logic [11:0] LSUAdrE; logic CPUBusy; logic DCacheStallM; logic CacheableM; @@ -104,8 +112,9 @@ module lsu ( logic LSUBusWriteCrit; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - logic [(`XLEN-1)/8:0] ByteMaskM; logic [`XLEN-1:0] WriteDataM; + logic [`LLEN-1:0] ReadDataM; + logic [(`LLEN-1)/8:0] ByteMaskM, FinalByteMaskM; // *** TO DO: Burst mode @@ -124,14 +133,14 @@ module lsu ( .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, + .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); end else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; assign IgnoreRequestTrapM = TrapM; assign CPUBusy = StallW; assign PreLSURWM = MemRWM; - assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0]; + assign LSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; assign LSUWriteDataM = WriteDataM; @@ -157,7 +166,7 @@ module lsu ( .PTE, .PageTypeWriteVal(PageType), .TLBWrite(DTLBWriteM), - .TLBFlush(DTLBFlushM), + .TLBFlush(sfencevmaM), .PhysicalAddress(LSUPAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), @@ -182,9 +191,10 @@ module lsu ( // Memory System // Either Data Cache or Data Tightly Integrated Memory or just bus interface ///////////////////////////////////////////////////////////////////////////////////////////// - logic [`XLEN-1:0] AMOWriteDataM, FinalWriteDataM, LittleEndianWriteDataM; - logic [`XLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; - logic [`XLEN-1:0] ReadDataWordMuxM; + logic [`XLEN-1:0] AMOWriteDataM, IEUWriteDataM, LittleEndianWriteDataM; + logic [`LLEN-1:0] FinalWriteDataM; + logic [`LLEN-1:0] ReadDataWordM, LittleEndianReadDataWordM; + logic [`LLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; logic SelUncachedAdr; assign IgnoreRequest = IgnoreRequestTLB | IgnoreRequestTrapM; @@ -192,51 +202,53 @@ module lsu ( if (`DMEM == `MEM_TIM) begin : dtim // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops - dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, - .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, - .DCacheStallM, .DCacheCommittedM, .ByteMaskM, .Cacheable(CacheableM), + dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM(IEUWriteDataM), //*** fix the dtim FinalWriteData + .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM, + .DCacheStallM, .DCacheCommittedM, .ByteMaskM(ByteMaskM[`XLEN/8-1:0]), .Cacheable(CacheableM), .DCacheMiss, .DCacheAccess); end if (`DBUS) begin : bus localparam CACHE_ENABLED = `DMEM == `MEM_CACHE; localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; - localparam integer LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; - logic [LINELEN-1:0] ReadDataLineM; + localparam integer LOGBWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] DCacheBusWriteData; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; logic DCacheBusAck; - logic SelBus; - logic [LOGWPL-1:0] WordCount; + logic [LOGBWPL-1:0] WordCount; - busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( + busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED) busdp( .clk, .reset, - .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusSize, + .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .WordCount, .LSUBusWriteCrit, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .SelUncachedAdr, .IgnoreRequest, .LSURWM, .CPUBusy, .CacheableM, .BusStall, .BusCommittedM); - mux2 #(`XLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1(DCacheBusWriteData[`XLEN-1:0]), + mux2 #(`LLEN) UnCachedDataMux(.d0(LittleEndianReadDataWordM), .d1({{`LLEN-`XLEN{1'b0}}, DCacheBusWriteData[`XLEN-1:0]}), .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM), + mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(IEUWriteDataM), .s(SelUncachedAdr), .y(LSUBusHWDATA)); if(CACHE_ENABLED) begin : dcache + if (`LLEN>`XLEN) + mux2 #(`LLEN) datamux({IEUWriteDataM, IEUWriteDataM}, FWriteDataM, FpLoadStoreM, FinalWriteDataM); + else + assign FinalWriteDataM = {{`LLEN-`XLEN{1'b0}}, IEUWriteDataM}; cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( + .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteMask(ByteMaskM), .WordCount, + .ByteMask(FinalByteMaskM), .WordCount, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .TrapM(1'b0), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), - .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); + .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0; @@ -251,7 +263,7 @@ module lsu ( // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, + atomic atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[`XLEN-1:0]), .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .AMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc @@ -261,10 +273,22 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// // Subword Accesses ///////////////////////////////////////////////////////////////////////////////////////////// - subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), - .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM, .ByteMaskM); subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), - .Funct3M(LSUFunct3M), .ReadDataM); + .FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM); + subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]), + .LSUFunct3M, .AMOWriteDataM, .LittleEndianWriteDataM); + + // Compute byte masks + swbytemaskword #(`LLEN) swbytemask(.Size(LSUFunct3M), .Adr(LSUPAdrM[$clog2(`LLEN/8)-1:0]), .ByteMask(ByteMaskM)); + // *** fix when when fstore2 is valid. I'm not sure this is even needed if LSUFunct3M can be 3'b100 for a 16 byte write. + //assign FinalByteMaskM = FStore2 ? '1 : ByteMaskM; + assign FinalByteMaskM = ByteMaskM; + + ///////////////////////////////////////////////////////////////////////////////////////////// + // MW Pipeline Register + ///////////////////////////////////////////////////////////////////////////////////////////// + + flopen #(`LLEN) ReadDataMWReg(clk, ~StallW, ReadDataM, ReadDataW); ///////////////////////////////////////////////////////////////////////////////////////////// // Big Endian Byte Swapper @@ -272,10 +296,10 @@ module lsu ( // swap the bytes when read from big-endian memory ///////////////////////////////////////////////////////////////////////////////////////////// if (`BIGENDIAN_SUPPORTED) begin:endian - bigendianswap storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(FinalWriteDataM)); - bigendianswap loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM)); + bigendianswap #(`XLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(IEUWriteDataM)); + bigendianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordM), .y(LittleEndianReadDataWordM)); end else begin - assign FinalWriteDataM = LittleEndianWriteDataM; + assign IEUWriteDataM = LittleEndianWriteDataM; assign LittleEndianReadDataWordM = ReadDataWordM; end diff --git a/pipelined/src/lsu/subwordread.sv b/pipelined/src/lsu/subwordread.sv index f66c6f858..d38595d49 100644 --- a/pipelined/src/lsu/subwordread.sv +++ b/pipelined/src/lsu/subwordread.sv @@ -32,10 +32,11 @@ module subwordread ( - input logic [`XLEN-1:0] ReadDataWordMuxM, + input logic [`LLEN-1:0] ReadDataWordMuxM, input logic [2:0] LSUPAdrM, input logic [2:0] Funct3M, - output logic [`XLEN-1:0] ReadDataM + input logic FpLoadStoreM, + output logic [`LLEN-1:0] ReadDataM ); logic [7:0] ByteM; @@ -74,18 +75,31 @@ module subwordread 1'b1: WordM = ReadDataWordMuxM[63:32]; endcase - // sign extension + logic [63:0] DblWordM; + assign DblWordM = ReadDataWordMuxM[63:0]; + + // sign extension/ NaN boxing always_comb case(Funct3M) - 3'b000: ReadDataM = {{56{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: ReadDataM = {{32{WordM[31]}}, WordM[31:0]}; // lw - 3'b011: ReadDataM = ReadDataWordMuxM; // ld - 3'b100: ReadDataM = {56'b0, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {48'b0, HalfwordM[15:0]}; // lhu - 3'b110: ReadDataM = {32'b0, WordM[31:0]}; // lwu + 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb + 3'b001: if(`ZFH_SUPPORTED) + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: if(`F_SUPPORTED) + ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw + else ReadDataM = {{`LLEN-32{WordM[31]}}, WordM[31:0]}; // lw + 3'b011: if(`D_SUPPORTED) + ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld + else ReadDataM = {{`LLEN-64{DblWordM[63]}}, DblWordM[63:0]}; // ld/fld + 3'b100: if(`Q_SUPPORTED) + ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq + else + ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + 3'b110: ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]}; // lwu default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase + end else begin:swrmux // 32-bit // byte mux always_comb @@ -105,13 +119,18 @@ module subwordread // sign extension always_comb - case(Funct3M) - 3'b000: ReadDataM = {{24{ByteM[7]}}, ByteM}; // lb - 3'b001: ReadDataM = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh - 3'b010: ReadDataM = ReadDataWordMuxM; // lw - 3'b100: ReadDataM = {24'b0, ByteM[7:0]}; // lbu - 3'b101: ReadDataM = {16'b0, HalfwordM[15:0]}; // lhu - default: ReadDataM = ReadDataWordMuxM; + case(Funct3M) + 3'b000: ReadDataM = {{`LLEN-8{ByteM[7]}}, ByteM}; // lb + 3'b001: if(`ZFH_SUPPORTED) + ReadDataM = {{`LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh + else ReadDataM = {{`LLEN-16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh + 3'b010: if(`F_SUPPORTED) + ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw + else ReadDataM = {{`LLEN-32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; // lw + 3'b011: ReadDataM = ReadDataWordMuxM; // fld + 3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu + 3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu + default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen endcase end endmodule diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv index 43c50e882..d42033ef7 100644 --- a/pipelined/src/lsu/subwordwrite.sv +++ b/pipelined/src/lsu/subwordwrite.sv @@ -34,13 +34,8 @@ module subwordwrite ( input logic [2:0] LSUPAdrM, input logic [2:0] LSUFunct3M, input logic [`XLEN-1:0] AMOWriteDataM, - output logic [`XLEN-1:0] LittleEndianWriteDataM, - output logic [`XLEN/8-1:0] ByteMaskM -); + output logic [`XLEN-1:0] LittleEndianWriteDataM); - // Compute byte masks - swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM)); - // Replicate data for subword writes if (`XLEN == 64) begin:sww always_comb diff --git a/pipelined/src/lsu/swbytemaskword.sv b/pipelined/src/lsu/swbytemaskword.sv new file mode 100644 index 000000000..4569355fb --- /dev/null +++ b/pipelined/src/lsu/swbytemaskword.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// swbytemask.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: On-chip RAM, external to core +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR CO/////////////////////////////////////////// +// swbytemask.sv +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module swbytemaskword #(parameter WORDLEN = 64)( + input logic [2:0] Size, + input logic [$clog2(WORDLEN/8)-1:0] Adr, + output logic [WORDLEN/8-1:0] ByteMask); + + assign ByteMask = ((2**(2**Size))-1) << Adr; + +/* Equivalent to the following for WORDLEN = 64 + if(WORDLEN == 64) begin + always_comb begin + case(Size[1:0]) + 2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb + 2'b01: case (Adr[2:1]) + 2'b00: ByteMask = 8'b0000_0011; + 2'b01: ByteMask = 8'b0000_1100; + 2'b10: ByteMask = 8'b0011_0000; + 2'b11: ByteMask = 8'b1100_0000; + endcase + 2'b10: if (Adr[2]) ByteMask = 8'b11110000; + else ByteMask = 8'b00001111; + 2'b11: ByteMask = 8'b1111_1111; + default ByteMask = 8'b0000_0000; + endcase + end + end +*/ + +endmodule + diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index eb0fc9bd0..f96d69f0d 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -61,7 +61,6 @@ module hptw logic DTLBWalk; // register TLBs translation miss requests logic [`PPN_BITS-1:0] BasePageTablePPN; logic [`PPN_BITS-1:0] CurrentPPN; - logic MemWrite; logic Executable, Writable, Readable, Valid, PTE_U; logic Misaligned, MegapageMisaligned; logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE; diff --git a/pipelined/src/mmu/pmpadrdec.sv b/pipelined/src/mmu/pmpadrdec.sv index f895ce77f..fc65a68c6 100644 --- a/pipelined/src/mmu/pmpadrdec.sv +++ b/pipelined/src/mmu/pmpadrdec.sv @@ -39,7 +39,6 @@ module pmpadrdec ( input logic [7:0] PMPCfg, input logic [`XLEN-1:0] PMPAdr, input logic PAgePMPAdrIn, - input logic FirstMatch, output logic PAgePMPAdrOut, output logic Match, Active, output logic L, X, W, R @@ -83,10 +82,10 @@ module pmpadrdec ( (AdrMode == NA4 | AdrMode == NAPOT) ? NAMatch : 0; - assign L = PMPCfg[7] & FirstMatch; - assign X = PMPCfg[2] & FirstMatch; - assign W = PMPCfg[1] & FirstMatch; - assign R = PMPCfg[0] & FirstMatch; + assign L = PMPCfg[7]; + assign X = PMPCfg[2]; + assign W = PMPCfg[1]; + assign R = PMPCfg[0]; assign Active = |PMPCfg[4:3]; endmodule diff --git a/pipelined/src/mmu/pmpchecker.sv b/pipelined/src/mmu/pmpchecker.sv index 1bf855072..33de9b30b 100644 --- a/pipelined/src/mmu/pmpchecker.sv +++ b/pipelined/src/mmu/pmpchecker.sv @@ -67,16 +67,16 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .FirstMatch, .Match, .Active, .L, .X, .W, .R); + .Match, .Active, .L, .X, .W, .R); priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; + assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active; - assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|X; - assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|W; - assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|R; + assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; + assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; + assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ; end else begin: pmpchecker // no checker assign PMPInstrAccessFaultF = 0; assign PMPLoadAccessFaultM = 0; diff --git a/pipelined/src/mmu/tlbcontrol.sv b/pipelined/src/mmu/tlbcontrol.sv index 3ab7a5c2a..5a9e4852d 100644 --- a/pipelined/src/mmu/tlbcontrol.sv +++ b/pipelined/src/mmu/tlbcontrol.sv @@ -58,8 +58,6 @@ module tlbcontrol #(parameter ITLB = 0) ( ); // Sections of the page table entry - logic [11:0] PageOffset; - logic [`SVMODE_BITS-1:0] SVMode; logic [1:0] EffectivePrivilegeMode; logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits diff --git a/pipelined/src/muldiv/muldiv.sv b/pipelined/src/muldiv/muldiv.sv index 53eef5eb7..5fa717e5f 100644 --- a/pipelined/src/muldiv/muldiv.sv +++ b/pipelined/src/muldiv/muldiv.sv @@ -41,7 +41,6 @@ module muldiv ( output logic [`XLEN-1:0] MDUResultW, // Divide Done output logic DivBusyE, - output logic DivE, // hazards input logic StallM, StallW, FlushM, FlushW, TrapM ); @@ -52,6 +51,7 @@ module muldiv ( logic [`XLEN*2-1:0] ProdM; logic DivSignedE; + logic DivE; logic W64M; // Multiplier diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv new file mode 100644 index 000000000..5363bb9b6 --- /dev/null +++ b/pipelined/src/ppa/ppa.sv @@ -0,0 +1,1007 @@ +// ppa.sv +// Teo Ene & David_Harris@hmc.edu 11 May 2022 +// & mmasserfrye@hmc.edu +// Measure PPA of various building blocks + +module ppa_comparator_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + +module ppa_comparator_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + +module ppa_comparator_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + +module ppa_comparator_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + +module ppa_comparator_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + ppa_comparator #(WIDTH) comp (.*); +endmodule + +module ppa_comparator #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, b, + input logic sgnd, + output logic [1:0] flags); + + logic eq, lt, ltu; + logic [WIDTH-1:0] af, bf; + + // For signed numbers, flip most significant bit + assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]}; + assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]}; + + // behavioral description gives best results + assign eq = (af == bf); + assign lt = (af < bf); + assign flags = {eq, lt}; +endmodule + +module ppa_add_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_add_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_add_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_add_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_add_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; +endmodule + +module ppa_mult_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + +module ppa_mult_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + +module ppa_mult_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + +module ppa_mult_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + +module ppa_mult_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, b, + output logic [WIDTH*2-1:0] y); //is this right width + assign y = a * b; +endmodule + +module ppa_alu_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + ppa_alu #(WIDTH) alu (.*); +endmodule + +module ppa_alu #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, + input logic [2:0] ALUControl, + input logic [2:0] Funct3, + output logic [WIDTH-1:0] Result, + output logic [WIDTH-1:0] Sum); + + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; + logic Carry, Neg; + logic LT, LTU; + logic W64, SubArith, ALUOp; + logic [2:0] ALUFunct; + logic Asign, Bsign; + + // Extract control signals + // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word + // SubArith indicates subtraction + // ALUOp = 0 for address generation addition or 1 for regular ALU + assign {W64, SubArith, ALUOp} = ALUControl; + + // addition + assign CondInvB = SubArith ? ~B : B; + assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + + // Shifts + ppa_shifter #(WIDTH) sh(.A, .Amt(B[$clog2(WIDTH)-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); + + // condition code flags based on subtract output Sum = A-B + // Overflow occurs when the numbers being subtracted have the opposite sign + // and the result has the opposite sign of A + assign Neg = Sum[WIDTH-1]; + assign Asign = A[WIDTH-1]; + assign Bsign = B[WIDTH-1]; + assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow + assign LTU = ~Carry; + + // SLT + assign SLT = {{(WIDTH-1){1'b0}}, LT}; + assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; + + // Select appropriate ALU Result + assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0 + always_comb + casez (ALUFunct) + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor + 3'b110: FullResult = A | B; // or + 3'b111: FullResult = A & B; // and + endcase + + assign Result = FullResult; + // not using W64 so it has the same architecture regardless of width + // // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits + // if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + // else assign Result = FullResult; +endmodule + +module ppa_shiftleft_8 #(parameter WIDTH=8) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_16 #(parameter WIDTH=16) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_32 #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_64 #(parameter WIDTH=64) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shiftleft_128 #(parameter WIDTH=128) ( + input logic [WIDTH-1:0] a, + input logic [$clog2(WIDTH)-1:0] amt, + output logic [WIDTH-1:0] y); + + assign y = a << amt; +endmodule + +module ppa_shifter #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Amt, + input logic Right, Arith, W64, + output logic [WIDTH-1:0] Y); + + logic [2*WIDTH-2:0] z, zshift; + logic [$clog2(WIDTH)-1:0] amttrunc, offset; + + // Handle left and right shifts with a funnel shifter. + // For RV32, only 32-bit shifts are needed. + // For RV64, 32 and 64-bit shifts are needed, with sign extension. + + // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) + // if (WIDTH == 64 | WIDTH ==128) begin:shifter // RV64 or 128 + // always_comb // funnel mux + // if (W64) begin // 32-bit shifts + // if (Right) + // if (Arith) z = {{WIDTH{1'b0}}, {WIDTH/2 -1{A[WIDTH/2 -1]}}, A[WIDTH/2 -1:0]}; + // else z = {{WIDTH*3/2-1{1'b0}}, A[WIDTH/2 -1:0]}; + // else z = {{WIDTH/2{1'b0}}, A[WIDTH/2 -1:0], {WIDTH-1{1'b0}}}; + // end else begin + // if (Right) + // if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + // else z = {{WIDTH-1{1'b0}}, A}; + // else z = {A, {WIDTH-1{1'b0}}}; + // end + // assign amttrunc = W64 ? {1'b0, Amt[$clog2(WIDTH)-2:0]} : Amt; // 32 or 64-bit shift + // end else begin:shifter // RV32 or less + // always_comb // funnel mux + // if (Right) + // if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + // else z = {{WIDTH-1{1'b0}}, A}; + // else z = {A, {WIDTH-1{1'b0}}}; + // assign amttrunc = Amt; // shift amount + // end + + always_comb // funnel mux + if (Right) + if (Arith) z = {{WIDTH-1{A[WIDTH-1]}}, A}; + else z = {{WIDTH-1{1'b0}}, A}; + else z = {A, {WIDTH-1{1'b0}}}; + assign amttrunc = Amt; // shift amount + + // opposite offset for right shfits + assign offset = Right ? amttrunc : ~amttrunc; + + // funnel operation + assign zshift = z >> offset; + assign Y = zshift[WIDTH-1:0]; +endmodule + + // module ppa_shifter_8 #(parameter WIDTH=8) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_16 #(parameter WIDTH=16) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_32 #(parameter WIDTH=32) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_64 #(parameter WIDTH=64) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + + // module ppa_shifter_128 #(parameter WIDTH=128) ( + // input logic [WIDTH-1:0] A, + // input logic [$clog2(WIDTH)-1:0] Amt, + // input logic Right, Arith, W64, + // output logic [WIDTH-1:0] Y); + + // ppa_shifter #(WIDTH) sh (.*); + // endmodule + +module ppa_prioritythermometer #(parameter N = 8) ( + input logic [N-1:0] a, + output logic [N-1:0] y); + + // Carefully crafted so design compiler will synthesize into a fast tree structure + // Rather than linear. + + // create thermometer code mask + genvar i; + assign y[0] = ~a[0]; + for (i=1; i Allowing coarser alignments in Vectored mode enables vectoring to be + // > implemented without a hardware adder circuit. + // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with + // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} + // However, this is program dependent, so not implemented at this time. + + always_comb + if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; + else PrivilegedTrapVector = MTVEC_REGW; + + if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec + always_comb + if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM) + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; + else + PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + else begin + assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + end + + always_comb + if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; + else if (mretM) PrivilegedNextPCM = MEPC_REGW; + else PrivilegedNextPCM = SEPC_REGW; + + /////////////////////////////////////////// + // CSRWriteValM + /////////////////////////////////////////// always_comb begin // Choose either rs1 or uimm[4:0] as source CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM; // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs - if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable}; + if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, MIP_REGW_writeable}; else CSRReadVal2M = CSRReadValM; // Compute AND/OR modification @@ -122,20 +172,28 @@ module csr #(parameter endcase end - // write CSRs + /////////////////////////////////////////// + // CSR Write values + /////////////////////////////////////////// assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? ((wfiM & InterruptM) ? PCM+4 : PCM) : CSRWriteValM; assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment - assign NextCauseM = TrapM ? CauseM : CSRWriteValM; + assign NextCauseM = TrapM ? {InterruptM, {(`XLEN-`LOG_XLEN-1){1'b0}}, CauseM}: CSRWriteValM; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign CSRMWriteM = CSRWriteM & (PrivilegeModeW == `M_MODE); assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW); assign CSRUWriteM = CSRWriteM; + assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); + assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; + + /////////////////////////////////////////// + // CSRs + /////////////////////////////////////////// csri csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, - .MExtIntM, .SExtIntM, .TimerIntM, .SwIntM, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable); + .MExtInt, .SExtInt, .MTimerInt, .MSwInt, + .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable); csrsr csrsr(.clk, .reset, .StallW, .WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM, .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW, @@ -145,7 +203,7 @@ module csr #(parameter .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TVM, .STATUS_FS, .BigEndianM); csrc counters(.clk, .reset, - .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, + .StallE, .StallM, .StallW, .FlushM, .FlushW, .InstrValidM, .LoadStallD, .CSRMWriteM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, @@ -166,7 +224,7 @@ module csr #(parameter .STATUS_TVM, .CSRWriteValM, .PrivilegeModeW, .CSRSReadValM, .STVEC_REGW, .SEPC_REGW, .SCOUNTEREN_REGW, - .SATP_REGW, .SIP_REGW, .SIE_REGW, + .SATP_REGW, .MIP_REGW, .MIE_REGW, .WriteSSTATUSM, .IllegalCSRSAccessM); csru csru(.clk, .reset, .InstrValidNotFlushedM, .StallW, .CSRUWriteM, .CSRAdrM, .CSRWriteValM, .STATUS_FS, .CSRUReadValM, diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv index 9d1417985..dbb6af756 100644 --- a/pipelined/src/privileged/csrc.sv +++ b/pipelined/src/privileged/csrc.sv @@ -43,7 +43,7 @@ module csrc #(parameter ) ( input logic clk, reset, input logic StallE, StallM, StallW, - input logic FlushE, FlushM, FlushW, + input logic FlushM, FlushW, input logic InstrValidM, LoadStallD, CSRMWriteM, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv index 343a900d9..bebad50dd 100644 --- a/pipelined/src/privileged/csri.sv +++ b/pipelined/src/privileged/csri.sv @@ -42,13 +42,11 @@ module csri #(parameter input logic CSRMWriteM, CSRSWriteM, input logic [`XLEN-1:0] CSRWriteValM, input logic [11:0] CSRAdrM, - (* mark_debug = "true" *) input logic MExtIntM, SExtIntM, TimerIntM, SwIntM, - input logic [11:0] MIDELEG_REGW, - output logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, - (* mark_debug = "true" *) output logic [11:0] IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 + (* mark_debug = "true" *) input logic MExtInt, SExtInt, MTimerInt, MSwInt, + output logic [11:0] MIP_REGW, MIE_REGW, + (* mark_debug = "true" *) output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0 ); - logic [11:0] IP_REGW, IE_REGW; logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK; logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM; @@ -63,8 +61,8 @@ module csri #(parameter // SEIP, STIP, SSIP is writable in MIP if S mode exists // SSIP is writable in SIP if S mode exists if (`S_SUPPORTED) begin:mask - assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writable in MIP (20210108-draft 3.1.9) - assign SIP_WRITE_MASK = 12'h002; // SSIP is writable in SIP (privileged 20210108-draft 4.1.3) + assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9) + assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3) assign MIE_WRITE_MASK = 12'hAAA; end else begin:mask assign MIP_WRITE_MASK = 12'h000; @@ -72,25 +70,13 @@ module csri #(parameter assign MIE_WRITE_MASK = 12'h888; end always @(posedge clk) - if (reset) IP_REGW_writeable <= 12'b0; - else if (WriteMIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); - else if (WriteSIPM) IP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK); + if (reset) MIP_REGW_writeable <= 12'b0; + else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK); + else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK); always @(posedge clk) - if (reset) IE_REGW <= 12'b0; - else if (WriteMIEM) IE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields - else if (WriteSIEM) IE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (IE_REGW & 12'h888); // only S fields - - assign IP_REGW = {MExtIntM,1'b0,SExtIntM|IP_REGW_writeable[9],1'b0,TimerIntM,1'b0,IP_REGW_writeable[5],1'b0,SwIntM,1'b0,IP_REGW_writeable[1],1'b0}; - - assign MIP_REGW = IP_REGW; - assign MIE_REGW = IE_REGW; - - if (`S_SUPPORTED) begin - assign SIP_REGW = IP_REGW & 12'h222; - assign SIE_REGW = IE_REGW & 12'h222; - end else begin - assign SIP_REGW = 12'b0; - assign SIE_REGW = 12'b0; - end + if (reset) MIE_REGW <= 12'b0; + else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields + else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields + assign MIP_REGW = {MExtInt,1'b0,SExtInt|MIP_REGW_writeable[9],1'b0,MTimerInt,1'b0,MIP_REGW_writeable[5],1'b0,MSwInt,1'b0,MIP_REGW_writeable[1],1'b0}; endmodule diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv index 21234fc60..33ffa0ecf 100644 --- a/pipelined/src/privileged/csrm.sv +++ b/pipelined/src/privileged/csrm.sv @@ -38,6 +38,7 @@ module csrm #(parameter MARCHID = 12'hF12, MIMPID = 12'hF13, MHARTID = 12'hF14, + MCONFIGPTR = 12'hF15, MSTATUS = 12'h300, MISA_ADR = 12'h301, MEDELEG = 12'h302, @@ -186,6 +187,7 @@ module csrm #(parameter MARCHID: CSRMReadValM = 0; MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0 + MCONFIGPTR: CSRMReadValM = 0; // hardwired to 0 MSTATUS: CSRMReadValM = MSTATUS_REGW; MSTATUSH: CSRMReadValM = MSTATUSH_REGW; MTVEC: CSRMReadValM = MTVEC_REGW; diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv index fb0b5cef7..d4000cdba 100644 --- a/pipelined/src/privileged/csrs.sv +++ b/pipelined/src/privileged/csrs.sv @@ -57,18 +57,15 @@ module csrs #(parameter input logic STATUS_TVM, input logic [`XLEN-1:0] CSRWriteValM, input logic [1:0] PrivilegeModeW, - output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW, + (* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW, (* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW, output logic [31:0] SCOUNTEREN_REGW, output logic [`XLEN-1:0] SATP_REGW, - (* mark_debug = "true" *) input logic [11:0] SIP_REGW, SIE_REGW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, output logic WriteSSTATUSM, output logic IllegalCSRSAccessM ); - //logic [`XLEN-1:0] zero = 0; - //logic [31:0] allones = {32{1'b1}}; - //logic [`XLEN-1:0] SEDELEG_MASK = ~(zero | 3'b111 << 9); // sedeleg[11:9] hardwired to zero per Privileged Spec 3.1.8 // Supervisor mode CSRs sometimes supported if (`S_SUPPORTED) begin:csrs @@ -105,8 +102,8 @@ module csrs #(parameter case (CSRAdrM) SSTATUS: CSRSReadValM = SSTATUS_REGW; STVEC: CSRSReadValM = STVEC_REGW; - SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIP_REGW}; - SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, SIE_REGW}; + SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222}; // only read supervisor fields + SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields SSCRATCH: CSRSReadValM = SSCRATCH_REGW; SEPC: CSRSReadValM = SEPC_REGW; SCAUSE: CSRSReadValM = SCAUSE_REGW; diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index ed5b51d4f..367c9e825 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -32,29 +32,67 @@ `include "wally-config.vh" module privdec ( + input logic clk, reset, + input logic StallM, input logic [31:20] InstrM, input logic PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, - input logic TrappedSRETM, WFITimeoutM, input logic [1:0] PrivilegeModeW, - input logic STATUS_TSR, STATUS_TVM, + input logic STATUS_TSR, STATUS_TVM, STATUS_TW, input logic [1:0] STATUS_FS, output logic IllegalInstrFaultM, - output logic sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM); + output logic EcallFaultM, BreakpointFaultM, + output logic sretM, mretM, wfiM, sfencevmaM); logic IllegalPrivilegedInstrM, IllegalOrDisabledFPUInstrM; + logic WFITimeoutM; + logic StallMQ; + logic ebreakM, ecallM; - // xRET defined in Privileged Spect 3.2.2 + /////////////////////////////////////////// + // Decode privileged instructions + /////////////////////////////////////////// assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & - PrivilegeModeW[0] & ~STATUS_TSR; + (PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); - assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); assign wfiM = PrivilegedM & (InstrM[31:20] == 12'b000100000101); assign sfencevmaM = PrivilegedM & (InstrM[31:25] == 7'b0001001) & (PrivilegeModeW == `M_MODE | (PrivilegeModeW == `S_MODE & ~STATUS_TVM)); + + /////////////////////////////////////////// + // WFI timeout Privileged Spec 3.1.6.5 + /////////////////////////////////////////// + if (`U_SUPPORTED) begin:wfi + logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; + assign WFICountPlus1 = WFICount + 1; + floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI + assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; + end else assign WFITimeoutM = 0; + + /////////////////////////////////////////// + // Extract exceptions by name and handle them + /////////////////////////////////////////// + assign BreakpointFaultM = ebreakM; // could have other causes from a debugger + assign EcallFaultM = ecallM; + + /////////////////////////////////////////// + // sfence.vma causes TLB flushes + /////////////////////////////////////////// + // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction + // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. + // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and + // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush + // after a cycle AND pulse it for another cycle on any further back-to-back sfences. +// flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); +// assign ITLBFlushF = sfencevmaM & ~StallMQ; +// assign DTLBFlushM = sfencevmaM; + + /////////////////////////////////////////// + // Fault on illegal instructions + /////////////////////////////////////////// assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM); assign IllegalOrDisabledFPUInstrM = IllegalFPUInstrM | (STATUS_FS == 2'b00); assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalOrDisabledFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | - TrappedSRETM | WFITimeoutM; + WFITimeoutM; endmodule diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 2d2877df2..f9f8a99a2 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -38,8 +38,8 @@ module privileged ( output logic [`XLEN-1:0] CSRReadValW, output logic [`XLEN-1:0] PrivilegedNextPCM, output logic RetM, TrapM, - output logic ITLBFlushF, DTLBFlushM, - input logic InstrValidM, CommittedM, DivE, + output logic sfencevmaM, + input logic InstrValidM, CommittedM, input logic FRegWriteM, LoadStallD, input logic BPPredDirWrongM, input logic BTBPredPCWrongM, @@ -55,7 +55,7 @@ module privileged ( input logic InstrMisalignedFaultM, IllegalIEUInstrFaultD, IllegalFPUInstrD, input logic LoadMisalignedFaultM, input logic StoreAmoMisalignedFaultM, - input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, + input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, input logic [`XLEN-1:0] IEUAdrM, input logic [4:0] SetFflagsM, @@ -69,7 +69,6 @@ module privileged ( input logic StoreAmoAccessFaultM, input logic SelHPTW, - output logic ExceptionM, output logic IllegalFPUInstrE, output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, @@ -82,76 +81,42 @@ module privileged ( output logic BreakpointFaultM, EcallFaultM, wfiM, IntPendingM, BigEndianM ); - logic [1:0] NextPrivilegeModeM; - - logic [`XLEN-1:0] CauseM, NextFaultMtvalM; - logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW; + logic [`LOG_XLEN-1:0] CauseM; logic [`XLEN-1:0] MEDELEG_REGW; logic [11:0] MIDELEG_REGW; - logic sretM, mretM, ecallM, ebreakM, sfencevmaM; + logic sretM, mretM; logic IllegalCSRAccessM; - logic IllegalIEUInstrFaultE, IllegalIEUInstrFaultM; + logic IllegalIEUInstrFaultM; logic IllegalFPUInstrM; - logic InstrPageFaultD, InstrPageFaultE, InstrPageFaultM; - logic InstrAccessFaultD, InstrAccessFaultE, InstrAccessFaultM; - logic IllegalInstrFaultM, TrappedSRETM; + logic InstrPageFaultM; + logic InstrAccessFaultM; + logic IllegalInstrFaultM; - logic MTrapM, STrapM, UTrapM; (* mark_debug = "true" *) logic InterruptM; logic STATUS_SPP, STATUS_TSR, STATUS_TW, STATUS_TVM; logic STATUS_MIE, STATUS_SIE; - logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW; - logic md; - logic StallMQ; - logic WFITimeoutM; - + logic [11:0] MIP_REGW, MIE_REGW; + logic [1:0] NextPrivilegeModeM; + logic DelegateM; /////////////////////////////////////////// // track the current privilege level /////////////////////////////////////////// - // get bits of DELEG registers based on CAUSE - assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; - - // PrivilegeMode FSM - always_comb begin - if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) - if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE)) - NextPrivilegeModeM = `S_MODE; - else NextPrivilegeModeM = `M_MODE; - end else if (mretM) NextPrivilegeModeM = STATUS_MPP; - else if (sretM) begin - if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin - NextPrivilegeModeM = PrivilegeModeW; - end else NextPrivilegeModeM = {1'b0, STATUS_SPP}; - end else NextPrivilegeModeM = PrivilegeModeW; - end - - assign TrappedSRETM = sretM & STATUS_TSR & PrivilegeModeW == `S_MODE; - - flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); - - /////////////////////////////////////////// - // WFI timeout Privileged Spec 3.1.6.5 - /////////////////////////////////////////// - if (`U_SUPPORTED) begin:wfi - logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1; - assign WFICountPlus1 = WFICount + 1; - floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount); // count while in WFI - assign WFITimeoutM = ((STATUS_TW & PrivilegeModeW != `M_MODE) | (`S_SUPPORTED & PrivilegeModeW == `U_MODE)) & WFICount[`WFI_TIMEOUT_BIT]; - end else assign WFITimeoutM = 0; - + privmode privmode(.clk, .reset, .StallW, .TrapM, .mretM, .sretM, .DelegateM, + .STATUS_MPP, .STATUS_SPP, .NextPrivilegeModeM, .PrivilegeModeW); /////////////////////////////////////////// // decode privileged instructions /////////////////////////////////////////// - privdec pmd(.InstrM(InstrM[31:20]), - .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM, - .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_FS, .IllegalInstrFaultM, - .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM); + privdec pmd(.clk, .reset, .StallM, .InstrM(InstrM[31:20]), + .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, + .PrivilegeModeW, .STATUS_TSR, .STATUS_TVM, .STATUS_TW, .STATUS_FS, .IllegalInstrFaultM, + .EcallFaultM, .BreakpointFaultM, + .sretM, .mretM, .wfiM, .sfencevmaM); /////////////////////////////////////////// // Control and Status Registers @@ -159,79 +124,47 @@ module privileged ( csr csr(.clk, .reset, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, - .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .wfiM, .InterruptM, - .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, + .InstrM, .PCM, .SrcAM, .IEUAdrM, + .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .NextPrivilegeModeM, .PrivilegeModeW, - .CauseM, .NextFaultMtvalM, .SelHPTW, + .CauseM, .SelHPTW, .STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM, - .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, .MEDELEG_REGW, .SATP_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, - .CSRReadValW, + .CSRReadValW,.PrivilegedNextPCM, .IllegalCSRAccessM, .BigEndianM); - /////////////////////////////////////////// - // Extract exceptions by name and handle them - /////////////////////////////////////////// + privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .InstrPageFaultF, .InstrAccessFaultF, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, + .IllegalFPUInstrE, + .InstrPageFaultM, .InstrAccessFaultM, .IllegalIEUInstrFaultM, .IllegalFPUInstrM); - assign BreakpointFaultM = ebreakM; // could have other causes too - assign EcallFaultM = ecallM; - - flopr #(1) StallMReg(.clk, .reset, .d(StallM), .q(StallMQ)); - assign ITLBFlushF = sfencevmaM & ~StallMQ; - assign DTLBFlushM = sfencevmaM; - // sets ITLBFlush to pulse for one cycle of the sfence.vma instruction - // In this instr we want to flush the tlb and then do a pagetable walk to update the itlb and continue the program. - // But we're still in the stalled sfence instruction, so if itlbflushf == sfencevmaM, tlbflush would never drop and - // the tlbwrite would never take place after the pagetable walk. by adding in ~StallMQ, we are able to drop itlbflush - // after a cycle AND pulse it for another cycle on any further back-to-back sfences. - - - // A page fault might occur because of insufficient privilege during a TLB - // lookup or a improperly formatted page table during walking - - // pipeline fault signals - flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, - {InstrPageFaultF, InstrAccessFaultF}, - {InstrPageFaultD, InstrAccessFaultD}); - flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, - {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, // ** vs IllegalInstrFaultInD - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); - flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, - {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, - {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); - // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021 - trap trap(.clk, .reset, + trap trap(.reset, .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM, .BreakpointFaultM, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM, .LoadPageFaultM, .StoreAmoPageFaultM, .mretM, .sretM, - .PrivilegeModeW, .NextPrivilegeModeM, - .MEPC_REGW, .SEPC_REGW, .STVEC_REGW, .MTVEC_REGW, - .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, + .PrivilegeModeW, + .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MEDELEG_REGW, .STATUS_MIE, .STATUS_SIE, - .PCM, - .IEUAdrM, - .InstrM, - .InstrValidM, .CommittedM, .DivE, - .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM, - .InterruptM, .IntPendingM, - .ExceptionM, - .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM); + .InstrValidM, .CommittedM, + .TrapM, .RetM, + .InterruptM, .IntPendingM, .DelegateM, + .CauseM); endmodule diff --git a/pipelined/src/privileged/privmode.sv b/pipelined/src/privileged/privmode.sv new file mode 100644 index 000000000..b09296429 --- /dev/null +++ b/pipelined/src/privileged/privmode.sv @@ -0,0 +1,59 @@ +/////////////////////////////////////////// +// privmode.sv +// +// Written: David_Harris@hmc.edu 12 May 2022 +// Modified: +// +// Purpose: Track privilege mode +// See RISC-V Privileged Mode Specification 20190608 3.1.10-11 +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module privmode ( + input logic clk, reset, + input logic StallW, TrapM, mretM, sretM, + input logic DelegateM, + input logic [1:0] STATUS_MPP, + input logic STATUS_SPP, + output logic [1:0] NextPrivilegeModeM, PrivilegeModeW +); + + if (`U_SUPPORTED) begin:privmode + // PrivilegeMode FSM + always_comb begin + if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) + if (`S_SUPPORTED & DelegateM) NextPrivilegeModeM = `S_MODE; + else NextPrivilegeModeM = `M_MODE; + end else if (mretM) NextPrivilegeModeM = STATUS_MPP; + else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP}; + else NextPrivilegeModeM = PrivilegeModeW; + end + + flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); + end else begin // only machine mode supported + assign NextPrivilegeModeM = `M_MODE; + assign PrivilegeModeW = `M_MODE; + end +endmodule \ No newline at end of file diff --git a/pipelined/src/privileged/privpiperegs.sv b/pipelined/src/privileged/privpiperegs.sv new file mode 100644 index 000000000..db1a77228 --- /dev/null +++ b/pipelined/src/privileged/privpiperegs.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// privpiperegs.sv +// +// Written: David_Harris@hmc.edu 12 May 2022 +// Modified: +// +// Purpose: Pipeline registers for early exceptions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module privpiperegs ( + input logic clk, reset, + input logic StallD, StallE, StallM, + input logic FlushD, FlushE, FlushM, + input logic InstrPageFaultF, InstrAccessFaultF, + input logic IllegalIEUInstrFaultD, IllegalFPUInstrD, + output logic IllegalFPUInstrE, + output logic InstrPageFaultM, InstrAccessFaultM, + output logic IllegalIEUInstrFaultM, IllegalFPUInstrM +); + + logic InstrPageFaultD, InstrAccessFaultD; + logic InstrPageFaultE, InstrAccessFaultE; + logic IllegalIEUInstrFaultE; + + // pipeline fault signals + flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD, + {InstrPageFaultF, InstrAccessFaultF}, + {InstrPageFaultD, InstrAccessFaultD}); + flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE, + {IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD}, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}); + flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM, + {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE}, + {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM}); +endmodule \ No newline at end of file diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index 953696a9a..35d680a62 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -32,133 +32,77 @@ `include "wally-config.vh" module trap ( - input logic clk, - input logic reset, + input logic reset, (* mark_debug = "true" *) input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM, (* mark_debug = "true" *) input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM, (* mark_debug = "true" *) input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM, (* mark_debug = "true" *) input logic LoadPageFaultM, StoreAmoPageFaultM, (* mark_debug = "true" *) input logic mretM, sretM, - input logic [1:0] PrivilegeModeW, NextPrivilegeModeM, - (* mark_debug = "true" *) input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, STVEC_REGW, MTVEC_REGW, - (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW, + input logic [1:0] PrivilegeModeW, + (* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, + input logic [`XLEN-1:0] MEDELEG_REGW, input logic STATUS_MIE, STATUS_SIE, - input logic [`XLEN-1:0] PCM, - input logic [`XLEN-1:0] IEUAdrM, - input logic [31:0] InstrM, - input logic InstrValidM, CommittedM, DivE, - output logic TrapM, MTrapM, STrapM, UTrapM, RetM, - output logic InterruptM, IntPendingM, - output logic ExceptionM, - output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM -// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW, -// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM + input logic InstrValidM, CommittedM, + output logic TrapM, RetM, + output logic InterruptM, IntPendingM, DelegateM, + output logic [`LOG_XLEN-1:0] CauseM ); logic MIntGlobalEnM, SIntGlobalEnM; + logic ExceptionM; (* mark_debug = "true" *) logic [11:0] PendingIntsM, ValidIntsM; - //logic InterruptM; - logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector; - logic Exception1M; + /////////////////////////////////////////// // Determine pending enabled interrupts // interrupt if any sources are pending // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage) // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice + /////////////////////////////////////////// assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) | ((PrivilegeModeW == `S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign PendingIntsM = MIP_REGW & MIE_REGW; assign IntPendingM = |PendingIntsM; assign ValidIntsM = {12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW; assign InterruptM = (|ValidIntsM) && InstrValidM && ~(CommittedM); // *** RT. CommittedM is a temporary hack to prevent integer division from having an interrupt during divide. + assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & + (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); + /////////////////////////////////////////// // Trigger Traps and RET // According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous. // Traps are the union of exceptions and interrupts. + /////////////////////////////////////////// assign ExceptionM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM | LoadMisalignedFaultM | StoreAmoMisalignedFaultM | InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | BreakpointFaultM | EcallFaultM | LoadAccessFaultM | StoreAmoAccessFaultM; - assign TrapM = ExceptionM | InterruptM; // *** clean this up later DH - assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE); - assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED; + assign TrapM = ExceptionM | InterruptM; assign RetM = mretM | sretM; - always_comb - if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; - else PrivilegedTrapVector = MTVEC_REGW; - - // Handle vectored traps (when mtvec/stvec csr value has bits [1:0] == 01) - // For vectored traps, set program counter to _tvec value + 4 times the cause code - // - // POSSIBLE OPTIMIZATION: - // From 20190608 privielegd spec page 27 (3.1.7) - // > Allowing coarser alignments in Vectored mode enables vectoring to be - // > implemented without a hardware adder circuit. - // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with - // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} - if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec - always_comb - if (PrivilegedTrapVector[1:0] == 2'b01 & CauseM[`XLEN-1] == 1) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + CauseM[`XLEN-3:0], 2'b00}; - else - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; - end - else begin - assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; - end - - always_comb - if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; - else if (mretM) PrivilegedNextPCM = MEPC_REGW; - else PrivilegedNextPCM = SEPC_REGW; - + /////////////////////////////////////////// // Cause priority defined in table 3.7 of 20190608 privileged spec // Exceptions are of lower priority than all interrupts (3.1.9) + /////////////////////////////////////////// always_comb - if (reset) CauseM = 0; // hard reset 3.3 - else if (ValidIntsM[11]) CauseM = (1 << (`XLEN-1)) + 11; // Machine External Int - else if (ValidIntsM[3]) CauseM = (1 << (`XLEN-1)) + 3; // Machine Sw Int - else if (ValidIntsM[7]) CauseM = (1 << (`XLEN-1)) + 7; // Machine Timer Int - else if (ValidIntsM[9]) CauseM = (1 << (`XLEN-1)) + 9; // Supervisor External Int - else if (ValidIntsM[1]) CauseM = (1 << (`XLEN-1)) + 1; // Supervisor Sw Int - else if (ValidIntsM[5]) CauseM = (1 << (`XLEN-1)) + 5; // Supervisor Timer Int - else if (InstrPageFaultM) CauseM = 12; - else if (InstrAccessFaultM) CauseM = 1; - else if (IllegalInstrFaultM) CauseM = 2; - else if (InstrMisalignedFaultM) CauseM = 0; - else if (BreakpointFaultM) CauseM = 3; - else if (EcallFaultM) CauseM = {{(`XLEN-2){1'b0}}, PrivilegeModeW} + 8; - else if (LoadMisalignedFaultM) CauseM = 4; + if (reset) CauseM = 0; // hard reset 3.3 + else if (ValidIntsM[11]) CauseM = 11; // Machine External Int + else if (ValidIntsM[3]) CauseM = 3; // Machine Sw Int + else if (ValidIntsM[7]) CauseM = 7; // Machine Timer Int + else if (ValidIntsM[9]) CauseM = 9; // Supervisor External Int + else if (ValidIntsM[1]) CauseM = 1; // Supervisor Sw Int + else if (ValidIntsM[5]) CauseM = 5; // Supervisor Timer Int + else if (InstrPageFaultM) CauseM = 12; + else if (InstrAccessFaultM) CauseM = 1; + else if (IllegalInstrFaultM) CauseM = 2; + else if (InstrMisalignedFaultM) CauseM = 0; + else if (BreakpointFaultM) CauseM = 3; + else if (EcallFaultM) CauseM = {{(`LOG_XLEN-4){1'b0}}, {2'b10}, PrivilegeModeW}; + else if (LoadMisalignedFaultM) CauseM = 4; else if (StoreAmoMisalignedFaultM) CauseM = 6; - else if (LoadPageFaultM) CauseM = 13; - else if (StoreAmoPageFaultM) CauseM = 15; - else if (LoadAccessFaultM) CauseM = 5; - else if (StoreAmoAccessFaultM) CauseM = 7; - else CauseM = 0; - - // MTVAL - // 3.1.17: on instruction fetch, load, or store address misaligned access or page fault - // mtval is written with the faulting virtual address. - // On illegal instruction trap, mtval may be written with faulting instruction - // For other traps (including interrupts), mtval is set to 0 - // *** hardware breakpoint is supposed to write faulting virtual address per priv p. 38 - // *** Page faults not yet implemented - // Technically - - always_comb - if (InstrPageFaultM) NextFaultMtvalM = PCM; - else if (InstrAccessFaultM) NextFaultMtvalM = PCM; - else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; - else if (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (EcallFaultM) NextFaultMtvalM = 0; - else if (BreakpointFaultM) NextFaultMtvalM = PCM; - else if (LoadMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoPageFaultM) NextFaultMtvalM = IEUAdrM; - else if (LoadAccessFaultM) NextFaultMtvalM = IEUAdrM; - else if (StoreAmoAccessFaultM) NextFaultMtvalM = IEUAdrM; - else NextFaultMtvalM = 0; + else if (LoadPageFaultM) CauseM = 13; + else if (StoreAmoPageFaultM) CauseM = 15; + else if (LoadAccessFaultM) CauseM = 5; + else if (StoreAmoAccessFaultM) CauseM = 7; + else CauseM = 0; endmodule diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/pipelined/src/uncore/ahbapbbridge.sv new file mode 100644 index 000000000..8ebd1d308 --- /dev/null +++ b/pipelined/src/uncore/ahbapbbridge.sv @@ -0,0 +1,110 @@ +/////////////////////////////////////////// +// ahbapbbridge.sv +// +// Written: David_Harris@hmc.edu & Nic Lucio 7 June 2022 +// +// Purpose: AHB to APB bridge +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ahbapbbridge #(PERIPHS = 2) ( + input logic HCLK, HRESETn, + input logic [PERIPHS-1:0] HSEL, + input logic [31:0] HADDR, + input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, + input logic HWRITE, + input logic [1:0] HTRANS, + input logic HREADY, +// input logic [3:0] HPROT, // not used + output logic [`XLEN-1:0] HRDATA, + output logic HRESP, HREADYOUT, + output logic PCLK, PRESETn, + output logic [PERIPHS-1:0] PSEL, + output logic PWRITE, + output logic PENABLE, + output logic [31:0] PADDR, + output logic [`XLEN-1:0] PWDATA, +// output logic [2:0] PPROT, // not used + output logic [`XLEN/8-1:0] PSTRB, +// output logic PWAKEUP // not used + input logic [PERIPHS-1:0] PREADY, + input var [PERIPHS-1:0][`XLEN-1:0] PRDATA +); + + + logic initTrans, initTransSel, initTransSelD; + logic nextPENABLE; + logic PREADYOUT; + + // convert AHB to APB signals + assign PCLK = HCLK; + assign PRESETn = HRESETn; + + // identify start of a transaction + assign initTrans = HTRANS[1] & HREADY; // start a transaction when the bus is ready and an active transaction is requested + assign initTransSel = initTrans & |HSEL; // capture data and address if any of the peripherals are selected + + // delay AHB Address phase signals to align with AHB Data phase because APB expects them at the same time + flopen #(32) addrreg(HCLK, HREADY, HADDR, PADDR); + flopenr #(1) writereg(HCLK, ~HRESETn, HREADY, HWRITE, PWRITE); + flopenr #(PERIPHS) selreg(HCLK, ~HRESETn, HREADY, HSEL & {PERIPHS{initTrans}}, PSEL); + // PPROT[2:0] = {Data/InstrB, Secure, Privileged}; + // assign PPROT = {~HPROT[0], 1'b0, HPROT[1]}; // protection not presently used + // assign PWAKEUP = 1'b1; // not used + + // AHB Data phase signal doesn't need delay. Note that they are guaranteed to remain stable until READY is asserted + assign PWDATA = HWDATA; + assign PSTRB = HWSTRB; + + // enable logic: goes high a cycle after initTrans, then back low on cycle after desired PREADY is asserted + // cycle1: AHB puts HADDR, HWRITE, HSEL on bus. initTrans is 1, and these are captured + // cycle2: AHB puts HWDATA on the bus. This effectively extends the setup phase + // cycle3: bridge raises PENABLE. Peripheral typically responds with PREADY. + // Read occurs by end of cycle. Write occurs at end of cycle. + flopr #(1) inittransreg(HCLK, ~HRESETn, initTransSel, initTransSelD); + assign nextPENABLE = PENABLE ? ~HREADY : initTransSelD; + flopr #(1) enablereg(HCLK, ~HRESETn, nextPENABLE, PENABLE); + + // result and ready multiplexer + int i; + always_comb begin + // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang + // *** also could assert ready right away + HRDATA = 0; + PREADYOUT = 1'b1; + for (i=0; i1 cycle to respond + // word aligned reads - if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000}; - else assign #2 entry = {HADDR[15:2], 2'b00}; + if (`XLEN==64) assign #2 entry = {PADDR[15:3], 3'b000}; + else assign #2 entry = {PADDR[15:2], 2'b00}; - swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM)); - // DH 2/20/21: Eventually allow MTIME to run off a separate clock // This will require synchronizing MTIME to the system clock // before it is read or compared to MTIMECMP. @@ -76,92 +66,90 @@ module clint ( // register access if (`XLEN==64) begin:clint // 64-bit - always @(posedge HCLK) begin + always @(posedge PCLK) begin case(entry) - 16'h0000: HREADCLINT <= {63'b0, MSIP}; - 16'h4000: HREADCLINT <= MTIMECMP; - 16'hBFF8: HREADCLINT <= MTIME; - default: HREADCLINT <= 0; + 16'h0000: PRDATA <= {63'b0, MSIP}; + 16'h4000: PRDATA <= MTIMECMP; + 16'hBFF8: PRDATA <= MTIME; + default: PRDATA <= 0; endcase end - always_ff @(posedge HCLK or negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK or negedge PRESETn) + if (~PRESETn) begin MSIP <= 0; - MTIMECMP <= 0; - // MTIMECMP is not reset + MTIMECMP <= 64'hFFFFFFFFFFFFFFFF; // Spec says MTIMECMP is not reset, but we reset to maximum value to prevent spurious timer interrupts end else if (memwrite) begin - if (entryd == 16'h0000) MSIP <= HWDATA[0]; - if (entryd == 16'h4000) begin + if (entry == 16'h0000) MSIP <= PWDATA[0]; + if (entry == 16'h4000) begin for(i=0;i<`XLEN/8;i++) - if(ByteMaskM[i]) - MTIMECMP[i*8 +: 8] <= HWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross + if(PSTRB[i]) + MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross end end // eventually replace MTIME logic below with timereg -// timereg tr(HCLK, HRESETn, TIMECLK, memwrite & (entryd==16'hBFF8), 1'b0, HWDATA, MTIME, done); +// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), 1'b0, PWDATA, MTIME, done); - always_ff @(posedge HCLK or negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK or negedge PRESETn) + if (~PRESETn) begin MTIME <= 0; - // MTIMECMP is not reset - end else if (memwrite & entryd == 16'hBFF8) begin + end else if (memwrite & entry == 16'hBFF8) begin // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed for(j=0;j<`XLEN/8;j++) - if(ByteMaskM[j]) - MTIME[j*8 +: 8] <= HWDATA[j*8 +: 8]; + if(PSTRB[j]) + MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8]; end else MTIME <= MTIME + 1; end else begin:clint // 32-bit - always @(posedge HCLK) begin + always @(posedge PCLK) begin case(entry) - 16'h0000: HREADCLINT <= {31'b0, MSIP}; - 16'h4000: HREADCLINT <= MTIMECMP[31:0]; - 16'h4004: HREADCLINT <= MTIMECMP[63:32]; - 16'hBFF8: HREADCLINT <= MTIME[31:0]; - 16'hBFFC: HREADCLINT <= MTIME[63:32]; - default: HREADCLINT <= 0; + 16'h0000: PRDATA <= {31'b0, MSIP}; + 16'h4000: PRDATA <= MTIMECMP[31:0]; + 16'h4004: PRDATA <= MTIMECMP[63:32]; + 16'hBFF8: PRDATA <= MTIME[31:0]; + 16'hBFFC: PRDATA <= MTIME[63:32]; + default: PRDATA <= 0; endcase end - always_ff @(posedge HCLK or negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK or negedge PRESETn) + if (~PRESETn) begin MSIP <= 0; MTIMECMP <= 0; // MTIMECMP is not reset ***? end else if (memwrite) begin - if (entryd == 16'h0000) MSIP <= HWDATA[0]; - if (entryd == 16'h4000) + if (entry == 16'h0000) MSIP <= PWDATA[0]; + if (entry == 16'h4000) for(j=0;j<`XLEN/8;j++) - if(ByteMaskM[j]) - MTIMECMP[j*8 +: 8] <= HWDATA[j*8 +: 8]; - if (entryd == 16'h4004) + if(PSTRB[j]) + MTIMECMP[j*8 +: 8] <= PWDATA[j*8 +: 8]; + if (entry == 16'h4004) for(j=0;j<`XLEN/8;j++) - if(ByteMaskM[j]) - MTIMECMP[32 + j*8 +: 8] <= HWDATA[j*8 +: 8]; + if(PSTRB[j]) + MTIMECMP[32 + j*8 +: 8] <= PWDATA[j*8 +: 8]; // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed end // eventually replace MTIME logic below with timereg -// timereg tr(HCLK, HRESETn, TIMECLK, memwrite & (entryd==16'hBFF8), memwrite & (entryd == 16'hBFFC), HWDATA, MTIME, done); - always_ff @(posedge HCLK or negedge HRESETn) - if (~HRESETn) begin +// timereg tr(PCLK, PRESETn, TIMECLK, memwrite & (entry==16'hBFF8), memwrite & (entry == 16'hBFFC), PWDATA, MTIME, done); + always_ff @(posedge PCLK or negedge PRESETn) + if (~PRESETn) begin MTIME <= 0; // MTIMECMP is not reset - end else if (memwrite & (entryd == 16'hBFF8)) begin + end else if (memwrite & (entry == 16'hBFF8)) begin for(i=0;i<`XLEN/8;i++) - if(ByteMaskM[i]) - MTIME[i*8 +: 8] <= HWDATA[i*8 +: 8]; - end else if (memwrite & (entryd == 16'hBFFC)) begin + if(PSTRB[i]) + MTIME[i*8 +: 8] <= PWDATA[i*8 +: 8]; + end else if (memwrite & (entry == 16'hBFFC)) begin // MTIME Counter. Eventually change this to run off separate clock. Synchronization then needed for(i=0;i<`XLEN/8;i++) - if(ByteMaskM[i]) - MTIME[32 + i*8 +: 8]<= HWDATA[i*8 +: 8]; + if(PSTRB[i]) + MTIME[32 + i*8 +: 8]<= PWDATA[i*8 +: 8]; end else MTIME <= MTIME + 1; end // Software interrupt when MSIP is set - assign SwIntM = MSIP; + assign MSwInt = MSIP; // Timer interrupt when MTIME >= MTIMECMP - assign TimerIntM = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison + assign MTimerInt = ({1'b0, MTIME} >= {1'b0, MTIMECMP}); // unsigned comparison endmodule @@ -185,18 +173,18 @@ module timeregsync( endmodule module timereg( - input logic HCLK, HRESETn, TIMECLK, + input logic PCLK, PRESETn, TIMECLK, input logic we0, we1, - input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN-1:0] PWDATA, output logic [63:0] MTIME, output logic done); -// if (`TIMEBASE_SYNC) begin:timereg // use HCLK for MTIME - if (1) begin:timereg // use HCLK for MTIME - timregsync timeregsync(.clk(HCLK), .resetn(HRESETn), .we0, .we1, .wd(HWDATA), .q(MTIME)); +// if (`TIMEBASE_SYNC) begin:timereg // use PCLK for MTIME + if (1) begin:timereg // use PCLK for MTIME + timregsync timeregsync(.clk(PCLK), .resetn(PRESETn), .we0, .we1, .wd(PWDATA), .q(MTIME)); assign done = 1; // immediately completes end else begin // use asynchronous TIMECLK - // TIME counter runs on TIMECLK but bus interface runs on HCLK + // TIME counter runs on TIMECLK but bus interface runs on PCLK // Need to synchronize reads and writes // This is subtle because synchronizing a binary counter on a per-bit basis could give a mix of old and new bits // Instead, we use a Gray coded counter that only changes one bit per cycle @@ -212,29 +200,29 @@ module timereg( // When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged // When the acknowledge falls, the transaction is done and the system is ready for another write. // ***look at redoing this assuming write enable and data are held rather than pulsed. - always_ff @(posedge HCLK or negedge HRESETn) - if (~HRESETn) + always_ff @(posedge PCLK or negedge PRESETn) + if (~PRESETn) req <= 0; // don't bother resetting wd else begin req <= we0 | we1 | req & ~ack; we0_stored <= we0; we1_stored <= we1; - wd_stored <= HWDATA; + wd_stored <= PWDATA; ack_stored <= ack; done <= ack_stored & ~ack; end // synchronize the reset and reqest into the TIMECLK domain - sync resetsync(TIMECLK, HRESETn, resetn_sync); + sync resetsync(TIMECLK, PRESETn, resetn_sync); sync rsync(TIMECLK, req, req_sync); - // synchronize the acknowledge back to the HCLK domain to indicate the request was handled and can be lowered - sync async(HCLK, req_sync, ack); + // synchronize the acknowledge back to the PCLK domain to indicate the request was handled and can be lowered + sync async(PCLK, req_sync, ack); timeregsync timeregsync(.clk(TIMECLK), .resetn(resetn_sync), .we0(we0_stored), .we1(we1_stored), .wd(wd_stored), .q(time_int)); binarytogray b2g(time_int, time_int_gc); flop gcreg(TIMECLK, time_int_gc, time_gc); - sync timesync[63:0](HCLK, time_gc, MTIME_GC); + sync timesync[63:0](PCLK, time_gc, MTIME_GC); graytobinary g2b(MTIME_GC, MTIME); end endmodule diff --git a/pipelined/src/uncore/gpio.sv b/pipelined/src/uncore/gpio_apb.sv similarity index 60% rename from pipelined/src/uncore/gpio.sv rename to pipelined/src/uncore/gpio_apb.sv index a70b44db4..e0d4f01d6 100644 --- a/pipelined/src/uncore/gpio.sv +++ b/pipelined/src/uncore/gpio_apb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// gpio.sv +// gpio_apb.sv // // Written: David_Harris@hmc.edu 14 January 2021 // Modified: bbracker@hmc.edu 15 Apr. 2021 @@ -32,16 +32,17 @@ `include "wally-config.vh" -module gpio ( - input logic HCLK, HRESETn, - input logic HSELGPIO, - input logic [7:0] HADDR, - input logic [`XLEN-1:0] HWDATA, - input logic HWRITE, - input logic HREADY, - input logic [1:0] HTRANS, - output logic [`XLEN-1:0] HREADGPIO, - output logic HRESPGPIO, HREADYGPIO, +module gpio_apb ( + input logic PCLK, PRESETn, + input logic PSEL, + input logic [7:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, + input logic [31:0] iof0, iof1, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, output logic GPIOIntr); @@ -49,39 +50,34 @@ module gpio ( logic [31:0] input0d, input1d, input2d, input3d; logic [31:0] input_val, input_en, output_en, output_val; logic [31:0] rise_ie, rise_ip, fall_ie, fall_ip, high_ie, high_ip, low_ie, low_ip; + logic [31:0] out_xor, iof_en, iof_sel, iof_out, gpio_out; - logic initTrans, memwrite; - logic [7:0] entry, entryd; + logic [7:0] entry; logic [31:0] Din, Dout; + logic memwrite; - // AHB I/O - assign entry = {HADDR[7:2],2'b0}; - assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00); - // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data - flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite); - flopr #(8) entrydflop(HCLK, ~HRESETn, entry, entryd); - assign HRESPGPIO = 0; // OK - assign HREADYGPIO = 1'b1; // GPIO never takes >1 cycle to respond + // APB I/O + assign entry = {PADDR[7:2],2'b00}; // 32-bit word-aligned accesses + assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase + assign PREADY = 1'b1; // GPIO never takes >1 cycle to respond // account for subword read/write circuitry // -- Note GPIO registers are 32 bits no matter what; access them with LW SW. // (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported") if (`XLEN == 64) begin - assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0]; - assign HREADGPIO = entryd[2] ? {Dout,32'b0} : {32'b0,Dout}; + assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0]; + assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout}; end else begin // 32-bit - assign Din = HWDATA[31:0]; - assign HREADGPIO = Dout; + assign Din = PWDATA[31:0]; + assign PRDATA = Dout; end // register access - always_ff @(posedge HCLK, negedge HRESETn) begin - // writes - if (~HRESETn) begin - // asynch reset + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin // asynch reset input_en <= 0; output_en <= 0; - // *** synch reset not yet implemented + // *** synch reset not yet implemented [DH: can we delete this comment? Check if a sync reset is required] output_val <= #1 0; rise_ie <= #1 0; rise_ip <= #1 0; @@ -91,12 +87,14 @@ module gpio ( high_ip <= #1 0; low_ie <= #1 0; low_ip <= #1 0; - end else begin - // writes - if (memwrite) + iof_en <= #1 0; + iof_sel <= #1 0; + out_xor <= #1 0; + end else begin // writes // According to FE310 spec: Once the interrupt is pending, it will remain set until a 1 is written to the *_ip register at that bit. /* verilator lint_off CASEINCOMPLETE */ - case(entryd) + if (memwrite) + case(entry) 8'h04: input_en <= #1 Din; 8'h08: output_en <= #1 Din; 8'h0C: output_val <= #1 Din; @@ -104,11 +102,23 @@ module gpio ( 8'h20: fall_ie <= #1 Din; 8'h28: high_ie <= #1 Din; 8'h30: low_ie <= #1 Din; - 8'h40: output_val <= #1 output_val ^ Din; // OUT_XOR + 8'h38: iof_en <= #1 Din; + 8'h3C: iof_sel <= #1 Din; + 8'h40: out_xor <= #1 Din; endcase /* verilator lint_on CASEINCOMPLETE */ - // reads - case(entry) + + // interrupts can be cleared by writing corresponding bits to a register + if (memwrite & entry == 8'h1C) rise_ip <= rise_ip & ~Din; + else rise_ip <= rise_ip | (input2d & ~input3d); + if (memwrite & (entry == 8'h24)) fall_ip <= fall_ip & ~Din; + else fall_ip <= fall_ip | (~input2d & input3d); + if (memwrite & (entry == 8'h2C)) high_ip <= high_ip & ~Din; + else high_ip <= high_ip | input3d; + if (memwrite & (entry == 8'h34)) low_ip <= low_ip & ~Din; + else low_ip <= low_ip | ~input3d; + + case(entry) // flop to sample inputs 8'h00: Dout <= #1 input_val; 8'h04: Dout <= #1 input_en; 8'h08: Dout <= #1 output_en; @@ -121,38 +131,26 @@ module gpio ( 8'h2C: Dout <= #1 high_ip; 8'h30: Dout <= #1 low_ie; 8'h34: Dout <= #1 low_ip; - 8'h40: Dout <= #1 0; // OUT_XOR reads as 0 + 8'h38: Dout <= #1 iof_en; + 8'h3C: Dout <= #1 iof_sel; + 8'h40: Dout <= #1 out_xor; default: Dout <= #1 0; endcase - // interrupts - if (memwrite & (entryd == 8'h1C)) - rise_ip <= rise_ip & ~Din; - else - rise_ip <= rise_ip | (input2d & ~input3d); - if (memwrite & (entryd == 8'h24)) - fall_ip <= fall_ip & ~Din; - else - fall_ip <= fall_ip | (~input2d & input3d); - if (memwrite & (entryd == 8'h2C)) - high_ip <= high_ip & ~Din; - else - high_ip <= high_ip | input3d; - if (memwrite & (entryd == 8'h34)) - low_ip <= low_ip & ~Din; - else - low_ip <= low_ip | ~input3d; end - end // chip i/o // connect OUT to IN for loopback testing if (`GPIO_LOOPBACK_TEST) assign input0d = ((output_en & GPIOPinsOut) | (~output_en & GPIOPinsIn)) & input_en; else assign input0d = GPIOPinsIn & input_en; - flop #(32) sync1(HCLK,input0d,input1d); - flop #(32) sync2(HCLK,input1d,input2d); - flop #(32) sync3(HCLK,input2d,input3d); + + // synchroninzer for inputs + flop #(32) sync1(PCLK,input0d,input1d); + flop #(32) sync2(PCLK,input1d,input2d); + flop #(32) sync3(PCLK,input2d,input3d); assign input_val = input3d; - assign GPIOPinsOut = output_val; + assign iof_out = iof_sel & iof1 | ~iof_sel & iof0; // per-bit mux between iof1 and iof0 + assign gpio_out = iof_en & iof_out | ~iof_en & output_val; // per-bit mux between IOF and output_val + assign GPIOPinsOut = gpio_out ^ out_xor; // per-bit flip output polarity assign GPIOPinsEn = output_en; assign GPIOIntr = |{(rise_ip & rise_ie),(fall_ip & fall_ie),(high_ip & high_ie),(low_ip & low_ie)}; diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic_apb.sv similarity index 85% rename from pipelined/src/uncore/plic.sv rename to pipelined/src/uncore/plic_apb.sv index fd3f5d1d2..51e94d7f4 100644 --- a/pipelined/src/uncore/plic.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// plic.sv +// plic_apb.sv // // Written: bbracker@hmc.edu 18 January 2021 // Modified: @@ -46,21 +46,21 @@ // number of conexts // hardcoded to 2 contexts for now; *** later upgrade to arbitrary (up to 15872) contexts -module plic ( - input logic HCLK, HRESETn, - input logic HSELPLIC, - input logic [27:0] HADDR, // *** could factor out entryd into HADDRd at the level of uncore - input logic HWRITE, - input logic HREADY, - input logic [1:0] HTRANS, - input logic [`XLEN-1:0] HWDATA, +module plic_apb ( + input logic PCLK, PRESETn, + input logic PSEL, + input logic [27:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, input logic UARTIntr,GPIOIntr, - output logic [`XLEN-1:0] HREADPLIC, - output logic HRESPPLIC, HREADYPLIC, - (* mark_debug = "true" *) output logic MExtIntM, SExtIntM); + (* mark_debug = "true" *) output logic MExtInt, SExtInt); logic memwrite, memread, initTrans; - logic [23:0] entry, entryd; + logic [23:0] entry; logic [31:0] Din, Dout; // context-independent signals @@ -81,31 +81,28 @@ module plic ( // ======= // AHB I/O // ======= - assign entry = {HADDR[23:2],2'b0}; - assign initTrans = HREADY & HSELPLIC & (HTRANS != 2'b00); - assign memread = initTrans & ~HWRITE; - // entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data - flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite); - flopr #(24) entrydflop(HCLK, ~HRESETn, entry, entryd); - assign HRESPPLIC = 0; // OK - assign HREADYPLIC = 1'b1; // PLIC never takes >1 cycle to respond + + assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase + assign memread = ~PWRITE & PSEL; // read at start of access phase. PENABLE hasn't set up before this + assign PREADY = 1'b1; // PLIC never takes >1 cycle to respond + assign entry = {PADDR[23:2],2'b0}; // account for subword read/write circuitry // -- Note PLIC registers are 32 bits no matter what; access them with LW SW. if (`XLEN == 64) begin - assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0]; - assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout}; + assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0]; + assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout}; end else begin // 32-bit - assign HREADPLIC = Dout; - assign Din = HWDATA[31:0]; + assign PRDATA = Dout; + assign Din = PWDATA[31:0]; end // ================== // Register Interface // ================== - always @(posedge HCLK,negedge HRESETn) begin + always @(posedge PCLK,negedge PRESETn) begin // resetting - if (~HRESETn) begin + if (~PRESETn) begin intPriority <= #1 {`N{3'b0}}; intEn <= #1 {2{`N'b0}}; intThreshold <= #1 {2{3'b0}}; @@ -113,8 +110,8 @@ module plic ( // writing end else begin if (memwrite) - casez(entryd) - 24'h0000??: intPriority[entryd[7:2]] <= #1 Din[2:0]; + casez(entry) + 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; `ifdef PLIC_NUM_SRC_LT_32 // *** switch to a generate for loop so as to deprecate PLIC_NUM_SRC_LT_32 and allow up to 1023 sources 24'h002000: intEn[0][`N:1] <= #1 Din[`N:1]; 24'h002080: intEn[1][`N:1] <= #1 Din[`N:1]; @@ -130,7 +127,7 @@ module plic ( 24'h201000: intThreshold[1] <= #1 Din[2:0]; 24'h201004: intInProgress <= #1 intInProgress & ~(`N'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion endcase - // reading + // Read synchronously because a read can have side effect of changing intInProgress if (memread) casez(entry) 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; @@ -159,9 +156,8 @@ module plic ( end default: Dout <= #1 32'h0; // invalid access endcase - else - Dout <= #1 32'h0; - end + else Dout <= #1 32'h0; + end end // connect sources to requests @@ -176,8 +172,9 @@ module plic ( end // pending interrupt requests - assign nextIntPending = (intPending | requests) & ~intInProgress; - flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending); + assign nextIntPending = (intPending | requests) & ~intInProgress; // dh changed back 7/9/22 see if Buildroot still boots. Confirmed to boot successfully. + //assign nextIntPending = requests; // DH: RT made this change May 2022, but it seems to be a bug to not consider intInProgress; see May 23, 2022 slack discussion + flopr #(`N) intPendingFlop(PCLK,~PRESETn,nextIntPending,intPending); // context-dependent signals genvar ctx; @@ -252,7 +249,7 @@ module plic ( end // is the max priority > threshold? // *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold? - assign MExtIntM = |(threshMask[0] & priorities_with_irqs[0]); - assign SExtIntM = |(threshMask[1] & priorities_with_irqs[1]); + assign MExtInt = |(threshMask[0] & priorities_with_irqs[0]); + assign SExtInt = |(threshMask[1] & priorities_with_irqs[1]); endmodule diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv index 442bfc508..b850321e8 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/ram.sv @@ -38,69 +38,39 @@ module ram #(parameter BASE=0, RANGE = 65535) ( input logic HREADY, input logic [1:0] HTRANS, input logic [`XLEN-1:0] HWDATA, - input logic [3:0] HSIZED, + input logic [`XLEN/8-1:0] HWSTRB, output logic [`XLEN-1:0] HREADRam, output logic HRESPRam, HREADYRam ); - // Desired changes. - // 1. find a way to merge read and write address into 1 port. - // 2. remove all unnecessary latencies. (HREADY needs to be able to constant high.) - // 3. implement burst. - // 4. remove the configurable latency. + localparam ADDR_WIDTH = $clog2(RANGE/8); + localparam OFFSET = $clog2(`XLEN/8); - logic [`XLEN/8-1:0] ByteMaskM; - logic [31:0] HWADDR, A; - logic prevHREADYRam, risingHREADYRam; + logic [`XLEN/8-1:0] ByteMask; + logic [31:0] HADDRD, RamAddr; logic initTrans; - logic memwrite; - logic [3:0] busycount; - - swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM)); + logic memwrite, memwriteD, memread; + logic nextHREADYRam; - assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); + // a new AHB transactions starts when HTRANS requests a transaction, + // the peripheral is selected, and the previous transaction is completing + assign initTrans = HREADY & HSELRam & (HTRANS[1]); + assign memwrite = initTrans & HWRITE; + assign memread = initTrans & ~HWRITE; + + flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); + flopenr #(32) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD); - // *** this seems like a weird way to use reset - flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam & HWRITE, memwrite); - flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A); - // busy FSM to extend READY signal - always @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin - busycount <= 0; - HREADYRam <= #1 0; - end else begin - if (initTrans) begin - busycount <= 0; - HREADYRam <= #1 0; - end else if (~HREADYRam) begin - if (busycount == 0) begin // Ram latency, for testing purposes. *** test with different values such as 2 - HREADYRam <= #1 1; - end else begin - busycount <= busycount + 1; - end - end - end + // Stall on a read after a write because the RAM can't take both adddresses on the same cycle + assign nextHREADYRam = ~(memwriteD & memread); + flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam); assign HRESPRam = 0; // OK - localparam ADDR_WDITH = $clog2(RANGE/8); - localparam OFFSET = $clog2(`XLEN/8); - - // Rising HREADY edge detector - // Indicates when ram is finishing up - // Needed because HREADY may go high for other reasons, - // and we only want to write data when finishing up. - flopenr #(1) prevhreadyRamreg(HCLK,~HRESETn, 1'b1, HREADYRam,prevHREADYRam); - assign risingHREADYRam = HREADYRam & ~prevHREADYRam; + // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address + mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); - always @(posedge HCLK) - HWADDR <= #1 A; - - bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA) - memory(.clk(HCLK), .enaA(1'b1), - .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam), - .enaB(memwrite & risingHREADYRam), .weB(ByteMaskM), - .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); - - + // single-ported RAM + bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH) + memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); endmodule diff --git a/pipelined/src/uncore/sdc/SDC.sv b/pipelined/src/uncore/sdc/SDC.sv index 2aa548d87..0c34e1843 100644 --- a/pipelined/src/uncore/sdc/SDC.sv +++ b/pipelined/src/uncore/sdc/SDC.sv @@ -144,7 +144,7 @@ module SDC // currently does not support writes - assign InitTrans = HREADY & HSELSDC & (HTRANS != 2'b00); + assign InitTrans = HREADY & HSELSDC & HTRANS[1]; //assign RegRead = InitTrans & ~HWRITE; // register resolve combo loop flopr #(1) RegReadReg(HCLK, ~HRESETn, InitTrans & ~HWRITE, RegRead); diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv index 7c46e885d..a55350c6a 100644 --- a/pipelined/src/uncore/uartPC16550D.sv +++ b/pipelined/src/uncore/uartPC16550D.sv @@ -40,7 +40,7 @@ module uartPC16550D( // Processor Interface - input logic HCLK, HRESETn, + input logic PCLK, PRESETn, input logic [2:0] A, input logic [7:0] Din, output logic [7:0] Dout, @@ -93,8 +93,8 @@ module uartPC16550D( logic [10:0] rxfifo[15:0]; logic [7:0] txfifo[15:0]; logic [4:0] rxfifotailunwrapped; - logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; - logic [3:0] rxfifoentries, txfifoentries; +(* mark_debug = "true" *) logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel; +(* mark_debug = "true" *) logic [3:0] rxfifoentries, txfifoentries; logic [3:0] rxbitsexpected, txbitsexpected; // receive data @@ -103,8 +103,8 @@ module uartPC16550D( logic rxcentered; logic rxparity, rxparitybit, rxstopbit; (* mark_debug = "true" *) logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr; - logic rxdataready; - logic rxfifoempty, rxfifotriggered, rxfifotimeout; +(* mark_debug = "true" *) logic rxdataready; +(* mark_debug = "true" *) logic rxfifoempty, rxfifotriggered, rxfifotimeout; logic rxfifodmaready; logic [8:0] rxdata9; logic [7:0] rxdata; @@ -119,20 +119,20 @@ module uartPC16550D( logic txfifoempty, txfifofull, txfifodmaready; // control signals - logic fifoenabled, fifodmamodesel, evenparitysel; +(* mark_debug = "true" *) logic fifoenabled, fifodmamodesel, evenparitysel; // interrupts - logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP; - logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP; - logic rxdataavailintr, modemstatusintr, intrpending; - logic [2:0] intrID; +(* mark_debug = "true" *) logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP; +(* mark_debug = "true" *) logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP; +(* mark_debug = "true" *) logic rxdataavailintr, modemstatusintr, intrpending; +(* mark_debug = "true" *) logic [2:0] intrID; logic baudpulseComb; /////////////////////////////////////////// // Input synchronization: 2-stage synchronizer /////////////////////////////////////////// - always_ff @(posedge HCLK) begin + always_ff @(posedge PCLK) begin {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb}; {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing @@ -142,8 +142,8 @@ module uartPC16550D( /////////////////////////////////////////// // Register interface (Table 1, note some are read only and some write only) /////////////////////////////////////////// - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin // Table 3 Reset Configuration + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin // Table 3 Reset Configuration IER <= #1 4'b0; FCR <= #1 8'b0; if (`QEMU) LCR <= #1 8'b0; else LCR <= #1 8'b11; // fpga only **** BUG @@ -165,6 +165,7 @@ module uartPC16550D( SCR <= #1 8'b0; // not strictly necessary to reset end else begin if (~MEMWb) begin + /* verilator lint_off CASEINCOMPLETE */ case (A) /* -----\/----- EXCLUDED -----\/----- 3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section @@ -177,34 +178,42 @@ module uartPC16550D( // freq /baud / 16 = div //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in - 3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in + 3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in 3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0]; - 3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing 3'b011: LCR <= #1 Din; 3'b100: MCR <= #1 Din[4:0]; - 3'b101: LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3 - 3'b110: MSR <= #1 Din[3:0]; 3'b111: SCR <= #1 Din; endcase + /* verilator lint_on CASEINCOMPLETE */ end - + // Line Status Register (8.6.3) - // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay. - LSR[0] <= #1 rxdataready; // Data ready - LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error - LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error - LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error - LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator - LSR[5] <= #1 THRE; // THRE - LSR[6] <= #1 ~txsrfull & THRE; // TEMT - if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error + // Ben 6/9/21 I don't like how this is a register. A lot of the individual bits have clocked components, so this just adds unecessary delay. + if (~MEMWb & (A == 3'b101)) + LSR[6:1] <= #1 Din[6:1]; // recommended only for test, see 8.6.3 + else begin + LSR[0] <= #1 rxdataready; // Data ready + LSR[1] <= #1 (LSR[1] | RXBR[10]) & ~squashRXerrIP;; // overrun error + LSR[2] <= #1 (LSR[2] | RXBR[9]) & ~squashRXerrIP; // parity error + LSR[3] <= #1 (LSR[3] | RXBR[8]) & ~squashRXerrIP; // framing error + LSR[4] <= #1 (LSR[4] | rxbreak) & ~squashRXerrIP; // break indicator + LSR[5] <= #1 THRE; // THRE + LSR[6] <= #1 ~txsrfull & THRE; // TEMT + if (rxfifohaserr) LSR[7] <= #1 1; // any bits in FIFO have error + end // Modem Status Register (8.6.8) - MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send - MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready - MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator - MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect + if (~MEMWb & (A == 3'b110)) + MSR <= #1 Din[3:0]; + else if (~MEMRb & (A == 3'b110)) + MSR <= #1 4'b0; // Reading MSR clears the flags in MSR bits 3:0 + else begin + MSR[0] <= #1 MSR[0] | CTSb2 ^ CTSbsync; // Delta Clear to Send + MSR[1] <= #1 MSR[1] | DSRb2 ^ DSRbsync; // Delta Data Set Ready + MSR[2] <= #1 MSR[2] | (~RIb2 & RIbsync); // Trailing Edge of Ring Indicator + MSR[3] <= #1 MSR[3] | DCDb2 ^ DCDbsync; // Delta Data Carrier Detect + end end always_comb if (~MEMRb) @@ -215,7 +224,8 @@ module uartPC16550D( 3'b011: Dout = LCR; 3'b100: Dout = {3'b000, MCR}; 3'b101: Dout = LSR; - 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; + // 3'b110: Dout = {~CTSbsync, ~DSRbsync, ~RIbsync, ~DCDbsync, MSR[3:0]}; + 3'b110: Dout = {~DCDbsync, ~RIbsync, ~DSRbsync, ~CTSbsync, MSR[3:0]}; 3'b111: Dout = SCR; endcase else Dout = 8'b0; @@ -229,8 +239,8 @@ module uartPC16550D( /////////////////////////////////////////// // Ross Thompson: Found a bug. If the baud rate dividers DLM, and DLL are reloaded // the baudcount is not reset to {DLM, DLL, UART_PRESCALE} - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin baudcount <= #1 1; baudpulse <= #1 0; end else if (~MEMWb & DLAB & (A == 3'b0 | A == 3'b1)) begin @@ -254,8 +264,8 @@ module uartPC16550D( /////////////////////////////////////////// // receive timing and control /////////////////////////////////////////// - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin rxoversampledcnt <= #1 0; rxstate <= #1 UART_IDLE; rxbitsreceived <= #1 0; @@ -288,8 +298,8 @@ module uartPC16550D( /////////////////////////////////////////// // receive shift register, buffer register, FIFO /////////////////////////////////////////// - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) rxshiftreg <= #1 10'b0000000001; // initialize so that there is a valid stop bit else if (rxcentered) rxshiftreg <= #1 {rxshiftreg[8:0], SINsync}; // capture bit assign rxparitybit = rxshiftreg[1]; // parity, if it exists, in bit 1 when all done assign rxstopbit = rxshiftreg[0]; @@ -304,21 +314,23 @@ module uartPC16550D( // ERROR CONDITIONS assign rxparity = ^rxdata; - assign rxparityerr = rxparity ^ rxparitybit ^ ~evenparitysel; // Check even/odd parity (*** check if LCR needs to be inverted) + assign rxparityerr = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted) assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full assign rxframingerr = ~rxstopbit; // framing error if no stop bit assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time // receive FIFO and register - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; end else begin - if (rxstate == UART_DONE) begin + if (~MEMWb & (A == 3'b010) & Din[1]) begin + rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; + end else if (rxstate == UART_DONE) begin RXBR <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; // load recevive buffer register - if (rxoverrunerr) $warning("UART RX Overrun Error\n"); - if (rxparityerr) $warning("UART RX Parity Error\n"); - if (rxframingerr) $warning("UART RX Framing Error\n"); + if (rxoverrunerr) $warning("UART RX Overrun Err\n"); + if (rxparityerr) $warning("UART RX Parity Err\n"); + if (rxframingerr) $warning("UART RX Framing Err\n"); if (fifoenabled) begin rxfifo[rxfifohead] <= #1 {rxoverrunerr, rxparityerr, rxframingerr, rxdata}; rxfifohead <= #1 rxfifohead + 1; @@ -326,8 +338,9 @@ module uartPC16550D( rxdataready <= #1 1; end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo if (fifoenabled) begin - if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1; - if (rxfifohead == rxfifotail +1) rxdataready <= #1 0; + if (~rxfifoempty) rxfifotail <= #1 rxfifotail + 1; + // if (rxfifoempty) rxdataready <= #1 0; + if (rxfifoentries == 1) rxdataready <= #1 0; // When reading the last entry, data ready becomes zero end else begin rxdataready <= #1 0; RXBR <= #1 {1'b0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode) @@ -367,8 +380,8 @@ module uartPC16550D( assign rxfifohaserr = |(RXerrbit & rxfullbit); // receive buffer register and ready bit - always_ff @(posedge HCLK, negedge HRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) - if (~HRESETn) rxfifodmaready <= #1 0; + always_ff @(posedge PCLK, negedge PRESETn) // track rxrdy for DMA mode (FCR3 = FCR0 = 1) + if (~PRESETn) rxfifodmaready <= #1 0; else if (rxfifotriggered | rxfifotimeout) rxfifodmaready <= #1 1; else if (rxfifoempty) rxfifodmaready <= #1 0; @@ -386,8 +399,8 @@ module uartPC16550D( /////////////////////////////////////////// // transmit timing and control /////////////////////////////////////////// - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin txoversampledcnt <= #1 0; txstate <= #1 UART_IDLE; txbitssent <= #1 0; @@ -405,7 +418,7 @@ module uartPC16550D( txstate <= #1 UART_IDLE; end - assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) + assign txbitsexpected = 4'd1 + (4'd5 + {2'b00, LCR[1:0]}) + {3'b000, LCR[3]} + 4'd1 + {3'b000, LCR[2]} - 4'd1; // start bit + data bits + (parity bit) + stop bit(s) - 1 // *** explain; is this necessary? if (`QEMU) assign txnextbit = txbaudpulse & (txoversampledcnt[1:0] == 2'b00); // implies txstate = UART_ACTIVE else assign txnextbit = txbaudpulse & (txoversampledcnt == 4'b0000); // implies txstate = UART_ACTIVE @@ -435,9 +448,11 @@ module uartPC16550D( end // registers & FIFO - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin + always_ff @(posedge PCLK, negedge PRESETn) + if (~PRESETn) begin txfifohead <= #1 0; txfifotail <= #1 0; txhrfull <= #1 0; txsrfull <= #1 0; TXHR <= #1 0; txsr <= #1 12'hfff; + end else if (~MEMWb & (A == 3'b010) & Din[2]) begin + txfifohead <= #1 0; txfifotail <= #1 0; end else begin if (~MEMWb & A == 3'b000 & ~DLAB) begin // writing transmit holding register or fifo if (fifoenabled) begin @@ -451,7 +466,7 @@ module uartPC16550D( end if (txstate == UART_IDLE) begin // move data into tx shift register if available if (fifoenabled) begin - if (~txfifoempty) begin + if (~txfifoempty & ~txsrfull) begin txsr <= #1 txdata; txfifotail <= #1 txfifotail+1; txsrfull <= #1 1; @@ -477,8 +492,8 @@ module uartPC16550D( assign txfifofull = (txfifoentries == 4'b1111); // transmit buffer ready bit - always_ff @(posedge HCLK, negedge HRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1) - if (~HRESETn) txfifodmaready <= #1 0; + always_ff @(posedge PCLK, negedge PRESETn) // track txrdy for DMA mode (FCR3 = FCR0 = 1) + if (~PRESETn) txfifodmaready <= #1 0; else if (txfifoempty) txfifodmaready <= #1 1; else if (txfifofull) txfifodmaready <= #1 0; @@ -514,18 +529,18 @@ module uartPC16550D( intrpending = 0; end end - always @(posedge HCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin + always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin // Side effect of reading LSR is lowering overrun, parity, framing, break intr's assign setSquashRXerrIP = ~MEMRb & (A==3'b101); assign resetSquashRXerrIP = (rxstate == UART_DONE); assign squashRXerrIP = (prevSquashRXerrIP | setSquashRXerrIP) & ~resetSquashRXerrIP; - flopr #(1) squashRXerrIPreg(HCLK, ~HRESETn, squashRXerrIP, prevSquashRXerrIP); + flopr #(1) squashRXerrIPreg(PCLK, ~PRESETn, squashRXerrIP, prevSquashRXerrIP); // Side effect of reading IIR is lowering THRE_IP if most significant intr assign setSquashTHRE_IP = ~MEMRb & (A==3'b010) & (intrID==3'h1); // there's a 1-cycle delay on set squash so that THRE_IP doesn't change during the process of reading IIR (otherwise combinational loop) assign resetSquashTHRE_IP = ~THRE; assign squashTHRE_IP = prevSquashTHRE_IP & ~resetSquashTHRE_IP; - flopr #(1) squashTHRE_IPreg(HCLK, ~HRESETn, squashTHRE_IP | setSquashTHRE_IP, prevSquashTHRE_IP); + flopr #(1) squashTHRE_IPreg(PCLK, ~PRESETn, squashTHRE_IP | setSquashTHRE_IP, prevSquashTHRE_IP); /////////////////////////////////////////// // modem control logic diff --git a/pipelined/src/uncore/uart.sv b/pipelined/src/uncore/uart_apb.sv similarity index 71% rename from pipelined/src/uncore/uart.sv rename to pipelined/src/uncore/uart_apb.sv index dc620d734..6108b5807 100644 --- a/pipelined/src/uncore/uart.sv +++ b/pipelined/src/uncore/uart_apb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// uart.sv +// uart_apb.sv // // Written: David_Harris@hmc.edu 21 January 2021 // Modified: @@ -32,23 +32,41 @@ `include "wally-config.vh" -module uart ( +module uart_apb ( + input logic PCLK, PRESETn, + input logic PSEL, + input logic [2:0] PADDR, + input logic [`XLEN-1:0] PWDATA, + input logic [`XLEN/8-1:0] PSTRB, + input logic PWRITE, + input logic PENABLE, + output logic [`XLEN-1:0] PRDATA, + output logic PREADY, +/* input logic HCLK, HRESETn, input logic HSELUART, input logic [2:0] HADDR, input logic HWRITE, - input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN-1:0] PWDATA, output logic [`XLEN-1:0] HREADUART, - output logic HRESPUART, HREADYUART, + output logic HRESPUART, HREADYUART, */ (* mark_debug = "true" *) input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface (* mark_debug = "true" *) output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface (* mark_debug = "true" *) output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU // UART interface signals - logic [2:0] A; + logic [2:0] entry; logic MEMRb, MEMWb, memread, memwrite; logic [7:0] Din, Dout; + assign memwrite = PWRITE & PENABLE & PSEL; // only write in access phase + assign memread = ~PWRITE & PENABLE & PSEL; + assign PREADY = 1'b1; // CLINT never takes >1 cycle to respond + assign entry = PADDR[2:0]; + assign MEMRb = ~memread; + assign MEMWb = ~memwrite; + +/* // rename processor interface signals to match PC16550D and provide one-byte interface flopr #(1) memreadreg(HCLK, ~HRESETn, (HSELUART & ~HWRITE), memread); flopr #(1) memwritereg(HCLK, ~HRESETn, (HSELUART & HWRITE), memwrite); @@ -58,29 +76,29 @@ module uart ( assign HRESPUART = 0; // OK assign HREADYUART = 1; // should idle high during address phase and respond high when done; will need to be modified if UART ever needs more than 1 cycle to do something - +*/ if (`XLEN == 64) begin:uart always_comb begin - HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; - case (A) - 3'b000: Din = HWDATA[7:0]; - 3'b001: Din = HWDATA[15:8]; - 3'b010: Din = HWDATA[23:16]; - 3'b011: Din = HWDATA[31:24]; - 3'b100: Din = HWDATA[39:32]; - 3'b101: Din = HWDATA[47:40]; - 3'b110: Din = HWDATA[55:48]; - 3'b111: Din = HWDATA[63:56]; + PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; + case (entry) + 3'b000: Din = PWDATA[7:0]; + 3'b001: Din = PWDATA[15:8]; + 3'b010: Din = PWDATA[23:16]; + 3'b011: Din = PWDATA[31:24]; + 3'b100: Din = PWDATA[39:32]; + 3'b101: Din = PWDATA[47:40]; + 3'b110: Din = PWDATA[55:48]; + 3'b111: Din = PWDATA[63:56]; endcase end end else begin:uart // 32-bit always_comb begin - HREADUART = {Dout, Dout, Dout, Dout}; - case (A[1:0]) - 2'b00: Din = HWDATA[7:0]; - 2'b01: Din = HWDATA[15:8]; - 2'b10: Din = HWDATA[23:16]; - 2'b11: Din = HWDATA[31:24]; + PRDATA = {Dout, Dout, Dout, Dout}; + case (entry[1:0]) + 2'b00: Din = PWDATA[7:0]; + 2'b01: Din = PWDATA[15:8]; + 2'b10: Din = PWDATA[23:16]; + 2'b11: Din = PWDATA[31:24]; endcase end end @@ -89,8 +107,8 @@ module uart ( // *** make sure reads don't occur on UART unless fully selected because they could change state. This applies to all peripherals uartPC16550D u( // Processor Interface - .HCLK, .HRESETn, - .A, .Din, + .PCLK, .PRESETn, + .A(entry), .Din, .Dout, .MEMRb, .MEMWb, .INTR, .TXRDYb, .RXRDYb, diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 7649745bc..888489b9f 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -39,6 +39,7 @@ module uncore ( input logic TIMECLK, input logic [31:0] HADDR, input logic [`AHBW-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, input logic HWRITE, input logic [2:0] HSIZE, input logic [2:0] HBURST, @@ -52,10 +53,9 @@ module uncore ( output logic HSELEXT, // delayed signals input logic [2:0] HADDRD, - input logic [3:0] HSIZED, input logic HWRITED, // peripheral pins - output logic TimerIntM, SwIntM, MExtIntM, SExtIntM, + output logic MTimerInt, MSwInt, MExtInt, SExtInt, input logic [31:0] GPIOPinsIn, output logic [31:0] GPIOPinsOut, GPIOPinsEn, input logic UARTSin, @@ -68,19 +68,28 @@ module uncore ( output logic [63:0] MTIME_CLINT ); - logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC; + logic [`XLEN-1:0] HREADRam, HREADSDC; logic [8:0] HSELRegions; logic HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; - logic HRESPRam, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART, HRESPSDC; - logic HREADYRam, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART, HRESPSDCD; + logic HRESPRam, HRESPSDC; + logic HREADYRam, HRESPSDCD; logic [`XLEN-1:0] HREADBootRom; logic HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC; logic HSELNoneD; logic UARTIntr,GPIOIntr; logic SDCIntM; + logic PCLK, PRESETn, PWRITE, PENABLE; + logic [3:0] PSEL, PREADY; + logic [31:0] PADDR; + logic [`XLEN-1:0] PWDATA; + logic [`XLEN/8-1:0] PSTRB; + logic [3:0][`XLEN-1:0] PRDATA; + logic [`XLEN-1:0] HREADBRIDGE; + logic HRESPBRIDGE, HREADYBRIDGE, HSELBRIDGE, HSELBRIDGED; + // Determine which region of physical memory (if any) is being accessed // Use a trimmed down portion of the PMA checker - only the address decoders // Set access types to all 1 as don't cares because the MMU has already done access checking @@ -89,130 +98,111 @@ module uncore ( // unswizzle HSEL signals assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; -// generate - // on-chip RAM - if (`RAM_SUPPORTED) begin : ram - ram #( - .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( - .HCLK, .HRESETn, - .HSELRam, .HADDR, - .HWRITE, .HREADY, .HSIZED, - .HTRANS, .HWDATA, .HREADRam, - .HRESPRam, .HREADYRam); - end + // AHB -> APB bridge + ahbapbbridge #(4) ahbapbbridge + (.HCLK, .HRESETn, .HSEL({HSELUART, HSELPLIC, HSELCLINT, HSELGPIO}), .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HTRANS, .HREADY, + .HRDATA(HREADBRIDGE), .HRESP(HRESPBRIDGE), .HREADYOUT(HREADYBRIDGE), + .PCLK, .PRESETn, .PSEL, .PWRITE, .PENABLE, .PADDR, .PWDATA, .PSTRB, .PREADY, .PRDATA); + assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected + + // on-chip RAM + if (`RAM_SUPPORTED) begin : ram + ram #( + .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( + .HCLK, .HRESETn, + .HSELRam, .HADDR, + .HWRITE, .HREADY, + .HTRANS, .HWDATA, .HWSTRB, .HREADRam, + .HRESPRam, .HREADYRam); + end - if (`BOOTROM_SUPPORTED) begin : bootrom - ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) - bootrom( - .HCLK, .HRESETn, - .HSELRam(HSELBootRom), .HADDR, - .HWRITE, .HREADY, .HTRANS, .HSIZED, - .HWDATA, - .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); - end + // *** switch to new RAM + if (`BOOTROM_SUPPORTED) begin : bootrom + ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) + bootrom( + .HCLK, .HRESETn, + .HSELRam(HSELBootRom), .HADDR, + .HWRITE, .HREADY, .HTRANS, + .HWDATA, .HWSTRB, + .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom)); + end - // memory-mapped I/O peripherals - if (`CLINT_SUPPORTED == 1) begin : clint - clint clint( - .HCLK, .HRESETn, .TIMECLK, - .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE, - .HWDATA, .HREADY, .HTRANS, .HSIZED, - .HREADCLINT, - .HRESPCLINT, .HREADYCLINT, - .MTIME(MTIME_CLINT), - .TimerIntM, .SwIntM); + // memory-mapped I/O peripherals + if (`CLINT_SUPPORTED == 1) begin : clint + clint_apb clint( + .PCLK, .PRESETn, .PSEL(PSEL[1]), .PADDR(PADDR[15:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PRDATA(PRDATA[1]), .PREADY(PREADY[1]), + .MTIME(MTIME_CLINT), + .MTimerInt, .MSwInt); - end else begin : clint - assign MTIME_CLINT = 0; - assign TimerIntM = 0; assign SwIntM = 0; - end - if (`PLIC_SUPPORTED == 1) begin : plic - plic plic( - .HCLK, .HRESETn, - .HSELPLIC, .HADDR(HADDR[27:0]), - .HWRITE, .HREADY, .HTRANS, .HWDATA, - .UARTIntr, .GPIOIntr, - .HREADPLIC, .HRESPPLIC, .HREADYPLIC, - .MExtIntM, .SExtIntM); - end else begin : plic - assign MExtIntM = 0; - assign SExtIntM = 0; - end - if (`GPIO_SUPPORTED == 1) begin : gpio - gpio gpio( - .HCLK, .HRESETn, .HSELGPIO, - .HADDR(HADDR[7:0]), - .HWDATA, - .HWRITE, .HREADY, - .HTRANS, - .HREADGPIO, - .HRESPGPIO, .HREADYGPIO, - .GPIOPinsIn, - .GPIOPinsOut, .GPIOPinsEn, - .GPIOIntr); + end else begin : clint + assign MTIME_CLINT = 0; + assign MTimerInt = 0; assign MSwInt = 0; + end + if (`PLIC_SUPPORTED == 1) begin : plic + plic_apb plic( + .PCLK, .PRESETn, .PSEL(PSEL[2]), .PADDR(PADDR[27:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PRDATA(PRDATA[2]), .PREADY(PREADY[2]), + .UARTIntr, .GPIOIntr, + .MExtInt, .SExtInt); + end else begin : plic + assign MExtInt = 0; + assign SExtInt = 0; + end + if (`GPIO_SUPPORTED == 1) begin : gpio + gpio_apb gpio( + .PCLK, .PRESETn, .PSEL(PSEL[0]), .PADDR(PADDR[7:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PRDATA(PRDATA[0]), .PREADY(PREADY[0]), + .iof0(), .iof1(), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOIntr); + end else begin : gpio + assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; + end + if (`UART_SUPPORTED == 1) begin : uart + uart_apb uart( + .PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE, + .PRDATA(PRDATA[3]), .PREADY(PREADY[3]), + .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface + .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface + .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU + end else begin : uart + assign UARTSout = 0; assign UARTIntr = 0; + end + if (`SDC_SUPPORTED == 1) begin : sdc + SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, + .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, + // sdc interface + .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, + // interrupt to PLIC + .SDCIntM + ); + end else begin : sdc + assign SDCCLK = 0; + assign SDCCmdOut = 0; + assign SDCCmdOE = 0; + end - end else begin : gpio - assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0; - end - if (`UART_SUPPORTED == 1) begin : uart - uart uart( - .HCLK, .HRESETn, - .HSELUART, - .HADDR(HADDR[2:0]), - .HWRITE, .HWDATA, - .HREADUART, .HRESPUART, .HREADYUART, - .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface - .SOUT(UARTSout), .RTSb(), .DTRb(), // to E1A driver to RS232 interface - .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb()); // to CPU - end else begin : uart - assign UARTSout = 0; assign UARTIntr = 0; - end - if (`SDC_SUPPORTED == 1) begin : sdc - SDC SDC(.HCLK, .HRESETn, .HSELSDC, .HADDR(HADDR[4:0]), .HWRITE, .HREADY, .HTRANS, - .HWDATA, .HREADSDC, .HRESPSDC, .HREADYSDC, - // sdc interface - .SDCCmdOut, .SDCCmdIn, .SDCCmdOE, .SDCDatIn, .SDCCLK, - // interrupt to PLIC - .SDCIntM - ); - end else begin : sdc - assign SDCCLK = 0; - assign SDCCmdOut = 0; - assign SDCCmdOE = 0; - end -// endgenerate - - // mux could also include external memory // AHB Read Multiplexer assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) | - ({`XLEN{HSELEXTD}} & HRDATAEXT) | - ({`XLEN{HSELCLINTD}} & HREADCLINT) | - ({`XLEN{HSELPLICD}} & HREADPLIC) | - ({`XLEN{HSELGPIOD}} & HREADGPIO) | + ({`XLEN{HSELEXTD}} & HRDATAEXT) | + ({`XLEN{HSELBRIDGED}} & HREADBRIDGE) | ({`XLEN{HSELBootRomD}} & HREADBootRom) | - ({`XLEN{HSELUARTD}} & HREADUART) | ({`XLEN{HSELSDCD}} & HREADSDC); assign HRESP = HSELRamD & HRESPRam | - HSELEXTD & HRESPEXT | - HSELCLINTD & HRESPCLINT | - HSELPLICD & HRESPPLIC | - HSELGPIOD & HRESPGPIO | + HSELEXTD & HRESPEXT | + HSELBRIDGE & HRESPBRIDGE | HSELBootRomD & HRESPBootRom | - HSELUARTD & HRESPUART | HSELSDC & HRESPSDC; assign HREADY = HSELRamD & HREADYRam | - HSELEXTD & HREADYEXT | - HSELCLINTD & HREADYCLINT | - HSELPLICD & HREADYPLIC | - HSELGPIOD & HREADYGPIO | + HSELEXTD & HREADYEXT | + HSELBRIDGED & HREADYBRIDGE | HSELBootRomD & HREADYBootRom | - HSELUARTD & HREADYUART | HSELSDCD & HREADYSDC | HSELNoneD; // don't lock up the bus if no region is being accessed // Address Decoder Delay (figure 4-2 in spec) flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); + flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED); endmodule diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 163c18138..200789c41 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -34,7 +34,7 @@ module wallypipelinedcore ( input logic clk, reset, // Privileged - input logic TimerIntM, MExtIntM, SExtIntM, SwIntM, + input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, // Bus Interface input logic [`AHBW-1:0] HRDATA, @@ -42,6 +42,7 @@ module wallypipelinedcore ( output logic HCLK, HRESETn, output logic [31:0] HADDR, output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -63,13 +64,11 @@ module wallypipelinedcore ( // new signals that must connect through DP logic MDUE, W64E; logic CSRReadM, CSRWriteM, PrivilegedM; - logic [1:0] AtomicE; logic [1:0] AtomicM; logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; (* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; - // logic [31:0] InstrF; - logic [31:0] InstrD, InstrW; + logic [31:0] InstrD; (* mark_debug = "true" *) logic [31:0] InstrM; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; @@ -84,9 +83,8 @@ module wallypipelinedcore ( logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM; logic InvalidateICacheM, FlushDCacheM; logic PCSrcE; - logic CSRWritePendingDEM; + logic CSRWriteFencePendingDEM; logic DivBusyE; - logic DivE; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; // floating point unit signals @@ -95,16 +93,20 @@ module wallypipelinedcore ( logic FStallD; logic FWriteIntE; logic [`XLEN-1:0] FWriteDataE; + logic FStore2; + logic [`FLEN-1:0] FWriteDataM; logic [`XLEN-1:0] FIntResM; + logic [`XLEN-1:0] FCvtIntResW; logic FDivBusyE; logic IllegalFPUInstrD, IllegalFPUInstrE; logic FRegWriteM; logic FPUStallD; + logic FpLoadStoreM; + logic [1:0] FResSelW; logic [4:0] SetFflagsM; // memory management unit signals logic ITLBWriteF; - logic ITLBFlushF, DTLBFlushM; logic ITLBMissF; logic [`XLEN-1:0] SATP_REGW; logic STATUS_MXR, STATUS_SUM, STATUS_MPRV; @@ -112,9 +114,10 @@ module wallypipelinedcore ( logic [1:0] PrivilegeModeW; logic [`XLEN-1:0] PTE; logic [1:0] PageType; - logic wfiM, IntPendingM; + logic sfencevmaM, wfiM, IntPendingM; logic SelHPTW; + // PMA checker signals var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; @@ -130,21 +133,23 @@ module wallypipelinedcore ( logic [`XLEN-1:0] IEUAdrE; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataE; (* mark_debug = "true" *) logic [`XLEN-1:0] IEUAdrM; - (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; - logic [`XLEN-1:0] ReadDataW; + logic [`LLEN-1:0] ReadDataW; logic CommittedM; // AHB ifu interface logic [`PA_BITS-1:0] IFUBusAdr; logic [`XLEN-1:0] IFUBusHRDATA; logic IFUBusRead; - logic IFUBusAck; + logic IFUBusAck, IFUBusInit; + logic [2:0] IFUBurstType; + logic [1:0] IFUTransType; + logic IFUTransComplete; // AHB LSU interface logic [`PA_BITS-1:0] LSUBusAdr; logic LSUBusRead; logic LSUBusWrite; - logic LSUBusAck; + logic LSUBusAck, LSUBusInit; logic [`XLEN-1:0] LSUBusHRDATA; logic [`XLEN-1:0] LSUBusHWDATA; @@ -156,8 +161,10 @@ module wallypipelinedcore ( logic [4:0] InstrClassM; logic InstrAccessFaultF; logic [2:0] LSUBusSize; + logic [2:0] LSUBurstType; + logic [1:0] LSUTransType; + logic LSUTransComplete; - logic ExceptionM; logic DCacheMiss; logic DCacheAccess; logic ICacheMiss; @@ -168,13 +175,11 @@ module wallypipelinedcore ( ifu ifu( .clk, .reset, - .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, - - .ExceptionM, + .StallF, .StallD, .StallE, .StallM, + .FlushF, .FlushD, .FlushE, .FlushM, // Fetch - .IFUBusHRDATA, .IFUBusAck, .PCF, .IFUBusAdr, - .IFUBusRead, .IFUStallF, + .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr, + .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete, .ICacheAccess, .ICacheMiss, // Execute @@ -196,7 +201,7 @@ module wallypipelinedcore ( // mmu management .PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, - .STATUS_MPP, .ITLBWriteF, .ITLBFlushF, + .STATUS_MPP, .ITLBWriteF, .sfencevmaM, .ITLBMissF, // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H @@ -221,7 +226,6 @@ module wallypipelinedcore ( // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU - .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU .WriteDataE, // Write data to LSU .Funct3M, // size and signedness to LSU @@ -229,9 +233,11 @@ module wallypipelinedcore ( .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage - .CSRReadValW, .ReadDataM, .MDUResultW, - .RdW, .ReadDataW, + .CSRReadValW, .MDUResultW, + .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, + .FCvtIntResW, + .FResSelW, // hazards .StallD, .StallE, .StallM, .StallW, @@ -239,7 +245,7 @@ module wallypipelinedcore ( .FPUStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE, .CSRReadM, .CSRWriteM, .PrivilegedM, - .CSRWritePendingDEM, .StoreStallD + .CSRWriteFencePendingDEM, .StoreStallD ); // integer execution unit: integer register file, datapath and controller @@ -251,12 +257,14 @@ module wallypipelinedcore ( .AtomicM, .TrapM, .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, + .FpLoadStoreM, + .FWriteDataM, .FStore2, //.DataMisalignedM(DataMisalignedM), .IEUAdrE, .IEUAdrM, .WriteDataE, - .ReadDataM, .FlushDCacheM, + .ReadDataW, .FlushDCacheM, // connected to ahb (all stay the same) - .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, - .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, + .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, + .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, // connect to csr or privilege and stay the same. .PrivilegeModeW, .BigEndianM, // connects to csr @@ -269,7 +277,7 @@ module wallypipelinedcore ( .STATUS_MPRV, // from csr .STATUS_MPP, // from csr - .DTLBFlushM, // connects to privilege + .sfencevmaM, // connects to privilege .LoadPageFaultM, // connects to privilege .StoreAmoPageFaultM, // connects to privilege .LoadMisalignedFaultM, // connects to privilege @@ -287,28 +295,37 @@ module wallypipelinedcore ( ahblite ebu(// IFU connections .clk, .reset, .UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00), - .IFUBusAdr, - .IFUBusRead, .IFUBusHRDATA, .IFUBusAck, + .IFUBusAdr, .IFUBusRead, + .IFUBusHRDATA, + .IFUBurstType, + .IFUTransType, + .IFUTransComplete, + .IFUBusAck, + .IFUBusInit, // Signals from Data Cache .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusHRDATA, .LSUBusSize, + .LSUBurstType, + .LSUTransType, + .LSUTransComplete, .LSUBusAck, + .LSUBusInit, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, - .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED); hazard hzu( - .BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM, + .BPPredWrongE, .CSRWriteFencePendingDEM, .RetM, .TrapM, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LSUStallM, .IFUStallF, .FPUStallD, .FStallD, .DivBusyE, .FDivBusyE, .EcallFaultM, .BreakpointFaultM, - .InvalidateICacheM, .wfiM, .IntPendingM, + .wfiM, .IntPendingM, // Stall & flush outputs .StallF, .StallD, .StallE, .StallM, .StallW, .FlushF, .FlushD, .FlushE, .FlushM, .FlushW @@ -322,8 +339,8 @@ module wallypipelinedcore ( .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .InstrM, .CSRReadValW, .PrivilegedNextPCM, .RetM, .TrapM, - .ITLBFlushF, .DTLBFlushM, - .InstrValidM, .CommittedM, .DivE, + .sfencevmaM, + .InstrValidM, .CommittedM, .FRegWriteM, .LoadStallD, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, @@ -331,7 +348,7 @@ module wallypipelinedcore ( .InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD, .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM, - .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .IEUAdrM, .SetFflagsM, @@ -339,7 +356,7 @@ module wallypipelinedcore ( // *** do these need to be split up into one for dmem and one for ifu? // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem? .InstrAccessFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, - .ExceptionM, .IllegalFPUInstrE, + .IllegalFPUInstrE, .PrivilegeModeW, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, @@ -351,8 +368,7 @@ module wallypipelinedcore ( assign RetM = 0; assign TrapM = 0; assign wfiM = 0; - assign ITLBFlushF = 0; - assign DTLBFlushM = 0; + assign sfencevmaM = 0; assign BigEndianM = 0; end if (`M_SUPPORTED) begin:mdu @@ -360,7 +376,7 @@ module wallypipelinedcore ( .clk, .reset, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, - .MDUResultW, .DivBusyE, .DivE, + .MDUResultW, .DivBusyE, .StallM, .StallW, .FlushM, .FlushW, .TrapM ); end else begin // no M instructions supported @@ -373,17 +389,22 @@ module wallypipelinedcore ( .clk, .reset, .FRM_REGW, // Rounding mode from CSR .InstrD, // instruction from IFU - .ReadDataW,// Read data from memory + .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory .ForwardedSrcAE, // Integer input being processed (from IEU) .StallE, .StallM, .StallW, // stall signals from HZU .FlushE, .FlushM, .FlushW, // flush signals from HZU .RdM, .RdW, // which FP register to write to (from IEU) .STATUS_FS, // is floating-point enabled? .FRegWriteM, // FP register write enable + .FpLoadStoreM, + .FStore2, .FStallD, // Stall the decode stage .FWriteIntE, // integer register write enable .FWriteDataE, // Data to be written to memory + .FWriteDataM, // Data to be written to memory .FIntResM, // data to be written to integer register + .FCvtIntResW, // fp -> int conversion result to be stored in int register + .FResSelW, // fpu result selection .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction .SetFflagsM // FPU flags (to privileged unit) diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/pipelined/src/wally/wallypipelinedsoc.sv index f199fe3e3..ff1d95005 100644 --- a/pipelined/src/wally/wallypipelinedsoc.sv +++ b/pipelined/src/wally/wallypipelinedsoc.sv @@ -48,6 +48,7 @@ module wallypipelinedsoc ( output logic HCLK, HRESETn, output logic [31:0] HADDR, output logic [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, output logic HWRITE, output logic [2:0] HSIZE, output logic [2:0] HBURST, @@ -72,29 +73,30 @@ module wallypipelinedsoc ( // logic reset; logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore logic HRESP; - logic TimerIntM, SwIntM; // from CLINT + logic MTimerInt, MSwInt; // from CLINT logic [63:0] MTIME_CLINT; // from CLINT to CSRs - logic MExtIntM,SExtIntM; // from PLIC + logic MExtInt,SExtInt; // from PLIC logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; + // synchronize reset to SOC clock domain synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); // instantiate processor and memories wallypipelinedcore core(.clk, .reset, - .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM, + .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, - .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, + .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HADDRD, .HSIZED, .HWRITED ); uncore uncore(.HCLK, .HRESETn, .TIMECLK, - .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, - .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HSIZED, .HWRITED, - .TimerIntM, .SwIntM, .MExtIntM, .SExtIntM, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, + .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT, + .HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HADDRD, .HWRITED, + .MTimerInt, .MSwInt, .MExtInt, .SExtInt, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .MTIME_CLINT, .HSELEXT, .SDCCmdOut, .SDCCmdOE, .SDCCmdIn, .SDCDatIn, .SDCCLK diff --git a/pipelined/src/wally/wallypipelinedsocwrapper.v b/pipelined/src/wally/wallypipelinedsocwrapper.v index d9c513404..2a25f476f 100644 --- a/pipelined/src/wally/wallypipelinedsocwrapper.v +++ b/pipelined/src/wally/wallypipelinedsocwrapper.v @@ -42,6 +42,7 @@ module wallypipelinedsocwrapper ( output HCLK, HRESETn, output [31:0] HADDR, output [`AHBW-1:0] HWDATA, + output logic [`XLEN/8-1:0] HWSTRB, output HWRITE, output [2:0] HSIZE, output [2:0] HBURST, diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index db5a11f86..ee249139d 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -1,7 +1,37 @@ -all: sqrttestgen testgen +all: exptestgen testgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2 sqrttestgen modtestgen sqrttestgen: sqrttestgen.c - gcc sqrttestgen.c -lm -o sqrttestgen + gcc sqrttestgen.c -o sqrttestgen -lm + ./sqrttestgen + +testgen: testgen.c + gcc testgen.c -o testgen -lm + ./testgen + +exptestgen: exptestgen.c + gcc -o exptestgen exptestgen.c -lm + ./exptestgen + +qslc_r4a2: qslc_r4a2.c + gcc qslc_r4a2.c -o qslc_r4a2 -lm + ./qslc_r4a2 > qslc_r4a2.sv + +qslc_r4a2b: qslc_r4a2b.c + gcc qslc_r4a2b.c -o qslc_r4a2b -lm + ./qslc_r4a2b > qslc_r4a2b.tv + +qslc_sqrt_r4a2: qslc_sqrt_r4a2.c + gcc qslc_sqrt_r4a2.c -o qslc_sqrt_r4a2 -lm + ./qslc_sqrt_r4a2 > qslc_sqrt_r4a2.sv + +inttestgen: inttestgen.c + gcc -lm -o inttestgen inttestgen.c + ./inttestgen + +modtestgen: modtestgen.c + gcc -lm -o modtestgen modtestgen.c + ./modtestgen + +clean: + rm -f testgen exptestgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2 sqrttestgen modtestgen -testgen: exptestgen.c - gcc exptestgen.c -lm -o exptestgen diff --git a/pipelined/srt/exptestgen b/pipelined/srt/exptestgen deleted file mode 100755 index 0b5085bcb..000000000 Binary files a/pipelined/srt/exptestgen and /dev/null differ diff --git a/pipelined/srt/exptestgen.c b/pipelined/srt/exptestgen.c index 2d5cfb861..61fe74aa4 100644 --- a/pipelined/srt/exptestgen.c +++ b/pipelined/srt/exptestgen.c @@ -21,7 +21,7 @@ /* Prototypes */ -void output(FILE *fptr, int e1, double a, int e2, double b, int r_exp, double r_mantissa); +void output(FILE *fptr, int aSign, int aExp, double aFrac, int bSign, int bExp, double bFrac, int rSign, int rExp, double rFrac); void printhex(FILE *fptr, double x); double random_input(void); double random_input_e(void); @@ -31,12 +31,13 @@ double random_input_e(void); void main(void) { FILE *fptr; - // e1 & e2 are exponents - // a & b are mantissas - // r_mantissa is result of mantissa divsion - // r_exp is result of exponent division - double a, b, r_mantissa, r_exp; - int e1, e2; + // aExp & bExp are exponents + // aFrac & bFrac are mantissas + // rFrac is result of fractional divsion + // rExp is result of exponent division + double aFrac, bFrac, rFrac; + int aExp, bExp, rExp; + int aSign, bSign, rSign; double mantissa[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -45,31 +46,34 @@ void main(void) int i, j; int bias = 1023; - if ((fptr = fopen("testvectors","w")) == NULL) { + if ((fptr = fopen("testvectors","w")) == NULL) { fprintf(stderr, "Couldn't write testvectors file\n"); exit(1); } for (i=0; i +#include +#include + +/* Constants */ + +#define ENTRIES 10 +#define RANDOM_VECS 500 + +/* Prototypes */ + +void output(FILE *fptr, long a, long b, long r); +void printhex(FILE *fptr, long x); +double random_input(void); + +/* Main */ + +void main(void) +{ + FILE *fptr; + long a, b, r; + long list[ENTRIES] = {1, 3, 5, 18, 25, 33, 42, 65, 103, 255}; + int i, j; + + if ((fptr = fopen("inttestvectors","w")) == NULL) { + fprintf(stderr, "Couldn't write testvectors file\n"); + exit(1); + } + + for (i=0; i +#include +#include + +/* Constants */ + +#define ENTRIES 10 +#define RANDOM_VECS 500 + +/* Prototypes */ + +void output(FILE *fptr, long a, long b, long rem); +void printhex(FILE *fptr, long x); +double random_input(void); + +/* Main */ + +void main(void) +{ + FILE *fptr; + long a, b, rem; + long list[ENTRIES] = {1, 3, 5, 18, 25, 33, 42, 65, 103, 255}; + int i, j; + + if ((fptr = fopen("modtestvectors","w")) == NULL) { + fprintf(stderr, "Couldn't write testvectors file\n"); + exit(1); + } + + for (i=0; i= PreprocB); + assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]); + + // Number of cycles of divider + assign dur = Int ? (intExp & {7{~intExp[6]}}) : (7)'(`DIVLEN); endmodule -/* - -////////// -// mux2 // -////////// -module mux2(input logic [55:0] in0, in1, - input logic sel, - output logic [55:0] out); - - assign #1 out = sel ? in1 : in0; -endmodule - -////////// -// flop // -////////// -module flop(clk, in, out); - input clk; - input [55:0] in; - output [55:0] out; - - logic [55:0] state; - - always @(posedge clk) - state <= #1 in; - - assign #1 out = state; -endmodule - -*/ - -////////// -// qsel // -////////// -module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits - input logic [Nf+3:Nf] ps, pc, - output logic qp, qz, qm +///////////////////////////////// +// Quotient Selection, Radix 2 // +///////////////////////////////// +module qsel2 ( + input logic [`DIVLEN+3:`DIVLEN] ps, pc, + input logic Sqrt, + output logic qp, qz, qn ); - logic [Nf+3:Nf] p, g; + logic [`DIVLEN+3:`DIVLEN] p, g; logic magnitude, sign, cout; // The quotient selection logic is presented for simplicity, not @@ -161,9 +190,9 @@ module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits assign p = ps ^ pc; assign g = ps & pc; - assign #1 magnitude = ~(&p[54:52]); - assign #1 cout = g[54] | (p[54] & (g[53] | p[53] & g[52])); - assign #1 sign = p[55] ^ cout; + assign #1 magnitude = ~(&p[`DIVLEN+2:`DIVLEN]); + assign #1 cout = g[`DIVLEN+2] | (p[`DIVLEN+2] & (g[`DIVLEN+1] | p[`DIVLEN+1] & (g[`DIVLEN]))); + assign #1 sign = p[`DIVLEN+3] ^ cout; /* assign #1 magnitude = ~((ps[54]^pc[54]) & (ps[53]^pc[53]) & (ps[52]^pc[52])); assign #1 sign = (ps[55]^pc[55])^ @@ -174,56 +203,154 @@ module qsel #(parameter Nf=52) ( // *** eventually just change to 4 bits // Produce quotient = +1, 0, or -1 assign #1 qp = magnitude & ~sign; assign #1 qz = ~magnitude; - assign #1 qm = magnitude & sign; + assign #1 qn = magnitude & sign; endmodule -////////// -// qacc // -////////// -module qacc #(parameter N=55) ( - input logic clk, - input logic req, - input logic qp, qz, qm, - output logic [N-1:0] rp, rm +//////////////////////////////////// +// Adder Input Selection, Radix 2 // +//////////////////////////////////// +module fsel2 ( + input logic sp, sn, + input logic [`DIVLEN+3:0] C, S, SM, + output logic [`DIVLEN+3:0] F ); + logic [`DIVLEN+3:0] FP, FN, FZ; + + // Generate for both positive and negative bits + assign FP = ~(S << 1) & C; + assign FN = (SM << 1) | (C & (~C << 2)); + assign FZ = '0; + + // Choose which adder input will be used + + always_comb + if (sp) F = FP; + else if (sn) F = FN; + else F = FZ; + + // assign F = sp ? FP : (sn ? FN : FZ); - flopr #(N) rmreg(clk, req, {rm[53:0], qm}, rm); - flopr #(N) rpreg(clk, req, {rp[53:0], qp}, rp); -/* always @(posedge clk) - begin - if (req) - begin - rp <= #1 0; - rm <= #1 0; - end - else - begin - rm <= #1 {rm[54:0], qm}; - rp <= #1 {rp[54:0], qp}; - end - end */ endmodule -///////// -// inv // -///////// -module inv(input logic [55:0] in, - output logic [55:0] out); +/////////////////////////////////// +// On-The-Fly Converter, Radix 2 // +/////////////////////////////////// +module otfc2 #(parameter N=66) ( + input logic clk, + input logic Start, + input logic qp, qz, qn, + output logic [N-3:0] Result +); + // The on-the-fly converter transfers the quotient + // bits to the quotient as they come. + // Use this otfc for division only. + logic [N+2:0] Q, QM, QNext, QMNext, QMMux; + logic [N+1:0] QR, QMR; - assign #1 out = ~in; + flopr #(N+3) Qreg(clk, Start, QNext, Q); + mux2 #(`DIVLEN+3) Qmux(QMNext, {(`DIVLEN+3){1'b1}}, Start, QMMux); + flop #(`DIVLEN+3) QMreg(clk, QMMux, QM); + + always_comb begin + QR = Q[N+1:0]; + QMR = QM[N+1:0]; // Shift Q and QM + if (qp) begin + QNext = {QR, 1'b1}; + QMNext = {QR, 1'b0}; + end else if (qz) begin + QNext = {QR, 1'b0}; + QMNext = {QMR, 1'b1}; + end else begin // If qp and qz are not true, then qn is + QNext = {QMR, 1'b1}; + QMNext = {QMR, 1'b0}; + end + end + assign Result = Q[N] ? Q[N-1:2] : Q[N-2:1]; + +endmodule + +/////////////////////////////// +// Square Root OTFC, Radix 2 // +/////////////////////////////// +module sotfc2( + input logic clk, + input logic Start, + input logic sp, sn, + input logic Sqrt, + input logic [`DIVLEN+3:0] C, + output logic [`DIVLEN+3:0] S, SM +); + // The on-the-fly converter transfers the square root + // bits to the quotient as they come. + // Use this otfc for division and square root. + logic [`DIVLEN+3:0] SNext, SMNext, SMux; + + flopr #(`DIVLEN+4) SMreg(clk, Start, SMNext, SM); + mux2 #(`DIVLEN+4) Smux(SNext, {3'b000, Sqrt, {(`DIVLEN){1'b0}}}, Start, SMux); + flop #(`DIVLEN+4) Sreg(clk, SMux, S); + + always_comb begin + if (sp) begin + SNext = S | (C & ~(C << 1)); + SMNext = S; + end else if (sn) begin + SNext = SM | (C & ~(C << 1)); + SMNext = SM; + end else begin // If sp and sn are not true, then sz is + SNext = S; + SMNext = SM | (C & ~(C << 1)); + end + end +endmodule + +////////////////////////// +// C Register for SOTFC // +////////////////////////// +module creg(input logic clk, + input logic Start, + input logic Sqrt, + output logic [`DIVLEN+3:0] C +); + logic [`DIVLEN+3:0] CMux; + + mux2 #(`DIVLEN+4) Cmux({1'b1, C[`DIVLEN+3:1]}, {4'b1111, Sqrt, {(`DIVLEN-1){1'b0}}}, Start, CMux); + flop #(`DIVLEN+4) cflop(clk, CMux, C); +endmodule + +///////////// +// counter // +///////////// +module srtcounter(input logic clk, + input logic req, + input logic [$clog2(`XLEN+1)-1:0] dur, + output logic done +); + + logic [$clog2(`XLEN+1)-1:0] count; + + // This block of control logic sequences the divider + // through its iterations. You may modify it if you + // build a divider which completes in fewer iterations. + // You are not responsible for the (trivial) circuit + // design of the block. + + always @(posedge clk) + begin + if (count == dur) done <= #1 1; + else if (done | req) done <= #1 0; + if (req) count <= #1 0; + else count <= #1 count+1; + end endmodule ////////// // mux3 // ////////// -module mux3onehot(in0, in1, in2, sel0, sel1, sel2, out); - input [55:0] in0; - input [55:0] in1; - input [55:0] in2; - input sel0; - input sel1; - input sel2; - output [55:0] out; +module mux3onehot #(parameter N=65) ( + input logic [N+3:0] in0, in1, in2, + input logic sel0, sel1, sel2, + output logic [N+3:0] out +); // lazy inspection of the selects // really we should make sure selects are mutually exclusive @@ -234,7 +361,7 @@ endmodule ///////// // csa // ///////// -module csa #(parameter N=56) ( +module csa #(parameter N=69) ( input logic [N-1:0] in1, in2, in3, input logic cin, output logic [N-1:0] out1, out2 @@ -249,41 +376,99 @@ module csa #(parameter N=56) ( // insert cin. assign #1 out1 = in1 ^ in2 ^ in3; - assign #1 out2 = {in1[54:0] & (in2[54:0] | in3[54:0]) | - (in2[54:0] & in3[54:0]), cin}; + assign #1 out2 = {in1[N-2:0] & (in2[N-2:0] | in3[N-2:0]) | + (in2[N-2:0] & in3[N-2:0]), cin}; endmodule -////////////// -// exponent // -////////////// -module exp(input [10:0] e1, e2, - output [10:0] e); // for double precision, exponent is 11 bits - assign e = (e1 - e2) + 11'd1023; // bias is hardcoded -endmodule ////////////// -// finaladd // +// expcalc // ////////////// -module finaladd( - input logic [54:0] rp, rm, - output logic [51:0] r +module expcalc( + input logic [`NE-1:0] XExp, YExp, + input logic Sqrt, + output logic [`NE-1:0] calcExp ); + logic [`NE+1:0] SExp, DExp, SXExp; + assign SXExp = {2'b00, XExp} - (`NE+2)'(`BIAS); + assign SExp = (SXExp >> 1) + (`NE+2)'(`BIAS); + assign DExp = {2'b00, XExp} - {2'b00, YExp} + (`NE+2)'(`BIAS); + assign calcExp = Sqrt ? SExp[`NE-1:0] : DExp[`NE-1:0]; - logic [54:0] diff; - - // this magic block performs the final addition for you - // to convert the positive and negative quotient digits - // into a normalized mantissa. It returns the 52 bit - // mantissa after shifting to guarantee a leading 1. - // You can assume this block operates in one cycle - // and do not need to budget it in your area and power - // calculations. - - // Since no rounding is performed, the result may be too - // small by one unit in the least significant place (ulp). - // The checker ignores such an error. - - assign #1 diff = rp - rm; - assign #1 r = diff[54] ? diff[53:2] : diff[52:1]; +endmodule + +module srtpostproc( + input logic [`DIVLEN+3:0] WS, WC, X, D, S, SM, + input logic [$clog2(`XLEN+1)-1:0] dur, zeroCntD, + input logic XSign, YSign, Signed, Int, Mod, + output logic [`DIVLEN-1:0] Result, + output logic calcSign +); + logic [`DIVLEN+3:0] W, shiftRem, intRem, intS; + logic [`DIVLEN-1:0] floatRes, intRes; + logic WSign; + + assign W = WS + WC; + assign WSign = W[`DIVLEN+3]; + // Remainder handling + always_comb begin + if (zeroCntD == ($clog2(`XLEN+1))'(`XLEN)) begin + intRem = X; + intS = -1; + end + else if (~Signed) begin + if (WSign) begin + intRem = W + D; + intS = SM; + end else begin + intRem = W; + intS = S; + end + end + else case ({YSign, XSign, WSign}) + 3'b000: begin + intRem = W; + intS = S; + end + 3'b001: begin + intRem = W + D; + intS = SM; + end + 3'b010: begin + intRem = W - D; + intS = ~S; + end + 3'b011: begin + intRem = W; + intS = ~SM; + end + 3'b100: begin + intRem = W; + intS = ~SM; + end + 3'b101: begin + intRem = W + D; + intS = ~SM + 1; + end + 3'b110: begin + intRem = W - D; + intS = S + 1; + end + 3'b111: begin + intRem = W; + intS = S; + end + endcase + end + assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0]; + assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0]; + assign shiftRem = (intRem >> (zeroCntD)); + always_comb begin + if (Int) begin + if (Mod) Result = shiftRem[`DIVLEN-1:0]; + else Result = intRes >> (`DIVLEN - dur); + end else Result = floatRes; + end + assign calcSign = XSign ^ YSign; endmodule diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index 23ab683d5..ce0417f56 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,9 +11,7 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - -`include "wally-config.vh" - + ///////// // srt // ///////// @@ -328,9 +326,7 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - //if (abs(correctr - r) > 1) // check if accurate to 1 ulp - // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." - if (correctr - r > 1) // check if accurate to 1 ulp + if ((correctr - r) > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/stine/Makefile b/pipelined/srt/stine/Makefile new file mode 100644 index 000000000..8f745b47a --- /dev/null +++ b/pipelined/srt/stine/Makefile @@ -0,0 +1,27 @@ + +CC = gcc +CFLAGS = -lm +LIBS = +OBJS4 = disp.o srt4div.o +OBJS2 = disp.o srt2div.o + +all: srt4div srt2div + +disp.o: disp.h disp.c + $(CC) -g -c -o disp.o disp.c + +srt4div.o: srt4div.c + $(CC) -g -c -o srt4div.o srt4div.c + +srt2div.o: srt2div.c + $(CC) -g -c -o srt2div.o srt2div.c + +srt4div: $(OBJS4) + $(CC) -g -O3 -o srt4div $(OBJS4) $(CFLAGS) + +srt2div: $(OBJS2) + $(CC) -g -O3 -o srt2div $(OBJS2) $(CFLAGS) + +clean: + rm -f *.o *~ + rm -f core diff --git a/pipelined/srt/stine/README b/pipelined/srt/stine/README new file mode 100755 index 000000000..6898c5cec --- /dev/null +++ b/pipelined/srt/stine/README @@ -0,0 +1 @@ +vsim -do iter64.do -c diff --git a/pipelined/srt/stine/README.md b/pipelined/srt/stine/README.md new file mode 100755 index 000000000..ebb006c95 --- /dev/null +++ b/pipelined/srt/stine/README.md @@ -0,0 +1,22 @@ +This is a novel integer divider using r4 division by recurrence. The +reference is: + +J. E. Stine and K. Hill, "An Efficient Implementation of Radix-4 +Integer Division Using Scaling," 2020 IEEE 63rd International Midwest +Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, +2020, pp. 1092-1095, doi: 10.1109/MWSCAS48704.2020.9184631. + +Although this version does not contain scaling, it could do this, if +needed. Moreover, a higher radix or overlapped radix can be done +easily to expand the the size. Also, the implementations here are +initially unsigned but hope to expand for signed, which should be +easy. + +There are two types of tests in this directory within each testbench. +One tests for 32-bits and the other 64-bits: + +int32div.do and int64div.do = test individual vector for debugging + +iter32.do and iter64.do = do not use any waveform generation and just +output lots of tests + diff --git a/pipelined/srt/stine/checkme.sh b/pipelined/srt/stine/checkme.sh new file mode 100755 index 000000000..acbd94008 --- /dev/null +++ b/pipelined/srt/stine/checkme.sh @@ -0,0 +1,19 @@ +#!/bin/sh +cat iter64_signed.out | grep "0 1$" +cat iter64_signed.out | grep "1 0$" +cat iter64_signed.out | grep "0 0$" +cat iter64_unsigned.out | grep "0 1$" +cat iter64_unsigned.out | grep "1 0$" +cat iter64_unsigned.out | grep "0 0$" +cat iter32_signed.out | grep "0 1$" +cat iter32_signed.out | grep "1 0$" +cat iter32_signed.out | grep "0 0$" +cat iter32_unsigned.out | grep "0 1$" +cat iter32_unsigned.out | grep "1 0$" +cat iter32_unsigned.out | grep "0 0$" +cat iter128_signed.out | grep "0 1$" +cat iter128_signed.out | grep "1 0$" +cat iter128_signed.out | grep "0 0$" +cat iter128_unsigned.out | grep "0 1$" +cat iter128_unsigned.out | grep "1 0$" +cat iter128_unsigned.out | grep "0 0$" diff --git a/pipelined/srt/stine/disp.c b/pipelined/srt/stine/disp.c new file mode 100755 index 000000000..66652cf01 --- /dev/null +++ b/pipelined/srt/stine/disp.c @@ -0,0 +1,60 @@ +#include "disp.h" + +double rnd_zero(double x, double bits) { + if (x < 0) + return ceiling(x, bits); + else + return flr(x, bits); +} + +double rne(double x, double precision) { + double scale, x_round; + scale = pow(2.0, precision); + x_round = rint(x * scale) / scale; + return x_round; +} + +double flr(double x, double precision) { + double scale, x_round; + scale = pow(2.0, precision); + x_round = floor(x * scale) / scale; + return x_round; +} + +double ceiling(double x, double precision) { + double scale, x_round; + scale = pow(2.0, precision); + x_round = ceil(x * scale) / scale; + return x_round; +} + +void disp_bin(double x, int bits_to_left, int bits_to_right, FILE *out_file) { + + double diff; + int i; + if (fabs(x) < pow(2.0, -bits_to_right)) { + for (i = -bits_to_left + 1; i <= bits_to_right; i++) { + fprintf(out_file,"0"); + } + return; + } + if (x < 0.0) { + // fprintf(out_file, "-"); + // x = - x; + x = pow(2.0, ((double) bits_to_left)) + x; + } + for (i = -bits_to_left + 1; i <= bits_to_right; i++) { + diff = pow(2.0, -i); + if (x < diff) { + fprintf(out_file, "0"); + } + else { + fprintf(out_file, "1"); + x -= diff; + } + if (i == 0) { + fprintf(out_file, "."); + } + } +} + diff --git a/pipelined/srt/stine/disp.h b/pipelined/srt/stine/disp.h new file mode 100755 index 000000000..bf2c78872 --- /dev/null +++ b/pipelined/srt/stine/disp.h @@ -0,0 +1,18 @@ +#include +#include +#include + +#ifndef DISP +#define DISP + +double rnd_zero(double x, double bits); + +double rne(double x, double precision); + +double flr(double x, double precision); + +double ceiling(double x, double precision); + +void disp_bin(double x, int bits_to_left, int bits_to_right, FILE *out_file); + +#endif diff --git a/pipelined/srt/stine/idiv-config.vh b/pipelined/srt/stine/idiv-config.vh new file mode 100644 index 000000000..8afa1e75b --- /dev/null +++ b/pipelined/srt/stine/idiv-config.vh @@ -0,0 +1,27 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: james.stine@okstate.edu 9 June 2022 +// Modified: +// +// Purpose: Specify which features are configured +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Integer division tests +`define IDIV_TESTS 1048576 diff --git a/pipelined/srt/stine/intdiv.sv b/pipelined/srt/stine/intdiv.sv new file mode 100755 index 000000000..03c7b8977 --- /dev/null +++ b/pipelined/srt/stine/intdiv.sv @@ -0,0 +1,2802 @@ +/////////////////////////////////////////// +// intdiv.sv +// +// Written: James.Stine@okstate.edu 1 February 2021 +// Modified: +// +// Purpose: Integer Divide instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// *** I added these verilator controls to clean up the +// lint output. The linter warnings should be fixed, but now the output is at +// least readable. +/* verilator lint_off COMBDLY */ +/* verilator lint_off IMPLICIT */ + +`include "idiv-config.vh" + +module intdiv #(parameter WIDTH=64) + (Qf, done, remf, div0, N, D, clk, reset, start, S); + + input logic [WIDTH-1:0] N, D; + input logic clk; + input logic reset; + input logic start; + input logic S; + + output logic [WIDTH-1:0] Qf; + output logic [WIDTH-1:0] remf; + output logic div0; + output logic done; + + logic enable; + logic state0; + logic V; + logic [$clog2(WIDTH):0] Num; + logic [$clog2(WIDTH)-1:0] P, NumIter, RemShift, RemShiftP; + logic [WIDTH-1:0] op1, op2, op1shift, Rem5; + logic [WIDTH:0] Qd, Rd, Qd2, Rd2; + logic [WIDTH:0] Q2d, Qd3; + logic [WIDTH-1:0] Q, Q2, rem0; + logic [3:0] quotient; + logic otfzero; + logic shiftResult; + + logic [WIDTH-1:0] twoD; + logic [WIDTH-1:0] twoN; + logic SignD; + logic SignN; + logic [WIDTH-1:0] QT, remT; + logic D_NegOne; + logic Max_N; + logic [1:0] QR; + logic tcQ, tcR; + + // Check if negative (two's complement) + // If so, convert to positive + adder #(WIDTH) cpa1 ((D ^ {WIDTH{D[WIDTH-1]&S}}), {{WIDTH-1{1'b0}}, D[WIDTH-1]&S}, twoD); + adder #(WIDTH) cpa2 ((N ^ {WIDTH{N[WIDTH-1]&S}}), {{WIDTH-1{1'b0}}, N[WIDTH-1]&S}, twoN); + assign SignD = D[WIDTH-1]; + assign SignN = N[WIDTH-1]; + // Max N and D = -1 (Overflow) + assign Max_N = (~|N[WIDTH-2:0]) & N[WIDTH-1]; + assign D_NegOne = &D; + + // Divider goes the distance to 37 cycles + // (thanks to the evil divisor for D = 0x1) + // The enable signal turns off register storage thus invalidating + // any future cycles. + + // Shift D, if needed (for integer) + // needed to allow qst to be in range for integer + // division [1,2) and allow integer divide to work. + // + // The V or valid bit can be used to determine if D + // is 0 and thus a divide by 0 exception. This div0 + // exception is given to FSM to tell the operation to + // quit gracefully. + + lod_hier #(WIDTH) p1 (.ZP(P), .ZV(V), .B(twoD)); + shift_left #(WIDTH) p2 (twoD, P, op2); + assign op1 = twoN; + assign div0 = ~V; + + // #iter: N = m+v+s = m+2+s (mod k = 0) + // v = 2 since \rho < 1 (add 4 to make sure its a ceil) + // k = 2 (r = 2^k) + adder #($clog2(WIDTH)+1) cpa3 ({1'b0, P}, + {{$clog2(WIDTH)+1-3{1'b0}}, shiftResult, ~shiftResult, 1'b0}, + Num); + + // Determine whether need to add just Q/Rem + assign shiftResult = P[0]; + // div by 2 (ceil) + assign NumIter = Num[$clog2(WIDTH):1]; + assign RemShift = P; + + // Avoid critical path of RemShift + flopr #($clog2(WIDTH)) reg1 (clk, reset, RemShift, RemShiftP); + + // FSM to control integer divider + // assume inputs are postive edge and + // datapath (divider) is negative edge + fsm64 #($clog2(WIDTH)) fsm1 (enablev, state0v, donev, otfzerov, + start, div0, NumIter, ~clk, reset); + + flopr #(1) rega (~clk, reset, donev, done); + flopr #(1) regc (~clk, reset, otfzerov, otfzero); + flopr #(1) regd (~clk, reset, enablev, enable); + flopr #(1) rege (~clk, reset, state0v, state0); + + // To obtain a correct remainder the last bit of the + // quotient has to be aligned with a radix-r boundary. + // Since the quotient is in the range 1/2 < q < 2 (one + // integer bit and m fractional bits), this is achieved by + // shifting N right by v+s so that (m+v+s) mod k = 0. And, + // the quotient has to be aligned to the integer position. + divide4 #(WIDTH) p3 (Qd, Q2d, Rd, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + // Storage registers to hold contents stable + flopenr #(WIDTH+1) reg3 (clk, reset, enable, Rd, Rd2); + flopenr #(WIDTH+1) reg4 (clk, reset, enable, Qd, Qd2); + flopenr #(WIDTH+1) reg5 (clk, reset, enable, Q2d, Qd3); + + // Probably not needed - just assigns results + assign Q = Qd2[WIDTH-1:0]; + assign Rem5 = Rd2[WIDTH:1]; + assign Q2 = Qd3[WIDTH-1:0]; + + // Adjust remainder by m (no need to adjust by + shift_right #(WIDTH) p4 (Rem5, RemShiftP, rem0); + + // Adjust Q/Rem for Signed + always_comb + casex({S, SignN, SignD}) + 3'b000 : QR = 2'b00; + 3'b001 : QR = 2'b00; + 3'b010 : QR = 2'b00; + 3'b011 : QR = 2'b00; + 3'b100 : QR = 2'b00; + 3'b101 : QR = 2'b10; + 3'b110 : QR = 2'b11; + 3'b111 : QR = 2'b01; + default: QR = 2'b00; + endcase // casex ({SignN, SignD, S}) + assign {tcQ, tcR} = QR; + + // When Dividend (N) and/or Divisor (D) are negative (first bit is '1'): + // - When N and D are negative: Remainder i + // s negative (undergoes a two's complement). + // - When N is negative: Quotient and Remainder are both negative (undergo a two's complement). + // - When D is negative: Quotient is negative (undergoes a two's complement). + adder #(WIDTH) cpa4 ((rem0 ^ {WIDTH{tcR}}), {{WIDTH-1{1'b0}}, tcR}, remT); + adder #(WIDTH) cpa5 ((Q ^ {WIDTH{tcQ}}), {{WIDTH-1{1'b0}}, tcQ}, QT); + + // RISC-V has exceptions for divide by 0 and overflow (see Table 6.1 of spec) + exception_int #(WIDTH) exc (QT, remT, N, S, div0, Max_N, D_NegOne, Qf, remf); + +endmodule // intdiv + +// Division by Recurrence (r=4) +module divide4 #(parameter WIDTH=64) + (Q, Q2, rem0, quotient, op1, op2, clk, reset, state0, + enable, otfzero, shiftResult); + + input logic [WIDTH-1:0] op1, op2; + input logic clk, state0; + input logic reset; + input logic enable; + input logic otfzero; + input logic shiftResult; + + output logic [WIDTH:0] rem0; + output logic [WIDTH:0] Q; + output logic [WIDTH:0] Q2; + output logic [3:0] quotient; + + logic [WIDTH+3:0] Sum, Carry; + logic [WIDTH:0] Qstar; + logic [WIDTH:0] QMstar; + logic [WIDTH:0] QM2star; + logic [7:0] qtotal; + logic [WIDTH+3:0] SumN, CarryN, SumN2, CarryN2; + logic [WIDTH+3:0] divi1, divi2, divi1c, divi2c, dive1; + logic [WIDTH+3:0] mdivi_temp, mdivi; + logic zero; + logic [1:0] qsel; + logic [1:0] Qin, QMin; + logic CshiftQ, CshiftQM; + logic [WIDTH+3:0] rem1, rem2, rem3; + logic [WIDTH+3:0] SumR, CarryR; + logic [WIDTH:0] Qt; + + // Create one's complement values of Divisor (for q*D) + assign divi1 = {3'h0, op2, 1'b0}; + assign divi2 = {2'h0, op2, 2'b0}; + assign divi1c = ~divi1; + assign divi2c = ~divi2; + // Shift x1 if not mod k + mux2 #(WIDTH+4) mx1 ({3'b000, op1, 1'b0}, {4'h0, op1}, shiftResult, dive1); + + // I I I . F F F F F ... (Robertson Criteria - \rho * qmax * D) + mux2 #(WIDTH+4) mx2 ({CarryN2[WIDTH+1:0], 2'h0}, {WIDTH+4{1'b0}}, state0, CarryN); + mux2 #(WIDTH+4) mx3 ({SumN2[WIDTH+1:0], 2'h0}, dive1, state0, SumN); + // Simplify QST + adder #(8) cpa1 (SumN[WIDTH+3:WIDTH-4], CarryN[WIDTH+3:WIDTH-4], qtotal); + // q = {+2, +1, -1, -2} else q = 0 + qst4 pd1 (qtotal[7:1], divi1[WIDTH-1:WIDTH-3], quotient); + assign ulp = quotient[2]|quotient[3]; + assign zero = ~(quotient[3]|quotient[2]|quotient[1]|quotient[0]); + // Map to binary encoding + assign qsel[1] = quotient[3]|quotient[2]; + assign qsel[0] = quotient[3]|quotient[1]; + mux4 #(WIDTH+4) mx4 (divi2, divi1, divi1c, divi2c, qsel, mdivi_temp); + mux2 #(WIDTH+4) mx5 (mdivi_temp, {WIDTH+4{1'b0}}, zero, mdivi); + csa #(WIDTH+4) csa1 (mdivi, SumN, {CarryN[WIDTH+3:1], ulp}, Sum, Carry); + // regs : save CSA + flopenr #(WIDTH+4) reg1 (clk, reset, enable, Sum, SumN2); + flopenr #(WIDTH+4) reg2 (clk, reset, enable, Carry, CarryN2); + // OTF + ls_control otf1 (quotient, Qin, QMin, CshiftQ, CshiftQM); + otf #(WIDTH+1) otf2 (Qin, QMin, CshiftQ, CshiftQM, + clk, otfzero, enable, Qstar, QMstar); + + // Correction and generation of Remainder + adder #(WIDTH+4) cpa2 (SumN2[WIDTH+3:0], CarryN2[WIDTH+3:0], rem1); + // Add back +D as correction + csa #(WIDTH+4) csa2 (CarryN2[WIDTH+3:0], SumN2[WIDTH+3:0], divi1, SumR, CarryR); + adder #(WIDTH+4) cpa3 (SumR, CarryR, rem2); + // Choose remainder (Rem or Rem+D) + mux2 #(WIDTH+4) mx6 (rem1, rem2, rem1[WIDTH+3], rem3); + // Choose correct Q or QM + mux2 #(WIDTH+1) mx7 (Qstar, QMstar, rem1[WIDTH+3], Qt); + // Final results + assign rem0 = rem3[WIDTH:0]; + assign Q = Qt; + +endmodule // divide4 + +module ls_control (quot, Qin, QMin, CshiftQ, CshiftQM); + + input logic [3:0] quot; + + output logic [1:0] Qin; + output logic [1:0] QMin; + output logic CshiftQ; + output logic CshiftQM; + + logic [5:0] qout; + + // q = {+2, +1, -1, -2} + always_comb + casex(quot) + 4'b0000 : qout = 6'b00_11_0_0; + 4'b0001 : qout = 6'b10_01_1_0; + 4'b0010 : qout = 6'b11_10_1_0; + 4'b0100 : qout = 6'b01_00_0_1; + 4'b1000 : qout = 6'b10_01_0_1; + default : qout = 6'bxx_xx_x_x; + endcase // case (quot) + + assign {Qin, QMin, CshiftQ, CshiftQM} = qout; + +endmodule // ls_control + +// On-the-fly Conversion per Ercegovac/Lang +module otf #(parameter WIDTH=8) + (Qin, QMin, CshiftQ, CshiftQM, clk, reset, enable, R2Q, R1Q); + + input logic [1:0] Qin, QMin; + input logic CshiftQ, CshiftQM; + input logic clk; + input logic reset; + input logic enable; + + output logic [WIDTH-1:0] R2Q; + output logic [WIDTH-1:0] R1Q; + + logic [WIDTH-1:0] Qstar, QMstar; + logic [WIDTH-1:0] M1Q, M2Q; + + // QM + mux2 #(WIDTH) m1 (QMstar, Qstar, CshiftQM, M1Q); + flopenr #(WIDTH) r1 (clk, reset, enable, {M1Q[WIDTH-3:0], QMin}, R1Q); + // Q + mux2 #(WIDTH) m2 (Qstar, QMstar, CshiftQ, M2Q); + flopenr #(WIDTH) r2 (clk, reset, enable, {M2Q[WIDTH-3:0], Qin}, R2Q); + + assign Qstar = R2Q; + assign QMstar = R1Q; + +endmodule // otf + +module adder #(parameter WIDTH=8) + (input logic [WIDTH-1:0] a, b, + output logic [WIDTH-1:0] y); + + assign y = a + b; + +endmodule // adder + +module fa (input logic a, b, c, output logic sum, carry); + + assign sum = a^b^c; + assign carry = a&b|a&c|b&c; + +endmodule // fa + +module csa #(parameter WIDTH=8) + (input logic [WIDTH-1:0] a, b, c, + output logic [WIDTH-1:0] sum, carry); + + logic [WIDTH:0] carry_temp; + genvar i; + generate + for (i=0;i B. LT and GT are both '0' if A = B. + +module magcompare2b (LT, GT, A, B); + + input logic [1:0] A; + input logic [1:0] B; + + output logic LT; + output logic GT; + + // Determine if A < B using a minimized sum-of-products expression + assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0]; + // Determine if A > B using a minimized sum-of-products expression + assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0]; + +endmodule // magcompare2b + +// J. E. Stine and M. J. Schulte, "A combined two's complement and +// floating-point comparator," 2005 IEEE International Symposium on +// Circuits and Systems, Kobe, 2005, pp. 89-92 Vol. 1. +// doi: 10.1109/ISCAS.2005.1464531 + +module magcompare8 (LT, EQ, A, B); + + input logic [7:0] A; + input logic [7:0] B; + + logic [3:0] s; + logic [3:0] t; + logic [1:0] u; + logic [1:0] v; + logic GT; + //wire LT; + + output logic EQ; + output logic LT; + + magcompare2b mag1 (s[0], t[0], A[1:0], B[1:0]); + magcompare2b mag2 (s[1], t[1], A[3:2], B[3:2]); + magcompare2b mag3 (s[2], t[2], A[5:4], B[5:4]); + magcompare2b mag4 (s[3], t[3], A[7:6], B[7:6]); + + magcompare2b mag5 (u[0], v[0], t[1:0], s[1:0]); + magcompare2b mag6 (u[1], v[1], t[3:2], s[3:2]); + + magcompare2b mag7 (LT, GT, v[1:0], u[1:0]); + + assign EQ = ~(GT | LT); + +endmodule // magcompare8 + +module exception_int #(parameter WIDTH=8) + (Q, rem, op1, S, div0, Max_N, D_NegOne, Qf, remf); + + input logic [WIDTH-1:0] Q; + input logic [WIDTH-1:0] rem; + input logic [WIDTH-1:0] op1; + input logic S; + input logic div0; + input logic Max_N; + input logic D_NegOne; + + output logic [WIDTH-1:0] Qf; + output logic [WIDTH-1:0] remf; + + always_comb + case ({div0, S, Max_N, D_NegOne}) + 4'b0000 : Qf = Q; + 4'b0001 : Qf = Q; + 4'b0010 : Qf = Q; + 4'b0011 : Qf = Q; + 4'b0100 : Qf = Q; + 4'b0101 : Qf = Q; + 4'b0110 : Qf = Q; + 4'b0111 : Qf = {1'b1, {WIDTH-1{1'h0}}}; + 4'b1000 : Qf = {WIDTH{1'b1}}; + 4'b1001 : Qf = {WIDTH{1'b1}}; + 4'b1010 : Qf = {WIDTH{1'b1}}; + 4'b1011 : Qf = {WIDTH{1'b1}}; + 4'b1100 : Qf = {WIDTH{1'b1}}; + 4'b1101 : Qf = {WIDTH{1'b1}}; + 4'b1110 : Qf = {WIDTH{1'b1}}; + 4'b1111 : Qf = {WIDTH{1'b1}}; + default: Qf = Q; + endcase + + always_comb + case ({div0, S, Max_N, D_NegOne}) + 4'b0000 : remf = rem; + 4'b0001 : remf = rem; + 4'b0010 : remf = rem; + 4'b0011 : remf = rem; + 4'b0100 : remf = rem; + 4'b0101 : remf = rem; + 4'b0110 : remf = rem; + 4'b0111 : remf = {WIDTH{1'h0}}; + 4'b1000 : remf = op1; + 4'b1001 : remf = op1; + 4'b1010 : remf = op1; + 4'b1011 : remf = op1; + 4'b1100 : remf = op1; + 4'b1101 : remf = op1; + 4'b1110 : remf = op1; + 4'b1111 : remf = op1; + default: remf = rem; + endcase + +endmodule // exception_int + +/* verilator lint_on COMBDLY */ +/* verilator lint_on IMPLICIT */ diff --git a/pipelined/srt/stine/iter128.do b/pipelined/srt/stine/iter128.do new file mode 100644 index 000000000..de3369ff4 --- /dev/null +++ b/pipelined/srt/stine/iter128.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/iter128S.do b/pipelined/srt/stine/iter128S.do new file mode 100644 index 000000000..7ddc416d7 --- /dev/null +++ b/pipelined/srt/stine/iter128S.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter128S.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/iter32.do b/pipelined/srt/stine/iter32.do new file mode 100755 index 000000000..02bd32512 --- /dev/null +++ b/pipelined/srt/stine/iter32.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/iter32S.do b/pipelined/srt/stine/iter32S.do new file mode 100644 index 000000000..52475b291 --- /dev/null +++ b/pipelined/srt/stine/iter32S.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter32S.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/iter64.do b/pipelined/srt/stine/iter64.do new file mode 100755 index 000000000..651c88cfd --- /dev/null +++ b/pipelined/srt/stine/iter64.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/iter64S.do b/pipelined/srt/stine/iter64S.do new file mode 100644 index 000000000..18c37a27f --- /dev/null +++ b/pipelined/srt/stine/iter64S.do @@ -0,0 +1,50 @@ +# Copyright 1991-2007 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv lod.sv shift.sv intdiv.sv test_iter64S.sv + +# start and run simulation +vsim -voptargs=+acc work.tb + + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 999586700ns +quit diff --git a/pipelined/srt/stine/lod.sv b/pipelined/srt/stine/lod.sv new file mode 100755 index 000000000..a7496757c --- /dev/null +++ b/pipelined/srt/stine/lod.sv @@ -0,0 +1,182 @@ +/////////////////////////////////////////// +// lod.sv +// +// Written: James.Stine@okstate.edu 1 February 2021 +// Modified: +// +// Purpose: Integer Divide instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module lod2 (P, V, B); + + input logic [1:0] B; + + output logic P; + output logic V; + + assign V = B[0] | B[1]; + assign P = B[0] & ~B[1]; + +endmodule // lo2 + +module lod_hier #(parameter WIDTH=8) + (input logic [WIDTH-1:0] B, + output logic [$clog2(WIDTH)-1:0] ZP, + output logic ZV); + + if (WIDTH == 128) + lod128 lod128 (ZP, ZV, B); + else if (WIDTH == 64) + lod64 lod64 (ZP, ZV, B); + else if (WIDTH == 32) + lod32 lod32 (ZP, ZV, B); + else if (WIDTH == 16) + lod16 lod16 (ZP, ZV, B); + else if (WIDTH == 8) + lod8 lod8 (ZP, ZV, B); + else if (WIDTH == 4) + lod4 lod4 (ZP, ZV, B); + +endmodule // lod_hier + +module lod4 (ZP, ZV, B); + + input logic [3:0] B; + + logic ZPa; + logic ZPb; + logic ZVa; + logic ZVb; + + output logic [1:0] ZP; + output logic ZV; + + lod2 l1(ZPa, ZVa, B[1:0]); + lod2 l2(ZPb, ZVb, B[3:2]); + + assign ZP[0:0] = ZVb ? ZPb : ZPa; + assign ZP[1] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod4 + +module lod8 (ZP, ZV, B); + + input logic [7:0] B; + + logic [1:0] ZPa; + logic [1:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [2:0] ZP; + output logic ZV; + + lod4 l1(ZPa, ZVa, B[3:0]); + lod4 l2(ZPb, ZVb, B[7:4]); + + assign ZP[1:0] = ZVb ? ZPb : ZPa; + assign ZP[2] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod8 + +module lod16 (ZP, ZV, B); + + input logic [15:0] B; + + logic [2:0] ZPa; + logic [2:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [3:0] ZP; + output logic ZV; + + lod8 l1(ZPa, ZVa, B[7:0]); + lod8 l2(ZPb, ZVb, B[15:8]); + + assign ZP[2:0] = ZVb ? ZPb : ZPa; + assign ZP[3] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod16 + +module lod32 (ZP, ZV, B); + + input logic [31:0] B; + + logic [3:0] ZPa; + logic [3:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [4:0] ZP; + output logic ZV; + + lod16 l1(ZPa, ZVa, B[15:0]); + lod16 l2(ZPb, ZVb, B[31:16]); + + assign ZP[3:0] = ZVb ? ZPb : ZPa; + assign ZP[4] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod32 + +module lod64 (ZP, ZV, B); + + input logic [63:0] B; + + logic [4:0] ZPa; + logic [4:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [5:0] ZP; + output logic ZV; + + lod32 l1(ZPa, ZVa, B[31:0]); + lod32 l2(ZPb, ZVb, B[63:32]); + + assign ZP[4:0] = ZVb ? ZPb : ZPa; + assign ZP[5] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod64 + +module lod128 (ZP, ZV, B); + + input logic [127:0] B; + + logic [5:0] ZPa; + logic [5:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [6:0] ZP; + output logic ZV; + + lod64 l1(ZPa, ZVa, B[63:0]); + lod64 l2(ZPb, ZVb, B[127:64]); + + assign ZP[5:0] = ZVb ? ZPb : ZPa; + assign ZP[6] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lod128 diff --git a/pipelined/srt/stine/lzd.do b/pipelined/srt/stine/lzd.do new file mode 100755 index 000000000..9ba020b3a --- /dev/null +++ b/pipelined/srt/stine/lzd.do @@ -0,0 +1,55 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog lod.sv lzd_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 350 +configure wave -valuecolwidth 200 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 800ns +quit diff --git a/pipelined/srt/stine/lzd.sv b/pipelined/srt/stine/lzd.sv new file mode 100755 index 000000000..277b45931 --- /dev/null +++ b/pipelined/srt/stine/lzd.sv @@ -0,0 +1,182 @@ +/////////////////////////////////////////// +// lzd.sv +// +// Written: James.Stine@okstate.edu 1 February 2021 +// Modified: +// +// Purpose: Integer Divide instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module lzd2 (P, V, B); + + input logic [1:0] B; + + output logic P; + output logic V; + + assign V = ~(B[0] & B[1]); + assign P = B[1]; + +endmodule // lzd2 + +module lzd_hier #(parameter WIDTH=8) + (input logic [WIDTH-1:0] B, + output logic [$clog2(WIDTH)-1:0] ZP, + output logic ZV); + + if (WIDTH == 128) + lzd128 lzd127 (ZP, ZV, B); + else if (WIDTH == 64) + lzd64 lzd64 (ZP, ZV, B); + else if (WIDTH == 32) + lzd32 lzd32 (ZP, ZV, B); + else if (WIDTH == 16) + lzd16 lzd16 (ZP, ZV, B); + else if (WIDTH == 8) + lzd8 lzd8 (ZP, ZV, B); + else if (WIDTH == 4) + lzd4 lzd4 (ZP, ZV, B); + +endmodule // lzd_hier + +module lzd4 (ZP, ZV, B); + + input logic [3:0] B; + + logic ZPa; + logic ZPb; + logic ZVa; + logic ZVb; + + output logic [1:0] ZP; + output logic ZV; + + lzd2 l1 (ZPa, ZVa, B[1:0]); + lzd2 l2 (ZPb, ZVb, B[3:2]); + + assign ZP[0:0] = ZVb ? ZPb : ZPa; + assign ZP[1] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd4 + +module lzd8 (ZP, ZV, B); + + input logic [7:0] B; + + logic [1:0] ZPa; + logic [1:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [2:0] ZP; + output logic ZV; + + lzd4 l1 (ZPa, ZVa, B[3:0]); + lzd4 l2 (ZPb, ZVb, B[7:4]); + + assign ZP[1:0] = ZVb ? ZPb : ZPa; + assign ZP[2] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd8 + +module lzd16 (ZP, ZV, B); + + input logic [15:0] B; + + logic [2:0] ZPa; + logic [2:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [3:0] ZP; + output logic ZV; + + lzd8 l1 (ZPa, ZVa, B[7:0]); + lzd8 l2 (ZPb, ZVb, B[15:8]); + + assign ZP[2:0] = ZVb ? ZPb : ZPa; + assign ZP[3] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd16 + +module lzd32 (ZP, ZV, B); + + input logic [31:0] B; + + logic [3:0] ZPa; + logic [3:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [4:0] ZP; + output logic ZV; + + lzd16 l1 (ZPa, ZVa, B[15:0]); + lzd16 l2 (ZPb, ZVb, B[31:16]); + + assign ZP[3:0] = ZVb ? ZPb : ZPa; + assign ZP[4] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd32 + +module lzd64 (ZP, ZV, B); + + input logic [63:0] B; + + logic [4:0] ZPa; + logic [4:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [5:0] ZP; + output logic ZV; + + lzd32 l1 (ZPa, ZVa, B[31:0]); + lzd32 l2 (ZPb, ZVb, B[63:32]); + + assign ZP[4:0] = ZVb ? ZPb : ZPa; + assign ZP[5] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd64 + +module lzd128 (ZP, ZV, B); + + input logic [127:0] B; + + logic [5:0] ZPa; + logic [5:0] ZPb; + logic ZVa; + logic ZVb; + + output logic [6:0] ZP; + output logic ZV; + + lzd64 l1 (ZPa, ZVa, B[64:0]); + lzd64 l2 (ZPb, ZVb, B[127:63]); + + assign ZP[5:0] = ZVb ? ZPb : ZPa; + assign ZP[6] = ~ZVb; + assign ZV = ZVa | ZVb; + +endmodule // lzd128 diff --git a/pipelined/srt/stine/lzd_tb.sv b/pipelined/srt/stine/lzd_tb.sv new file mode 100755 index 000000000..2980d5f4d --- /dev/null +++ b/pipelined/srt/stine/lzd_tb.sv @@ -0,0 +1,59 @@ +// +// File name : tb +// Title : test +// project : HW3 +// Library : test +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +// Top level stimulus module + +`timescale 1ns/1ps +module stimulus; + + logic [7:0] B; + logic [2:0] ZP; + logic ZV; + + logic clk; + + integer handle3; + integer desc3; + integer i; + + // instatiate part to test + lzd_hier #(8) dut (B, ZP, ZV); + + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + handle3 = $fopen("lzd.out"); + desc3 = handle3; + end + + initial + begin + for (i=0; i < 256; i=i+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + B = $random; + end + @(negedge clk) + begin + $fdisplay(desc3, "%b || %b %b", B, ZP, ZV); + end + end // for (i=0; i < 256; i=i+1) + $finish;// + end // initial begin + +endmodule // stimulus diff --git a/pipelined/srt/stine/mux.sv b/pipelined/srt/stine/mux.sv new file mode 100755 index 000000000..d13045e6d --- /dev/null +++ b/pipelined/srt/stine/mux.sv @@ -0,0 +1,51 @@ +module mux2 #(parameter WIDTH = 8) + (input logic [WIDTH-1:0] d0, d1, + input logic s, + output logic [WIDTH-1:0] y); + + assign y = s ? d1 : d0; + +endmodule // mux2 + +module mux3 #(parameter WIDTH = 8) + (input logic [WIDTH-1:0] d0, d1, d2, + input logic [1:0] s, + output logic [WIDTH-1:0] y); + + assign y = s[1] ? d2 : (s[0] ? d1 : d0); + +endmodule // mux3 + +module mux4 #(parameter WIDTH = 8) + (input logic [WIDTH-1:0] d0, d1, d2, d3, + input logic [1:0] s, + output logic [WIDTH-1:0] y); + + assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); + +endmodule // mux4 + +module mux21x32 (Z, A, B, Sel); + + input logic [31:0] A; + input logic [31:0] B; + input logic Sel; + + output logic [31:0] Z; + + assign Z = Sel ? B : A; + +endmodule // mux21x32 + +module mux21x64 (Z, A, B, Sel); + + input logic [63:0] A; + input logic [63:0] B; + input logic Sel; + + output logic [63:0] Z; + + assign Z = Sel ? B : A; + +endmodule // mux21x64 + diff --git a/pipelined/srt/stine/notes b/pipelined/srt/stine/notes new file mode 100644 index 000000000..77311b177 --- /dev/null +++ b/pipelined/srt/stine/notes @@ -0,0 +1,30 @@ +Dividend x --(0.10101111), divisord --(0.11000101)(i -- 16(0.1100)2- 12) + +X = 175 (xAF) +D = 197 (xC5) + +X = 175/256 = 0.68359375 +D = 197/256 = 0.76953125 + +Note: Add lg(r) extra iterations due to shifting of computed q + q_{computed} = q / radix + +./srt4div 0.68359375 0.76953125 8 10 + +r=2 +X = 0.10011111 +D = 0.11000101 + +X = 159 (9F) +D = 197 (C5) + +X = 159/256 = 0.62109375 +D = 197/256 = 0.76953125 + +./srt2div 0.62109375 0.76953125 8 9 + + + + + + diff --git a/pipelined/srt/stine/otf4.in b/pipelined/srt/stine/otf4.in new file mode 100644 index 000000000..e448c1d09 --- /dev/null +++ b/pipelined/srt/stine/otf4.in @@ -0,0 +1,23 @@ +.i 4 +.o 6 +.ilb quot[3] quot[2] quot[1] quot[0] +.ob Qin[1] Qin[0] QMin[1] QMin[0] CshiftQ CshiftQM + +0000 001100 +0001 100110 +0010 111010 +0011 ------ +0100 010001 +0101 ------ +0110 ------ +0111 ------ +1000 100101 +1001 ------ +1010 ------ +1011 ------ +1100 ------ +1101 ------ +1110 ------ +1111 ------ + +.e \ No newline at end of file diff --git a/pipelined/srt/stine/pd_bad.png b/pipelined/srt/stine/pd_bad.png new file mode 100644 index 000000000..39df5cdaa Binary files /dev/null and b/pipelined/srt/stine/pd_bad.png differ diff --git a/pipelined/srt/stine/pd_cpa.png b/pipelined/srt/stine/pd_cpa.png new file mode 100644 index 000000000..d80104024 Binary files /dev/null and b/pipelined/srt/stine/pd_cpa.png differ diff --git a/pipelined/srt/stine/pd_csa.pdf b/pipelined/srt/stine/pd_csa.pdf new file mode 100644 index 000000000..00a67f88b Binary files /dev/null and b/pipelined/srt/stine/pd_csa.pdf differ diff --git a/pipelined/srt/stine/pd_csa.png b/pipelined/srt/stine/pd_csa.png new file mode 100644 index 000000000..9cf58ce48 Binary files /dev/null and b/pipelined/srt/stine/pd_csa.png differ diff --git a/pipelined/srt/stine/qslc_r4a2 b/pipelined/srt/stine/qslc_r4a2 new file mode 100755 index 000000000..6d6db4d49 Binary files /dev/null and b/pipelined/srt/stine/qslc_r4a2 differ diff --git a/pipelined/srt/stine/qslc_r4a2.c b/pipelined/srt/stine/qslc_r4a2.c new file mode 100644 index 000000000..8e68f9983 --- /dev/null +++ b/pipelined/srt/stine/qslc_r4a2.c @@ -0,0 +1,198 @@ +/* + Program: qslc_r4a2.c + Description: Prints out Quotient Selection Table (assumes CPA is utilized to reduce memory) + User: James E. Stine + +*/ + +#include +#include + +#define DIVISOR_SIZE 3 +#define CARRY_SIZE 7 +#define SUM_SIZE 7 +#define TOT_SIZE 7 + +void disp_binary(double, int, int); + +struct bits { + unsigned int divisor : DIVISOR_SIZE; + int tot : TOT_SIZE; +} pla; + +/* + + Function: disp_binary + Description: This function displays a Double-Precision number into + four 16 bit integers using the global union variable + dp_number + Argument List: double x The value to be converted + int bits_to_left Number of bits left of radix point + int bits_to_right Number of bits right of radix point + Return value: none + +*/ +void disp_binary(double x, int bits_to_left, int bits_to_right) { + int i; + double diff; + + if (fabs(x) < pow(2.0, ((double) -bits_to_right)) ) { + for (i = -bits_to_left + 1; i <= bits_to_right; i++) { + printf("0"); + } + if (i == bits_to_right+1) + ; + + return; + } + + if (x < 0.0) + x = pow(2.0, ((double) bits_to_left)) + x; + + for (i = -bits_to_left + 1; i <= bits_to_right; i++) { + diff = pow(2.0, ((double) -i) ); + if (x < diff) + printf("0"); + else { + printf("1"); + x -= diff; + } + if (i == 0) + ; + + } + +} + +int main() { + int m; + int n; + int o; + pla.divisor = 0; + pla.tot = 0; + printf("\tcase({D[5:3],Wmsbs})\n"); + for (o=0; o < pow(2.0, DIVISOR_SIZE); o++) { + for (m=0; m < pow(2.0, TOT_SIZE); m++) { + printf("\t\t10'b"); + disp_binary((double) pla.divisor, DIVISOR_SIZE, 0); + printf("_"); + disp_binary((double) pla.tot, TOT_SIZE, 0); + printf(": q = 4'b"); + + /* + 4 bits for Radix 4 (a=2) + 1000 = +2 + 0100 = +1 + 0000 = 0 + 0010 = -1 + 0001 = -2 + */ + switch (pla.divisor) { + case 0: + if ((pla.tot) >= 12) + printf("1000"); + else if ((pla.tot) >= 4) + printf("0100"); + else if ((pla.tot) >= -4) + printf("0000"); + else if ((pla.tot) >= -13) + printf("0010"); + else + printf("0001"); + break; + case 1: + if ((pla.tot) >= 14) + printf("1000"); + else if ((pla.tot) >= 4) + printf("0100"); + else if ((pla.tot) >= -6) + printf("0000"); + else if ((pla.tot) >= -15) + printf("0010"); + else + printf("0001"); + break; + case 2: + if ((pla.tot) >= 15) + printf("1000"); + else if ((pla.tot) >= 4) + printf("0100"); + else if ((pla.tot) >= -6) + printf("0000"); + else if ((pla.tot) >= -16) + printf("0010"); + else + printf("0001"); + break; + case 3: + if ((pla.tot) >= 16) + printf("1000"); + else if ((pla.tot) >= 4) + printf("0100"); + else if ((pla.tot) >= -6) + printf("0000"); + else if ((pla.tot) >= -18) + printf("0010"); + else + printf("0001"); + break; + case 4: + if ((pla.tot) >= 18) + printf("1000"); + else if ((pla.tot) >= 6) + printf("0100"); + else if ((pla.tot) >= -8) + printf("0000"); + else if ((pla.tot) >= -20) + printf("0010"); + else + printf("0001"); + break; + case 5: + if ((pla.tot) >= 20) + printf("1000"); + else if ((pla.tot) >= 6) + printf("0100"); + else if ((pla.tot) >= -8) + printf("0000"); + else if ((pla.tot) >= -20) + printf("0010"); + else + printf("0001"); + break; + case 6: + if ((pla.tot) >= 20) + printf("1000"); + else if ((pla.tot) >= 8) + printf("0100"); + else if ((pla.tot) >= -8) + printf("0000"); + else if ((pla.tot) >= -22) + printf("0010"); + else + printf("0001"); + break; + case 7: + if ((pla.tot) >= 24) + printf("1000"); + else if ((pla.tot) >= 8) + printf("0100"); + else if ((pla.tot) >= -8) + printf("0000"); + else if ((pla.tot) >= -24) + printf("0010"); + else + printf("0001"); + break; + default: printf ("XXX"); + + } + + printf(";\n"); + (pla.tot)++; + } + (pla.divisor)++; + } + printf("\tendcase\n"); + +} diff --git a/pipelined/srt/stine/run.sh b/pipelined/srt/stine/run.sh new file mode 100755 index 000000000..6dcde6c26 --- /dev/null +++ b/pipelined/srt/stine/run.sh @@ -0,0 +1,8 @@ +#!/bin/sh +vsim -do iter32S.do -c +vsim -do iter32.do -c +vsim -do iter64.do -c +vsim -do iter64S.do -c +vsim -do iter128.do -c +vsim -do iter128S.do -c + diff --git a/pipelined/srt/stine/shift.sv b/pipelined/srt/stine/shift.sv new file mode 100755 index 000000000..9738d93fe --- /dev/null +++ b/pipelined/srt/stine/shift.sv @@ -0,0 +1,73 @@ +/////////////////////////////////////////// +// shifters.sv +// +// Written: James.Stine@okstate.edu 1 February 2021 +// Modified: +// +// Purpose: Integer Divide instructions +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +module shift_right #(parameter WIDTH=8) + (input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Shift, + output logic [WIDTH-1:0] Z); + + logic [WIDTH-1:0] stage [$clog2(WIDTH):0]; + logic sign; + genvar i; + + assign stage[0] = A; + generate + for (i=0;i<$clog2(WIDTH);i=i+1) + begin : genbit + mux2 #(WIDTH) mux_inst (stage[i], + {{(WIDTH/(2**(i+1))){1'b0}}, stage[i][WIDTH-1:WIDTH/(2**(i+1))]}, + Shift[$clog2(WIDTH)-i-1], + stage[i+1]); + end + endgenerate + assign Z = stage[$clog2(WIDTH)]; + +endmodule // shift_right + +module shift_left #(parameter WIDTH=8) + (input logic [WIDTH-1:0] A, + input logic [$clog2(WIDTH)-1:0] Shift, + output logic [WIDTH-1:0] Z); + + logic [WIDTH-1:0] stage [$clog2(WIDTH):0]; + genvar i; + + assign stage[0] = A; + generate + for (i=0;i<$clog2(WIDTH);i=i+1) + begin : genbit + mux2 #(WIDTH) mux_inst (stage[i], + {stage[i][WIDTH-1-WIDTH/(2**(i+1)):0], {(WIDTH/(2**(i+1))){1'b0}}}, + Shift[$clog2(WIDTH)-i-1], + stage[i+1]); + end + endgenerate + assign Z = stage[$clog2(WIDTH)]; + +endmodule // shift_left + + + + diff --git a/pipelined/srt/stine/shift_left.do b/pipelined/srt/stine/shift_left.do new file mode 100755 index 000000000..a178c3cc0 --- /dev/null +++ b/pipelined/srt/stine/shift_left.do @@ -0,0 +1,55 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv shift.sv shift_left_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 800ns +quit diff --git a/pipelined/srt/stine/shift_left_tb.sv b/pipelined/srt/stine/shift_left_tb.sv new file mode 100755 index 000000000..2d5d3dad8 --- /dev/null +++ b/pipelined/srt/stine/shift_left_tb.sv @@ -0,0 +1,71 @@ +// +// File name : tb +// Title : test +// project : HW3 +// Library : test +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +// Top level stimulus module + +`timescale 1ns/1ps + +`define XLEN 32 +module stimulus; + + logic [`XLEN-1:0] A; + logic [$clog2(`XLEN)-1:0] Shift; + logic [`XLEN-1:0] Z; + logic [`XLEN-1:0] Z_corr; + + //logic [63:0] A; + //logic [5:0] Shift; + //logic [63:0] Z; + //logic [63:0] Z_corr; + //logic [63:0] Z_orig; + + + logic clk; + + integer handle3; + integer desc3; + integer i; + + // instatiate part to test + shift_left dut1 (A, Shift, Z); + assign Z_corr = (A << Shift); + + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + handle3 = $fopen("shift_left.out"); + desc3 = handle3; + end + + initial + begin + for (i=0; i < 256; i=i+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + A = $random; + Shift = $random; + end + @(negedge clk) + begin + $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); + end + end // for (i=0; i < 256; i=i+1) + $finish;// + end // initial begin + +endmodule // stimulus diff --git a/pipelined/srt/stine/shift_right.do b/pipelined/srt/stine/shift_right.do new file mode 100755 index 000000000..bf02e75c1 --- /dev/null +++ b/pipelined/srt/stine/shift_right.do @@ -0,0 +1,55 @@ +# Copyright 1991-2016 Mentor Graphics Corporation +# +# Modification by Oklahoma State University +# Use with Testbench +# James Stine, 2008 +# Go Cowboys!!!!!! +# +# All Rights Reserved. +# +# THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION +# WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION +# OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. + +# Use this run.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do run.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do run.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +vlog mux.sv shift.sv shift_right_tb.sv + +# start and run simulation +vsim -voptargs=+acc work.stimulus + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave -hex -r /stimulus/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {75 ns} +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 + +-- Run the Simulation +run 800ns +quit diff --git a/pipelined/srt/stine/shift_right_tb.sv b/pipelined/srt/stine/shift_right_tb.sv new file mode 100755 index 000000000..b35277484 --- /dev/null +++ b/pipelined/srt/stine/shift_right_tb.sv @@ -0,0 +1,64 @@ +// +// File name : tb +// Title : test +// project : HW3 +// Library : test +// Purpose : definition of modules for testbench +// notes : +// +// Copyright Oklahoma State University +// + +// Top level stimulus module + +`timescale 1ns/1ps + +`define XLEN 32 +module stimulus; + + logic [`XLEN-1:0] A; + logic [$clog2(`XLEN)-1:0] Shift; + logic [`XLEN-1:0] Z; + logic [`XLEN-1:0] Z_corr; + + logic clk; + + integer handle3; + integer desc3; + integer i; + + // instatiate part to test + shift_right dut1 (A, Shift, Z); + assign Z_corr = (A >> Shift); + + initial + begin + clk = 1'b1; + forever #5 clk = ~clk; + end + + initial + begin + handle3 = $fopen("shift_right.out"); + desc3 = handle3; + #250 $finish; + end + + initial + begin + for (i=0; i < 128; i=i+1) + begin + // Put vectors before beginning of clk + @(posedge clk) + begin + A = $random; + Shift = $random; + end + @(negedge clk) + begin + $fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr)); + end + end // @(negedge clk) + end // for (j=0; j < 32; j=j+1) + +endmodule // stimulus diff --git a/pipelined/srt/stine/shifter.sv b/pipelined/srt/stine/shifter.sv new file mode 100755 index 000000000..779a02a47 --- /dev/null +++ b/pipelined/srt/stine/shifter.sv @@ -0,0 +1,18 @@ +module shifter_right(input logic signed [63:0] a, + input logic [ 5:0] shamt, + output logic signed [63:0] y); + + + y = a >> shamt; + +endmodule // shifter_right + +module shifter_left(input logic signed [63:0] a, + input logic [ 5:0] shamt, + output logic signed [63:0] y); + + + y = a << shamt; + +endmodule // shifter_right + diff --git a/pipelined/srt/stine/srt2div b/pipelined/srt/stine/srt2div new file mode 100755 index 000000000..92734241f Binary files /dev/null and b/pipelined/srt/stine/srt2div differ diff --git a/pipelined/srt/stine/srt2div.c b/pipelined/srt/stine/srt2div.c new file mode 100755 index 000000000..9b404d94b --- /dev/null +++ b/pipelined/srt/stine/srt2div.c @@ -0,0 +1,114 @@ +#include "disp.h" + +// QSLC is for division by recuerrence for +// r=2 using a CPA - See 5.109 EL +int qst (double D, double prem) { + + int q; + + // For Debugging + printf("rw --> %lg\n", prem); + + if (prem >= 0.5) { + q = 1; + } else if (prem >= -0.5) { + q = 0; + } else { + q = -1; + } + return q; + +} + +/* + This routine performs a radix-2 SRT division + algorithm. The user inputs the numerator, the denominator, + and the number of iterations. It assumes that 0.5 <= D < 1. + +*/ + +int main(int argc, char* argv[]) { + + double P, N, D, Q, RQ, RD, RREM, scale; + int q; + int num_iter, i; + int prec; + int radix = 2; + + if (argc < 5) { + fprintf(stderr, + "Usage: %s numerator denominator num_iterations prec\n", + argv[0]); + exit(1); + } + sscanf(argv[1],"%lg", &N); + sscanf(argv[2],"%lg", &D); + sscanf(argv[3],"%d", &num_iter); + sscanf(argv[4],"%d", &prec); + // Round to precision + N = rne(N, prec); + D = rne(D, prec); + printf("N = "); + disp_bin(N, 3, prec, stdout); + printf("\n"); + printf("D = "); + disp_bin(D, 3, prec, stdout); + printf("\n"); + + Q = 0; + P = N * pow(2.0, -log2(radix)); + printf("N = %lg, D = %lg, N/D = %lg, num_iter = %d \n\n", + N, D, N/D, num_iter); + for (scale = 1, i = 0; i < num_iter; i++) { + scale = scale * pow(2.0, -log2(radix)); + q = qst(flr(2*D, 1), 2*P); + printf("2*W[n] = "); + disp_bin(radix*P, 3, prec, stdout); + printf("\n"); + printf("q*D = "); + disp_bin(q*D, 3, prec, stdout); + printf("\n"); + printf("W[n+1] = "); + disp_bin(P ,3, prec, stdout); + printf("\n"); + // Recurrence + P = radix * P - q * D; + Q = Q + q*scale; + printf("i = %d, q = %d, Q = %1.18lf, W = %1.18lf\n", i, q, Q, P); + printf("i = %d, q = %d", i, q); + printf(", Q = "); + disp_bin(Q, 3, prec, stdout); + printf(", W = "); + disp_bin(P, 3, prec, stdout); + printf("\n\n"); + } + if (P < 0) { + Q = Q - scale; + P = P + D; + printf("\nCorrecting Negative Remainder\n"); + printf("Q = %1.18lf, W = %1.18lf\n", Q, P); + printf("Q = "); + disp_bin(Q, 3, prec, stdout); + printf(", W = "); + disp_bin(P, 3, prec, stdout); + printf("\n"); + } + + // Output Results + RQ = N/D; + // Since q_{computed} = q / radix, multiply by radix + RD = Q * radix; + printf("true = %1.18lf, computed = %1.18lf, \n", RQ, RD); + printf("true = "); + disp_bin(RQ, 3, prec, stdout); + printf(", computed = "); + disp_bin(RD, 3, prec, stdout); + printf("\n\n"); + printf("REM = %1.18lf \n", P); + printf("REM = "); + disp_bin(P, 3, prec, stdout); + printf("\n\n"); + + return 0; + +} diff --git a/pipelined/srt/stine/srt4_pd.m b/pipelined/srt/stine/srt4_pd.m new file mode 100644 index 000000000..815c84c75 --- /dev/null +++ b/pipelined/srt/stine/srt4_pd.m @@ -0,0 +1,508 @@ +% +% PD Region for Np = 3; Nd = 4; +% w/CPA +% +% Clear all variables and screen +clear +clf +% Define the number of bits (input Dividend) +n = 4; +% +% Define Divisor Range +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dminimum = 1.0/2; +Dmaximum = 2.0/2; +% Define an ulp +ulp = 2^(-n); +% radix = beta +beta = 4; +% rho = redundancy factor -> SHOULD ALWAYS BE >= THAN 1/2 +% +% SD representations have alpha < beta - 1 +% +% alpha = ceil(beta/2) minimially redundant +% alpha = beta -1 maximally redundant (rho = 1) +% alpha = (beta-1)/2 nonredundant +% alpha > beta - 1 over-redundant +% +rho = 2/3; +% Calculation of max digit set +alpha = rho*(beta-1); +% Da contains digit set +q = []; +for i = -alpha:alpha + q = [q; i]; +end +% 4r(i-1)/D values +hold on +% figure(1) +grid off +for i = 1:length(q) + x = -rho+q(i):ulp:rho+q(i); + % Plot redundancy (overlap) Positive + z = [rho+q(i),rho+q(i)]; + y = [x(length(x))-q(i),0]; + % Plot redundancy (overlap) Negative + if (i ~= length(q)) + w = [-rho+q(i+1)-q(i+1),0]; + u = [-rho+q(i+1),-rho+q(i+1)]; + % plot(u,w,'b') + end + % plot(x,x-q(i)) + % plot(z,y,'r') + +end +% title('Robertson Diagram for Radix-4 SRT Divison') + +Np = 3; +Nd = 4; +Dmin = Dminimum; +Dmax = Dmaximum; +ulpd = 2^(-Nd); +ulpp = 2^(-Np); + +% +% Plot Atkins P-D plot +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dmin = Dminimum; +Dmax = Dmaximum; +for i = 1:length(q) + D = Dmin:ulp:Dmax; + P1 = (rho+q(i))*D; + P2 = (-rho+q(i))*D; + hold on + p1 = plot(D,P1); + p1.Color = '#0000ff'; + p2 = plot(D,P2); + p2.Color = '#ff0000'; + axis([Dmin Dmax -beta*rho*Dmaximum beta*rho*Dmaximum]) + xticks(D) + p1.LineWidth = 2.0; + p2.LineWidth = 2.0; +end + +% Let's make x/y axis binary +j = []; +for i=1:length(D) + j = [j disp_bin(D(i), 1, 4)]; +end +yk = []; +yk2 = []; +for i=-2.5:0.5:2.5; + yk = [yk disp_bin(i, 3, 3)]; + yk2 = [yk2 i]; +end +xtickangle(90) +xticklabels(j) +yticklabels(yk) + +% Let's draw allow points on PD plot +% Positive Portions +index = 1; +i = 0:ulpp:rho*beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k') +end + +j = Dmin:ulpd:Dmax; +for i = 0:ulpp:rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k') +end + +% Negative Portions +index = 1; +i = 0:-ulpp:rho*-beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k') +end + +j = Dmin:ulpd:Dmax; +for i = 0:-ulpp:-rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k') +end + +% Labels and Printing +xlh = xlabel(['Divisor (d)']); +%xlh.FontSize = 18; +xlh.Position(2) = xlh.Position(2) - 0.1; +ylh = ylabel(['P = 4 \cdot w_i']); +ylh.Position(1) = ylh.Position(1)-0.02; +%ylh.FontSize = 18; + +% Containment Values (placed manually although not bad) +m2 = [3/4 7/8 1.0 1.0 5/4 5/4 5/4 3/2 3/2]; +m1 = [1/4 1/4 1/4 1/4 1/2 1/2 1/2 1/2 1/2]; +m0 = [-1/4 -1/4 -1/4 -1/4 -1/2 -1/2 -1/2 -1/2 -1/2]; +m1b = [-3/4 -7/8 -1 -1 -5/4 -5/4 -5/4 -3/2 -3/2]; +x2 = Dmin:ulpd:Dmax; +s2 = stairs(x2, m2); +s2.Color = '#8f08d1'; +s2.LineWidth = 3.0; +%s2.LineStyle = '--'; +s1 = stairs(x2, m1); +s1.Color = '#8f08d1'; +s1.LineWidth = 3.0; +s0 = stairs(x2, m0); +s0.Color = '#8f08d1'; +s0.LineWidth = 3.0; +s1b = stairs(x2, m1b); +s1b.Color = '#8f08d1'; +s1b.LineWidth = 3.0; + +% Place manually Quotient (ugh) +j = Dmin+ulpd/2:ulpd:Dmax; +i = rho*beta*Dmaximum-ulpp*3/4:-ulpp:-rho*beta*Dmaximum; +text(j(1), i(1), '2') +text(j(1), i(2), '2') +text(j(1), i(3), '2') +text(j(1), i(4), '2') +text(j(1), i(5), '2') +text(j(1), i(6), '2') +text(j(1), i(7), '2') +text(j(1), i(8), '2') +text(j(1), i(9), '2') +text(j(1), i(10), '2') +text(j(1), i(11), '2') +text(j(1), i(12), '2') +text(j(1), i(13), '2') +text(j(1), i(14), '2') +text(j(1), i(15), '2') +text(j(1), i(16), '1') +text(j(1), i(17), '1') +text(j(1), i(18), '1') +text(j(1), i(19), '1') +text(j(1), i(20), '0') +text(j(1), i(21), '0') +text(j(1), i(22), '0') +text(j(1), i(23), '0') +text(j(1), i(24), '-1') +text(j(1), i(25), '-1') +text(j(1), i(26), '-1') +text(j(1), i(27), '-1') +text(j(1), i(28), '-2') +text(j(1), i(29), '-2') +text(j(1), i(30), '-2') +text(j(1), i(31), '-2') +text(j(1), i(32), '-2') +text(j(1), i(33), '-2') +text(j(1), i(34), '-2') +text(j(1), i(35), '-2') +text(j(1), i(36), '-2') +text(j(1), i(37), '-2') +text(j(1), i(38), '-2') +text(j(1), i(39), '-2') +text(j(1), i(40), '-2') +text(j(1), i(41), '-2') +text(j(1), i(42), '-2') + +text(j(2), i(1), '2') +text(j(2), i(2), '2') +text(j(2), i(3), '2') +text(j(2), i(4), '2') +text(j(2), i(5), '2') +text(j(2), i(6), '2') +text(j(2), i(7), '2') +text(j(2), i(8), '2') +text(j(2), i(9), '2') +text(j(2), i(10), '2') +text(j(2), i(11), '2') +text(j(2), i(12), '2') +text(j(2), i(13), '2') +text(j(2), i(14), '2') +text(j(2), i(15), '1') +text(j(2), i(16), '1') +text(j(2), i(17), '1') +text(j(2), i(18), '1') +text(j(2), i(19), '1') +text(j(2), i(20), '0') +text(j(2), i(21), '0') +text(j(2), i(22), '0') +text(j(2), i(23), '0') +text(j(2), i(24), '-1') +text(j(2), i(25), '-1') +text(j(2), i(26), '-1') +text(j(2), i(27), '-1') +text(j(2), i(28), '-1') +text(j(2), i(29), '-2') +text(j(2), i(30), '-2') +text(j(2), i(31), '-2') +text(j(2), i(32), '-2') +text(j(2), i(33), '-2') +text(j(2), i(34), '-2') +text(j(2), i(35), '-2') +text(j(2), i(36), '-2') +text(j(2), i(37), '-2') +text(j(2), i(38), '-2') +text(j(2), i(39), '-2') +text(j(2), i(40), '-2') +text(j(2), i(41), '-2') +text(j(2), i(42), '-2') + +text(j(3), i(1), '2') +text(j(3), i(2), '2') +text(j(3), i(3), '2') +text(j(3), i(4), '2') +text(j(3), i(5), '2') +text(j(3), i(6), '2') +text(j(3), i(7), '2') +text(j(3), i(8), '2') +text(j(3), i(9), '2') +text(j(3), i(10), '2') +text(j(3), i(11), '2') +text(j(3), i(12), '2') +text(j(3), i(13), '2') +text(j(3), i(14), '1') +text(j(3), i(15), '1') +text(j(3), i(16), '1') +text(j(3), i(17), '1') +text(j(3), i(18), '1') +text(j(3), i(19), '1') +text(j(3), i(20), '0') +text(j(3), i(21), '0') +text(j(3), i(22), '0') +text(j(3), i(23), '0') +text(j(3), i(24), '-1') +text(j(3), i(25), '-1') +text(j(3), i(26), '-1') +text(j(3), i(27), '-1') +text(j(3), i(28), '-1') +text(j(3), i(29), '-1') +text(j(3), i(30), '-2') +text(j(3), i(31), '-2') +text(j(3), i(32), '-2') +text(j(3), i(33), '-2') +text(j(3), i(34), '-2') +text(j(3), i(35), '-2') +text(j(3), i(36), '-2') +text(j(3), i(37), '-2') +text(j(3), i(38), '-2') +text(j(3), i(39), '-2') +text(j(3), i(40), '-2') +text(j(3), i(41), '-2') +text(j(3), i(42), '-2') + +text(j(4), i(1), '2') +text(j(4), i(2), '2') +text(j(4), i(3), '2') +text(j(4), i(4), '2') +text(j(4), i(5), '2') +text(j(4), i(6), '2') +text(j(4), i(7), '2') +text(j(4), i(8), '2') +text(j(4), i(9), '2') +text(j(4), i(10), '2') +text(j(4), i(11), '2') +text(j(4), i(12), '2') +text(j(4), i(13), '2') +text(j(4), i(14), '1') +text(j(4), i(15), '1') +text(j(4), i(16), '1') +text(j(4), i(17), '1') +text(j(4), i(18), '1') +text(j(4), i(19), '1') +text(j(4), i(20), '0') +text(j(4), i(21), '0') +text(j(4), i(22), '0') +text(j(4), i(23), '0') +text(j(4), i(24), '-1') +text(j(4), i(25), '-1') +text(j(4), i(26), '-1') +text(j(4), i(27), '-1') +text(j(4), i(28), '-1') +text(j(4), i(29), '-1') +text(j(4), i(30), '-2') +text(j(4), i(31), '-2') +text(j(4), i(32), '-2') +text(j(4), i(33), '-2') +text(j(4), i(34), '-2') +text(j(4), i(35), '-2') +text(j(4), i(36), '-2') +text(j(4), i(37), '-2') +text(j(4), i(38), '-2') +text(j(4), i(39), '-2') +text(j(4), i(40), '-2') +text(j(4), i(41), '-2') +text(j(4), i(42), '-2') + +text(j(5), i(1), '2') +text(j(5), i(2), '2') +text(j(5), i(3), '2') +text(j(5), i(4), '2') +text(j(5), i(5), '2') +text(j(5), i(6), '2') +text(j(5), i(7), '2') +text(j(5), i(8), '2') +text(j(5), i(9), '2') +text(j(5), i(10), '2') +text(j(5), i(11), '2') +text(j(5), i(12), '1') +text(j(5), i(13), '1') +text(j(5), i(14), '1') +text(j(5), i(15), '1') +text(j(5), i(16), '1') +text(j(5), i(17), '1') +text(j(5), i(18), '0') +text(j(5), i(19), '0') +text(j(5), i(20), '0') +text(j(5), i(21), '0') +text(j(5), i(22), '0') +text(j(5), i(23), '0') +text(j(5), i(24), '0') +text(j(5), i(25), '0') +text(j(5), i(26), '-1') +text(j(5), i(27), '-1') +text(j(5), i(28), '-1') +text(j(5), i(29), '-1') +text(j(5), i(30), '-1') +text(j(5), i(31), '-1') +text(j(5), i(32), '-2') +text(j(5), i(33), '-2') +text(j(5), i(34), '-2') +text(j(5), i(35), '-2') +text(j(5), i(36), '-2') +text(j(5), i(37), '-2') +text(j(5), i(38), '-2') +text(j(5), i(39), '-2') +text(j(5), i(40), '-2') +text(j(5), i(41), '-2') +text(j(5), i(42), '-2') + +text(j(6), i(1), '2') +text(j(6), i(2), '2') +text(j(6), i(3), '2') +text(j(6), i(4), '2') +text(j(6), i(5), '2') +text(j(6), i(6), '2') +text(j(6), i(7), '2') +text(j(6), i(8), '2') +text(j(6), i(9), '2') +text(j(6), i(10), '2') +text(j(6), i(11), '2') +text(j(6), i(12), '1') +text(j(6), i(13), '1') +text(j(6), i(14), '1') +text(j(6), i(15), '1') +text(j(6), i(16), '1') +text(j(6), i(17), '1') +text(j(6), i(18), '0') +text(j(6), i(19), '0') +text(j(6), i(20), '0') +text(j(6), i(21), '0') +text(j(6), i(22), '0') +text(j(6), i(23), '0') +text(j(6), i(24), '0') +text(j(6), i(25), '0') +text(j(6), i(26), '-1') +text(j(6), i(27), '-1') +text(j(6), i(28), '-1') +text(j(6), i(29), '-1') +text(j(6), i(30), '-1') +text(j(6), i(31), '-1') +text(j(6), i(32), '-2') +text(j(6), i(33), '-2') +text(j(6), i(34), '-2') +text(j(6), i(35), '-2') +text(j(6), i(36), '-2') +text(j(6), i(37), '-2') +text(j(6), i(38), '-2') +text(j(6), i(39), '-2') +text(j(6), i(40), '-2') +text(j(6), i(41), '-2') +text(j(6), i(42), '-2') + +text(j(7), i(1), '2') +text(j(7), i(2), '2') +text(j(7), i(3), '2') +text(j(7), i(4), '2') +text(j(7), i(5), '2') +text(j(7), i(6), '2') +text(j(7), i(7), '2') +text(j(7), i(8), '2') +text(j(7), i(9), '2') +text(j(7), i(10), '2') +text(j(7), i(11), '2') +text(j(7), i(12), '1') +text(j(7), i(13), '1') +text(j(7), i(14), '1') +text(j(7), i(15), '1') +text(j(7), i(16), '1') +text(j(7), i(17), '1') +text(j(7), i(18), '0') +text(j(7), i(19), '0') +text(j(7), i(20), '0') +text(j(7), i(21), '0') +text(j(7), i(22), '0') +text(j(7), i(23), '0') +text(j(7), i(24), '0') +text(j(7), i(25), '0') +text(j(7), i(26), '-1') +text(j(7), i(27), '-1') +text(j(7), i(28), '-1') +text(j(7), i(29), '-1') +text(j(7), i(30), '-1') +text(j(7), i(31), '-1') +text(j(7), i(32), '-2') +text(j(7), i(33), '-2') +text(j(7), i(34), '-2') +text(j(7), i(35), '-2') +text(j(7), i(36), '-2') +text(j(7), i(37), '-2') +text(j(7), i(38), '-2') +text(j(7), i(39), '-2') +text(j(7), i(40), '-2') +text(j(7), i(41), '-2') +text(j(7), i(42), '-2') + +text(j(8), i(1), '2') +text(j(8), i(2), '2') +text(j(8), i(3), '2') +text(j(8), i(4), '2') +text(j(8), i(5), '2') +text(j(8), i(6), '2') +text(j(8), i(7), '2') +text(j(8), i(8), '2') +text(j(8), i(9), '2') +text(j(8), i(10), '1') +text(j(8), i(11), '1') +text(j(8), i(12), '1') +text(j(8), i(13), '1') +text(j(8), i(14), '1') +text(j(8), i(15), '1') +text(j(8), i(16), '1') +text(j(8), i(17), '1') +text(j(8), i(18), '0') +text(j(8), i(19), '0') +text(j(8), i(20), '0') +text(j(8), i(21), '0') +text(j(8), i(22), '0') +text(j(8), i(23), '0') +text(j(8), i(24), '0') +text(j(8), i(25), '0') +text(j(8), i(26), '-1') +text(j(8), i(27), '-1') +text(j(8), i(28), '-1') +text(j(8), i(29), '-1') +text(j(8), i(30), '-2') +text(j(8), i(31), '-2') +text(j(8), i(32), '-2') +text(j(8), i(33), '-2') +text(j(8), i(34), '-2') +text(j(8), i(35), '-2') +text(j(8), i(36), '-2') +text(j(8), i(37), '-2') +text(j(8), i(38), '-2') +text(j(8), i(39), '-2') +text(j(8), i(40), '-2') +text(j(8), i(41), '-2') +text(j(8), i(42), '-2') + +print -dpng pd_cpa.png + + + + + diff --git a/pipelined/srt/stine/srt4_pd2.m b/pipelined/srt/stine/srt4_pd2.m new file mode 100644 index 000000000..9c60923aa --- /dev/null +++ b/pipelined/srt/stine/srt4_pd2.m @@ -0,0 +1,333 @@ +% +% Clear all variables and screen +clear +clf +% Define the number of bits (input Dividend) +n = 4; +% +% Define Divisor Range +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dminimum = 1.0/2; +Dmaximum = 2.0/2; +% Define an ulp +ulp = 2^(-n); +% radix = beta +beta = 4; +% rho = redundancy factor -> SHOULD ALWAYS BE >= THAN 1/2 +% +% SD representations have alpha < beta - 1 +% +% alpha = ceil(beta/2) minimially redundant +% alpha = beta -1 maximally redundant (rho = 1) +% alpha = (beta-1)/2 nonredundant +% alpha > beta - 1 over-redundant +% +rho = 2/3; +% Calculation of max digit set +alpha = rho*(beta-1); +% Da contains digit set +q = []; +for i = -alpha:alpha + q = [q; i]; +end +% 4r(i-1)/D values +hold on +% figure(1) +grid off +for i = 1:length(q) + x = -rho+q(i):ulp:rho+q(i); + % Plot redundancy (overlap) Positive + z = [rho+q(i),rho+q(i)]; + y = [x(length(x))-q(i),0]; + % Plot redundancy (overlap) Negative + if (i ~= length(q)) + w = [-rho+q(i+1)-q(i+1),0]; + u = [-rho+q(i+1),-rho+q(i+1)]; + % plot(u,w,'b') + end + % plot(x,x-q(i)) + % plot(z,y,'r') + +end +% title('Robertson Diagram for Radix-4 SRT Divison') + +Np = 3; +Nd = 3; +Dmin = Dminimum; +Dmax = Dmaximum; +ulpd = 2^(-Nd); +ulpp = 2^(-Np); + +% +% Plot Atkins P-D plot +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dmin = Dminimum; +Dmax = Dmaximum; +for i = 1:length(q) + D = Dmin:ulpd:Dmax; + P1 = (rho+q(i))*D; + P2 = (-rho+q(i))*D; + hold on + p1 = plot(D,P1,'b'); + p2 = plot(D,P2,'r'); + axis([Dmin Dmax -beta*rho*Dmaximum beta*rho*Dmaximum]) + xticks(D) + p1.LineWidth = 2.0; + p2.LineWidth = 2.0; +end + +% Let's make x axis binary +D = Dmin:ulpd:Dmax; +j = []; +for i=1:length(D) + j = [j disp_bin(D(i), 1, 3)]; +end +yk = []; +yk2 = []; +for i=-2.5:0.5:2.5; + yk = [yk disp_bin(i, 3, 3)]; + yk2 = [yk2 i]; +end +xtickangle(90) +xticklabels(j) +yticklabels(yk) + +% Let's draw allow points on PD plot +% Positive Portions +index = 1; +i = 0:ulpp:rho*beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k'); +end + +j = Dmin:ulpd:Dmax; +for i = 0:ulpp:rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k'); +end + +% Negative Portions +index = 1; +i = 0:-ulpp:rho*-beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k'); +end + +j = Dmin:ulpd:Dmax; +for i = 0:-ulpp:-rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k'); +end + +% Labels and Printing +xlh = xlabel(['Divisor (d)']); +xlh.Position(2) = xlh.Position(2) - 0.1; +xlh.FontSize = 18; +ylh = ylabel(['P = 4 \cdot w_i']); +ylh.Position(1) = ylh.Position(1)-0.02; +ylh.FontSize = 18; + +% Containment Values (placed manually although not bad) +m2 = [5/6 1.0 5/4 11/8 11/8]; +m1 = [1/4 1/4 1/2 1/2 1/2]; +m0 = [-1/4 -1/4 -1/2 -1/2 -1/2]; +m1b = [-5/6 -1 -5/4 -11/8 -11/8]; +x2 = Dmin:ulpd:Dmax; +s2 = stairs(x2, m2); +s2.Color = '#8f08d1'; +s2.LineWidth = 3.0; +s1 = stairs(x2, m1); +s1.Color = '#8f08d1'; +s1.LineWidth = 3.0; +s0 = stairs(x2, m0); +s0.Color = '#8f08d1'; +s0.LineWidth = 3.0; +s1b = stairs(x2, m1b); +s1b.Color = '#8f08d1'; +s1b.LineWidth = 3.0; + +% Place manually Quotient (ugh) +j = Dmin+ulpd/2:ulpd:Dmax; +i = rho*beta*Dmaximum-ulpp*3/4:-ulpp:-rho*beta*Dmaximum; +text(j(1), i(1), '2') +text(j(1), i(2), '2') +text(j(1), i(3), '2') +text(j(1), i(4), '2') +text(j(1), i(5), '2') +text(j(1), i(6), '2') +text(j(1), i(7), '2') +text(j(1), i(8), '2') +text(j(1), i(9), '2') +text(j(1), i(10), '2') +text(j(1), i(11), '2') +text(j(1), i(12), '2') +text(j(1), i(13), '2') +text(j(1), i(14), '2') +error1 = text(j(1), i(15), 'Full Precision', 'FontSize', 16); +text(j(1), i(16), '1') +text(j(1), i(17), '1') +text(j(1), i(18), '1') +text(j(1), i(19), '1') +text(j(1), i(20), '0') +text(j(1), i(21), '0') +text(j(1), i(22), '0') +text(j(1), i(23), '0') +text(j(1), i(24), '-1') +text(j(1), i(25), '-1') +text(j(1), i(26), '-1') +text(j(1), i(27), '-1') +error2 = text(j(1), i(28), 'Full Precision', 'FontSize', 16); +text(j(1), i(29), '-2') +text(j(1), i(30), '-2') +text(j(1), i(31), '-2') +text(j(1), i(32), '-2') +text(j(1), i(33), '-2') +text(j(1), i(34), '-2') +text(j(1), i(35), '-2') +text(j(1), i(36), '-2') +text(j(1), i(37), '-2') +text(j(1), i(38), '-2') +text(j(1), i(39), '-2') +text(j(1), i(40), '-2') +text(j(1), i(41), '-2') +text(j(1), i(42), '-2') + +text(j(2), i(1), '2') +text(j(2), i(2), '2') +text(j(2), i(3), '2') +text(j(2), i(4), '2') +text(j(2), i(5), '2') +text(j(2), i(6), '2') +text(j(2), i(7), '2') +text(j(2), i(8), '2') +text(j(2), i(9), '2') +text(j(2), i(10), '2') +text(j(2), i(11), '2') +text(j(2), i(12), '2') +text(j(2), i(13), '2') +text(j(2), i(14), '1') +text(j(2), i(15), '1') +text(j(2), i(16), '1') +text(j(2), i(17), '1') +text(j(2), i(18), '1') +text(j(2), i(19), '1') +text(j(2), i(20), '0') +text(j(2), i(21), '0') +text(j(2), i(22), '0') +text(j(2), i(23), '0') +text(j(2), i(24), '-1') +text(j(2), i(25), '-1') +text(j(2), i(26), '-1') +text(j(2), i(27), '-1') +text(j(2), i(28), '-1') +text(j(2), i(29), '-1') +text(j(2), i(30), '-2') +text(j(2), i(31), '-2') +text(j(2), i(32), '-2') +text(j(2), i(33), '-2') +text(j(2), i(34), '-2') +text(j(2), i(35), '-2') +text(j(2), i(36), '-2') +text(j(2), i(37), '-2') +text(j(2), i(38), '-2') +text(j(2), i(39), '-2') +text(j(2), i(40), '-2') +text(j(2), i(41), '-2') +text(j(2), i(42), '-2') + +text(j(3), i(1), '2') +text(j(3), i(2), '2') +text(j(3), i(3), '2') +text(j(3), i(4), '2') +text(j(3), i(5), '2') +text(j(3), i(6), '2') +text(j(3), i(7), '2') +text(j(3), i(8), '2') +text(j(3), i(9), '2') +text(j(3), i(10), '2') +text(j(3), i(11), '2') +text(j(3), i(12), '1') +text(j(3), i(13), '1') +text(j(3), i(14), '1') +text(j(3), i(15), '1') +text(j(3), i(16), '1') +text(j(3), i(17), '1') +text(j(3), i(18), '0') +text(j(3), i(19), '0') +text(j(3), i(20), '0') +text(j(3), i(21), '0') +text(j(3), i(22), '0') +text(j(3), i(23), '0') +text(j(3), i(24), '0') +text(j(3), i(25), '0') +text(j(3), i(26), '-1') +text(j(3), i(27), '-1') +text(j(3), i(28), '-1') +text(j(3), i(29), '-1') +text(j(3), i(30), '-1') +text(j(3), i(31), '-1') +text(j(3), i(32), '-2') +text(j(3), i(33), '-2') +text(j(3), i(34), '-2') +text(j(3), i(35), '-2') +text(j(3), i(36), '-2') +text(j(3), i(37), '-2') +text(j(3), i(38), '-2') +text(j(3), i(39), '-2') +text(j(3), i(40), '-2') +text(j(3), i(41), '-2') +text(j(3), i(42), '-2') + +text(j(4), i(1), '2') +text(j(4), i(2), '2') +text(j(4), i(3), '2') +text(j(4), i(4), '2') +text(j(4), i(5), '2') +text(j(4), i(6), '2') +text(j(4), i(7), '2') +text(j(4), i(8), '2') +text(j(4), i(9), '2') +text(j(4), i(10), '2') +text(j(4), i(11), '1') +text(j(4), i(12), '1') +text(j(4), i(13), '1') +text(j(4), i(14), '1') +text(j(4), i(15), '1') +text(j(4), i(16), '1') +text(j(4), i(17), '1') +text(j(4), i(18), '0') +text(j(4), i(19), '0') +text(j(4), i(20), '0') +text(j(4), i(21), '0') +text(j(4), i(22), '0') +text(j(4), i(23), '0') +text(j(4), i(24), '0') +text(j(4), i(25), '0') +text(j(4), i(26), '-1') +text(j(4), i(27), '-1') +text(j(4), i(28), '-1') +text(j(4), i(29), '-1') +text(j(4), i(30), '-1') +text(j(4), i(31), '-1') +text(j(4), i(32), '-1') +text(j(4), i(33), '-2') +text(j(4), i(34), '-2') +text(j(4), i(35), '-2') +text(j(4), i(36), '-2') +text(j(4), i(37), '-2') +text(j(4), i(38), '-2') +text(j(4), i(39), '-2') +text(j(4), i(40), '-2') +text(j(4), i(41), '-2') +text(j(4), i(42), '-2') + + + +print -dpng pd_bad.png + + + + + diff --git a/pipelined/srt/stine/srt4_pd3.m b/pipelined/srt/stine/srt4_pd3.m new file mode 100644 index 000000000..695b3c7f6 --- /dev/null +++ b/pipelined/srt/stine/srt4_pd3.m @@ -0,0 +1,855 @@ +% +% Clear all variables and screen +clear +clf +% Define the number of bits (input Dividend) +n = 4; +% +% Define Divisor Range +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dminimum = 1.0/2; +Dmaximum = 2.0/2; +% Define an ulp +ulp = 2^(-n); +% radix = beta +beta = 4; +% rho = redundancy factor -> SHOULD ALWAYS BE >= THAN 1/2 +% +% SD representations have alpha < beta - 1 +% +% alpha = ceil(beta/2) minimially redundant +% alpha = beta -1 maximally redundant (rho = 1) +% alpha = (beta-1)/2 nonredundant +% alpha > beta - 1 over-redundant +% +rho = 2/3; +% Calculation of max digit set +alpha = rho*(beta-1); +% Da contains digit set +q = []; +for i = -alpha:alpha + q = [q; i]; +end +% 4r(i-1)/D values +hold on +% figure(1) +grid off +for i = 1:length(q) + x = -rho+q(i):ulp:rho+q(i); + % Plot redundancy (overlap) Positive + z = [rho+q(i),rho+q(i)]; + y = [x(length(x))-q(i),0]; + % Plot redundancy (overlap) Negative + if (i ~= length(q)) + w = [-rho+q(i+1)-q(i+1),0]; + u = [-rho+q(i+1),-rho+q(i+1)]; + % plot(u,w,'b') + end + % plot(x,x-q(i)) + % plot(z,y,'r') + +end +% title('Robertson Diagram for Radix-4 SRT Divison') + +% +% Plot Atkins P-D plot +% Normalized Floating Point [Dmin,Dmax] = [1,2] +% Normalized Fixed Point [Dmin, Dmax] =[1/2,1] +% +Dmin = Dminimum; +Dmax = Dmaximum; +for i = 1:length(q) + D = Dmin:ulp:Dmax; + P1 = (rho+q(i))*D; + P2 = (-rho+q(i))*D; + hold on + p1 = plot(D,P1,'b'); + p2 = plot(D,P2,'r'); + axis([Dmin Dmax -beta*rho*Dmaximum beta*rho*Dmaximum]) + xticks(D) + p1.LineWidth = 2.0; + p2.LineWidth = 2.0; +end + +% Let's make x axis binary +j = []; +for i=1:length(D) + j = [j disp_bin(D(i), 1, 4)]; +end +yk = []; +yk2 = []; +for i=-2.5:0.5:2.5; + yk = [yk disp_bin(i, 3, 4)]; + yk2 = [yk2 i]; +end +xtickangle(90) +xticklabels(j) +yticklabels(yk) + +Np = 4; +Nd = 4; +Dmin = Dminimum; +Dmax = Dmaximum; +ulpd = 2^(-Nd); +ulpp = 2^(-Np); + +% Let's draw allow points on PD plot +% Positive Portions +index = 1; +i = 0:ulpp:rho*beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k'); +end + +j = Dmin:ulpd:Dmax; +for i = 0:ulpp:rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k'); +end + +% Negative Portions +index = 1; +i = 0:-ulpp:rho*-beta*Dmaximum; +for j = Dmin:ulpd:Dmax + plot(j*ones(1,length(i)),i,'k'); +end + +j = Dmin:ulpd:Dmax; +for i = 0:-ulpp:-rho*beta*Dmaximum + plot(j,i*ones(length(j)),'k'); +end + +% Labels and Printing +xlh = xlabel(['Divisor (d)']); +xlh.Position(2) = xlh.Position(2) - 0.1; +%xlh.FontSize = 18; +ylh = ylabel(['P = 4 \cdot w_i']); +ylh.Position(1) = ylh.Position(1)-0.02; +%ylh.FontSize = 18; + +% Containment Values (placed manually although not bad) +m2 = [3/4 7/8 15/16 1.0 9/8 19/16 5/4 6/4 6/4]; +m1 = [1/4 1/4 1/4 1/4 3/8 3/8 1/2 1/2 1/2]; +m0 = [-1/4 -3/8 -3/8 -3/8 -1/2 -1/2 -1/2 -1/2 -1/2]; +m1b = [-13/16 -15/16 -1 -9/8 -5/4 -5/4 -11/8 -6/4 -6/4]; +x2 = Dmin:ulpd:Dmax; +s2 = stairs(x2, m2); +s2.Color = '#8f08d1'; +s2.LineWidth = 3.0; +s1 = stairs(x2, m1); +s1.Color = '#8f08d1'; +s1.LineWidth = 3.0; +s0 = stairs(x2, m0); +s0.Color = '#8f08d1'; +s0.LineWidth = 3.0; +s1b = stairs(x2, m1b); +s1b.Color = '#8f08d1'; +s1b.LineWidth = 3.0; + +% Place manually Quotient (ugh) +j = Dmin+ulpd/2:ulpd:Dmax; +i = rho*beta*Dmaximum-ulpp:-ulpp:-rho*beta*Dmaximum; + +% 1 +text(j(1), i(1), '2') +text(j(1), i(2), '2') +text(j(1), i(3), '2') +text(j(1), i(4), '2') +text(j(1), i(5), '2') +text(j(1), i(6), '2') +text(j(1), i(7), '2') +text(j(1), i(8), '2') +text(j(1), i(9), '2') +text(j(1), i(10), '2') +text(j(1), i(11), '2') +text(j(1), i(12), '2') +text(j(1), i(13), '2') +text(j(1), i(14), '2') +text(j(1), i(15), '2') +text(j(1), i(16), '2') +text(j(1), i(17), '2') +text(j(1), i(18), '2') +text(j(1), i(19), '2') +text(j(1), i(20), '2') +text(j(1), i(21), '2') +text(j(1), i(22), '2') +text(j(1), i(23), '2') +text(j(1), i(24), '2') +text(j(1), i(25), '2') +text(j(1), i(26), '2') +text(j(1), i(27), '2') +text(j(1), i(28), '2') +text(j(1), i(29), '2') +text(j(1), i(30), '2') +text(j(1), i(31), '1') +text(j(1), i(32), '1') +text(j(1), i(33), '1') +text(j(1), i(34), '1') +text(j(1), i(35), '1') +text(j(1), i(36), '1') +text(j(1), i(37), '1') +text(j(1), i(38), '1') +text(j(1), i(39), '0') +text(j(1), i(40), '0') +text(j(1), i(41), '0') +text(j(1), i(42), '0') + +text(j(1), i(43), '0') +text(j(1), i(44), '0') +text(j(1), i(45), '0') +text(j(1), i(46), '0') +text(j(1), i(47), '-1') +text(j(1), i(48), '-1') +text(j(1), i(49), '-1') +text(j(1), i(50), '-1') +text(j(1), i(51), '-1') +text(j(1), i(52), '-1') +text(j(1), i(53), '-1') +text(j(1), i(54), '-1') +text(j(1), i(55), '-1') +text(j(1), i(56), '-2') +text(j(1), i(57), '-2') +text(j(1), i(58), '-2') +text(j(1), i(59), '-2') +text(j(1), i(60), '-2') +text(j(1), i(61), '-2') +text(j(1), i(62), '-2') +text(j(1), i(63), '-2') +text(j(1), i(64), '-2') +text(j(1), i(65), '-2') +text(j(1), i(66), '-2') +text(j(1), i(67), '-2') +text(j(1), i(68), '-2') +text(j(1), i(69), '-2') +text(j(1), i(70), '-2') +text(j(1), i(71), '-2') +text(j(1), i(72), '-2') +text(j(1), i(73), '-2') +text(j(1), i(74), '-2') +text(j(1), i(75), '-2') +text(j(1), i(76), '-2') +text(j(1), i(77), '-2') +text(j(1), i(78), '-2') +text(j(1), i(79), '-2') +text(j(1), i(80), '-2') +text(j(1), i(81), '-2') +text(j(1), i(82), '-2') +text(j(1), i(83), '-2') +text(j(1), i(84), '-2') + +text(j(2), i(1), '2') +text(j(2), i(2), '2') +text(j(2), i(3), '2') +text(j(2), i(4), '2') +text(j(2), i(5), '2') +text(j(2), i(6), '2') +text(j(2), i(7), '2') +text(j(2), i(8), '2') +text(j(2), i(9), '2') +text(j(2), i(10), '2') +text(j(2), i(11), '2') +text(j(2), i(12), '2') +text(j(2), i(13), '2') +text(j(2), i(14), '2') +text(j(2), i(15), '2') +text(j(2), i(16), '2') +text(j(2), i(17), '2') +text(j(2), i(18), '2') +text(j(2), i(19), '2') +text(j(2), i(20), '2') +text(j(2), i(21), '2') +text(j(2), i(22), '2') +text(j(2), i(23), '2') +text(j(2), i(24), '2') +text(j(2), i(25), '2') +text(j(2), i(26), '2') +text(j(2), i(27), '2') +text(j(2), i(28), '2') +text(j(2), i(29), '1') +text(j(2), i(30), '1') +text(j(2), i(31), '1') +text(j(2), i(32), '1') +text(j(2), i(33), '1') +text(j(2), i(34), '1') +text(j(2), i(35), '1') +text(j(2), i(36), '1') +text(j(2), i(37), '1') +text(j(2), i(38), '1') +text(j(2), i(39), '0') +text(j(2), i(40), '0') +text(j(2), i(41), '0') +text(j(2), i(42), '0') + +text(j(2), i(43), '0') +text(j(2), i(44), '0') +text(j(2), i(45), '0') +text(j(2), i(46), '0') +text(j(2), i(47), '0') +text(j(2), i(48), '0') +text(j(2), i(49), '-1') +text(j(2), i(50), '-1') +text(j(2), i(51), '-1') +text(j(2), i(52), '-1') +text(j(2), i(53), '-1') +text(j(2), i(54), '-1') +text(j(2), i(55), '-1') +text(j(2), i(56), '-1') +text(j(2), i(57), '-1') +text(j(2), i(58), '-2') +text(j(2), i(59), '-2') +text(j(2), i(60), '-2') +text(j(2), i(61), '-2') +text(j(2), i(62), '-2') +text(j(2), i(63), '-2') +text(j(2), i(64), '-2') +text(j(2), i(65), '-2') +text(j(2), i(66), '-2') +text(j(2), i(67), '-2') +text(j(2), i(68), '-2') +text(j(2), i(69), '-2') +text(j(2), i(70), '-2') +text(j(2), i(71), '-2') +text(j(2), i(72), '-2') +text(j(2), i(73), '-2') +text(j(2), i(74), '-2') +text(j(2), i(75), '-2') +text(j(2), i(76), '-2') +text(j(2), i(77), '-2') +text(j(2), i(78), '-2') +text(j(2), i(79), '-2') +text(j(2), i(80), '-2') +text(j(2), i(81), '-2') +text(j(2), i(82), '-2') +text(j(2), i(83), '-2') +text(j(2), i(84), '-2') + +% 3 +text(j(3), i(1), '2') +text(j(3), i(2), '2') +text(j(3), i(3), '2') +text(j(3), i(4), '2') +text(j(3), i(5), '2') +text(j(3), i(6), '2') +text(j(3), i(7), '2') +text(j(3), i(8), '2') +text(j(3), i(9), '2') +text(j(3), i(10), '2') +text(j(3), i(11), '2') +text(j(3), i(12), '2') +text(j(3), i(13), '2') +text(j(3), i(14), '2') +text(j(3), i(15), '2') +text(j(3), i(16), '2') +text(j(3), i(17), '2') +text(j(3), i(18), '2') +text(j(3), i(19), '2') +text(j(3), i(20), '2') +text(j(3), i(21), '2') +text(j(3), i(22), '2') +text(j(3), i(23), '2') +text(j(3), i(24), '2') +text(j(3), i(25), '2') +text(j(3), i(26), '2') +text(j(3), i(27), '2') +text(j(3), i(28), '1') +text(j(3), i(29), '1') +text(j(3), i(30), '1') +text(j(3), i(31), '1') +text(j(3), i(32), '1') +text(j(3), i(33), '1') +text(j(3), i(34), '1') +text(j(3), i(35), '1') +text(j(3), i(36), '1') +text(j(3), i(37), '1') +text(j(3), i(38), '1') +text(j(3), i(39), '0') +text(j(3), i(40), '0') +text(j(3), i(41), '0') +text(j(3), i(42), '0') + +text(j(3), i(43), '0') +text(j(3), i(44), '0') +text(j(3), i(45), '0') +text(j(3), i(46), '0') +text(j(3), i(47), '0') +text(j(3), i(48), '0') +text(j(3), i(49), '-1') +text(j(3), i(50), '-1') +text(j(3), i(51), '-1') +text(j(3), i(52), '-1') +text(j(3), i(53), '-1') +text(j(3), i(54), '-1') +text(j(3), i(55), '-1') +text(j(3), i(56), '-1') +text(j(3), i(57), '-1') +text(j(3), i(58), '-1') +text(j(3), i(59), '-2') +text(j(3), i(60), '-2') +text(j(3), i(61), '-2') +text(j(3), i(62), '-2') +text(j(3), i(63), '-2') +text(j(3), i(64), '-2') +text(j(3), i(65), '-2') +text(j(3), i(66), '-2') +text(j(3), i(67), '-2') +text(j(3), i(68), '-2') +text(j(3), i(69), '-2') +text(j(3), i(70), '-2') +text(j(3), i(71), '-2') +text(j(3), i(72), '-2') +text(j(3), i(73), '-2') +text(j(3), i(74), '-2') +text(j(3), i(75), '-2') +text(j(3), i(76), '-2') +text(j(3), i(77), '-2') +text(j(3), i(78), '-2') +text(j(3), i(79), '-2') +text(j(3), i(80), '-2') +text(j(3), i(81), '-2') +text(j(3), i(82), '-2') +text(j(3), i(83), '-2') +text(j(3), i(84), '-2') + +% 4 +text(j(4), i(1), '2') +text(j(4), i(2), '2') +text(j(4), i(3), '2') +text(j(4), i(4), '2') +text(j(4), i(5), '2') +text(j(4), i(6), '2') +text(j(4), i(7), '2') +text(j(4), i(8), '2') +text(j(4), i(9), '2') +text(j(4), i(10), '2') +text(j(4), i(11), '2') +text(j(4), i(12), '2') +text(j(4), i(13), '2') +text(j(4), i(14), '2') +text(j(4), i(15), '2') +text(j(4), i(16), '2') +text(j(4), i(17), '2') +text(j(4), i(18), '2') +text(j(4), i(19), '2') +text(j(4), i(20), '2') +text(j(4), i(21), '2') +text(j(4), i(22), '2') +text(j(4), i(23), '2') +text(j(4), i(24), '2') +text(j(4), i(25), '2') +text(j(4), i(26), '2') +text(j(4), i(27), '1') +text(j(4), i(28), '1') +text(j(4), i(29), '1') +text(j(4), i(30), '1') +text(j(4), i(31), '1') +text(j(4), i(32), '1') +text(j(4), i(33), '1') +text(j(4), i(34), '1') +text(j(4), i(35), '1') +text(j(4), i(36), '1') +text(j(4), i(37), '1') +text(j(4), i(38), '1') +text(j(4), i(39), '0') +text(j(4), i(40), '0') +text(j(4), i(41), '0') +text(j(4), i(42), '0') + +text(j(4), i(43), '0') +text(j(4), i(44), '0') +text(j(4), i(45), '0') +text(j(4), i(46), '0') +text(j(4), i(47), '0') +text(j(4), i(48), '0') +text(j(4), i(49), '-1') +text(j(4), i(50), '-1') +text(j(4), i(51), '-1') +text(j(4), i(52), '-1') +text(j(4), i(53), '-1') +text(j(4), i(54), '-1') +text(j(4), i(55), '-1') +text(j(4), i(56), '-1') +text(j(4), i(57), '-1') +text(j(4), i(58), '-1') +text(j(4), i(59), '-1') +text(j(4), i(60), '-1') +text(j(4), i(61), '-2') +text(j(4), i(62), '-2') +text(j(4), i(63), '-2') +text(j(4), i(64), '-2') +text(j(4), i(65), '-2') +text(j(4), i(66), '-2') +text(j(4), i(67), '-2') +text(j(4), i(68), '-2') +text(j(4), i(69), '-2') +text(j(4), i(70), '-2') +text(j(4), i(71), '-2') +text(j(4), i(72), '-2') +text(j(4), i(73), '-2') +text(j(4), i(74), '-2') +text(j(4), i(75), '-2') +text(j(4), i(76), '-2') +text(j(4), i(77), '-2') +text(j(4), i(78), '-2') +text(j(4), i(79), '-2') +text(j(4), i(80), '-2') +text(j(4), i(81), '-2') +text(j(4), i(82), '-2') +text(j(4), i(83), '-2') +text(j(4), i(84), '-2') + +% 5 +text(j(5), i(1), '2') +text(j(5), i(2), '2') +text(j(5), i(3), '2') +text(j(5), i(4), '2') +text(j(5), i(5), '2') +text(j(5), i(6), '2') +text(j(5), i(7), '2') +text(j(5), i(8), '2') +text(j(5), i(9), '2') +text(j(5), i(10), '2') +text(j(5), i(11), '2') +text(j(5), i(12), '2') +text(j(5), i(13), '2') +text(j(5), i(14), '2') +text(j(5), i(15), '2') +text(j(5), i(16), '2') +text(j(5), i(17), '2') +text(j(5), i(18), '2') +text(j(5), i(19), '2') +text(j(5), i(20), '2') +text(j(5), i(21), '2') +text(j(5), i(22), '2') +text(j(5), i(23), '2') +text(j(5), i(24), '2') +text(j(5), i(25), '1') +text(j(5), i(26), '1') +text(j(5), i(27), '1') +text(j(5), i(28), '1') +text(j(5), i(29), '1') +text(j(5), i(30), '1') +text(j(5), i(31), '1') +text(j(5), i(32), '1') +text(j(5), i(33), '1') +text(j(5), i(34), '1') +text(j(5), i(35), '1') +text(j(5), i(36), '1') +text(j(5), i(37), '0') +text(j(5), i(38), '0') +text(j(5), i(39), '0') +text(j(5), i(40), '0') +text(j(5), i(41), '0') +text(j(5), i(42), '0') + +text(j(5), i(43), '0') +text(j(5), i(44), '0') +text(j(5), i(45), '0') +text(j(5), i(46), '0') +text(j(5), i(47), '0') +text(j(5), i(48), '0') +text(j(5), i(49), '0') +text(j(5), i(50), '0') +text(j(5), i(51), '-1') +text(j(5), i(52), '-1') +text(j(5), i(53), '-1') +text(j(5), i(54), '-1') +text(j(5), i(55), '-1') +text(j(5), i(56), '-1') +text(j(5), i(57), '-1') +text(j(5), i(58), '-1') +text(j(5), i(59), '-1') +text(j(5), i(60), '-1') +text(j(5), i(61), '-1') +text(j(5), i(62), '-1') +text(j(5), i(63), '-2') +text(j(5), i(64), '-2') +text(j(5), i(65), '-2') +text(j(5), i(66), '-2') +text(j(5), i(67), '-2') +text(j(5), i(68), '-2') +text(j(5), i(69), '-2') +text(j(5), i(70), '-2') +text(j(5), i(71), '-2') +text(j(5), i(72), '-2') +text(j(5), i(73), '-2') +text(j(5), i(74), '-2') +text(j(5), i(75), '-2') +text(j(5), i(76), '-2') +text(j(5), i(77), '-2') +text(j(5), i(78), '-2') +text(j(5), i(79), '-2') +text(j(5), i(80), '-2') +text(j(5), i(81), '-2') +text(j(5), i(82), '-2') +text(j(5), i(83), '-2') +text(j(5), i(84), '-2') + +% 6 +text(j(6), i(1), '2') +text(j(6), i(2), '2') +text(j(6), i(3), '2') +text(j(6), i(4), '2') +text(j(6), i(5), '2') +text(j(6), i(6), '2') +text(j(6), i(7), '2') +text(j(6), i(8), '2') +text(j(6), i(9), '2') +text(j(6), i(10), '2') +text(j(6), i(11), '2') +text(j(6), i(12), '2') +text(j(6), i(13), '2') +text(j(6), i(14), '2') +text(j(6), i(15), '2') +text(j(6), i(16), '2') +text(j(6), i(17), '2') +text(j(6), i(18), '2') +text(j(6), i(19), '2') +text(j(6), i(20), '2') +text(j(6), i(21), '2') +text(j(6), i(22), '2') +text(j(6), i(23), '2') +text(j(6), i(24), '1') +text(j(6), i(25), '1') +text(j(6), i(26), '1') +text(j(6), i(27), '1') +text(j(6), i(28), '1') +text(j(6), i(29), '1') +text(j(6), i(30), '1') +text(j(6), i(31), '1') +text(j(6), i(32), '1') +text(j(6), i(33), '1') +text(j(6), i(34), '1') +text(j(6), i(35), '1') +text(j(6), i(36), '1') +text(j(6), i(37), '0') +text(j(6), i(38), '0') +text(j(6), i(39), '0') +text(j(6), i(40), '0') +text(j(6), i(41), '0') +text(j(6), i(42), '0') + +text(j(6), i(43), '0') +text(j(6), i(44), '0') +text(j(6), i(45), '0') +text(j(6), i(46), '0') +text(j(6), i(47), '0') +text(j(6), i(48), '0') +text(j(6), i(49), '0') +text(j(6), i(50), '0') +text(j(6), i(51), '-1') +text(j(6), i(52), '-1') +text(j(6), i(53), '-1') +text(j(6), i(54), '-1') +text(j(6), i(55), '-1') +text(j(6), i(56), '-1') +text(j(6), i(57), '-1') +text(j(6), i(58), '-1') +text(j(6), i(59), '-1') +text(j(6), i(60), '-1') +text(j(6), i(61), '-1') +text(j(6), i(62), '-1') +text(j(6), i(63), '-2') +text(j(6), i(64), '-2') +text(j(6), i(65), '-2') +text(j(6), i(66), '-2') +text(j(6), i(67), '-2') +text(j(6), i(68), '-2') +text(j(6), i(69), '-2') +text(j(6), i(70), '-2') +text(j(6), i(71), '-2') +text(j(6), i(72), '-2') +text(j(6), i(73), '-2') +text(j(6), i(74), '-2') +text(j(6), i(75), '-2') +text(j(6), i(76), '-2') +text(j(6), i(77), '-2') +text(j(6), i(78), '-2') +text(j(6), i(79), '-2') +text(j(6), i(80), '-2') +text(j(6), i(81), '-2') +text(j(6), i(82), '-2') +text(j(6), i(83), '-2') +text(j(6), i(84), '-2') + +% 7 +text(j(7), i(1), '2') +text(j(7), i(2), '2') +text(j(7), i(3), '2') +text(j(7), i(4), '2') +text(j(7), i(5), '2') +text(j(7), i(6), '2') +text(j(7), i(7), '2') +text(j(7), i(8), '2') +text(j(7), i(9), '2') +text(j(7), i(10), '2') +text(j(7), i(11), '2') +text(j(7), i(12), '2') +text(j(7), i(13), '2') +text(j(7), i(14), '2') +text(j(7), i(15), '2') +text(j(7), i(16), '2') +text(j(7), i(17), '2') +text(j(7), i(18), '2') +text(j(7), i(19), '2') +text(j(7), i(20), '2') +text(j(7), i(21), '2') +text(j(7), i(22), '2') +text(j(7), i(23), '1') +text(j(7), i(24), '1') +text(j(7), i(25), '1') +text(j(7), i(26), '1') +text(j(7), i(27), '1') +text(j(7), i(28), '1') +text(j(7), i(29), '1') +text(j(7), i(30), '1') +text(j(7), i(31), '1') +text(j(7), i(32), '1') +text(j(7), i(33), '1') +text(j(7), i(34), '1') +text(j(7), i(35), '0') +text(j(7), i(36), '0') +text(j(7), i(37), '0') +text(j(7), i(38), '0') +text(j(7), i(39), '0') +text(j(7), i(40), '0') +text(j(7), i(41), '0') +text(j(7), i(42), '0') + +text(j(7), i(43), '0') +text(j(7), i(44), '0') +text(j(7), i(45), '0') +text(j(7), i(46), '0') +text(j(7), i(47), '0') +text(j(7), i(48), '0') +text(j(7), i(49), '0') +text(j(7), i(50), '0') +text(j(7), i(51), '-1') +text(j(7), i(52), '-1') +text(j(7), i(53), '-1') +text(j(7), i(54), '-1') +text(j(7), i(55), '-1') +text(j(7), i(56), '-1') +text(j(7), i(57), '-1') +text(j(7), i(58), '-1') +text(j(7), i(59), '-1') +text(j(7), i(60), '-1') +text(j(7), i(61), '-1') +text(j(7), i(62), '-1') +text(j(7), i(63), '-1') +text(j(7), i(64), '-1') +text(j(7), i(65), '-2') +text(j(7), i(66), '-2') +text(j(7), i(67), '-2') +text(j(7), i(68), '-2') +text(j(7), i(69), '-2') +text(j(7), i(70), '-2') +text(j(7), i(71), '-2') +text(j(7), i(72), '-2') +text(j(7), i(73), '-2') +text(j(7), i(74), '-2') +text(j(7), i(75), '-2') +text(j(7), i(76), '-2') +text(j(7), i(77), '-2') +text(j(7), i(78), '-2') +text(j(7), i(79), '-2') +text(j(7), i(80), '-2') +text(j(7), i(81), '-2') +text(j(7), i(82), '-2') +text(j(7), i(83), '-2') +text(j(7), i(84), '-2') + +% 8 +text(j(8), i(1), '2') +text(j(8), i(2), '2') +text(j(8), i(3), '2') +text(j(8), i(4), '2') +text(j(8), i(5), '2') +text(j(8), i(6), '2') +text(j(8), i(7), '2') +text(j(8), i(8), '2') +text(j(8), i(9), '2') +text(j(8), i(10), '2') +text(j(8), i(11), '2') +text(j(8), i(12), '2') +text(j(8), i(13), '2') +text(j(8), i(14), '2') +text(j(8), i(15), '2') +text(j(8), i(16), '2') +text(j(8), i(17), '2') +text(j(8), i(18), '2') +text(j(8), i(19), '1') +text(j(8), i(20), '1') +text(j(8), i(21), '1') +text(j(8), i(22), '1') +text(j(8), i(23), '1') +text(j(8), i(24), '1') +text(j(8), i(25), '1') +text(j(8), i(26), '1') +text(j(8), i(27), '1') +text(j(8), i(28), '1') +text(j(8), i(29), '1') +text(j(8), i(30), '1') +text(j(8), i(31), '1') +text(j(8), i(32), '1') +text(j(8), i(33), '1') +text(j(8), i(34), '1') +text(j(8), i(35), '0') +text(j(8), i(36), '0') +text(j(8), i(37), '0') +text(j(8), i(38), '0') +text(j(8), i(39), '0') +text(j(8), i(40), '0') +text(j(8), i(41), '0') +text(j(8), i(42), '0') + +text(j(8), i(43), '0') +text(j(8), i(44), '0') +text(j(8), i(45), '0') +text(j(8), i(46), '0') +text(j(8), i(47), '0') +text(j(8), i(48), '0') +text(j(8), i(49), '0') +text(j(8), i(50), '0') +text(j(8), i(51), '-1') +text(j(8), i(52), '-1') +text(j(8), i(53), '-1') +text(j(8), i(54), '-1') +text(j(8), i(55), '-1') +text(j(8), i(56), '-1') +text(j(8), i(57), '-1') +text(j(8), i(58), '-1') +text(j(8), i(59), '-1') +text(j(8), i(60), '-1') +text(j(8), i(61), '-1') +text(j(8), i(62), '-1') +text(j(8), i(63), '-1') +text(j(8), i(64), '-1') +text(j(8), i(65), '-1') +text(j(8), i(66), '-1') +text(j(8), i(67), '-2') +text(j(8), i(68), '-2') +text(j(8), i(69), '-2') +text(j(8), i(70), '-2') +text(j(8), i(71), '-2') +text(j(8), i(72), '-2') +text(j(8), i(73), '-2') +text(j(8), i(74), '-2') +text(j(8), i(75), '-2') +text(j(8), i(76), '-2') +text(j(8), i(77), '-2') +text(j(8), i(78), '-2') +text(j(8), i(79), '-2') +text(j(8), i(80), '-2') +text(j(8), i(81), '-2') +text(j(8), i(82), '-2') +text(j(8), i(83), '-2') +text(j(8), i(84), '-2') + +orient('landscape') +print -dpng 'pd_csa.png' + + + + + diff --git a/pipelined/srt/stine/srt4div b/pipelined/srt/stine/srt4div new file mode 100755 index 000000000..a780abd4b Binary files /dev/null and b/pipelined/srt/stine/srt4div differ diff --git a/pipelined/srt/stine/srt4div.c b/pipelined/srt/stine/srt4div.c new file mode 100755 index 000000000..65fdac53b --- /dev/null +++ b/pipelined/srt/stine/srt4div.c @@ -0,0 +1,226 @@ +#include "disp.h" +#include + +// QSLC is for division by recuerrence for +// r=4 using a CPA - See Table 5.9 EL +int qslc (double prem, double d) { + + int q; + + // For Debugging + printf("d --> %lg\n", d); + printf("rw --> %lg\n", prem); + + if ((d>=8.0)&&(d<9.0)) { + if (prem>=6.0) + q = 2; + else if (prem>=2.0) + q = 1; + else if (prem>=-2.0) + q = 0; + else if (prem >= -6) + q = -1; + else + q = -2; + return q; + } + + if ((d>=9.0)&&(d<10.0)) { + if (prem>=7) + q = 2; + else if (prem>=2.0) + q = 1; + else if (prem>=-2.0) + q = 0; + else if (prem >= 7.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=10.0)&&(d<11.0)) { + if (prem>=8.0) + q = 2; + else if (prem>=2.0) + q = 1; + else if (prem>=-2.0) + q = 0; + else if (prem >= -8.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=11.0)&&(d<12.0)) { + if (prem>=8.0) + q = 2; + else if (prem>=2.0) + q = 1; + else if (prem>=-2.0) + q = 0; + else if (prem >= -8.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=12.0)&&(d<13.0)) { + if (prem>=10.0) + q = 2; + else if (prem>=4.0) + q = 1; + else if (prem>=-4.0) + q = 0; + else if (prem >= -10.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=13.0)&&(d<14.0)) { + if (prem>=10.0) + q = 2; + else if (prem>=4.0) + q = 1; + else if (prem>=-4.0) + q = 0; + else if (prem >= -10.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=14.0)&&(d<15.0)) { + if (prem>=10.0) + q = 2; + else if (prem>=4.0) + q = 1; + else if (prem>=-4.0) + q = 0; + else if (prem >= -10.0) + q = -1; + else + q = -2; + return q; + } + + if ((d>=15.0)&&(d<16.0)) { + if (prem>=12.0) + q = 2; + else if (prem>=4.0) + q = 1; + else if (prem>=-4.0) + q = 0; + else if (prem >= -12.0) + q = -1; + else + q = -2; + return q; + } + +} + + +/* + This routine performs a radix-4 SRT division + algorithm. The user inputs the numerator, the denominator, + and the number of iterations. It assumes that 0.5 <= D < 1. + +*/ + +int main(int argc, char* argv[]) { + + double P, N, D, Q, RQ, RD, RREM, scale; + int q; + int num_iter, i; + int prec; + int radix = 4; + + if (argc < 5) { + fprintf(stderr, + "Usage: %s numerator denominator num_iterations prec\n", + argv[0]); + exit(1); + } + sscanf(argv[1],"%lg", &N); + sscanf(argv[2],"%lg", &D); + sscanf(argv[3],"%d", &num_iter); + sscanf(argv[4],"%d", &prec); + // Round to precision + N = rne(N, prec); + D = rne(D, prec); + printf("N = "); + disp_bin(N, 3, prec, stdout); + printf("\n"); + printf("D = "); + disp_bin(D, 3, prec, stdout); + printf("\n"); + + Q = 0; + P = N * pow(2.0, -log2(radix)); + printf("N = %lg, D = %lg, N/D = %lg, num_iter = %d \n\n", + N, D, N/D, num_iter); + for (scale = 1, i = 0; i < num_iter; i++) { + // Shift by r + scale = scale * pow(2.0, -log2(radix)); + // (4*P)*8 because of footnote in Table 5.9, page 296 EL + // i.e., real value = shown value / 8 + // D*16 since we use 4 bits of D (1 bit known) + q = qslc(flr((radix * P) * 8, 3), D*16); + printf("4*W[n] = "); + disp_bin(radix*P, 3, prec, stdout); + printf("\n"); + printf("q*D = "); + disp_bin(q*D, 3, prec, stdout); + printf("\n"); + printf("W[n+1] = "); + disp_bin(P ,3, prec, stdout); + printf("\n"); + // Recurrence + P = radix * P - q * D; + // OTFC + Q = Q + q * scale; + printf("i = %d, q = %d, Q = %1.18lf, W = %1.18lf\n", i, q, Q, P); + printf("i = %d, q = %d", i, q); + printf(", Q = "); + disp_bin(Q, 3, prec, stdout); + printf(", W = "); + disp_bin(P, 3, prec, stdout); + printf("\n\n"); + } + // Is shifted partial remainder negative? + if (P < 0) { + Q = Q - pow(2.0, -prec); + P = P + D; + printf("\nCorrecting Negative Remainder\n"); + printf("Q = %1.18lf, W = %1.18lf\n", Q, P); + printf("Q = "); + disp_bin(Q, 3, prec, stdout); + printf(", W = "); + disp_bin(P, 3, prec, stdout); + printf("\n"); + } + + // Output Results + RQ = flr(N/D, prec); + // Since q_{computed} = q / radix, multiply by radix + RD = Q * radix; + printf("true = %1.18lf, computed = %1.18lf, \n", RQ, RD); + printf("true = "); + disp_bin(RQ, 3, prec, stdout); + printf(", computed = "); + disp_bin(RD, 3, prec, stdout); + printf("\n\n"); + printf("REM = %1.18lf \n", P); + printf("REM = "); + disp_bin(P, 3, prec, stdout); + printf("\n\n"); + + return 0; + +} diff --git a/pipelined/srt/stine/test_iter128.sv b/pipelined/srt/stine/test_iter128.sv new file mode 100644 index 000000000..c2f8f5a73 --- /dev/null +++ b/pipelined/srt/stine/test_iter128.sv @@ -0,0 +1,79 @@ +`include "idiv-config.vh" + +module tb; + + logic [127:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [127:0] Q; + logic [127:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [127:0] Ncomp; + logic [127:0] Dcomp; + logic [127:0] Qcomp; + logic [127:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter128_unsigned.out"); + end + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b0; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 128'h0; + #0 D = 128'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = {$urandom(), $urandom(), $urandom(), $urandom()}; + D = {$urandom(), $urandom(), $urandom(), $urandom()}; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (2) + @(posedge clk); + start <= 1'b0; + repeat (41) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = Ncomp/Dcomp; + Rcomp = Ncomp%Dcomp; + vectornum = vectornum + 1; + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end // for (i=0; i<2, i=i+1) + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb diff --git a/pipelined/srt/stine/test_iter128S.sv b/pipelined/srt/stine/test_iter128S.sv new file mode 100644 index 000000000..7757041f6 --- /dev/null +++ b/pipelined/srt/stine/test_iter128S.sv @@ -0,0 +1,90 @@ +`include "idiv-config.vh" + +module tb; + + logic [127:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [127:0] Q; + logic [127:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [31:0] rnd1; + logic [31:0] rnd2; + logic [127:0] Ncomp; + logic [127:0] Dcomp; + logic [127:0] Qcomp; + logic [127:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(128) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter128_signed.out"); + end + + /* + // VCD generation for power estimation + initial + begin + $dumpfile("iter128_signed.vcd"); + $dumpvars (0,tb.dut); + end + */ + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b1; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 128'h0; + #0 D = 128'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = {$urandom(), $urandom(), $urandom(), $urandom()}; + D = {$urandom(), $urandom(), $urandom(), $urandom()}; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (1) + @(posedge clk); + start <= 1'b0; + repeat (65) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = $signed(Ncomp)/$signed(Dcomp); + Rcomp = $signed(Ncomp)%$signed(Dcomp); + vectornum = vectornum + 1; + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb diff --git a/pipelined/srt/stine/test_iter32.sv b/pipelined/srt/stine/test_iter32.sv new file mode 100755 index 000000000..6590b5a16 --- /dev/null +++ b/pipelined/srt/stine/test_iter32.sv @@ -0,0 +1,85 @@ +`include "idiv-config.vh" + +module tb; + + logic [31:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [31:0] Q; + logic [31:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [31:0] Ncomp; + logic [31:0] Dcomp; + logic [31:0] Qcomp; + logic [31:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter32_unsigned.out"); + end + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b0; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 32'h0; + #0 D = 32'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = $urandom; + D = $urandom; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (2) + @(posedge clk); + start <= 1'b0; + repeat (41) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = Ncomp/Dcomp; + Rcomp = Ncomp%Dcomp; + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + vectornum = vectornum + 1; + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end // for (i=0; i<2, i=i+1) + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb + + + + + + diff --git a/pipelined/srt/stine/test_iter32S.sv b/pipelined/srt/stine/test_iter32S.sv new file mode 100644 index 000000000..e3b271b4e --- /dev/null +++ b/pipelined/srt/stine/test_iter32S.sv @@ -0,0 +1,79 @@ +`include "idiv-config.vh" + +module tb; + + logic [31:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [31:0] Q; + logic [31:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [31:0] Ncomp; + logic [31:0] Dcomp; + logic [31:0] Qcomp; + logic [31:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(32) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter32_signed.out"); + end + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b1; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 32'h0; + #0 D = 32'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = $urandom; + D = $urandom; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (2) + @(posedge clk); + start <= 1'b0; + repeat (41) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = $signed(Ncomp)/$signed(Dcomp); + Rcomp = $signed(Ncomp)%$signed(Dcomp); + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + vectornum = vectornum + 1; + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end // for (i=0; i<2, i=i+1) + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb diff --git a/pipelined/srt/stine/test_iter64.sv b/pipelined/srt/stine/test_iter64.sv new file mode 100755 index 000000000..3da85c20a --- /dev/null +++ b/pipelined/srt/stine/test_iter64.sv @@ -0,0 +1,79 @@ +`include "idiv-config.vh" + +module tb; + + logic [63:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [63:0] Q; + logic [63:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [63:0] Ncomp; + logic [63:0] Dcomp; + logic [63:0] Qcomp; + logic [63:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter64_unsigned.out"); + end + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b0; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 64'h0; + #0 D = 64'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = {$urandom(), $urandom()}; + D = {$urandom(), $urandom()}; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (2) + @(posedge clk); + start <= 1'b0; + repeat (41) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = Ncomp/Dcomp; + Rcomp = Ncomp%Dcomp; + vectornum = vectornum + 1; + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end // for (i=0; i<2, i=i+1) + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb diff --git a/pipelined/srt/stine/test_iter64S.sv b/pipelined/srt/stine/test_iter64S.sv new file mode 100644 index 000000000..cdfb573a7 --- /dev/null +++ b/pipelined/srt/stine/test_iter64S.sv @@ -0,0 +1,79 @@ +`include "idiv-config.vh" + +module tb; + + logic [63:0] N, D; + logic clk; + logic reset; + logic start; + logic S; + + logic [63:0] Q; + logic [63:0] rem0; + logic div0; + logic done; + + integer handle3; + integer desc3; + integer i; + + logic [63:0] Ncomp; + logic [63:0] Dcomp; + logic [63:0] Qcomp; + logic [63:0] Rcomp; + + logic [31:0] vectornum; + logic [31:0] errors; + + intdiv #(64) dut (Q, done, rem0, div0, N, D, clk, reset, start, S); + + initial + begin + clk = 1'b0; + forever #5 clk = ~clk; + end + + initial + begin + vectornum = 0; + errors = 0; + handle3 = $fopen("iter64_signed.out"); + end + + always @(posedge clk, posedge reset) + begin + desc3 = handle3; + #0 start = 1'b0; + #0 S = 1'b1; + #0 reset = 1'b1; + #30 reset = 1'b0; + #30 N = 64'h0; + #0 D = 64'h0; + for (i=0; i<`IDIV_TESTS; i=i+1) + begin + N = {$urandom(), $urandom()}; + D = {$urandom(), $urandom()}; + start <= 1'b1; + // Wait 2 cycles (to be sure) + repeat (2) + @(posedge clk); + start <= 1'b0; + repeat (41) + @(posedge clk); + Ncomp = N; + Dcomp = D; + Qcomp = $signed(Ncomp)/$signed(Dcomp); + Rcomp = $signed(Ncomp)%$signed(Dcomp); + if ((Q !== Qcomp)) begin + errors = errors + 1; + end + vectornum = vectornum + 1; + $fdisplay(desc3, "%h %h %h %h || %h %h || %b %b", + N, D, Q, rem0, Qcomp, Rcomp, + (Q==Qcomp), (rem0==Rcomp)); + end // for (i=0; i<2, i=i+1) + $display("%d tests completed, %d errors", vectornum, errors); + $finish; + end + +endmodule // tb diff --git a/pipelined/srt/stine/tmp b/pipelined/srt/stine/tmp new file mode 100644 index 000000000..c7cdf64f8 --- /dev/null +++ b/pipelined/srt/stine/tmp @@ -0,0 +1,1026 @@ + case({D[5:3],Wmsbs}) + 10'b000_0000000: q = 4'b0000; + 10'b000_0000001: q = 4'b0000; + 10'b000_0000010: q = 4'b0000; + 10'b000_0000011: q = 4'b0000; + 10'b000_0000100: q = 4'b0100; + 10'b000_0000101: q = 4'b0100; + 10'b000_0000110: q = 4'b0100; + 10'b000_0000111: q = 4'b0100; + 10'b000_0001000: q = 4'b0100; + 10'b000_0001001: q = 4'b0100; + 10'b000_0001010: q = 4'b0100; + 10'b000_0001011: q = 4'b0100; + 10'b000_0001100: q = 4'b1000; + 10'b000_0001101: q = 4'b1000; + 10'b000_0001110: q = 4'b1000; + 10'b000_0001111: q = 4'b1000; + 10'b000_0010000: q = 4'b1000; + 10'b000_0010001: q = 4'b1000; + 10'b000_0010010: q = 4'b1000; + 10'b000_0010011: q = 4'b1000; + 10'b000_0010100: q = 4'b1000; + 10'b000_0010101: q = 4'b1000; + 10'b000_0010110: q = 4'b1000; + 10'b000_0010111: q = 4'b1000; + 10'b000_0011000: q = 4'b1000; + 10'b000_0011001: q = 4'b1000; + 10'b000_0011010: q = 4'b1000; + 10'b000_0011011: q = 4'b1000; + 10'b000_0011100: q = 4'b1000; + 10'b000_0011101: q = 4'b1000; + 10'b000_0011110: q = 4'b1000; + 10'b000_0011111: q = 4'b1000; + 10'b000_0100000: q = 4'b1000; + 10'b000_0100001: q = 4'b1000; + 10'b000_0100010: q = 4'b1000; + 10'b000_0100011: q = 4'b1000; + 10'b000_0100100: q = 4'b1000; + 10'b000_0100101: q = 4'b1000; + 10'b000_0100110: q = 4'b1000; + 10'b000_0100111: q = 4'b1000; + 10'b000_0101000: q = 4'b1000; + 10'b000_0101001: q = 4'b1000; + 10'b000_0101010: q = 4'b1000; + 10'b000_0101011: q = 4'b1000; + 10'b000_0101100: q = 4'b1000; + 10'b000_0101101: q = 4'b1000; + 10'b000_0101110: q = 4'b1000; + 10'b000_0101111: q = 4'b1000; + 10'b000_0110000: q = 4'b1000; + 10'b000_0110001: q = 4'b1000; + 10'b000_0110010: q = 4'b1000; + 10'b000_0110011: q = 4'b1000; + 10'b000_0110100: q = 4'b1000; + 10'b000_0110101: q = 4'b1000; + 10'b000_0110110: q = 4'b1000; + 10'b000_0110111: q = 4'b1000; + 10'b000_0111000: q = 4'b1000; + 10'b000_0111001: q = 4'b1000; + 10'b000_0111010: q = 4'b1000; + 10'b000_0111011: q = 4'b1000; + 10'b000_0111100: q = 4'b1000; + 10'b000_0111101: q = 4'b1000; + 10'b000_0111110: q = 4'b1000; + 10'b000_0111111: q = 4'b1000; + 10'b000_1000000: q = 4'b0001; + 10'b000_1000001: q = 4'b0001; + 10'b000_1000010: q = 4'b0001; + 10'b000_1000011: q = 4'b0001; + 10'b000_1000100: q = 4'b0001; + 10'b000_1000101: q = 4'b0001; + 10'b000_1000110: q = 4'b0001; + 10'b000_1000111: q = 4'b0001; + 10'b000_1001000: q = 4'b0001; + 10'b000_1001001: q = 4'b0001; + 10'b000_1001010: q = 4'b0001; + 10'b000_1001011: q = 4'b0001; + 10'b000_1001100: q = 4'b0001; + 10'b000_1001101: q = 4'b0001; + 10'b000_1001110: q = 4'b0001; + 10'b000_1001111: q = 4'b0001; + 10'b000_1010000: q = 4'b0001; + 10'b000_1010001: q = 4'b0001; + 10'b000_1010010: q = 4'b0001; + 10'b000_1010011: q = 4'b0001; + 10'b000_1010100: q = 4'b0001; + 10'b000_1010101: q = 4'b0001; + 10'b000_1010110: q = 4'b0001; + 10'b000_1010111: q = 4'b0001; + 10'b000_1011000: q = 4'b0001; + 10'b000_1011001: q = 4'b0001; + 10'b000_1011010: q = 4'b0001; + 10'b000_1011011: q = 4'b0001; + 10'b000_1011100: q = 4'b0001; + 10'b000_1011101: q = 4'b0001; + 10'b000_1011110: q = 4'b0001; + 10'b000_1011111: q = 4'b0001; + 10'b000_1100000: q = 4'b0001; + 10'b000_1100001: q = 4'b0001; + 10'b000_1100010: q = 4'b0001; + 10'b000_1100011: q = 4'b0001; + 10'b000_1100100: q = 4'b0001; + 10'b000_1100101: q = 4'b0001; + 10'b000_1100110: q = 4'b0001; + 10'b000_1100111: q = 4'b0001; + 10'b000_1101000: q = 4'b0001; + 10'b000_1101001: q = 4'b0001; + 10'b000_1101010: q = 4'b0001; + 10'b000_1101011: q = 4'b0001; + 10'b000_1101100: q = 4'b0001; + 10'b000_1101101: q = 4'b0001; + 10'b000_1101110: q = 4'b0001; + 10'b000_1101111: q = 4'b0001; + 10'b000_1110000: q = 4'b0001; + 10'b000_1110001: q = 4'b0001; + 10'b000_1110010: q = 4'b0001; + 10'b000_1110011: q = 4'b0010; + 10'b000_1110100: q = 4'b0010; + 10'b000_1110101: q = 4'b0010; + 10'b000_1110110: q = 4'b0010; + 10'b000_1110111: q = 4'b0010; + 10'b000_1111000: q = 4'b0010; + 10'b000_1111001: q = 4'b0010; + 10'b000_1111010: q = 4'b0010; + 10'b000_1111011: q = 4'b0010; + 10'b000_1111100: q = 4'b0000; + 10'b000_1111101: q = 4'b0000; + 10'b000_1111110: q = 4'b0000; + 10'b000_1111111: q = 4'b0000; + 10'b001_0000000: q = 4'b0000; + 10'b001_0000001: q = 4'b0000; + 10'b001_0000010: q = 4'b0000; + 10'b001_0000011: q = 4'b0000; + 10'b001_0000100: q = 4'b0100; + 10'b001_0000101: q = 4'b0100; + 10'b001_0000110: q = 4'b0100; + 10'b001_0000111: q = 4'b0100; + 10'b001_0001000: q = 4'b0100; + 10'b001_0001001: q = 4'b0100; + 10'b001_0001010: q = 4'b0100; + 10'b001_0001011: q = 4'b0100; + 10'b001_0001100: q = 4'b0100; + 10'b001_0001101: q = 4'b0100; + 10'b001_0001110: q = 4'b1000; + 10'b001_0001111: q = 4'b1000; + 10'b001_0010000: q = 4'b1000; + 10'b001_0010001: q = 4'b1000; + 10'b001_0010010: q = 4'b1000; + 10'b001_0010011: q = 4'b1000; + 10'b001_0010100: q = 4'b1000; + 10'b001_0010101: q = 4'b1000; + 10'b001_0010110: q = 4'b1000; + 10'b001_0010111: q = 4'b1000; + 10'b001_0011000: q = 4'b1000; + 10'b001_0011001: q = 4'b1000; + 10'b001_0011010: q = 4'b1000; + 10'b001_0011011: q = 4'b1000; + 10'b001_0011100: q = 4'b1000; + 10'b001_0011101: q = 4'b1000; + 10'b001_0011110: q = 4'b1000; + 10'b001_0011111: q = 4'b1000; + 10'b001_0100000: q = 4'b1000; + 10'b001_0100001: q = 4'b1000; + 10'b001_0100010: q = 4'b1000; + 10'b001_0100011: q = 4'b1000; + 10'b001_0100100: q = 4'b1000; + 10'b001_0100101: q = 4'b1000; + 10'b001_0100110: q = 4'b1000; + 10'b001_0100111: q = 4'b1000; + 10'b001_0101000: q = 4'b1000; + 10'b001_0101001: q = 4'b1000; + 10'b001_0101010: q = 4'b1000; + 10'b001_0101011: q = 4'b1000; + 10'b001_0101100: q = 4'b1000; + 10'b001_0101101: q = 4'b1000; + 10'b001_0101110: q = 4'b1000; + 10'b001_0101111: q = 4'b1000; + 10'b001_0110000: q = 4'b1000; + 10'b001_0110001: q = 4'b1000; + 10'b001_0110010: q = 4'b1000; + 10'b001_0110011: q = 4'b1000; + 10'b001_0110100: q = 4'b1000; + 10'b001_0110101: q = 4'b1000; + 10'b001_0110110: q = 4'b1000; + 10'b001_0110111: q = 4'b1000; + 10'b001_0111000: q = 4'b1000; + 10'b001_0111001: q = 4'b1000; + 10'b001_0111010: q = 4'b1000; + 10'b001_0111011: q = 4'b1000; + 10'b001_0111100: q = 4'b1000; + 10'b001_0111101: q = 4'b1000; + 10'b001_0111110: q = 4'b1000; + 10'b001_0111111: q = 4'b1000; + 10'b001_1000000: q = 4'b0001; + 10'b001_1000001: q = 4'b0001; + 10'b001_1000010: q = 4'b0001; + 10'b001_1000011: q = 4'b0001; + 10'b001_1000100: q = 4'b0001; + 10'b001_1000101: q = 4'b0001; + 10'b001_1000110: q = 4'b0001; + 10'b001_1000111: q = 4'b0001; + 10'b001_1001000: q = 4'b0001; + 10'b001_1001001: q = 4'b0001; + 10'b001_1001010: q = 4'b0001; + 10'b001_1001011: q = 4'b0001; + 10'b001_1001100: q = 4'b0001; + 10'b001_1001101: q = 4'b0001; + 10'b001_1001110: q = 4'b0001; + 10'b001_1001111: q = 4'b0001; + 10'b001_1010000: q = 4'b0001; + 10'b001_1010001: q = 4'b0001; + 10'b001_1010010: q = 4'b0001; + 10'b001_1010011: q = 4'b0001; + 10'b001_1010100: q = 4'b0001; + 10'b001_1010101: q = 4'b0001; + 10'b001_1010110: q = 4'b0001; + 10'b001_1010111: q = 4'b0001; + 10'b001_1011000: q = 4'b0001; + 10'b001_1011001: q = 4'b0001; + 10'b001_1011010: q = 4'b0001; + 10'b001_1011011: q = 4'b0001; + 10'b001_1011100: q = 4'b0001; + 10'b001_1011101: q = 4'b0001; + 10'b001_1011110: q = 4'b0001; + 10'b001_1011111: q = 4'b0001; + 10'b001_1100000: q = 4'b0001; + 10'b001_1100001: q = 4'b0001; + 10'b001_1100010: q = 4'b0001; + 10'b001_1100011: q = 4'b0001; + 10'b001_1100100: q = 4'b0001; + 10'b001_1100101: q = 4'b0001; + 10'b001_1100110: q = 4'b0001; + 10'b001_1100111: q = 4'b0001; + 10'b001_1101000: q = 4'b0001; + 10'b001_1101001: q = 4'b0001; + 10'b001_1101010: q = 4'b0001; + 10'b001_1101011: q = 4'b0001; + 10'b001_1101100: q = 4'b0001; + 10'b001_1101101: q = 4'b0001; + 10'b001_1101110: q = 4'b0001; + 10'b001_1101111: q = 4'b0001; + 10'b001_1110000: q = 4'b0001; + 10'b001_1110001: q = 4'b0010; + 10'b001_1110010: q = 4'b0010; + 10'b001_1110011: q = 4'b0010; + 10'b001_1110100: q = 4'b0010; + 10'b001_1110101: q = 4'b0010; + 10'b001_1110110: q = 4'b0010; + 10'b001_1110111: q = 4'b0010; + 10'b001_1111000: q = 4'b0010; + 10'b001_1111001: q = 4'b0010; + 10'b001_1111010: q = 4'b0000; + 10'b001_1111011: q = 4'b0000; + 10'b001_1111100: q = 4'b0000; + 10'b001_1111101: q = 4'b0000; + 10'b001_1111110: q = 4'b0000; + 10'b001_1111111: q = 4'b0000; + 10'b010_0000000: q = 4'b0000; + 10'b010_0000001: q = 4'b0000; + 10'b010_0000010: q = 4'b0000; + 10'b010_0000011: q = 4'b0000; + 10'b010_0000100: q = 4'b0100; + 10'b010_0000101: q = 4'b0100; + 10'b010_0000110: q = 4'b0100; + 10'b010_0000111: q = 4'b0100; + 10'b010_0001000: q = 4'b0100; + 10'b010_0001001: q = 4'b0100; + 10'b010_0001010: q = 4'b0100; + 10'b010_0001011: q = 4'b0100; + 10'b010_0001100: q = 4'b0100; + 10'b010_0001101: q = 4'b0100; + 10'b010_0001110: q = 4'b0100; + 10'b010_0001111: q = 4'b1000; + 10'b010_0010000: q = 4'b1000; + 10'b010_0010001: q = 4'b1000; + 10'b010_0010010: q = 4'b1000; + 10'b010_0010011: q = 4'b1000; + 10'b010_0010100: q = 4'b1000; + 10'b010_0010101: q = 4'b1000; + 10'b010_0010110: q = 4'b1000; + 10'b010_0010111: q = 4'b1000; + 10'b010_0011000: q = 4'b1000; + 10'b010_0011001: q = 4'b1000; + 10'b010_0011010: q = 4'b1000; + 10'b010_0011011: q = 4'b1000; + 10'b010_0011100: q = 4'b1000; + 10'b010_0011101: q = 4'b1000; + 10'b010_0011110: q = 4'b1000; + 10'b010_0011111: q = 4'b1000; + 10'b010_0100000: q = 4'b1000; + 10'b010_0100001: q = 4'b1000; + 10'b010_0100010: q = 4'b1000; + 10'b010_0100011: q = 4'b1000; + 10'b010_0100100: q = 4'b1000; + 10'b010_0100101: q = 4'b1000; + 10'b010_0100110: q = 4'b1000; + 10'b010_0100111: q = 4'b1000; + 10'b010_0101000: q = 4'b1000; + 10'b010_0101001: q = 4'b1000; + 10'b010_0101010: q = 4'b1000; + 10'b010_0101011: q = 4'b1000; + 10'b010_0101100: q = 4'b1000; + 10'b010_0101101: q = 4'b1000; + 10'b010_0101110: q = 4'b1000; + 10'b010_0101111: q = 4'b1000; + 10'b010_0110000: q = 4'b1000; + 10'b010_0110001: q = 4'b1000; + 10'b010_0110010: q = 4'b1000; + 10'b010_0110011: q = 4'b1000; + 10'b010_0110100: q = 4'b1000; + 10'b010_0110101: q = 4'b1000; + 10'b010_0110110: q = 4'b1000; + 10'b010_0110111: q = 4'b1000; + 10'b010_0111000: q = 4'b1000; + 10'b010_0111001: q = 4'b1000; + 10'b010_0111010: q = 4'b1000; + 10'b010_0111011: q = 4'b1000; + 10'b010_0111100: q = 4'b1000; + 10'b010_0111101: q = 4'b1000; + 10'b010_0111110: q = 4'b1000; + 10'b010_0111111: q = 4'b1000; + 10'b010_1000000: q = 4'b0001; + 10'b010_1000001: q = 4'b0001; + 10'b010_1000010: q = 4'b0001; + 10'b010_1000011: q = 4'b0001; + 10'b010_1000100: q = 4'b0001; + 10'b010_1000101: q = 4'b0001; + 10'b010_1000110: q = 4'b0001; + 10'b010_1000111: q = 4'b0001; + 10'b010_1001000: q = 4'b0001; + 10'b010_1001001: q = 4'b0001; + 10'b010_1001010: q = 4'b0001; + 10'b010_1001011: q = 4'b0001; + 10'b010_1001100: q = 4'b0001; + 10'b010_1001101: q = 4'b0001; + 10'b010_1001110: q = 4'b0001; + 10'b010_1001111: q = 4'b0001; + 10'b010_1010000: q = 4'b0001; + 10'b010_1010001: q = 4'b0001; + 10'b010_1010010: q = 4'b0001; + 10'b010_1010011: q = 4'b0001; + 10'b010_1010100: q = 4'b0001; + 10'b010_1010101: q = 4'b0001; + 10'b010_1010110: q = 4'b0001; + 10'b010_1010111: q = 4'b0001; + 10'b010_1011000: q = 4'b0001; + 10'b010_1011001: q = 4'b0001; + 10'b010_1011010: q = 4'b0001; + 10'b010_1011011: q = 4'b0001; + 10'b010_1011100: q = 4'b0001; + 10'b010_1011101: q = 4'b0001; + 10'b010_1011110: q = 4'b0001; + 10'b010_1011111: q = 4'b0001; + 10'b010_1100000: q = 4'b0001; + 10'b010_1100001: q = 4'b0001; + 10'b010_1100010: q = 4'b0001; + 10'b010_1100011: q = 4'b0001; + 10'b010_1100100: q = 4'b0001; + 10'b010_1100101: q = 4'b0001; + 10'b010_1100110: q = 4'b0001; + 10'b010_1100111: q = 4'b0001; + 10'b010_1101000: q = 4'b0001; + 10'b010_1101001: q = 4'b0001; + 10'b010_1101010: q = 4'b0001; + 10'b010_1101011: q = 4'b0001; + 10'b010_1101100: q = 4'b0001; + 10'b010_1101101: q = 4'b0001; + 10'b010_1101110: q = 4'b0001; + 10'b010_1101111: q = 4'b0001; + 10'b010_1110000: q = 4'b0010; + 10'b010_1110001: q = 4'b0010; + 10'b010_1110010: q = 4'b0010; + 10'b010_1110011: q = 4'b0010; + 10'b010_1110100: q = 4'b0010; + 10'b010_1110101: q = 4'b0010; + 10'b010_1110110: q = 4'b0010; + 10'b010_1110111: q = 4'b0010; + 10'b010_1111000: q = 4'b0010; + 10'b010_1111001: q = 4'b0010; + 10'b010_1111010: q = 4'b0000; + 10'b010_1111011: q = 4'b0000; + 10'b010_1111100: q = 4'b0000; + 10'b010_1111101: q = 4'b0000; + 10'b010_1111110: q = 4'b0000; + 10'b010_1111111: q = 4'b0000; + 10'b011_0000000: q = 4'b0000; + 10'b011_0000001: q = 4'b0000; + 10'b011_0000010: q = 4'b0000; + 10'b011_0000011: q = 4'b0000; + 10'b011_0000100: q = 4'b0100; + 10'b011_0000101: q = 4'b0100; + 10'b011_0000110: q = 4'b0100; + 10'b011_0000111: q = 4'b0100; + 10'b011_0001000: q = 4'b0100; + 10'b011_0001001: q = 4'b0100; + 10'b011_0001010: q = 4'b0100; + 10'b011_0001011: q = 4'b0100; + 10'b011_0001100: q = 4'b0100; + 10'b011_0001101: q = 4'b0100; + 10'b011_0001110: q = 4'b0100; + 10'b011_0001111: q = 4'b0100; + 10'b011_0010000: q = 4'b1000; + 10'b011_0010001: q = 4'b1000; + 10'b011_0010010: q = 4'b1000; + 10'b011_0010011: q = 4'b1000; + 10'b011_0010100: q = 4'b1000; + 10'b011_0010101: q = 4'b1000; + 10'b011_0010110: q = 4'b1000; + 10'b011_0010111: q = 4'b1000; + 10'b011_0011000: q = 4'b1000; + 10'b011_0011001: q = 4'b1000; + 10'b011_0011010: q = 4'b1000; + 10'b011_0011011: q = 4'b1000; + 10'b011_0011100: q = 4'b1000; + 10'b011_0011101: q = 4'b1000; + 10'b011_0011110: q = 4'b1000; + 10'b011_0011111: q = 4'b1000; + 10'b011_0100000: q = 4'b1000; + 10'b011_0100001: q = 4'b1000; + 10'b011_0100010: q = 4'b1000; + 10'b011_0100011: q = 4'b1000; + 10'b011_0100100: q = 4'b1000; + 10'b011_0100101: q = 4'b1000; + 10'b011_0100110: q = 4'b1000; + 10'b011_0100111: q = 4'b1000; + 10'b011_0101000: q = 4'b1000; + 10'b011_0101001: q = 4'b1000; + 10'b011_0101010: q = 4'b1000; + 10'b011_0101011: q = 4'b1000; + 10'b011_0101100: q = 4'b1000; + 10'b011_0101101: q = 4'b1000; + 10'b011_0101110: q = 4'b1000; + 10'b011_0101111: q = 4'b1000; + 10'b011_0110000: q = 4'b1000; + 10'b011_0110001: q = 4'b1000; + 10'b011_0110010: q = 4'b1000; + 10'b011_0110011: q = 4'b1000; + 10'b011_0110100: q = 4'b1000; + 10'b011_0110101: q = 4'b1000; + 10'b011_0110110: q = 4'b1000; + 10'b011_0110111: q = 4'b1000; + 10'b011_0111000: q = 4'b1000; + 10'b011_0111001: q = 4'b1000; + 10'b011_0111010: q = 4'b1000; + 10'b011_0111011: q = 4'b1000; + 10'b011_0111100: q = 4'b1000; + 10'b011_0111101: q = 4'b1000; + 10'b011_0111110: q = 4'b1000; + 10'b011_0111111: q = 4'b1000; + 10'b011_1000000: q = 4'b0001; + 10'b011_1000001: q = 4'b0001; + 10'b011_1000010: q = 4'b0001; + 10'b011_1000011: q = 4'b0001; + 10'b011_1000100: q = 4'b0001; + 10'b011_1000101: q = 4'b0001; + 10'b011_1000110: q = 4'b0001; + 10'b011_1000111: q = 4'b0001; + 10'b011_1001000: q = 4'b0001; + 10'b011_1001001: q = 4'b0001; + 10'b011_1001010: q = 4'b0001; + 10'b011_1001011: q = 4'b0001; + 10'b011_1001100: q = 4'b0001; + 10'b011_1001101: q = 4'b0001; + 10'b011_1001110: q = 4'b0001; + 10'b011_1001111: q = 4'b0001; + 10'b011_1010000: q = 4'b0001; + 10'b011_1010001: q = 4'b0001; + 10'b011_1010010: q = 4'b0001; + 10'b011_1010011: q = 4'b0001; + 10'b011_1010100: q = 4'b0001; + 10'b011_1010101: q = 4'b0001; + 10'b011_1010110: q = 4'b0001; + 10'b011_1010111: q = 4'b0001; + 10'b011_1011000: q = 4'b0001; + 10'b011_1011001: q = 4'b0001; + 10'b011_1011010: q = 4'b0001; + 10'b011_1011011: q = 4'b0001; + 10'b011_1011100: q = 4'b0001; + 10'b011_1011101: q = 4'b0001; + 10'b011_1011110: q = 4'b0001; + 10'b011_1011111: q = 4'b0001; + 10'b011_1100000: q = 4'b0001; + 10'b011_1100001: q = 4'b0001; + 10'b011_1100010: q = 4'b0001; + 10'b011_1100011: q = 4'b0001; + 10'b011_1100100: q = 4'b0001; + 10'b011_1100101: q = 4'b0001; + 10'b011_1100110: q = 4'b0001; + 10'b011_1100111: q = 4'b0001; + 10'b011_1101000: q = 4'b0001; + 10'b011_1101001: q = 4'b0001; + 10'b011_1101010: q = 4'b0001; + 10'b011_1101011: q = 4'b0001; + 10'b011_1101100: q = 4'b0001; + 10'b011_1101101: q = 4'b0001; + 10'b011_1101110: q = 4'b0010; + 10'b011_1101111: q = 4'b0010; + 10'b011_1110000: q = 4'b0010; + 10'b011_1110001: q = 4'b0010; + 10'b011_1110010: q = 4'b0010; + 10'b011_1110011: q = 4'b0010; + 10'b011_1110100: q = 4'b0010; + 10'b011_1110101: q = 4'b0010; + 10'b011_1110110: q = 4'b0010; + 10'b011_1110111: q = 4'b0010; + 10'b011_1111000: q = 4'b0010; + 10'b011_1111001: q = 4'b0010; + 10'b011_1111010: q = 4'b0000; + 10'b011_1111011: q = 4'b0000; + 10'b011_1111100: q = 4'b0000; + 10'b011_1111101: q = 4'b0000; + 10'b011_1111110: q = 4'b0000; + 10'b011_1111111: q = 4'b0000; + 10'b100_0000000: q = 4'b0000; + 10'b100_0000001: q = 4'b0000; + 10'b100_0000010: q = 4'b0000; + 10'b100_0000011: q = 4'b0000; + 10'b100_0000100: q = 4'b0000; + 10'b100_0000101: q = 4'b0000; + 10'b100_0000110: q = 4'b0100; + 10'b100_0000111: q = 4'b0100; + 10'b100_0001000: q = 4'b0100; + 10'b100_0001001: q = 4'b0100; + 10'b100_0001010: q = 4'b0100; + 10'b100_0001011: q = 4'b0100; + 10'b100_0001100: q = 4'b0100; + 10'b100_0001101: q = 4'b0100; + 10'b100_0001110: q = 4'b0100; + 10'b100_0001111: q = 4'b0100; + 10'b100_0010000: q = 4'b0100; + 10'b100_0010001: q = 4'b0100; + 10'b100_0010010: q = 4'b1000; + 10'b100_0010011: q = 4'b1000; + 10'b100_0010100: q = 4'b1000; + 10'b100_0010101: q = 4'b1000; + 10'b100_0010110: q = 4'b1000; + 10'b100_0010111: q = 4'b1000; + 10'b100_0011000: q = 4'b1000; + 10'b100_0011001: q = 4'b1000; + 10'b100_0011010: q = 4'b1000; + 10'b100_0011011: q = 4'b1000; + 10'b100_0011100: q = 4'b1000; + 10'b100_0011101: q = 4'b1000; + 10'b100_0011110: q = 4'b1000; + 10'b100_0011111: q = 4'b1000; + 10'b100_0100000: q = 4'b1000; + 10'b100_0100001: q = 4'b1000; + 10'b100_0100010: q = 4'b1000; + 10'b100_0100011: q = 4'b1000; + 10'b100_0100100: q = 4'b1000; + 10'b100_0100101: q = 4'b1000; + 10'b100_0100110: q = 4'b1000; + 10'b100_0100111: q = 4'b1000; + 10'b100_0101000: q = 4'b1000; + 10'b100_0101001: q = 4'b1000; + 10'b100_0101010: q = 4'b1000; + 10'b100_0101011: q = 4'b1000; + 10'b100_0101100: q = 4'b1000; + 10'b100_0101101: q = 4'b1000; + 10'b100_0101110: q = 4'b1000; + 10'b100_0101111: q = 4'b1000; + 10'b100_0110000: q = 4'b1000; + 10'b100_0110001: q = 4'b1000; + 10'b100_0110010: q = 4'b1000; + 10'b100_0110011: q = 4'b1000; + 10'b100_0110100: q = 4'b1000; + 10'b100_0110101: q = 4'b1000; + 10'b100_0110110: q = 4'b1000; + 10'b100_0110111: q = 4'b1000; + 10'b100_0111000: q = 4'b1000; + 10'b100_0111001: q = 4'b1000; + 10'b100_0111010: q = 4'b1000; + 10'b100_0111011: q = 4'b1000; + 10'b100_0111100: q = 4'b1000; + 10'b100_0111101: q = 4'b1000; + 10'b100_0111110: q = 4'b1000; + 10'b100_0111111: q = 4'b1000; + 10'b100_1000000: q = 4'b0001; + 10'b100_1000001: q = 4'b0001; + 10'b100_1000010: q = 4'b0001; + 10'b100_1000011: q = 4'b0001; + 10'b100_1000100: q = 4'b0001; + 10'b100_1000101: q = 4'b0001; + 10'b100_1000110: q = 4'b0001; + 10'b100_1000111: q = 4'b0001; + 10'b100_1001000: q = 4'b0001; + 10'b100_1001001: q = 4'b0001; + 10'b100_1001010: q = 4'b0001; + 10'b100_1001011: q = 4'b0001; + 10'b100_1001100: q = 4'b0001; + 10'b100_1001101: q = 4'b0001; + 10'b100_1001110: q = 4'b0001; + 10'b100_1001111: q = 4'b0001; + 10'b100_1010000: q = 4'b0001; + 10'b100_1010001: q = 4'b0001; + 10'b100_1010010: q = 4'b0001; + 10'b100_1010011: q = 4'b0001; + 10'b100_1010100: q = 4'b0001; + 10'b100_1010101: q = 4'b0001; + 10'b100_1010110: q = 4'b0001; + 10'b100_1010111: q = 4'b0001; + 10'b100_1011000: q = 4'b0001; + 10'b100_1011001: q = 4'b0001; + 10'b100_1011010: q = 4'b0001; + 10'b100_1011011: q = 4'b0001; + 10'b100_1011100: q = 4'b0001; + 10'b100_1011101: q = 4'b0001; + 10'b100_1011110: q = 4'b0001; + 10'b100_1011111: q = 4'b0001; + 10'b100_1100000: q = 4'b0001; + 10'b100_1100001: q = 4'b0001; + 10'b100_1100010: q = 4'b0001; + 10'b100_1100011: q = 4'b0001; + 10'b100_1100100: q = 4'b0001; + 10'b100_1100101: q = 4'b0001; + 10'b100_1100110: q = 4'b0001; + 10'b100_1100111: q = 4'b0001; + 10'b100_1101000: q = 4'b0001; + 10'b100_1101001: q = 4'b0001; + 10'b100_1101010: q = 4'b0001; + 10'b100_1101011: q = 4'b0001; + 10'b100_1101100: q = 4'b0010; + 10'b100_1101101: q = 4'b0010; + 10'b100_1101110: q = 4'b0010; + 10'b100_1101111: q = 4'b0010; + 10'b100_1110000: q = 4'b0010; + 10'b100_1110001: q = 4'b0010; + 10'b100_1110010: q = 4'b0010; + 10'b100_1110011: q = 4'b0010; + 10'b100_1110100: q = 4'b0010; + 10'b100_1110101: q = 4'b0010; + 10'b100_1110110: q = 4'b0010; + 10'b100_1110111: q = 4'b0010; + 10'b100_1111000: q = 4'b0000; + 10'b100_1111001: q = 4'b0000; + 10'b100_1111010: q = 4'b0000; + 10'b100_1111011: q = 4'b0000; + 10'b100_1111100: q = 4'b0000; + 10'b100_1111101: q = 4'b0000; + 10'b100_1111110: q = 4'b0000; + 10'b100_1111111: q = 4'b0000; + 10'b101_0000000: q = 4'b0000; + 10'b101_0000001: q = 4'b0000; + 10'b101_0000010: q = 4'b0000; + 10'b101_0000011: q = 4'b0000; + 10'b101_0000100: q = 4'b0000; + 10'b101_0000101: q = 4'b0000; + 10'b101_0000110: q = 4'b0100; + 10'b101_0000111: q = 4'b0100; + 10'b101_0001000: q = 4'b0100; + 10'b101_0001001: q = 4'b0100; + 10'b101_0001010: q = 4'b0100; + 10'b101_0001011: q = 4'b0100; + 10'b101_0001100: q = 4'b0100; + 10'b101_0001101: q = 4'b0100; + 10'b101_0001110: q = 4'b0100; + 10'b101_0001111: q = 4'b0100; + 10'b101_0010000: q = 4'b0100; + 10'b101_0010001: q = 4'b0100; + 10'b101_0010010: q = 4'b0100; + 10'b101_0010011: q = 4'b0100; + 10'b101_0010100: q = 4'b1000; + 10'b101_0010101: q = 4'b1000; + 10'b101_0010110: q = 4'b1000; + 10'b101_0010111: q = 4'b1000; + 10'b101_0011000: q = 4'b1000; + 10'b101_0011001: q = 4'b1000; + 10'b101_0011010: q = 4'b1000; + 10'b101_0011011: q = 4'b1000; + 10'b101_0011100: q = 4'b1000; + 10'b101_0011101: q = 4'b1000; + 10'b101_0011110: q = 4'b1000; + 10'b101_0011111: q = 4'b1000; + 10'b101_0100000: q = 4'b1000; + 10'b101_0100001: q = 4'b1000; + 10'b101_0100010: q = 4'b1000; + 10'b101_0100011: q = 4'b1000; + 10'b101_0100100: q = 4'b1000; + 10'b101_0100101: q = 4'b1000; + 10'b101_0100110: q = 4'b1000; + 10'b101_0100111: q = 4'b1000; + 10'b101_0101000: q = 4'b1000; + 10'b101_0101001: q = 4'b1000; + 10'b101_0101010: q = 4'b1000; + 10'b101_0101011: q = 4'b1000; + 10'b101_0101100: q = 4'b1000; + 10'b101_0101101: q = 4'b1000; + 10'b101_0101110: q = 4'b1000; + 10'b101_0101111: q = 4'b1000; + 10'b101_0110000: q = 4'b1000; + 10'b101_0110001: q = 4'b1000; + 10'b101_0110010: q = 4'b1000; + 10'b101_0110011: q = 4'b1000; + 10'b101_0110100: q = 4'b1000; + 10'b101_0110101: q = 4'b1000; + 10'b101_0110110: q = 4'b1000; + 10'b101_0110111: q = 4'b1000; + 10'b101_0111000: q = 4'b1000; + 10'b101_0111001: q = 4'b1000; + 10'b101_0111010: q = 4'b1000; + 10'b101_0111011: q = 4'b1000; + 10'b101_0111100: q = 4'b1000; + 10'b101_0111101: q = 4'b1000; + 10'b101_0111110: q = 4'b1000; + 10'b101_0111111: q = 4'b1000; + 10'b101_1000000: q = 4'b0001; + 10'b101_1000001: q = 4'b0001; + 10'b101_1000010: q = 4'b0001; + 10'b101_1000011: q = 4'b0001; + 10'b101_1000100: q = 4'b0001; + 10'b101_1000101: q = 4'b0001; + 10'b101_1000110: q = 4'b0001; + 10'b101_1000111: q = 4'b0001; + 10'b101_1001000: q = 4'b0001; + 10'b101_1001001: q = 4'b0001; + 10'b101_1001010: q = 4'b0001; + 10'b101_1001011: q = 4'b0001; + 10'b101_1001100: q = 4'b0001; + 10'b101_1001101: q = 4'b0001; + 10'b101_1001110: q = 4'b0001; + 10'b101_1001111: q = 4'b0001; + 10'b101_1010000: q = 4'b0001; + 10'b101_1010001: q = 4'b0001; + 10'b101_1010010: q = 4'b0001; + 10'b101_1010011: q = 4'b0001; + 10'b101_1010100: q = 4'b0001; + 10'b101_1010101: q = 4'b0001; + 10'b101_1010110: q = 4'b0001; + 10'b101_1010111: q = 4'b0001; + 10'b101_1011000: q = 4'b0001; + 10'b101_1011001: q = 4'b0001; + 10'b101_1011010: q = 4'b0001; + 10'b101_1011011: q = 4'b0001; + 10'b101_1011100: q = 4'b0001; + 10'b101_1011101: q = 4'b0001; + 10'b101_1011110: q = 4'b0001; + 10'b101_1011111: q = 4'b0001; + 10'b101_1100000: q = 4'b0001; + 10'b101_1100001: q = 4'b0001; + 10'b101_1100010: q = 4'b0001; + 10'b101_1100011: q = 4'b0001; + 10'b101_1100100: q = 4'b0001; + 10'b101_1100101: q = 4'b0001; + 10'b101_1100110: q = 4'b0001; + 10'b101_1100111: q = 4'b0001; + 10'b101_1101000: q = 4'b0001; + 10'b101_1101001: q = 4'b0001; + 10'b101_1101010: q = 4'b0001; + 10'b101_1101011: q = 4'b0001; + 10'b101_1101100: q = 4'b0010; + 10'b101_1101101: q = 4'b0010; + 10'b101_1101110: q = 4'b0010; + 10'b101_1101111: q = 4'b0010; + 10'b101_1110000: q = 4'b0010; + 10'b101_1110001: q = 4'b0010; + 10'b101_1110010: q = 4'b0010; + 10'b101_1110011: q = 4'b0010; + 10'b101_1110100: q = 4'b0010; + 10'b101_1110101: q = 4'b0010; + 10'b101_1110110: q = 4'b0010; + 10'b101_1110111: q = 4'b0010; + 10'b101_1111000: q = 4'b0000; + 10'b101_1111001: q = 4'b0000; + 10'b101_1111010: q = 4'b0000; + 10'b101_1111011: q = 4'b0000; + 10'b101_1111100: q = 4'b0000; + 10'b101_1111101: q = 4'b0000; + 10'b101_1111110: q = 4'b0000; + 10'b101_1111111: q = 4'b0000; + 10'b110_0000000: q = 4'b0000; + 10'b110_0000001: q = 4'b0000; + 10'b110_0000010: q = 4'b0000; + 10'b110_0000011: q = 4'b0000; + 10'b110_0000100: q = 4'b0000; + 10'b110_0000101: q = 4'b0000; + 10'b110_0000110: q = 4'b0000; + 10'b110_0000111: q = 4'b0000; + 10'b110_0001000: q = 4'b0100; + 10'b110_0001001: q = 4'b0100; + 10'b110_0001010: q = 4'b0100; + 10'b110_0001011: q = 4'b0100; + 10'b110_0001100: q = 4'b0100; + 10'b110_0001101: q = 4'b0100; + 10'b110_0001110: q = 4'b0100; + 10'b110_0001111: q = 4'b0100; + 10'b110_0010000: q = 4'b0100; + 10'b110_0010001: q = 4'b0100; + 10'b110_0010010: q = 4'b0100; + 10'b110_0010011: q = 4'b0100; + 10'b110_0010100: q = 4'b1000; + 10'b110_0010101: q = 4'b1000; + 10'b110_0010110: q = 4'b1000; + 10'b110_0010111: q = 4'b1000; + 10'b110_0011000: q = 4'b1000; + 10'b110_0011001: q = 4'b1000; + 10'b110_0011010: q = 4'b1000; + 10'b110_0011011: q = 4'b1000; + 10'b110_0011100: q = 4'b1000; + 10'b110_0011101: q = 4'b1000; + 10'b110_0011110: q = 4'b1000; + 10'b110_0011111: q = 4'b1000; + 10'b110_0100000: q = 4'b1000; + 10'b110_0100001: q = 4'b1000; + 10'b110_0100010: q = 4'b1000; + 10'b110_0100011: q = 4'b1000; + 10'b110_0100100: q = 4'b1000; + 10'b110_0100101: q = 4'b1000; + 10'b110_0100110: q = 4'b1000; + 10'b110_0100111: q = 4'b1000; + 10'b110_0101000: q = 4'b1000; + 10'b110_0101001: q = 4'b1000; + 10'b110_0101010: q = 4'b1000; + 10'b110_0101011: q = 4'b1000; + 10'b110_0101100: q = 4'b1000; + 10'b110_0101101: q = 4'b1000; + 10'b110_0101110: q = 4'b1000; + 10'b110_0101111: q = 4'b1000; + 10'b110_0110000: q = 4'b1000; + 10'b110_0110001: q = 4'b1000; + 10'b110_0110010: q = 4'b1000; + 10'b110_0110011: q = 4'b1000; + 10'b110_0110100: q = 4'b1000; + 10'b110_0110101: q = 4'b1000; + 10'b110_0110110: q = 4'b1000; + 10'b110_0110111: q = 4'b1000; + 10'b110_0111000: q = 4'b1000; + 10'b110_0111001: q = 4'b1000; + 10'b110_0111010: q = 4'b1000; + 10'b110_0111011: q = 4'b1000; + 10'b110_0111100: q = 4'b1000; + 10'b110_0111101: q = 4'b1000; + 10'b110_0111110: q = 4'b1000; + 10'b110_0111111: q = 4'b1000; + 10'b110_1000000: q = 4'b0001; + 10'b110_1000001: q = 4'b0001; + 10'b110_1000010: q = 4'b0001; + 10'b110_1000011: q = 4'b0001; + 10'b110_1000100: q = 4'b0001; + 10'b110_1000101: q = 4'b0001; + 10'b110_1000110: q = 4'b0001; + 10'b110_1000111: q = 4'b0001; + 10'b110_1001000: q = 4'b0001; + 10'b110_1001001: q = 4'b0001; + 10'b110_1001010: q = 4'b0001; + 10'b110_1001011: q = 4'b0001; + 10'b110_1001100: q = 4'b0001; + 10'b110_1001101: q = 4'b0001; + 10'b110_1001110: q = 4'b0001; + 10'b110_1001111: q = 4'b0001; + 10'b110_1010000: q = 4'b0001; + 10'b110_1010001: q = 4'b0001; + 10'b110_1010010: q = 4'b0001; + 10'b110_1010011: q = 4'b0001; + 10'b110_1010100: q = 4'b0001; + 10'b110_1010101: q = 4'b0001; + 10'b110_1010110: q = 4'b0001; + 10'b110_1010111: q = 4'b0001; + 10'b110_1011000: q = 4'b0001; + 10'b110_1011001: q = 4'b0001; + 10'b110_1011010: q = 4'b0001; + 10'b110_1011011: q = 4'b0001; + 10'b110_1011100: q = 4'b0001; + 10'b110_1011101: q = 4'b0001; + 10'b110_1011110: q = 4'b0001; + 10'b110_1011111: q = 4'b0001; + 10'b110_1100000: q = 4'b0001; + 10'b110_1100001: q = 4'b0001; + 10'b110_1100010: q = 4'b0001; + 10'b110_1100011: q = 4'b0001; + 10'b110_1100100: q = 4'b0001; + 10'b110_1100101: q = 4'b0001; + 10'b110_1100110: q = 4'b0001; + 10'b110_1100111: q = 4'b0001; + 10'b110_1101000: q = 4'b0001; + 10'b110_1101001: q = 4'b0001; + 10'b110_1101010: q = 4'b0010; + 10'b110_1101011: q = 4'b0010; + 10'b110_1101100: q = 4'b0010; + 10'b110_1101101: q = 4'b0010; + 10'b110_1101110: q = 4'b0010; + 10'b110_1101111: q = 4'b0010; + 10'b110_1110000: q = 4'b0010; + 10'b110_1110001: q = 4'b0010; + 10'b110_1110010: q = 4'b0010; + 10'b110_1110011: q = 4'b0010; + 10'b110_1110100: q = 4'b0010; + 10'b110_1110101: q = 4'b0010; + 10'b110_1110110: q = 4'b0010; + 10'b110_1110111: q = 4'b0010; + 10'b110_1111000: q = 4'b0000; + 10'b110_1111001: q = 4'b0000; + 10'b110_1111010: q = 4'b0000; + 10'b110_1111011: q = 4'b0000; + 10'b110_1111100: q = 4'b0000; + 10'b110_1111101: q = 4'b0000; + 10'b110_1111110: q = 4'b0000; + 10'b110_1111111: q = 4'b0000; + 10'b111_0000000: q = 4'b0000; + 10'b111_0000001: q = 4'b0000; + 10'b111_0000010: q = 4'b0000; + 10'b111_0000011: q = 4'b0000; + 10'b111_0000100: q = 4'b0000; + 10'b111_0000101: q = 4'b0000; + 10'b111_0000110: q = 4'b0000; + 10'b111_0000111: q = 4'b0000; + 10'b111_0001000: q = 4'b0100; + 10'b111_0001001: q = 4'b0100; + 10'b111_0001010: q = 4'b0100; + 10'b111_0001011: q = 4'b0100; + 10'b111_0001100: q = 4'b0100; + 10'b111_0001101: q = 4'b0100; + 10'b111_0001110: q = 4'b0100; + 10'b111_0001111: q = 4'b0100; + 10'b111_0010000: q = 4'b0100; + 10'b111_0010001: q = 4'b0100; + 10'b111_0010010: q = 4'b0100; + 10'b111_0010011: q = 4'b0100; + 10'b111_0010100: q = 4'b0100; + 10'b111_0010101: q = 4'b0100; + 10'b111_0010110: q = 4'b0100; + 10'b111_0010111: q = 4'b0100; + 10'b111_0011000: q = 4'b1000; + 10'b111_0011001: q = 4'b1000; + 10'b111_0011010: q = 4'b1000; + 10'b111_0011011: q = 4'b1000; + 10'b111_0011100: q = 4'b1000; + 10'b111_0011101: q = 4'b1000; + 10'b111_0011110: q = 4'b1000; + 10'b111_0011111: q = 4'b1000; + 10'b111_0100000: q = 4'b1000; + 10'b111_0100001: q = 4'b1000; + 10'b111_0100010: q = 4'b1000; + 10'b111_0100011: q = 4'b1000; + 10'b111_0100100: q = 4'b1000; + 10'b111_0100101: q = 4'b1000; + 10'b111_0100110: q = 4'b1000; + 10'b111_0100111: q = 4'b1000; + 10'b111_0101000: q = 4'b1000; + 10'b111_0101001: q = 4'b1000; + 10'b111_0101010: q = 4'b1000; + 10'b111_0101011: q = 4'b1000; + 10'b111_0101100: q = 4'b1000; + 10'b111_0101101: q = 4'b1000; + 10'b111_0101110: q = 4'b1000; + 10'b111_0101111: q = 4'b1000; + 10'b111_0110000: q = 4'b1000; + 10'b111_0110001: q = 4'b1000; + 10'b111_0110010: q = 4'b1000; + 10'b111_0110011: q = 4'b1000; + 10'b111_0110100: q = 4'b1000; + 10'b111_0110101: q = 4'b1000; + 10'b111_0110110: q = 4'b1000; + 10'b111_0110111: q = 4'b1000; + 10'b111_0111000: q = 4'b1000; + 10'b111_0111001: q = 4'b1000; + 10'b111_0111010: q = 4'b1000; + 10'b111_0111011: q = 4'b1000; + 10'b111_0111100: q = 4'b1000; + 10'b111_0111101: q = 4'b1000; + 10'b111_0111110: q = 4'b1000; + 10'b111_0111111: q = 4'b1000; + 10'b111_1000000: q = 4'b0001; + 10'b111_1000001: q = 4'b0001; + 10'b111_1000010: q = 4'b0001; + 10'b111_1000011: q = 4'b0001; + 10'b111_1000100: q = 4'b0001; + 10'b111_1000101: q = 4'b0001; + 10'b111_1000110: q = 4'b0001; + 10'b111_1000111: q = 4'b0001; + 10'b111_1001000: q = 4'b0001; + 10'b111_1001001: q = 4'b0001; + 10'b111_1001010: q = 4'b0001; + 10'b111_1001011: q = 4'b0001; + 10'b111_1001100: q = 4'b0001; + 10'b111_1001101: q = 4'b0001; + 10'b111_1001110: q = 4'b0001; + 10'b111_1001111: q = 4'b0001; + 10'b111_1010000: q = 4'b0001; + 10'b111_1010001: q = 4'b0001; + 10'b111_1010010: q = 4'b0001; + 10'b111_1010011: q = 4'b0001; + 10'b111_1010100: q = 4'b0001; + 10'b111_1010101: q = 4'b0001; + 10'b111_1010110: q = 4'b0001; + 10'b111_1010111: q = 4'b0001; + 10'b111_1011000: q = 4'b0001; + 10'b111_1011001: q = 4'b0001; + 10'b111_1011010: q = 4'b0001; + 10'b111_1011011: q = 4'b0001; + 10'b111_1011100: q = 4'b0001; + 10'b111_1011101: q = 4'b0001; + 10'b111_1011110: q = 4'b0001; + 10'b111_1011111: q = 4'b0001; + 10'b111_1100000: q = 4'b0001; + 10'b111_1100001: q = 4'b0001; + 10'b111_1100010: q = 4'b0001; + 10'b111_1100011: q = 4'b0001; + 10'b111_1100100: q = 4'b0001; + 10'b111_1100101: q = 4'b0001; + 10'b111_1100110: q = 4'b0001; + 10'b111_1100111: q = 4'b0001; + 10'b111_1101000: q = 4'b0010; + 10'b111_1101001: q = 4'b0010; + 10'b111_1101010: q = 4'b0010; + 10'b111_1101011: q = 4'b0010; + 10'b111_1101100: q = 4'b0010; + 10'b111_1101101: q = 4'b0010; + 10'b111_1101110: q = 4'b0010; + 10'b111_1101111: q = 4'b0010; + 10'b111_1110000: q = 4'b0010; + 10'b111_1110001: q = 4'b0010; + 10'b111_1110010: q = 4'b0010; + 10'b111_1110011: q = 4'b0010; + 10'b111_1110100: q = 4'b0010; + 10'b111_1110101: q = 4'b0010; + 10'b111_1110110: q = 4'b0010; + 10'b111_1110111: q = 4'b0010; + 10'b111_1111000: q = 4'b0000; + 10'b111_1111001: q = 4'b0000; + 10'b111_1111010: q = 4'b0000; + 10'b111_1111011: q = 4'b0000; + 10'b111_1111100: q = 4'b0000; + 10'b111_1111101: q = 4'b0000; + 10'b111_1111110: q = 4'b0000; + 10'b111_1111111: q = 4'b0000; + endcase diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 8b3fec51d..1b40c673a 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,26 +1,28 @@ +`include "wally-config.vh" + ///////////// // counter // ///////////// -module counter(input logic clk, - input logic req, - output logic done); +// module counter(input logic clk, +// input logic req, +// output logic done); - logic [5:0] count; +// logic [7:0] count; - // This block of control logic sequences the divider - // through its iterations. You may modify it if you - // build a divider which completes in fewer iterations. - // You are not responsible for the (trivial) circuit - // design of the block. +// // This block of control logic sequences the divider +// // through its iterations. You may modify it if you +// // build a divider which completes in fewer iterations. +// // You are not responsible for the (trivial) circuit +// // design of the block. - always @(posedge clk) - begin - if (count == 54) done <= #1 1; - else if (done | req) done <= #1 0; - if (req) count <= #1 0; - else count <= #1 count+1; - end -endmodule +// always @(posedge clk) +// begin +// if (count == `DIVLEN + 2) done <= #1 1; +// else if (done | req) done <= #1 0; +// if (req) count <= #1 0; +// else count <= #1 count+1; +// end +// endmodule /////////// // clock // @@ -37,40 +39,24 @@ endmodule // testbench // ////////// module testbench; - logic clk; - logic req; - logic done; - logic [63:0] a; - logic [63:0] b; - logic [63:0] result; - logic [51:0] r; - logic [54:0] rp, rm; // positive quotient digits - logic [10:0] e; // output exponent + logic clk; + logic req; + logic done; + logic Int, Sqrt, Mod; + logic [`XLEN-1:0] a, b; + logic [`NF-1:0] afrac, bfrac; + logic [`NE-1:0] aExp, bExp; + logic asign, bsign; + logic [`NF-1:0] r; + logic [`XLEN-1:0] rInt; + logic [`DIVLEN-1:0] Quot; - // input logic for Unpacker - // input logic [63:0] X, Y, Z, - numbers - // input logic FmtE, ---- format, 1 is for double precision, 0 is single - // input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide - // all variables are commented in fpu.sv - - // output logic from Unpacker - logic XSgnE, YSgnE, ZSgnE; - logic [10:0] XExpE, YExpE, ZExpE; // exponent - logic [52:0] XManE, YManE, ZManE; - logic XNormE; - logic XNaNE, YNaNE, ZNaNE; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XDenormE, YDenormE, ZDenormE; // denormals - logic XZeroE, YZeroE, ZZeroE; - logic [10:0] BiasE; // currrently hardcoded, will probs be removed - logic XInfE, YInfE, ZInfE; - logic XExpMaxE; // says exponent is all ones, can ignore - // Test parameters - parameter MEM_SIZE = 60000; + parameter MEM_SIZE = 40000; parameter MEM_WIDTH = 64+64+64; - `define memr 63:0 + // Test sizes + `define memr 63:0 `define memb 127:64 `define mema 191:128 @@ -78,31 +64,28 @@ module testbench; logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a // bit field of an array - logic [63:0] correctr, nextr, diffn, diffp; + logic [63:0] correctr, nextr, diffn, diffp; + logic [10:0] rExp; + logic rsign; integer testnum, errors; - // Unpacker - // Note: BiasE will probably get taken out eventually - unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0), - .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE), - .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE), - .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE), - .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE), - .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE)); + // Equip Int, Sqrt, or IntMod test + assign Int = 1'b0; + assign Mod = 1'b0; + assign Sqrt = 1'b1; // Divider - srt #(52) srt(.clk, .Start(req), + srt srt(.clk, .Start(req), .Stall(1'b0), .Flush(1'b0), - .SrcXExpE(XExpE), .SrcYExpE(YExpE), - .SrcXFrac(XManE[51:0]), .SrcYFrac(YManE[51:0]), - .SrcA('0), .SrcB('0), .Fmt(2'b00), - .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), - .Quot(r), .Rem(), .Exp(e), .Flags()); - - assign result = {1'b0, e, r}; + .XExp(aExp), .YExp(bExp), .rExp, + .XSign(asign), .YSign(bsign), .rsign, + .SrcXFrac(afrac), .SrcYFrac(bfrac), + .SrcA(a), .SrcB(b), .Fmt(2'b00), + .W64(1'b1), .Signed(1'b0), .Int, .Mod, .Sqrt, + .Result(Quot), .Flags(), .done); // Counter - counter counter(clk, req, done); + // counter counter(clk, req, done); initial @@ -118,52 +101,81 @@ module testbench; begin testnum = 0; errors = 0; - $readmemh ("testvectors", Tests); + $readmemh ("sqrttestvectors", Tests); Vec = Tests[testnum]; a = Vec[`mema]; + {asign, aExp, afrac} = a; b = Vec[`memb]; + {bsign, bExp, bfrac} = b; nextr = Vec[`memr]; + r = Quot[(`DIVLEN - 2):(`DIVLEN - `NF - 1)]; + rInt = Quot; req <= #5 1; end // Apply directed test vectors read from file. - always @(posedge clk) - begin - if (done) - begin - req <= #5 1; - diffp = correctr - result; - diffn = result - correctr; - if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp - begin - errors = errors+1; - $display("a = %h b = %h result = %h",a,b,correctr); - $display("result was %h, should be %h %h %h\n", result, correctr, diffn, diffp); - $display("at fail"); - $display("failed\n"); - $stop; - end - if (a === 64'hxxxxxxxxxxxxxxxx) - begin - $display("%d Tests completed successfully", testnum); - $stop; - end - end - if (req) - begin - req <= #5 0; - correctr = nextr; - $display("pre increment"); - testnum = testnum+1; - a = Vec[`mema]; - b = Vec[`memb]; - Vec = Tests[testnum]; - $display("a = %h b = %h result = %h",a,b,nextr); - nextr = Vec[`memr]; - $display("after increment"); - end + always @(posedge clk) begin + r = Quot[(`DIVLEN - 2):(`DIVLEN - `NF - 1)]; + rInt = Quot; + if (done) begin + if (~Int & ~Sqrt) begin // This test case checks floating point division + req <= #5 1; + diffp = correctr[51:0] - r; + diffn = r - correctr[51:0]; + if ((rsign !== correctr[63]) | (rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp + begin + errors = errors+1; + $display("result was %h_%h, should be %h %h %h\n", rExp, r, correctr, diffn, diffp); + $display("failed\n"); + $stop; + end + if (afrac === 52'hxxxxxxxxxxxxx) + begin + $display("%d Tests completed successfully", testnum); + $stop; + end + end else if (~Sqrt) begin // This test case works for both integer divide and integer modulo + req <= #5 1; + diffp = correctr[63:0] - rInt; + if (($signed(diffp) != 0) | (diffp === 64'bx)) // check if accurate to 1 ulp + begin + errors = errors+1; + $display("result was %h, should be %h %h\n", rInt, correctr, diffp); + $display("failed\n"); + end + if (afrac === 52'hxxxxxxxxxxxxx) + begin + $display("%d Tests completed successfully", testnum - errors); + $stop; + end + end else begin // This test case verifies square root + req <= #5 1; + diffp = correctr[51:0] - r; + diffn = r - correctr[51:0]; + if ((rExp !== correctr[62:52]) | ($signed(diffn) > 1) | ($signed(diffp) > 1) | (diffn === 64'bx) | (diffp === 64'bx)) // check if accurate to 1 ulp + begin + errors = errors + 1; + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); + $display("failed\n"); + end + if (afrac === 52'hxxxxxxxxxxxxx) begin + $display("%d Tests completed successfully", testnum-errors); + $stop; end + end end - + if (req) begin + req <= #5 0; + correctr = nextr; + testnum = testnum+1; + Vec = Tests[testnum]; + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + {asign, aExp, afrac} = a; + b = Vec[`memb]; + {bsign, bExp, bfrac} = b; + nextr = Vec[`memr]; + end + end endmodule diff --git a/pipelined/srt/testgen b/pipelined/srt/testgen deleted file mode 100755 index bb01f81bc..000000000 Binary files a/pipelined/srt/testgen and /dev/null differ diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 143ef058f..98d52819b 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double x1, x2, a, b, r; + double a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,7 +63,6 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { - printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/srt/testvectors b/pipelined/srt/testvectors deleted file mode 100644 index c6412a9e6..000000000 --- a/pipelined/srt/testvectors +++ /dev/null @@ -1,289 +0,0 @@ -4000000000000000_4000000000000000_3ff0000000000000 -4018000000000000_4000000000000000_4008000000000000 -4024000000000000_4000000000000000_4014000000000000 -4032000000000000_4000000000000000_4022000000000000 -4041000000000000_4000000000000000_4031000000000000 -405c000000000000_4000000000000000_404c000000000000 -406e000000000000_4000000000000000_405e000000000000 -407ffff583a53b8e_4000000000000000_406ffff583a53b8e -408199999999999a_4000000000000000_407199999999999a -4093333333333333_4000000000000000_4083333333333333 -40a028f5c28f5c29_4000000000000000_409028f5c28f5c29 -40b004189374bc6a_4000000000000000_40a004189374bc6a -40c00068db8bac71_4000000000000000_40b00068db8bac71 -40dd1745d1745d17_4000000000000000_40cd1745d1745d17 -40e5555555555555_4000000000000000_40d5555555555555 -40f999999999999a_4000000000000000_40e999999999999a -410c71c71c71c71c_4000000000000000_40fc71c71c71c71c -4000000000000000_4018000000000000_3fe5555555555555 -4018000000000000_4018000000000000_3ff0000000000000 -4024000000000000_4018000000000000_400aaaaaaaaaaaab -4032000000000000_4018000000000000_4018000000000000 -4041000000000000_4018000000000000_4026aaaaaaaaaaab -405c000000000000_4018000000000000_4032aaaaaaaaaaab -406e000000000000_4018000000000000_4044000000000000 -407ffff583a53b8e_4018000000000000_4055554e57c37d09 -408199999999999a_4018000000000000_4067777777777778 -4093333333333333_4018000000000000_4079999999999999 -40a028f5c28f5c29_4018000000000000_40858bf258bf258c -40b004189374bc6a_4018000000000000_40955acb6f46508d -40c00068db8bac71_4018000000000000_40a555e124ba3b41 -40dd1745d1745d17_4018000000000000_40b364d9364d9365 -40e5555555555555_4018000000000000_40cc71c71c71c71c -40f999999999999a_4018000000000000_40d1111111111111 -410c71c71c71c71c_4018000000000000_40e2f684bda12f68 -4000000000000000_4024000000000000_3fd999999999999a -4018000000000000_4024000000000000_3fe3333333333333 -4024000000000000_4024000000000000_3ff0000000000000 -4032000000000000_4024000000000000_400ccccccccccccd -4041000000000000_4024000000000000_401b333333333333 -405c000000000000_4024000000000000_4026666666666666 -406e000000000000_4024000000000000_4038000000000000 -407ffff583a53b8e_4024000000000000_40499991361dc93e -408199999999999a_4024000000000000_405c28f5c28f5c2a -4093333333333333_4024000000000000_406eb851eb851eb8 -40a028f5c28f5c29_4024000000000000_4079db22d0e56042 -40b004189374bc6a_4024000000000000_4089a027525460aa -40c00068db8bac71_4024000000000000_40999a415f45e0b5 -40dd1745d1745d17_4024000000000000_40a745d1745d1746 -40e5555555555555_4024000000000000_40b1111111111111 -40f999999999999a_4024000000000000_40c47ae147ae147b -410c71c71c71c71c_4024000000000000_40d6c16c16c16c16 -4000000000000000_4032000000000000_3fcc71c71c71c71c -4018000000000000_4032000000000000_3fd5555555555555 -4024000000000000_4032000000000000_3fe1c71c71c71c72 -4032000000000000_4032000000000000_3ff0000000000000 -4041000000000000_4032000000000000_400e38e38e38e38e -405c000000000000_4032000000000000_4018e38e38e38e39 -406e000000000000_4032000000000000_402aaaaaaaaaaaab -407ffff583a53b8e_4032000000000000_403c71bdca59fc0c -408199999999999a_4032000000000000_404f49f49f49f4a0 -4093333333333333_4032000000000000_4051111111111111 -40a028f5c28f5c29_4032000000000000_406cba9876543210 -40b004189374bc6a_4032000000000000_407c790f3f086b67 -40c00068db8bac71_4032000000000000_408c7281864da457 -40dd1745d1745d17_4032000000000000_4099dbcc48676f31 -40e5555555555555_4032000000000000_40a2f684bda12f68 -40f999999999999a_4032000000000000_40b6c16c16c16c17 -410c71c71c71c71c_4032000000000000_40c948b0fcd6e9e0 -4000000000000000_4041000000000000_3fbe1e1e1e1e1e1e -4018000000000000_4041000000000000_3fc6969696969697 -4024000000000000_4041000000000000_3fd2d2d2d2d2d2d3 -4032000000000000_4041000000000000_3fe0f0f0f0f0f0f1 -4041000000000000_4041000000000000_3ff0000000000000 -405c000000000000_4041000000000000_400a5a5a5a5a5a5a -406e000000000000_4041000000000000_401c3c3c3c3c3c3c -407ffff583a53b8e_4041000000000000_402e1e143faa9268 -408199999999999a_4041000000000000_4030909090909091 -4093333333333333_4041000000000000_4042121212121212 -40a028f5c28f5c29_4041000000000000_405e6b3804d19e6b -40b004189374bc6a_4041000000000000_406e25d3e863448b -40c00068db8bac71_4041000000000000_407e1ee37f25085c -40dd1745d1745d17_4041000000000000_408b6132a7041b61 -40e5555555555555_4041000000000000_4094141414141414 -40f999999999999a_4041000000000000_40a8181818181818 -410c71c71c71c71c_4041000000000000_40bac5701ac5701a -4000000000000000_405c000000000000_3fa2492492492492 -4018000000000000_405c000000000000_3fbb6db6db6db6db -4024000000000000_405c000000000000_3fc6db6db6db6db7 -4032000000000000_405c000000000000_3fd4924924924925 -4041000000000000_405c000000000000_3fe36db6db6db6db -405c000000000000_405c000000000000_3ff0000000000000 -406e000000000000_405c000000000000_4001249249249249 -407ffff583a53b8e_405c000000000000_4012491e945e6b2d -408199999999999a_405c000000000000_40241d41d41d41d5 -4093333333333333_405c000000000000_4035f15f15f15f16 -40a028f5c28f5c29_405c000000000000_404277f44c118de6 -40b004189374bc6a_405c000000000000_40524dd2f1a9fbe7 -40c00068db8bac71_405c000000000000_4062499c689fa081 -40dd1745d1745d17_405c000000000000_40709f959c427e56 -40e5555555555555_405c000000000000_4088618618618618 -40f999999999999a_405c000000000000_409d41d41d41d41e -410c71c71c71c71c_405c000000000000_40a0410410410410 -4000000000000000_406e000000000000_3f91111111111111 -4018000000000000_406e000000000000_3fa999999999999a -4024000000000000_406e000000000000_3fb5555555555555 -4032000000000000_406e000000000000_3fc3333333333333 -4041000000000000_406e000000000000_3fd2222222222222 -405c000000000000_406e000000000000_3fedddddddddddde -406e000000000000_406e000000000000_3ff0000000000000 -407ffff583a53b8e_406e000000000000_4001110b796930d4 -408199999999999a_406e000000000000_4012c5f92c5f92c6 -4093333333333333_406e000000000000_40247ae147ae147b -40a028f5c28f5c29_406e000000000000_40313cc1e098ead6 -40b004189374bc6a_406e000000000000_4041156f8c384071 -40c00068db8bac71_406e000000000000_40511180ea2e95ce -40dd1745d1745d17_406e000000000000_406f07c1f07c1f07 -40e5555555555555_406e000000000000_4076c16c16c16c16 -40f999999999999a_406e000000000000_408b4e81b4e81b4f -410c71c71c71c71c_406e000000000000_409e573ac901e573 -4000000000000000_407ffff583a53b8e_3f8000053e2f1a08 -4018000000000000_407ffff583a53b8e_3f980007dd46a70b -4024000000000000_407ffff583a53b8e_3fa400068dbae089 -4032000000000000_407ffff583a53b8e_3fb20005e5f4fd48 -4041000000000000_407ffff583a53b8e_3fc1000592120ba8 -405c000000000000_407ffff583a53b8e_3fdc00092cd26d8d -406e000000000000_407ffff583a53b8e_3fee0009d49850ce -407ffff583a53b8e_407ffff583a53b8e_3ff0000000000000 -408199999999999a_407ffff583a53b8e_4001999f5e009ca2 -4093333333333333_407ffff583a53b8e_401333397dd21f3c -40a028f5c28f5c29_407ffff583a53b8e_402028fb0e2a73e4 -40b004189374bc6a_407ffff583a53b8e_4030041dd2fb6fd0 -40c00068db8bac71_407ffff583a53b8e_4040006e19dd229c -40dd1745d1745d17_407ffff583a53b8e_405d174f59ca00c8 -40e5555555555555_407ffff583a53b8e_4065555c52e9780a -40f999999999999a_407ffff583a53b8e_407999a1fd1829a6 -410c71c71c71c71c_407ffff583a53b8e_408c71d06e8ca00d -4000000000000000_408199999999999a_3f7d1745d1745d17 -4018000000000000_408199999999999a_3f85d1745d1745d1 -4024000000000000_408199999999999a_3f922e8ba2e8ba2e -4032000000000000_408199999999999a_3fa05d1745d1745d -4041000000000000_408199999999999a_3fbee8ba2e8ba2e8 -405c000000000000_408199999999999a_3fc9745d1745d174 -406e000000000000_408199999999999a_3fdb45d1745d1745 -407ffff583a53b8e_408199999999999a_3fed173c4921d90c -408199999999999a_408199999999999a_3ff0000000000000 -4093333333333333_408199999999999a_4001745d1745d174 -40a028f5c28f5c29_408199999999999a_401d61bed61bed61 -40b004189374bc6a_408199999999999a_402d1eb851eb851d -40c00068db8bac71_408199999999999a_403d180477e6ade4 -40dd1745d1745d17_408199999999999a_404a723f789854a0 -40e5555555555555_408199999999999a_405364d9364d9364 -40f999999999999a_408199999999999a_406745d1745d1746 -410c71c71c71c71c_408199999999999a_4079dbcc48676f30 -4000000000000000_4093333333333333_3f6aaaaaaaaaaaab -4018000000000000_4093333333333333_3f74000000000000 -4024000000000000_4093333333333333_3f80aaaaaaaaaaab -4032000000000000_4093333333333333_3f9e000000000000 -4041000000000000_4093333333333333_3fac555555555556 -405c000000000000_4093333333333333_3fb7555555555556 -406e000000000000_4093333333333333_3fc9000000000000 -407ffff583a53b8e_4093333333333333_3fdaaaa1edb45c4c -408199999999999a_4093333333333333_3fed555555555556 -4093333333333333_4093333333333333_3ff0000000000000 -40a028f5c28f5c29_4093333333333333_400aeeeeeeeeeeef -40b004189374bc6a_4093333333333333_401ab17e4b17e4b1 -40c00068db8bac71_4093333333333333_402aab596de8ca12 -40dd1745d1745d17_4093333333333333_40383e0f83e0f83e -40e5555555555555_4093333333333333_4041c71c71c71c72 -40f999999999999a_4093333333333333_4055555555555556 -410c71c71c71c71c_4093333333333333_4067b425ed097b42 -4000000000000000_40a028f5c28f5c29_3f5faee41e6a7498 -4018000000000000_40a028f5c28f5c29_3f67c32b16cfd772 -4024000000000000_40a028f5c28f5c29_3f73cd4e930288df -4032000000000000_40a028f5c28f5c29_3f81d260511be196 -4041000000000000_40a028f5c28f5c29_3f90d4e930288df1 -405c000000000000_40a028f5c28f5c29_3fabb9079a9d2605 -406e000000000000_40a028f5c28f5c29_3fbdb3f5dc83cd4f -407ffff583a53b8e_40a028f5c28f5c29_3fcfaed9bca398bf -408199999999999a_40a028f5c28f5c29_3fd16cfd7720f354 -4093333333333333_40a028f5c28f5c29_3fe30288df0cac5b -40a028f5c28f5c29_40a028f5c28f5c29_3ff0000000000000 -40b004189374bc6a_40a028f5c28f5c29_400fb70081c635bb -40c00068db8bac71_40a028f5c28f5c29_401fafb3c1f3a182 -40dd1745d1745d17_40a028f5c28f5c29_402ccd899003afd0 -40e5555555555555_40a028f5c28f5c29_40351f42bef1a310 -40f999999999999a_40a028f5c28f5c29_404958b67ebb907a -410c71c71c71c71c_40a028f5c28f5c29_405c29ae53ecd96a -4000000000000000_40b004189374bc6a_3f4ff7d0f16c2e0a -4018000000000000_40b004189374bc6a_3f57f9dcb5112287 -4024000000000000_40b004189374bc6a_3f63fae296e39cc6 -4032000000000000_40b004189374bc6a_3f71fb6587ccd9e5 -4041000000000000_40b004189374bc6a_3f80fba700417875 -405c000000000000_40b004189374bc6a_3f9bf8d6d33ea848 -406e000000000000_40b004189374bc6a_3fadf853e2556b29 -407ffff583a53b8e_40b004189374bc6a_3fbff7c677bfebb5 -408199999999999a_40b004189374bc6a_3fc1951951951953 -4093333333333333_40b004189374bc6a_3fd32e4a2a741b9f -40a028f5c28f5c29_40b004189374bc6a_3fe024d3c19930d9 -40b004189374bc6a_40b004189374bc6a_3ff0000000000000 -40c00068db8bac71_40b004189374bc6a_400ff8a272e15ca2 -40dd1745d1745d17_40b004189374bc6a_401d0fd53890e409 -40e5555555555555_40b004189374bc6a_40254fe0a0f2c95b -40f999999999999a_40b004189374bc6a_4039930d8df024d5 -410c71c71c71c71c_40b004189374bc6a_404c6a80d6990c7a -4000000000000000_40c00068db8bac71_3f3fff2e4e46e7a8 -4018000000000000_40c00068db8bac71_3f47ff62bab52dbe -4024000000000000_40c00068db8bac71_3f53ff7cf0ec50c9 -4032000000000000_40c00068db8bac71_3f61ff8a0c07e24f -4041000000000000_40c00068db8bac71_3f70ff909995ab11 -405c000000000000_40c00068db8bac71_3f8bff48847e0ab3 -406e000000000000_40c00068db8bac71_3f9dff3b6962792e -407ffff583a53b8e_40c00068db8bac71_3fafff23d230d9a4 -408199999999999a_40c00068db8bac71_3fb1992644a6ff6a -4093333333333333_40c00068db8bac71_3fc332b5622a8afe -40a028f5c28f5c29_40c00068db8bac71_3fd0288bdd4a34fd -40b004189374bc6a_40c00068db8bac71_3fe003af9fc0ed8b -40c00068db8bac71_40c00068db8bac71_3ff0000000000000 -40dd1745d1745d17_40c00068db8bac71_400d16872fe35e3c -40e5555555555555_40c00068db8bac71_401554c989849a70 -40f999999999999a_40c00068db8bac71_402998f1d838b954 -410c71c71c71c71c_40c00068db8bac71_403c710cb75b7895 -4000000000000000_40dd1745d1745d17_3f2199999999999a -4018000000000000_40dd1745d1745d17_3f3a666666666667 -4024000000000000_40dd1745d1745d17_3f46000000000000 -4032000000000000_40dd1745d1745d17_3f53cccccccccccd -4041000000000000_40dd1745d1745d17_3f62b33333333333 -405c000000000000_40dd1745d1745d17_3f7ecccccccccccd -406e000000000000_40dd1745d1745d17_3f80800000000000 -407ffff583a53b8e_40dd1745d1745d17_3f919993d5347a5b -408199999999999a_40dd1745d1745d17_3fa35c28f5c28f5d -4093333333333333_40dd1745d1745d17_3fb51eb851eb851f -40a028f5c28f5c29_40dd1745d1745d17_3fc1c6a7ef9db22d -40b004189374bc6a_40dd1745d1745d17_3fd19e1b089a0275 -40c00068db8bac71_40dd1745d1745d17_3fe19a0cf1800a7c -40dd1745d1745d17_40dd1745d1745d17_3ff0000000000000 -40e5555555555555_40dd1745d1745d17_4007777777777777 -40f999999999999a_40dd1745d1745d17_401c28f5c28f5c2a -410c71c71c71c71c_40dd1745d1745d17_402f49f49f49f49f -4000000000000000_40e5555555555555_3f18000000000000 -4018000000000000_40e5555555555555_3f22000000000000 -4024000000000000_40e5555555555555_3f3e000000000000 -4032000000000000_40e5555555555555_3f4b000000000000 -4041000000000000_40e5555555555555_3f59800000000000 -405c000000000000_40e5555555555555_3f65000000000000 -406e000000000000_40e5555555555555_3f76800000000000 -407ffff583a53b8e_40e5555555555555_3f87fff822bbecab -408199999999999a_40e5555555555555_3f9a666666666667 -4093333333333333_40e5555555555555_3faccccccccccccd -40a028f5c28f5c29_40e5555555555555_3fb83d70a3d70a3e -40b004189374bc6a_40e5555555555555_3fc80624dd2f1a9f -40c00068db8bac71_40e5555555555555_3fd8009d495182aa -40dd1745d1745d17_40e5555555555555_3fe5d1745d1745d2 -40e5555555555555_40e5555555555555_3ff0000000000000 -40f999999999999a_40e5555555555555_4003333333333334 -410c71c71c71c71c_40e5555555555555_4015555555555555 -4000000000000000_40f999999999999a_3f04000000000000 -4018000000000000_40f999999999999a_3f1e000000000000 -4024000000000000_40f999999999999a_3f29000000000000 -4032000000000000_40f999999999999a_3f36800000000000 -4041000000000000_40f999999999999a_3f45400000000000 -405c000000000000_40f999999999999a_3f51800000000000 -406e000000000000_40f999999999999a_3f62c00000000000 -407ffff583a53b8e_40f999999999999a_3f73fff972474538 -408199999999999a_40f999999999999a_3f86000000000000 -4093333333333333_40f999999999999a_3f97ffffffffffff -40a028f5c28f5c29_40f999999999999a_3fa4333333333333 -40b004189374bc6a_40f999999999999a_3fb4051eb851eb84 -40c00068db8bac71_40f999999999999a_3fc40083126e978d -40dd1745d1745d17_40f999999999999a_3fd22e8ba2e8ba2e -40e5555555555555_40f999999999999a_3feaaaaaaaaaaaaa -40f999999999999a_40f999999999999a_3ff0000000000000 -410c71c71c71c71c_40f999999999999a_4001c71c71c71c71 -4000000000000000_410c71c71c71c71c_3ef2000000000000 -4018000000000000_410c71c71c71c71c_3f0b000000000000 -4024000000000000_410c71c71c71c71c_3f16800000000000 -4032000000000000_410c71c71c71c71c_3f24400000000000 -4041000000000000_410c71c71c71c71c_3f33200000000000 -405c000000000000_410c71c71c71c71c_3f4f800000000000 -406e000000000000_410c71c71c71c71c_3f50e00000000000 -407ffff583a53b8e_410c71c71c71c71c_3f61fffa1a0cf180 -408199999999999a_410c71c71c71c71c_3f73ccccccccccce -4093333333333333_410c71c71c71c71c_3f8599999999999a -40a028f5c28f5c29_410c71c71c71c71c_3f922e147ae147ae -40b004189374bc6a_410c71c71c71c71c_3fa2049ba5e353f8 -40c00068db8bac71_410c71c71c71c71c_3fb20075f6fd21ff -40dd1745d1745d17_410c71c71c71c71c_3fc05d1745d1745d -40e5555555555555_410c71c71c71c71c_3fd8000000000000 -40f999999999999a_410c71c71c71c71c_3fecccccccccccce -410c71c71c71c71c_410c71c71c71c71c_3ff0000000000000 diff --git a/pipelined/testbench/testbench-coremark_bare.sv b/pipelined/testbench/testbench-coremark_bare.sv deleted file mode 100644 index 6bde61db4..000000000 --- a/pipelined/testbench/testbench-coremark_bare.sv +++ /dev/null @@ -1,145 +0,0 @@ -/////////////////////////////////////////// -// testbench-imperas.sv -// -// Written: David_Harris@hmc.edu 9 January 2021 -// Modified: -// -// Purpose: Wally Testbench and helper modules -// Applies test programs from the Imperas suite -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" -module testbench(); - logic clk; - logic reset, reset_ext; - int test, i, errors, totalerrors; - logic [31:0] sig32[10000:0]; - logic [`XLEN-1:0] signature[10000:0]; - logic [`XLEN-1:0] testadr; - string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [`XLEN-1:0] meminit; - string tests[]; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; - logic [31:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - - // pick tests based on modes supported - initial -// tests = {"../../tests/imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"}; - tests = {"../../benchmarks/riscv-coremark/work/coremark.bare.riscv.memfile", "1000"}; - string signame, memfilename; - logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; - logic UARTSin, UARTSout; - logic SDCCLK; - logic SDCCmdIn; - logic SDCCmdOut; - logic SDCCmdOE; - logic [3:0] SDCDatIn; - - logic HREADY; - logic HSELEXT; - - assign SDCmd = 1'bz; - assign SDCDat = 4'bz; - - - // instantiate device to be tested - assign GPIOPinsIn = 0; - assign UARTSin = 1; - assign HREADYEXT = 1; - assign HRESPEXT = 0; - assign HRDATAEXT = 0; - wallypipelinedsoc dut(.clk, .reset_ext, .reset(), .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, - .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, - .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); - - logic [31:0] InstrW; - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); - - // Track names of instructions - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.FinalInstrRawF, - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - dut.core.ifu.InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); -/* - instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE, - dut.core.ifu.icache.controller.FinalInstrRawF, - dut.core.ifu.InstrD, dut.core.ifu.InstrE, - dut.core.ifu.InstrM, InstrW, - InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); -*/ - logic [`XLEN-1:0] PCW; - flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, dut.core.ifu.PCM, PCW); - - // initialize tests - integer j; - initial - begin - totalerrors = 0; - // read test vectors into memory - memfilename = tests[0]; - $readmemh(memfilename, dut.uncore.ram.ram.RAM); - //for(j=268437955; j < 268566528; j = j+1) - //dut.uncore.ram.RAM[j] = 64'b0; -// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr"; -// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab"; - //dut.uncore.ram.RAM[268437713]=64'b1; - reset_ext = 1; # 22; reset_ext = 0; - end - // generate clock to sequence tests - always - begin - clk = 1; # 5; clk = 0; # 5; - end - always @(negedge clk) - begin - if (dut.core.priv.priv.ecallM) begin - #20; - $display("Code ended with ebreakM"); - $stop; - end - end - - initial begin -// $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.memory); -// $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.memory); - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); - - end - - - -endmodule -/* verilator lint_on STMTDLY */ -/* verilator lint_on WIDTH */ diff --git a/pipelined/testbench/testbench-f64.sv b/pipelined/testbench/testbench-f64.sv deleted file mode 100755 index a0c7e6a31..000000000 --- a/pipelined/testbench/testbench-f64.sv +++ /dev/null @@ -1,123 +0,0 @@ -// testbench -module testbench (); - - logic [63:0] op1; - logic [63:0] op2; - logic [2:0] FOpCtrlE; - logic [2:0] FrmE; - logic op_type; - logic FmtE; - logic OvEn; - logic UnEn; - - logic XSgnE, YSgnE, ZSgnE; - logic XSgnM, YSgnM; - logic [10:0] XExpE, YExpE, ZExpE; - logic [10:0] XExpM, YExpM, ZExpM; - logic [52:0] XManE, YManE, ZManE; - logic [52:0] XManM, YManM, ZManM; - - logic [10:0] BiasE; - logic XNaNE, YNaNE, ZNaNE; - logic XNaNM, YNaNM, ZNaNM; - logic XSNaNE, YSNaNE, ZSNaNE; - logic XSNaNM, YSNaNM, ZSNaNM; - logic XDenormE, YDenormE, ZDenormE; - logic XZeroE, YZeroE, ZZeroE; - logic XZeroM, YZeroM, ZZeroM; - logic XInfE, YInfE, ZInfE; - logic XInfM, YInfM, ZInfM; - logic XExpMaxE; - logic XNormE; - logic FDivBusyE; - - logic start; - logic reset; - - logic XDenorm; - logic YDenorm; - logic [63:0] AS_Result; - logic [4:0] Flags; - logic Denorm; - logic done; - - logic clk; - logic [63:0] yexpected; - logic [63:0] vectornum, errors; // bookkeeping variables - logic [199:0] testvectors[50000:0]; // array of testvectors - logic [7:0] flags_expected; - - integer handle3; - integer desc3; - - // instantiate device under test - unpack unpack(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE, - .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, - .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, - .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE); - fpdiv fdivsqrt (.op1, .op2, .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]), - .reset, .clk, .start, .P(~FmtE), .OvEn(1'b0), .UnEn(1'b0), - .XNaNQ(XNaNE), .YNaNQ(YNaNE), .XInfQ(XInfE), .YInfQ(YInfE), .XZeroQ(XZeroE), .YZeroQ(YZeroE), - .FDivBusyE, .done(done), .AS_Result(AS_Result), .Flags(Flags)); - - - // current fpdivsqrt does not operation on denorms yet - assign Denorm = XDenormE | YDenormE | Flags[3]; - - // generate clock to sequence tests - always - begin - clk = 1; # 5; clk = 0; # 5; - end - - initial - begin - handle3 = $fopen("f64_div_rne.out"); - $readmemh("../testbench/fp/vectors/f64_div_rne.tv", testvectors); - vectornum = 0; errors = 0; - start = 1'b0; - // reset - reset = 1; #27; reset = 0; - end - - initial - begin - desc3 = handle3; - // Operation (if applicable) - #0 op_type = 1'b0; - // Precision (32-bit or 64-bit) - #0 FmtE = 1'b1; - // From fctrl logic to dictate operation - #0 FOpCtrlE = 3'b000; - // Rounding Mode - #0 FrmE = 3'b000; - // Trap masking (n/a for RISC-V) - #0 OvEn = 1'b0; - #0 UnEn = 1'b0; - end - - always @(posedge clk) - begin - if (~reset) - begin - #0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum]; - #50 start = 1'b1; - repeat (2) - @(posedge clk); - // deassert start after 2 cycles - start = 1'b0; - repeat (10) - @(posedge clk); - $fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected)); - vectornum = vectornum + 1; - if (testvectors[vectornum] === 200'bx) begin - $display("%d tests completed", vectornum); - $finish; - end - end // if (~reset) - $display("%d vectors processed", vectornum); - end // always @ (posedge clk) - -endmodule // tb - - diff --git a/pipelined/testbench/testbench-fp.sv b/pipelined/testbench/testbench-fp.sv new file mode 100644 index 000000000..88190aad2 --- /dev/null +++ b/pipelined/testbench/testbench-fp.sv @@ -0,0 +1,1297 @@ +/////////////////////////////////////////// +// +// Written: me@KatherineParry.com +// Modified: 7/5/2022 +// +// Purpose: Testbench for Testfloat +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" +`include "tests-fp.vh" + +// steps to run FMA Tests +// 1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh +// 2) go to riscv-wally/pipelined/testbench/fp/Tests +// 3) run ./sim-fma-batch +module testbenchfp; + parameter TEST="none"; + + string Tests[]; // list of tests to be run + logic [2:0] OpCtrl[]; // list of op controls + logic [2:0] Unit[]; // list of units being tested + logic WriteInt[]; // Is being written to integer resgiter + logic [2:0] Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100 + logic [1:0] Fmt[]; // list of formats for the other units + + + logic clk=0; + logic [31:0] TestNum=0; // index for the test + logic [31:0] OpCtrlNum=0; // index for OpCtrl + logic [31:0] errors=0; // how many errors + logic [31:0] VectorNum=0; // index for test vector + logic [31:0] FrmNum=0; // index for rounding mode + logic [`FLEN*4+7:0] TestVectors[6133248:0]; // list of test vectors + + logic [1:0] FmtVal; // value of the current Fmt + logic [2:0] UnitVal, OpCtrlVal, FrmVal; // vlaue of the currnet Unit/OpCtrl/FrmVal + logic WriteIntVal; // value of the current WriteInt + logic [`FLEN-1:0] X, Y, Z; // inputs read from TestFloat + logic [`XLEN-1:0] SrcA; // integer input + logic [`FLEN-1:0] Ans; // correct answer from TestFloat + logic [`FLEN-1:0] Res; // result from other units + logic [4:0] AnsFlg; // correct flags read from testfloat + logic [4:0] ResFlg, Flg; // Result flags + logic [`FMTBITS-1:0] ModFmt; // format - 10 = half, 00 = single, 01 = double, 11 = quad + logic [`FLEN-1:0] FpRes, FpCmpRes; // Results from each unit + logic [`XLEN-1:0] IntRes, CmpRes; // Results from each unit + logic [4:0] FmaFlg, CvtFlg, DivFlg, CmpFlg; // Outputed flags + logic AnsNaN, ResNaN, NaNGood; + logic Xs, Ys, Zs; // sign of the inputs + logic [`NE-1:0] Xe, Ye, Ze; // exponent of the inputs + logic [`NF:0] Xm, Ym, Zm; // mantissas of the inputs + logic XNaN, YNaN, ZNaN; // is the input NaN + logic XSNaN, YSNaN, ZSNaN; // is the input a signaling NaN + logic XDenorm, ZDenorm; // is the input denormalized + logic XInf, YInf, ZInf; // is the input infinity + logic XZero, YZero, ZZero; // is the input zero + logic XExpMax, YExpMax, ZExpMax; // is the input's exponent all ones + logic [`CVTLEN-1:0] CvtLzcInE; // input to the Leading Zero Counter (priority encoder) + logic IntZero; + logic CvtResSgnE; + logic [`NE:0] CvtCalcExpE; // the calculated expoent + logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by + logic [`DIVb-(`RADIX/4):0] Quot; + logic CvtResDenormUfE; + logic [`DURLEN-1:0] EarlyTermShift; + logic DivStart, DivBusy; + logic reset = 1'b0; + logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; + logic [`DURLEN-1:0] Dur; + + // in-between FMA signals + logic Mult; + logic Ss; + logic [`NE+1:0] Pe; + logic [`NE+1:0] Se; + logic ZmSticky; + logic KillProd; + logic [$clog2(3*`NF+7)-1:0] SCnt; + logic [3*`NF+5:0] Sm; + logic InvA; + logic NegSum; + logic As; + logic Ps; + logic DivSticky; + logic DivDone; + logic DivNegSticky; + logic [`NE+1:0] DivCalcExp; + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||| ||||||| ||| ||||||| |||||||| ||||||||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // select tests relevent to the specified configuration + // cvtint - test integer conversion unit (fcvtint) + // cvtfp - test floating-point conversion unit (fcvtfp) + // cmp - test comparison unit's LT, LE, EQ opperations (fcmp) + // add - test addition + // sub - test subtraction + // div - test division + // sqrt - test square root + // all - test all of the above + initial begin + $display("TEST is %s", TEST); + if (`Q_SUPPORTED) begin // if Quad percision is supported + if (TEST === "cvtint"| TEST === "all") begin // if testing integer conversion + // add the 128-bit cvtint tests to the to-be-tested list + Tests = {Tests, f128rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported add their conversions + Tests = {Tests, f128rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if the floating-point conversions are being tested + if(`D_SUPPORTED) begin // if double precision is supported + // add the 128 <-> 64 bit conversions to the to-be-tested list + Tests = {Tests, f128f64cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b01, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if(`F_SUPPORTED) begin // if single precision is supported + // add the 128 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f128f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 128 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f128f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b11}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b11}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin// if comparisons are being tested + // add the compare tests/op-ctrls/unit/fmt + Tests = {Tests, f128cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the addition tests/op-ctrls/unit/fmt + Tests = {Tests, f128add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the subtraction tests/op-ctrls/unit/fmt + Tests = {Tests, f128sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the multiply tests/op-ctrls/unit/fmt + Tests = {Tests, f128mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the divide tests/op-ctrls/unit/fmt + Tests = {Tests, f128div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tested + // add the square-root tests/op-ctrls/unit/fmt + Tests = {Tests, f128sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fused-mutliply-add is being tested + Tests = {Tests, f128fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b11}; + end + end + end + if (`D_SUPPORTED) begin // if double precision is supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f64rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + if (`XLEN == 64) begin // if 64-bit integers are being supported + Tests = {Tests, f64rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversions are being tested + if(`F_SUPPORTED) begin // if single precision is supported + // add the 64 <-> 32 bit conversions to the to-be-tested list + Tests = {Tests, f64f32cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b00, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if(`ZFH_SUPPORTED) begin // if half precision is supported + // add the 64 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f64f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b01}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b01}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if square-root is being tessted + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f64sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + if (TEST === "fma" | TEST === "all") begin // if the fused multiply add is being tested + Tests = {Tests, f64fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b01}; + end + end + end + if (`F_SUPPORTED) begin // if single precision being supported + if (TEST === "cvtint"| TEST === "all") begin // if integer conversion is being tested + Tests = {Tests, f32rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f32rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (TEST === "cvtfp" | TEST === "all") begin // if floating point conversion is being tested + if(`ZFH_SUPPORTED) begin + // add the 32 <-> 16 bit conversions to the to-be-tested list + Tests = {Tests, f32f16cvt}; + // add the op-ctrls (i.e. the format of the result) + OpCtrl = {OpCtrl, 3'b10, 3'b00}; + WriteInt = {WriteInt, 1'b0, 1'b0}; + // add the unit being tested and fmt (input format) + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b00}; + end + for(int i = 0; i<5; i++) begin + Unit = {Unit, `CVTFPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparision is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtration is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiply is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f32sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + Tests = {Tests, f32fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b00}; + end + end + end + if (`ZFH_SUPPORTED) begin // if half precision supported + if (TEST === "cvtint"| TEST === "all") begin // if in conversions are being tested + Tests = {Tests, f16rv32cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UI_OPCTRL, `FROM_I_OPCTRL, `TO_UI_OPCTRL, `TO_I_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + if (`XLEN == 64) begin // if 64-bit integers are supported + Tests = {Tests, f16rv64cvtint}; + // add the op-codes for these tests to the op-code list + OpCtrl = {OpCtrl, `FROM_UL_OPCTRL, `FROM_L_OPCTRL, `TO_UL_OPCTRL, `TO_L_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b1, 1'b1}; + // add what unit is used and the fmt to their lists (one for each test) + for(int i = 0; i<20; i++) begin + Unit = {Unit, `CVTINTUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + if (TEST === "cmp" | TEST === "all") begin // if comparisions are being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16cmp}; + OpCtrl = {OpCtrl, `EQ_OPCTRL, `LE_OPCTRL, `LT_OPCTRL}; + WriteInt = {WriteInt, 1'b0, 1'b0, 1'b0}; + for(int i = 0; i<15; i++) begin + Unit = {Unit, `CMPUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "add" | TEST === "all") begin // if addition is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16add}; + OpCtrl = {OpCtrl, `ADD_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sub" | TEST === "all") begin // if subtraction is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sub}; + OpCtrl = {OpCtrl, `SUB_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "mul" | TEST === "all") begin // if multiplication is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16mul}; + OpCtrl = {OpCtrl, `MUL_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "div" | TEST === "all") begin // if division is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16div}; + OpCtrl = {OpCtrl, `DIV_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "sqrt" | TEST === "all") begin // if sqrt is being tested + // add the correct tests/op-ctrls/unit/fmt to their lists + Tests = {Tests, f16sqrt}; + OpCtrl = {OpCtrl, `SQRT_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `DIVUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + if (TEST === "fma" | TEST === "all") begin // if fma is being tested + Tests = {Tests, f16fma}; + OpCtrl = {OpCtrl, `FMA_OPCTRL}; + WriteInt = {WriteInt, 1'b0}; + for(int i = 0; i<5; i++) begin + Unit = {Unit, `FMAUNIT}; + Fmt = {Fmt, 2'b10}; + end + end + end + + // check if nothing is being tested + if (Tests.size() == 0) begin + $display("TEST %s not supported in this configuration", TEST); + $stop; + end + end + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||||| |||||||| ||||||||| ||||||| ||||||||| |||||||| ||||||| ||||||||| + // ||| ||| ||| ||| ||| || || ||| ||| ||| ||| + // |||||||| |||||||| ||||||||| || || ||| |||||||| ||||||| ||| + // ||| || ||| ||| ||| || || ||| ||| ||| ||| + // ||| ||| |||||||| ||| ||| ||||||| ||| |||||||| ||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // Read the first test + initial begin + $display("\n\nRunning %s vectors", Tests[TestNum]); + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + // set the test index to 0 + TestNum = 0; + end + + // set a the signals for all tests + always_comb UnitVal = Unit[TestNum]; + always_comb FmtVal = Fmt[TestNum]; + always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; + always_comb WriteIntVal = WriteInt[OpCtrlNum]; + always_comb FrmVal = Frm[FrmNum]; + + // modify the format signal if only 2 percisions supported + // - 1 for the larger precision + // - 0 for the smaller precision + always_comb begin + if(`FMTBITS == 1) ModFmt = FmtVal == `FMT; + else ModFmt = FmtVal; + end + + // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector + readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, + .Xs, .Ys, .Zs, .Unit(UnitVal), + .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal), + .Xm, .Ym, .Zm, .DivStart, + .XNaN, .YNaN, .ZNaN, + .XSNaN, .YSNaN, .ZSNaN, + .XDenorm, .ZDenorm, + .XZero, .YZero, .ZZero, + .XInf, .YInf, .ZInf, .XExpMax, + .X, .Y, .Z); + + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||| ||| ||| ||| ||| + // ||||||| ||||||||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // instantiate devices under test + fma fma(.Xs(Xs), .Ys(Ys), .Zs(Zs), + .Xe(Xe), .Ye(Ye), .Ze(Ze), + .Xm(Xm), .Ym(Ym), .Zm(Zm), + .XZero, .YZero, .ZZero, .Ss, .Se, + .OpCtrl(OpCtrlVal), .Fmt(ModFmt), .Sm, .NegSum, .InvA, .SCnt, .As, .Ps, + .Pe, .ZmSticky, .KillProd); + + postprocess postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]), + .Ze(Ze), .ZDenorm(ZDenorm), .OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp), + .Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivS(DivSticky), .FmaSs(Ss), + .XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResDenormUf(CvtResDenormUfE), + .XZero(XZero), .YZero(YZero), .ZZero(ZZero), .CvtShiftAmt(CvtShiftAmtE), + .XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal), + .XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero, + .FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se), + .FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal), + .PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes)); + + fcvt fcvt (.Xs(Xs), .Xe(Xe), .Xm(Xm), .Int(SrcA), .ToInt(WriteIntVal), + .XZero(XZero), .XDenorm(XDenorm), .OpCtrl(OpCtrlVal), .IntZero, + .Fmt(ModFmt), .Ce(CvtCalcExpE), .ShiftAmt(CvtShiftAmtE), .ResDenormUf(CvtResDenormUfE), .Cs(CvtResSgnE), .LzcIn(CvtLzcInE)); + fcmp fcmp (.Fmt(ModFmt), .OpCtrl(OpCtrlVal), .Xs, .Ys, .Xe, .Ye, + .Xm, .Ym, .XZero, .YZero, .CmpIntRes(CmpRes), + .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes)); + divsqrt divsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]), + .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart), + .StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp), + .EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone); + + assign CmpFlg[3:0] = 0; + + // produce clock + always begin + clk = 1; #5; clk = 0; #5; + end + +/////////////////////////////////////////////////////////////////////////////////////////////// + +// ||||| ||| |||||||||| ||||| ||| +// ||||||| ||| ||| ||| ||||||| ||| +// |||| ||| ||| |||||||||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| ||| ||| ||| ||| |||| ||| ||| +// |||| |||||| ||| ||| |||| |||||| + +/////////////////////////////////////////////////////////////////////////////////////////////// + + //Check if the correct answer and result is a NaN + always_comb begin + if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin + // an integer output can't be a NaN + AnsNaN = 1'b0; + ResNaN = 1'b0; + end + else if (UnitVal === `CVTFPUNIT) begin + case (OpCtrlVal[1:0]) + 4'b11: begin // quad + AnsNaN = &Ans[`Q_LEN-2:`NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`NF]&(|Res[`Q_NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + end + endcase + end + else begin + case (FmtVal) + 4'b11: begin // quad + AnsNaN = &Ans[`Q_LEN-2:`Q_NF]&(|Ans[`Q_NF-1:0]); + ResNaN = &Res[`Q_LEN-2:`Q_NF]&(|Res[`Q_NF-1:0]); + end + 4'b01: begin // double + AnsNaN = &Ans[`D_LEN-2:`D_NF]&(|Ans[`D_NF-1:0]); + ResNaN = &Res[`D_LEN-2:`D_NF]&(|Res[`D_NF-1:0]); + end + 4'b00: begin // single + AnsNaN = &Ans[`S_LEN-2:`S_NF]&(|Ans[`S_NF-1:0]); + ResNaN = &Res[`S_LEN-2:`S_NF]&(|Res[`S_NF-1:0]); + end + 4'b10: begin // half + AnsNaN = &Ans[`H_LEN-2:`H_NF]&(|Ans[`H_NF-1:0]); + ResNaN = &Res[`H_LEN-2:`H_NF]&(|Res[`H_NF-1:0]); + end + endcase + end + end +always_comb begin + // select the result to check + case (UnitVal) + `FMAUNIT: Res = FpRes; + `DIVUNIT: Res = FpRes; + `CMPUNIT: Res = CmpRes; + `CVTINTUNIT: if(WriteIntVal) Res = IntRes; else Res = FpRes; + `CVTFPUNIT: Res = FpRes; + endcase + + // select the flag to check + case (UnitVal) + `FMAUNIT: ResFlg = Flg; + `DIVUNIT: ResFlg = Flg; + `CMPUNIT: ResFlg = CmpFlg; + `CVTINTUNIT: ResFlg = Flg; + `CVTFPUNIT: ResFlg = Flg; + endcase +end + // check results on falling edge of clk + always @(negedge clk) begin + + + // check if the NaN value is good. IEEE754-2019 sections 6.3 and 6.2.3 specify: + // - the sign of the NaN does not matter for the opperations being tested + // - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter + if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT) + case (FmtVal) + 4'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]})) | + (ZNaN&(Res[`Q_LEN-2:0] === {Z[`Q_LEN-2:`Q_NF],1'b1,Z[`Q_NF-2:0]}))); + 4'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]})) | + (ZNaN&(Res[`D_LEN-2:0] === {Z[`D_LEN-2:`D_NF],1'b1,Z[`D_NF-2:0]}))); + 4'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]})) | + (ZNaN&(Res[`S_LEN-2:0] === {Z[`S_LEN-2:`S_NF],1'b1,Z[`S_NF-2:0]}))); + 4'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]})) | + (ZNaN&(Res[`H_LEN-2:0] === {Z[`H_LEN-2:`H_NF],1'b1,Z[`H_NF-2:0]}))); + endcase + else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format + case (OpCtrlVal[1:0]) + 2'b11: NaNGood = (((`IEEE754==0)&AnsNaN&(Res === {1'b0, {`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`Q_LEN-2:0] === {{`Q_NE+1{1'b1}}, {`Q_NF-1{1'b0}}})) | + (AnsNaN&(Res[`Q_LEN-2:0] === Ans[`Q_LEN-2:0])) | + (XNaN&(Res[`Q_LEN-2:0] === {X[`Q_LEN-2:`Q_NF],1'b1,X[`Q_NF-2:0]})) | + (YNaN&(Res[`Q_LEN-2:0] === {Y[`Q_LEN-2:`Q_NF],1'b1,Y[`Q_NF-2:0]}))); + 2'b01: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`D_LEN-1:0] === {1'b0, {`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`D_LEN-2:0] === {{`D_NE+1{1'b1}}, {`D_NF-1{1'b0}}})) | + (AnsNaN&(Res[`D_LEN-2:0] === Ans[`D_LEN-2:0])) | + (XNaN&(Res[`D_LEN-2:0] === {X[`D_LEN-2:`D_NF],1'b1,X[`D_NF-2:0]})) | + (YNaN&(Res[`D_LEN-2:0] === {Y[`D_LEN-2:`D_NF],1'b1,Y[`D_NF-2:0]}))); + 2'b00: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`S_LEN-1:0] === {1'b0, {`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`S_LEN-2:0] === {{`S_NE+1{1'b1}}, {`S_NF-1{1'b0}}})) | + (AnsNaN&(Res[`S_LEN-2:0] === Ans[`S_LEN-2:0])) | + (XNaN&(Res[`S_LEN-2:0] === {X[`S_LEN-2:`S_NF],1'b1,X[`S_NF-2:0]})) | + (YNaN&(Res[`S_LEN-2:0] === {Y[`S_LEN-2:`S_NF],1'b1,Y[`S_NF-2:0]}))); + 2'b10: NaNGood = (((`IEEE754==0)&AnsNaN&(Res[`H_LEN-1:0] === {1'b0, {`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsFlg[4]&(Res[`H_LEN-2:0] === {{`H_NE+1{1'b1}}, {`H_NF-1{1'b0}}})) | + (AnsNaN&(Res[`H_LEN-2:0] === Ans[`H_LEN-2:0])) | + (XNaN&(Res[`H_LEN-2:0] === {X[`H_LEN-2:`H_NF],1'b1,X[`H_NF-2:0]})) | + (YNaN&(Res[`H_LEN-2:0] === {Y[`H_LEN-2:`H_NF],1'b1,Y[`H_NF-2:0]}))); + endcase + else NaNGood = 1'b0; // integers can't be NaNs + + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + // ||| ||| ||| ||| ||| ||| ||| + // ||| |||||||||| ||||||| ||| |||||| + // ||| ||| ||| ||| ||| ||| ||| + // ||||||| ||| ||| ||||||| ||||||| ||| ||| + + /////////////////////////////////////////////////////////////////////////////////////////////// + + // check if result is correct + // - wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage) + if(~((Res === Ans | NaNGood | NaNGood === 1'bx) & (ResFlg === AnsFlg | AnsFlg === 5'bx))&~((DivBusy===1'b1)|DivStart)&(UnitVal !== `CVTINTUNIT)&(UnitVal !== `CMPUNIT)) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + // TestFloat sets the result to all 1's when there is an invalid result, however in + // http://www.jhauser.us/arithmetic/TestFloat-3/doc/TestFloat-general.html it says + // for an unsigned integer result 0 is also okay + + // Testfloat outputs 800... for both the largest integer values for both positive and negitive numbers but + // the riscv spec specifies 2^31-1 for positive values out of range and NaNs ie 7fff... + else if ((UnitVal === `CVTINTUNIT) & ~(((WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&(Res[`XLEN-1:0] === (`XLEN)'(0))) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&OpCtrlVal[1]&(Res[`XLEN-1:0] === {1'b0, {`XLEN-1{1'b1}}})) | + (WriteIntVal&OpCtrlVal[0]&AnsFlg[4]&(~Xs|XNaN)&~OpCtrlVal[1]&(Res[`XLEN-1:0] === {{`XLEN-32{1'b0}}, 1'b0, {31{1'b1}}})) | + (~(WriteIntVal&~OpCtrlVal[0]&AnsFlg[4]&Xs&~XNaN)&(Res === Ans | NaNGood | NaNGood === 1'bx))) & (ResFlg === AnsFlg | AnsFlg === 5'bx))) begin + errors += 1; + $display("There is an error in %s", Tests[TestNum]); + $display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg); + $stop; + end + + if(~(DivBusy|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector + + if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file + + // increment the test + TestNum += 1; + + // clear the vectors + for(int i=0; i<6133248; i++) TestVectors[i] = {`FLEN*4+8{1'bx}}; + // read next files + $readmemh({`PATH, Tests[TestNum]}, TestVectors); + + // set the vector index back to 0 + VectorNum = 0; + // incemet the operation if all the rounding modes have been tested + if(FrmNum === 4) OpCtrlNum += 1; + // increment the rounding mode or loop back to rne + if(FrmNum < 4) FrmNum += 1; + else FrmNum = 0; + + // if no more Tests - finish + if(Tests[TestNum] === "") begin + $display("\nAll Tests completed with %d errors\n", errors); + $stop; + end + + $display("Running %s vectors", Tests[TestNum]); + end + end +endmodule + + + + +module readvectors ( + input logic clk, + input logic [`FLEN*4+7:0] TestVector, + input logic [`FMTBITS-1:0] ModFmt, + input logic [1:0] Fmt, + input logic [2:0] Unit, + input logic [31:0] VectorNum, + input logic [31:0] TestNum, + input logic [2:0] OpCtrl, + output logic [`FLEN-1:0] Ans, + output logic [`XLEN-1:0] SrcA, + output logic [4:0] AnsFlg, + output logic Xs, Ys, Zs, // sign bits of XYZ + output logic [`NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision) + output logic [`NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision) + output logic XNaN, YNaN, ZNaN, // is XYZ a NaN + output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN + output logic XDenorm, ZDenorm, // is XYZ denormalized + output logic XZero, YZero, ZZero, // is XYZ zero + output logic XInf, YInf, ZInf, // is XYZ infinity + output logic XExpMax, + output logic DivStart, + output logic [`FLEN-1:0] X, Y, Z +); + logic XEn, YEn, ZEn; + + // apply test vectors on rising edge of clk + // Format of vectors Inputs(1/2/3)_AnsFlg + always @(VectorNum) begin + #1; + AnsFlg = TestVector[4:0]; + DivStart = 1'b0; + case (Unit) + `FMAUNIT: + case (Fmt) + 2'b11: begin // quad + if(OpCtrl === `FMA_OPCTRL) begin + X = TestVector[8+4*(`Q_LEN)-1:8+3*(`Q_LEN)]; + Y = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Z = TestVector[8+2*(`Q_LEN)-1:8+`Q_LEN]; + end + else begin + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + if(OpCtrl === `MUL_OPCTRL) Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; else Y = {2'b0, {`Q_NE-1{1'b1}}, (`Q_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = 0; else Z = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + end + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+4*(`D_LEN)-1:8+3*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+`D_LEN]}; + end + else begin + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + else Y = {{`FLEN-`D_LEN{1'b1}}, 2'b0, {`D_NE-1{1'b1}}, (`D_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`D_LEN{1'b1}}, {`D_LEN{1'b0}}}; + else Z = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + end + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: if (`S_SUPPORTED)begin // single + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+4*(`S_LEN)-1:8+3*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+`S_LEN]}; + end + else begin + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + else Y = {{`FLEN-`S_LEN{1'b1}}, 2'b0, {`S_NE-1{1'b1}}, (`S_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`S_LEN{1'b1}}, {`S_LEN{1'b0}}}; + else Z = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+(`S_LEN)]}; + end + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + if(OpCtrl === `FMA_OPCTRL) begin + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+4*(`H_LEN)-1:8+3*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+`H_LEN]}; + end + else begin + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + if(OpCtrl === `MUL_OPCTRL) Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + else Y = {{`FLEN-`H_LEN{1'b1}}, 2'b0, {`H_NE-1{1'b1}}, (`H_NF)'(0)}; + if(OpCtrl === `MUL_OPCTRL) Z = {{`FLEN-`H_LEN{1'b1}}, {`H_LEN{1'b0}}}; + else Z = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + end + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + `DIVUNIT: + if(OpCtrl[0]) + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + if (~clk) #5; + DivStart = 1'b1; #10 // one clk cycle + DivStart = 1'b0; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + endcase + else + case (Fmt) + 2'b11: begin // quad + X = TestVector[8+3*(`Q_LEN)-1:8+2*(`Q_LEN)]; + Y = TestVector[8+2*(`Q_LEN)-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + if (~clk) #5; + DivStart = 1'b1; #10 // one clk cycle + DivStart = 1'b0; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+3*(`D_LEN)-1:8+2*(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+2*(`D_LEN)-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+3*(`S_LEN)-1:8+2*(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+2*(`S_LEN)-1:8+1*(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+3*(`H_LEN)-1:8+2*(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+2*(`H_LEN)-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + if (~clk) #5; + DivStart = 1'b1; #10 + DivStart = 1'b0; + end + endcase + `CMPUNIT: + case (Fmt) + 2'b11: begin // quad + X = TestVector[12+2*(`Q_LEN)-1:12+(`Q_LEN)]; + Y = TestVector[12+(`Q_LEN)-1:12]; + Ans = TestVector[8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+2*(`D_LEN)-1:12+(`D_LEN)]}; + Y = {{`FLEN-`D_LEN{1'b1}}, TestVector[12+(`D_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+2*(`S_LEN)-1:12+(`S_LEN)]}; + Y = {{`FLEN-`S_LEN{1'b1}}, TestVector[12+(`S_LEN)-1:12]}; + Ans = TestVector[8]; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+2*(`H_LEN)-1:12+(`H_LEN)]}; + Y = {{`FLEN-`H_LEN{1'b1}}, TestVector[12+(`H_LEN)-1:12]}; + Ans = TestVector[8]; + end + endcase + `CVTFPUNIT: + case (Fmt) + 2'b11: begin // quad + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {TestVector[8+`Q_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {TestVector[8+`Q_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {TestVector[8+`Q_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {TestVector[8+`Q_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b01: if (`D_SUPPORTED)begin // double + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // double + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`D_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b00: if (`S_SUPPORTED)begin // single + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: begin // single + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`S_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + 2'b10: begin // half + case (OpCtrl[1:0]) + 2'b11: begin // quad + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`Q_LEN-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: if (`D_SUPPORTED)begin // double + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`D_LEN-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b00: if (`S_SUPPORTED)begin // single + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`S_LEN-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // half + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`H_LEN+`H_LEN-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + endcase + end + endcase + + `CVTINTUNIT: + case (Fmt) + 2'b11: begin // quad + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> quad + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`Q_LEN+`XLEN-1:8+(`Q_LEN)]; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b10: begin // int -> quad + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`Q_LEN+32-1]}}, TestVector[8+`Q_LEN+32-1:8+(`Q_LEN)]}; + Ans = TestVector[8+(`Q_LEN-1):8]; + end + 2'b01: begin // quad -> long + X = {TestVector[8+`XLEN+`Q_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // quad -> int + X = {TestVector[8+32+`Q_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b01: if (`D_SUPPORTED)begin // double + // {Int->Fp?, is the integer a long} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> double + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`D_LEN+`XLEN-1:8+(`D_LEN)]; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b10: begin // int -> double + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`D_LEN+32-1]}}, TestVector[8+`D_LEN+32-1:8+(`D_LEN)]}; + Ans = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+(`D_LEN-1):8]}; + end + 2'b01: begin // double -> long + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+`XLEN+`D_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // double -> int + X = {{`FLEN-`D_LEN{1'b1}}, TestVector[8+32+`D_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b00: if (`S_SUPPORTED)begin // single + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> single + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`S_LEN+`XLEN-1:8+(`S_LEN)]; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b10: begin // int -> single + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`S_LEN+32-1]}}, TestVector[8+`S_LEN+32-1:8+(`S_LEN)]}; + Ans = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+(`S_LEN-1):8]}; + end + 2'b01: begin // single -> long + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+`XLEN+`S_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // single -> int + X = {{`FLEN-`S_LEN{1'b1}}, TestVector[8+32+`S_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]}; + end + endcase + end + 2'b10: begin // half + // {is the integer a long, is the opperation to an integer} + casex ({OpCtrl[2:1]}) + 2'b11: begin // long -> half + X = {`FLEN{1'bx}}; + SrcA = TestVector[8+`H_LEN+`XLEN-1:8+(`H_LEN)]; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + 2'b10: begin // int -> half + // correctly sign extend the integer depending on if it's a signed/unsigned test + X = {`FLEN{1'bx}}; + SrcA = {{`XLEN-32{TestVector[8+`H_LEN+32-1]}}, TestVector[8+`H_LEN+32-1:8+(`H_LEN)]}; + Ans = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+(`H_LEN-1):8]}; + end + 2'b01: begin // half -> long + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+`XLEN+`H_LEN-1:8+(`XLEN)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {TestVector[8+(`XLEN-1):8]}; + end + 2'b00: begin // half -> int + X = {{`FLEN-`H_LEN{1'b1}}, TestVector[8+32+`H_LEN-1:8+(32)]}; + SrcA = {`XLEN{1'bx}}; + Ans = {{`XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]}; + end + endcase + end + endcase + endcase + end + + assign XEn = ~((Unit == `CVTINTUNIT)&OpCtrl[2]); + assign YEn = ~((Unit == `CVTINTUNIT)|(Unit == `CVTFPUNIT)|((Unit == `DIVUNIT)&OpCtrl[0])); + assign ZEn = (Unit == `FMAUNIT); + + unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze, + .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN, + .XDenorm, .ZDenorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf, + .XEn, .YEn, .ZEn, .XExpMax); +endmodule \ No newline at end of file diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index 60aec7d5d..e7f64033c 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -45,7 +45,7 @@ module testbench; parameter INSTR_WAVEON = 0; // # of instructions at which to turn on waves in graphical sim parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; - parameter NO_IE_MTIME_CHECKPOINT = 0; + parameter NO_SPOOFING = 0; @@ -95,7 +95,7 @@ module testbench; logic [`XLEN-1:0] ExpectedRegValue``STAGE; \ logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \ string ExpectedCSRArray``STAGE[10:0]; \ - logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; + logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0]; // *** might be redundant? `DECLARE_TRACE_SCANNER_SIGNALS(E) `DECLARE_TRACE_SCANNER_SIGNALS(M) // M-stage expected values @@ -138,16 +138,16 @@ module testbench; `define RF dut.core.ieu.dp.regf.rf `define PC dut.core.ifu.pcreg.q `define PRIV_BASE dut.core.priv.priv - `define PRIV `PRIV_BASE.privmodereg.q + `define PRIV `PRIV_BASE.privmode.privmode.privmodereg.q `define CSR_BASE `PRIV_BASE.csr - `define MEIP `PRIV_BASE.MExtIntM - `define SEIP `PRIV_BASE.SExtIntM - `define MTIP `PRIV_BASE.TimerIntM + `define MEIP `PRIV_BASE.MExtInt + `define SEIP `PRIV_BASE.SExtInt + `define MTIP `PRIV_BASE.MTimerInt `define HPMCOUNTER `CSR_BASE.counters.counters.HPMCOUNTER_REGW `define MEDELEG `CSR_BASE.csrm.deleg.MEDELEGreg.q `define MIDELEG `CSR_BASE.csrm.deleg.MIDELEGreg.q - `define MIE `CSR_BASE.csri.IE_REGW - `define MIP `CSR_BASE.csri.IP_REGW_writeable + `define MIE `CSR_BASE.csri.MIE_REGW + `define MIP `CSR_BASE.csri.MIP_REGW_writeable `define MCAUSE `CSR_BASE.csrm.MCAUSEreg.q `define SCAUSE `CSR_BASE.csrs.csrs.SCAUSEreg.q `define MEPC `CSR_BASE.csrm.MEPCreg.q @@ -218,7 +218,7 @@ module testbench; /////////////////////////////// Cache Issue /////////////////////////////////// /////////////////////////////////////////////////////////////////////////////// logic probe; - if (NO_IE_MTIME_CHECKPOINT) + if (NO_SPOOFING) assign probe = testbench.dut.core.PCM == 64'hffffffff80200c8c & testbench.dut.core.InstrM != 32'h14021273 & testbench.dut.core.InstrValidM; @@ -352,13 +352,25 @@ module testbench; end \ end + // Initializing all zeroes into the branch predictor memory. + genvar adrindex; + for(adrindex = 0; adrindex < 1024; adrindex++) begin + initial begin + force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + #1; + release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex]; + release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex]; + end + end + genvar i; `INIT_CHECKPOINT_SIMPLE_ARRAY(RF, [`XLEN-1:0],31,1); `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,0); `INIT_CHECKPOINT_VAL(PC, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MEDELEG, [`XLEN-1:0]); `INIT_CHECKPOINT_VAL(MIDELEG, [`XLEN-1:0]); - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin `INIT_CHECKPOINT_VAL(MIE, [11:0]); `INIT_CHECKPOINT_VAL(MIP, [11:0]); end @@ -395,7 +407,7 @@ module testbench; // ========== INITIALIZATION ========== initial begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin force `MEIP = 0; force `SEIP = 0; force `UART_IP = 0; @@ -405,8 +417,6 @@ module testbench; $sformat(linuxImageDir,"%s/buildroot/output/images/",RISCV_DIR); if (CHECKPOINT!=0) $sformat(checkpointDir,"%s/linux-testvectors/checkpoint%0d/",RISCV_DIR,CHECKPOINT); - $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem); - $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem); ProgramAddrMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.addr"}; ProgramLabelMapFile = {linuxImageDir,"disassembly/vmlinux.objdump.lab"}; // initialize bootrom @@ -462,7 +472,7 @@ module testbench; release `INSTRET; end // Get the E-stage trace reader ahead of the M-stage trace reader - matchCountE = $fgets(lineE,traceFileE); + matchCountE = $fgets(lineE,traceFileE); // *** look at removing? end /////////////////////////////////////////////////////////////////////////////// @@ -547,16 +557,16 @@ module testbench; if(`"STAGE`"=="M") begin \ // override on special conditions \ if ((dut.core.lsu.LSUPAdrM == 'h10000002) | (dut.core.lsu.LSUPAdrM == 'h10000005) | (dut.core.lsu.LSUPAdrM == 'h10000006)) begin \ - if(!NO_IE_MTIME_CHECKPOINT) begin \ - $display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, AttemptedInstructionCount); \ - force dut.core.ieu.dp.ReadDataM = ExpectedMemReadDataM; \ + if(!NO_SPOOFING) begin \ + $display("%tns, %d instrs: Overwrite UART's Register in memory stage.", $time, AttemptedInstructionCount); \ + force dut.core.lsu.ReadDataM = ExpectedMemReadDataM; \ end \ end else \ - if(!NO_IE_MTIME_CHECKPOINT) \ - release dut.core.ieu.dp.ReadDataM; \ + if(!NO_SPOOFING) \ + release dut.core.lsu.ReadDataM; \ if(textM.substr(0,5) == "rdtime") begin \ //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \ - if(!NO_IE_MTIME_CHECKPOINT) \ + if(!NO_SPOOFING) \ force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \ end \ end \ @@ -633,7 +643,7 @@ module testbench; if(~dut.core.StallW) begin if(textW.substr(0,5) == "rdtime") begin //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, AttemptedInstructionCount); - if(!NO_IE_MTIME_CHECKPOINT) + if(!NO_SPOOFING) release dut.uncore.clint.clint.MTIME; end //if (ExpectedIEUAdrM == 'h10000005) begin @@ -656,7 +666,7 @@ module testbench; // turn on waves if (AttemptedInstructionCount == INSTR_WAVEON) $stop; // end sim - if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; + if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end fault = 0; if (`DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) @@ -692,8 +702,6 @@ module testbench; "sstatus": `checkCSR(`CSR_BASE.csrs.SSTATUS_REGW) "mtvec": `checkCSR(`CSR_BASE.csrm.MTVEC_REGW) "mie": `checkCSR(`CSR_BASE.csrm.MIE_REGW) - "sip": `checkCSR(`CSR_BASE.csrs.SIP_REGW) - "sie": `checkCSR(`CSR_BASE.csrs.SIE_REGW) "mideleg": `checkCSR(`CSR_BASE.csrm.MIDELEG_REGW) "medeleg": `checkCSR(`CSR_BASE.csrm.MEDELEG_REGW) "mepc": `checkCSR(`CSR_BASE.csrm.MEPC_REGW) @@ -704,7 +712,7 @@ module testbench; "stval": `checkCSR(`CSR_BASE.csrs.csrs.STVAL_REGW) "mip": begin `checkCSR(`CSR_BASE.csrm.MIP_REGW) - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<11) == 0) force `MEIP = 0; if ((ExpectedCSRArrayValueW[NumCSRPostWIndex] & 1<<09) == 0) @@ -720,7 +728,7 @@ module testbench; if (fault == 1) begin errorCount +=1; $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); - $stop; + $stop; $stop; end end // if (`DEBUG_TRACE >= 1) end // if (checkInstrW) @@ -736,7 +744,7 @@ module testbench; always @(negedge clk) begin if(checkInterruptM) begin if((interruptInstrCount+1) == AttemptedInstructionCount) begin - if(!NO_IE_MTIME_CHECKPOINT) begin + if(!NO_SPOOFING) begin case (interruptCauseVal) 11: begin force `MEIP = 1; @@ -767,7 +775,7 @@ module testbench; end end end - + diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index bf4903e51..3aa123fc3 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -51,11 +51,11 @@ module testbench; string tests[]; logic [3:0] dummy; - string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; logic HWRITE; logic [2:0] HSIZE; logic [2:0] HBURST; @@ -65,7 +65,11 @@ logic [3:0] dummy; logic HCLK, HRESETn; logic [`XLEN-1:0] PCW; + string ProgramAddrMapFile, ProgramLabelMapFile; + integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; + logic DCacheFlushDone, DCacheFlushStart; + logic riscofTest; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); @@ -85,9 +89,9 @@ logic [3:0] dummy; if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv}; else tests = {arch64c}; "arch64m": if (`M_SUPPORTED) tests = arch64m; - "arch64d": if (`D_SUPPORTED) tests = arch64d; + "arch64f": if (`F_SUPPORTED) tests = arch64f; + "arch64d": if (`D_SUPPORTED) tests = arch64d; "imperas64i": tests = imperas64i; -// "imperas64mmu": if (`VIRTMEM_SUPPORTED) tests = imperas64mmu; "imperas64f": if (`F_SUPPORTED) tests = imperas64f; "imperas64d": if (`D_SUPPORTED) tests = imperas64d; "imperas64m": if (`M_SUPPORTED) tests = imperas64m; @@ -95,8 +99,8 @@ logic [3:0] dummy; "imperas64c": if (`C_SUPPORTED) tests = imperas64c; else tests = imperas64iNOc; "testsBP64": tests = testsBP64; - "wally64i": tests = wally64i; // *** redo - "wally64priv": tests = wally64priv;// *** redo + "wally64i": tests = wally64i; + "wally64priv": tests = wally64priv; "wally64periph": tests = wally64periph; "coremark": tests = coremark; endcase @@ -109,16 +113,19 @@ logic [3:0] dummy; else tests = {arch32c}; "arch32m": if (`M_SUPPORTED) tests = arch32m; "arch32f": if (`F_SUPPORTED) tests = arch32f; + "arch32d": if (`D_SUPPORTED) tests = arch32d; "imperas32i": tests = imperas32i; -// "imperas32mmu": if (`VIRTMEM_SUPPORTED) tests = imperas32mmu; "imperas32f": if (`F_SUPPORTED) tests = imperas32f; "imperas32m": if (`M_SUPPORTED) tests = imperas32m; "wally32a": if (`A_SUPPORTED) tests = wally32a; "imperas32c": if (`C_SUPPORTED) tests = imperas32c; else tests = imperas32iNOc; - "wally32i": tests = wally32i; // *** redo + "wally32i": tests = wally32i; "wally32e": tests = wally32e; - "wally32priv": tests = wally32priv; // *** redo + "wally32priv": tests = wally32priv; + "wally32periph": tests = wally32periph; + "embench": tests = embench; + "coremark": tests = coremark; endcase end if (tests.size() == 0) begin @@ -127,7 +134,8 @@ logic [3:0] dummy; end end - string signame, memfilename, pathname; + string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; + integer outputFilePointer; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -150,7 +158,7 @@ logic [3:0] dummy; assign HRDATAEXT = 0; wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, - .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, + .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); @@ -162,8 +170,8 @@ logic [3:0] dummy; InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests - localparam integer MemStartAddr = `RAM_BASE>>(1+`XLEN/32); - localparam integer MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32); + localparam integer MemStartAddr = 0; + localparam integer MemEndAddr = `RAM_RANGE>>1+(`XLEN/32); initial begin @@ -171,6 +179,8 @@ logic [3:0] dummy; totalerrors = 0; testadr = 0; testadrNoBase = 0; + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests + riscofTest = tests[0] == "1" | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not // guarantee the initialized reads. For example a strcmp can read 6 byte @@ -183,16 +193,25 @@ logic [3:0] dummy; // read test vectors into memory pathname = tvpaths[tests[0].atoi()]; -/* if (tests[0] == `IMPERASTEST) + /* if (tests[0] == `IMPERASTEST) pathname = tvpaths[0]; else pathname = tvpaths[1]; */ - memfilename = {pathname, tests[test], ".elf.memfile"}; + if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; + else memfilename = {pathname, tests[test], ".elf.memfile"}; if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); - ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; - ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + if (riscofTest) begin + ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"}; + end else begin + ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"}; + ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"}; + end + // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array + // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test) + updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray); $display("Read memfile %s", memfilename); reset_ext = 1; # 42; reset_ext = 0; end @@ -204,94 +223,120 @@ logic [3:0] dummy; // if ($time % 100000 == 0) $display("Time is %0t", $time); end + logic [`XLEN-1:0] debugmemoryadr; + assign debugmemoryadr = dut.uncore.ram.ram.memory.RAM[5140]; + // check results always @(negedge clk) begin if (TEST == "coremark") - if (dut.core.priv.priv.ecallM) begin + if (dut.core.priv.priv.EcallFaultM) begin $display("Benchmark: coremark is done."); $stop; end + // Termination condition (i.e. we finished running current test) if (DCacheFlushDone) begin - + integer begin_signature_addr; + begin_signature_addr = ProgramAddrLabelArray["begin_signature"]; + if (!begin_signature_addr) + $display("begin_signature addr not found in %s", ProgramLabelMapFile); + testadr = ($unsigned(begin_signature_addr))/(`XLEN/8); + testadrNoBase = (begin_signature_addr - `RAM_BASE)/(`XLEN/8); #600; // give time for instructions in pipeline to finish - // clear signature to prevent contamination from previous tests - for(i=0; i= 4 & sig32[i-4] === 'bx) begin - if (i == 4) begin - i = SIGNATURESIZE+1; // flag empty file - $display(" Error: empty test file"); - end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency + $fclose(outputFilePointer); + $display("Embench Benchmark: created output file: %s", outputfile); + end else begin + // for tests with no self checking mechanism, read .signature.output file and compare to check for errors + // clear signature to prevent contamination from previous tests + for(i=0; i XLEN unleses data cache is supported"); assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); @@ -358,11 +415,13 @@ module riscvassertions; assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); -// assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); + // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); end endmodule @@ -384,8 +443,13 @@ module DCacheFlushFSM localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN; - localparam integer lognumlines = $clog2(numlines); + localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; + localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; + +//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM; + localparam integer numwords = sramlen/`XLEN; + localparam integer lognumlines = $clog2(numlines); localparam integer loglinebytelen = $clog2(linebytelen); localparam integer lognumways = $clog2(numways); localparam integer tagstart = lognumlines + loglinebytelen; @@ -393,65 +457,71 @@ module DCacheFlushFSM genvar index, way, cacheWord; - logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheValid [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic CacheDirty [numways-1:0] [numlines-1:0] [numwords-1:0]; - logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0]; - for(index = 0; index < numlines; index++) begin - for(way = 0; way < numways; way++) begin - for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin - copyShadow #(.tagstart(tagstart), - .loglinebytelen(loglinebytelen)) - copyShadow(.clk, - .start, - .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), - .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), - .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), - .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), - .index(index), - .cacheWord(cacheWord), - .CacheData(CacheData[way][index][cacheWord]), - .CacheAdr(CacheAdr[way][index][cacheWord]), - .CacheTag(CacheTag[way][index][cacheWord]), - .CacheValid(CacheValid[way][index][cacheWord]), - .CacheDirty(CacheDirty[way][index][cacheWord])); - end - end + logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [sramlen-1:0] cacheline; + logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0]; + for(index = 0; index < numlines; index++) begin + for(way = 0; way < numways; way++) begin + for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin + copyShadow #(.tagstart(tagstart), + .loglinebytelen(loglinebytelen), .sramlen(sramlen)) + copyShadow(.clk, + .start, + .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]), + .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]), + .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]), + .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]), + .index(index), + .cacheWord(cacheWord), + .CacheData(CacheData[way][index][cacheWord]), + .CacheAdr(CacheAdr[way][index][cacheWord]), + .CacheTag(CacheTag[way][index][cacheWord]), + .CacheValid(CacheValid[way][index][cacheWord]), + .CacheDirty(CacheDirty[way][index][cacheWord])); + end end + end - integer i, j, k; + integer i, j, k, l; - always @(posedge clk) begin - if (start) begin #1 - #1 - for(i = 0; i < numlines; i++) begin - for(j = 0; j < numways; j++) begin - for(k = 0; k < numwords; k++) begin - if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin - ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k]; - end - end - end - end - end - end - - - end + always @(posedge clk) begin + if (start) begin #1 + #1 + for(i = 0; i < numlines; i++) begin + for(j = 0; j < numways; j++) begin + for(l = 0; l < cachesramwords; l++) begin + if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin + for(k = 0; k < numwords; k++) begin + //cacheline = CacheData[j][i][0]; + // does not work with modelsim + // # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions. + // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions + //ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k]; + ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN]; + end + end + end + end + end + end + end + end flop #(1) doneReg(.clk, .d(start), .q(done)); endmodule module copyShadow - #(parameter tagstart, loglinebytelen) + #(parameter tagstart, loglinebytelen, sramlen) (input logic clk, input logic start, input logic [`PA_BITS-1:tagstart] tag, input logic valid, dirty, - input logic [`XLEN-1:0] data, + input logic [sramlen-1:0] data, input logic [32-1:0] index, input logic [32-1:0] cacheWord, - output logic [`XLEN-1:0] CacheData, + output logic [sramlen-1:0] CacheData, output logic [`PA_BITS-1:0] CacheAdr, output logic [`XLEN-1:0] CacheTag, output logic CacheValid, @@ -464,9 +534,30 @@ module copyShadow CacheValid = valid; CacheDirty = dirty; CacheData = data; - CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(`XLEN/8)); + CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8)); end end -endmodule +endmodule +task automatic updateProgramAddrLabelArray; + input string ProgramAddrMapFile, ProgramLabelMapFile; + inout integer ProgramAddrLabelArray [string]; + // Gets the memory location of begin_signature + integer ProgramLabelMapFP, ProgramAddrMapFP; + ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r"); + ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r"); + + if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files + while (!$feof(ProgramLabelMapFP)) begin + string label, adrstr; + integer returncode; + returncode = $fscanf(ProgramLabelMapFP, "%s\n", label); + returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr); + if (ProgramAddrLabelArray.exists(label)) + ProgramAddrLabelArray[label] = adrstr.atohex(); + end + end + $fclose(ProgramLabelMapFP); + $fclose(ProgramAddrMapFP); +endtask diff --git a/pipelined/testbench/tests-fp.vh b/pipelined/testbench/tests-fp.vh new file mode 100644 index 000000000..ff5cf2fb8 --- /dev/null +++ b/pipelined/testbench/tests-fp.vh @@ -0,0 +1,561 @@ +`define PATH "../../tests/fp/vectors/" +`define ADD_OPCTRL 3'b110 +`define MUL_OPCTRL 3'b100 +`define SUB_OPCTRL 3'b111 +`define FMA_OPCTRL 3'b000 +`define DIV_OPCTRL 3'b000 +`define SQRT_OPCTRL 3'b001 +`define LE_OPCTRL 3'b011 +`define LT_OPCTRL 3'b001 +`define EQ_OPCTRL 3'b010 +`define TO_UI_OPCTRL 3'b000 +`define TO_I_OPCTRL 3'b001 +`define TO_UL_OPCTRL 3'b010 +`define TO_L_OPCTRL 3'b011 +`define FROM_UI_OPCTRL 3'b100 +`define FROM_I_OPCTRL 3'b101 +`define FROM_UL_OPCTRL 3'b110 +`define FROM_L_OPCTRL 3'b111 +`define RNE 3'b000 +`define RZ 3'b001 +`define RU 3'b011 +`define RD 3'b010 +`define RNM 3'b100 +`define FMAUNIT 2 +`define DIVUNIT 1 +`define CVTINTUNIT 0 +`define CVTFPUNIT 4 +`define CMPUNIT 3 + +string f16rv32cvtint[] = '{ + "ui32_to_f16_rne.tv", + "ui32_to_f16_rz.tv", + "ui32_to_f16_ru.tv", + "ui32_to_f16_rd.tv", + "ui32_to_f16_rnm.tv", + "i32_to_f16_rne.tv", + "i32_to_f16_rz.tv", + "i32_to_f16_ru.tv", + "i32_to_f16_rd.tv", + "i32_to_f16_rnm.tv", + "f16_to_ui32_rne.tv", + "f16_to_ui32_rz.tv", + "f16_to_ui32_ru.tv", + "f16_to_ui32_rd.tv", + "f16_to_ui32_rnm.tv", + "f16_to_i32_rne.tv", + "f16_to_i32_rz.tv", + "f16_to_i32_ru.tv", + "f16_to_i32_rd.tv", + "f16_to_i32_rnm.tv" +}; + +string f16rv64cvtint[] = '{ + "ui64_to_f16_rne.tv", + "ui64_to_f16_rz.tv", + "ui64_to_f16_ru.tv", + "ui64_to_f16_rd.tv", + "ui64_to_f16_rnm.tv", + "i64_to_f16_rne.tv", + "i64_to_f16_rz.tv", + "i64_to_f16_ru.tv", + "i64_to_f16_rd.tv", + "i64_to_f16_rnm.tv", + "f16_to_ui64_rne.tv", + "f16_to_ui64_rz.tv", + "f16_to_ui64_ru.tv", + "f16_to_ui64_rd.tv", + "f16_to_ui64_rnm.tv", + "f16_to_i64_rne.tv", + "f16_to_i64_rz.tv", + "f16_to_i64_ru.tv", + "f16_to_i64_rd.tv", + "f16_to_i64_rnm.tv" +}; + +string f32rv32cvtint[] = '{ + "ui32_to_f32_rne.tv", + "ui32_to_f32_rz.tv", + "ui32_to_f32_ru.tv", + "ui32_to_f32_rd.tv", + "ui32_to_f32_rnm.tv", + "i32_to_f32_rne.tv", + "i32_to_f32_rz.tv", + "i32_to_f32_ru.tv", + "i32_to_f32_rd.tv", + "i32_to_f32_rnm.tv", + "f32_to_ui32_rne.tv", + "f32_to_ui32_rz.tv", + "f32_to_ui32_ru.tv", + "f32_to_ui32_rd.tv", + "f32_to_ui32_rnm.tv", + "f32_to_i32_rne.tv", + "f32_to_i32_rz.tv", + "f32_to_i32_ru.tv", + "f32_to_i32_rd.tv", + "f32_to_i32_rnm.tv" +}; + +string f32rv64cvtint[] = '{ + "ui64_to_f32_rne.tv", + "ui64_to_f32_rz.tv", + "ui64_to_f32_ru.tv", + "ui64_to_f32_rd.tv", + "ui64_to_f32_rnm.tv", + "i64_to_f32_rne.tv", + "i64_to_f32_rz.tv", + "i64_to_f32_ru.tv", + "i64_to_f32_rd.tv", + "i64_to_f32_rnm.tv", + "f32_to_ui64_rne.tv", + "f32_to_ui64_rz.tv", + "f32_to_ui64_ru.tv", + "f32_to_ui64_rd.tv", + "f32_to_ui64_rnm.tv", + "f32_to_i64_rne.tv", + "f32_to_i64_rz.tv", + "f32_to_i64_ru.tv", + "f32_to_i64_rd.tv", + "f32_to_i64_rnm.tv" +}; + + +string f64rv32cvtint[] = '{ + "ui32_to_f64_rne.tv", + "ui32_to_f64_rz.tv", + "ui32_to_f64_ru.tv", + "ui32_to_f64_rd.tv", + "ui32_to_f64_rnm.tv", + "i32_to_f64_rne.tv", + "i32_to_f64_rz.tv", + "i32_to_f64_ru.tv", + "i32_to_f64_rd.tv", + "i32_to_f64_rnm.tv", + "f64_to_ui32_rne.tv", + "f64_to_ui32_rz.tv", + "f64_to_ui32_ru.tv", + "f64_to_ui32_rd.tv", + "f64_to_ui32_rnm.tv", + "f64_to_i32_rne.tv", + "f64_to_i32_rz.tv", + "f64_to_i32_ru.tv", + "f64_to_i32_rd.tv", + "f64_to_i32_rnm.tv" +}; + +string f64rv64cvtint[] = '{ + "ui64_to_f64_rne.tv", + "ui64_to_f64_rz.tv", + "ui64_to_f64_ru.tv", + "ui64_to_f64_rd.tv", + "ui64_to_f64_rnm.tv", + "i64_to_f64_rne.tv", + "i64_to_f64_rz.tv", + "i64_to_f64_ru.tv", + "i64_to_f64_rd.tv", + "i64_to_f64_rnm.tv", + "f64_to_ui64_rne.tv", + "f64_to_ui64_rz.tv", + "f64_to_ui64_ru.tv", + "f64_to_ui64_rd.tv", + "f64_to_ui64_rnm.tv", + "f64_to_i64_rne.tv", + "f64_to_i64_rz.tv", + "f64_to_i64_ru.tv", + "f64_to_i64_rd.tv", + "f64_to_i64_rnm.tv" +}; + +string f128rv64cvtint[] = '{ + "ui64_to_f128_rne.tv", + "ui64_to_f128_rz.tv", + "ui64_to_f128_ru.tv", + "ui64_to_f128_rd.tv", + "ui64_to_f128_rnm.tv", + "i64_to_f128_rne.tv", + "i64_to_f128_rz.tv", + "i64_to_f128_ru.tv", + "i64_to_f128_rd.tv", + "i64_to_f128_rnm.tv", + "f128_to_ui64_rne.tv", + "f128_to_ui64_rz.tv", + "f128_to_ui64_ru.tv", + "f128_to_ui64_rd.tv", + "f128_to_ui64_rnm.tv", + "f128_to_i64_rne.tv", + "f128_to_i64_rz.tv", + "f128_to_i64_ru.tv", + "f128_to_i64_rd.tv", + "f128_to_i64_rnm.tv" +}; + +string f128rv32cvtint[] = '{ + "ui32_to_f128_rne.tv", + "ui32_to_f128_rz.tv", + "ui32_to_f128_ru.tv", + "ui32_to_f128_rd.tv", + "ui32_to_f128_rnm.tv", + "i32_to_f128_rne.tv", + "i32_to_f128_rz.tv", + "i32_to_f128_ru.tv", + "i32_to_f128_rd.tv", + "i32_to_f128_rnm.tv", + "f128_to_ui32_rne.tv", + "f128_to_ui32_rz.tv", + "f128_to_ui32_ru.tv", + "f128_to_ui32_rd.tv", + "f128_to_ui32_rnm.tv", + "f128_to_i32_rne.tv", + "f128_to_i32_rz.tv", + "f128_to_i32_ru.tv", + "f128_to_i32_rd.tv", + "f128_to_i32_rnm.tv" +}; + + +string f32f16cvt[] = '{ + "f32_to_f16_rne.tv", + "f32_to_f16_rz.tv", + "f32_to_f16_ru.tv", + "f32_to_f16_rd.tv", + "f32_to_f16_rnm.tv", + "f16_to_f32_rne.tv", + "f16_to_f32_rz.tv", + "f16_to_f32_ru.tv", + "f16_to_f32_rd.tv", + "f16_to_f32_rnm.tv" +}; + +string f64f16cvt[] = '{ + "f64_to_f16_rne.tv", + "f64_to_f16_rz.tv", + "f64_to_f16_ru.tv", + "f64_to_f16_rd.tv", + "f64_to_f16_rnm.tv", + "f16_to_f64_rne.tv", + "f16_to_f64_rz.tv", + "f16_to_f64_ru.tv", + "f16_to_f64_rd.tv", + "f16_to_f64_rnm.tv" +}; + +string f128f16cvt[] = '{ + "f128_to_f16_rne.tv", + "f128_to_f16_rz.tv", + "f128_to_f16_ru.tv", + "f128_to_f16_rd.tv", + "f128_to_f16_rnm.tv", + "f16_to_f128_rne.tv", + "f16_to_f128_rz.tv", + "f16_to_f128_ru.tv", + "f16_to_f128_rd.tv", + "f16_to_f128_rnm.tv" +}; + +string f64f32cvt[] = '{ + "f64_to_f32_rne.tv", + "f64_to_f32_rz.tv", + "f64_to_f32_ru.tv", + "f64_to_f32_rd.tv", + "f64_to_f32_rnm.tv", + "f32_to_f64_rne.tv", + "f32_to_f64_rz.tv", + "f32_to_f64_ru.tv", + "f32_to_f64_rd.tv", + "f32_to_f64_rnm.tv" +}; + + +string f128f32cvt[] = '{ + "f128_to_f32_rne.tv", + "f128_to_f32_rz.tv", + "f128_to_f32_ru.tv", + "f128_to_f32_rd.tv", + "f128_to_f32_rnm.tv", + "f32_to_f128_rne.tv", + "f32_to_f128_rz.tv", + "f32_to_f128_ru.tv", + "f32_to_f128_rd.tv", + "f32_to_f128_rnm.tv" +}; + + +string f128f64cvt[] = '{ + "f128_to_f64_rne.tv", + "f128_to_f64_rz.tv", + "f128_to_f64_ru.tv", + "f128_to_f64_rd.tv", + "f128_to_f64_rnm.tv", + "f64_to_f128_rne.tv", + "f64_to_f128_rz.tv", + "f64_to_f128_ru.tv", + "f64_to_f128_rd.tv", + "f64_to_f128_rnm.tv" +}; + +string f16add[] = '{ + "f16_add_rne.tv", + "f16_add_rz.tv", + "f16_add_ru.tv", + "f16_add_rd.tv", + "f16_add_rnm.tv" +}; + +string f32add[] = '{ + "f32_add_rne.tv", + "f32_add_rz.tv", + "f32_add_ru.tv", + "f32_add_rd.tv", + "f32_add_rnm.tv" +}; + +string f64add[] = '{ + "f64_add_rne.tv", + "f64_add_rz.tv", + "f64_add_ru.tv", + "f64_add_rd.tv", + "f64_add_rnm.tv" +}; + +string f128add[] = '{ + "f128_add_rne.tv", + "f128_add_rz.tv", + "f128_add_ru.tv", + "f128_add_rd.tv", + "f128_add_rnm.tv" +}; + +string f16sub[] = '{ + "f16_sub_rne.tv", + "f16_sub_rz.tv", + "f16_sub_ru.tv", + "f16_sub_rd.tv", + "f16_sub_rnm.tv" +}; + +string f32sub[] = '{ + "f32_sub_rne.tv", + "f32_sub_rz.tv", + "f32_sub_ru.tv", + "f32_sub_rd.tv", + "f32_sub_rnm.tv" +}; + +string f64sub[] = '{ + "f64_sub_rne.tv", + "f64_sub_rz.tv", + "f64_sub_ru.tv", + "f64_sub_rd.tv", + "f64_sub_rnm.tv" +}; + +string f128sub[] = '{ + "f128_sub_rne.tv", + "f128_sub_rz.tv", + "f128_sub_ru.tv", + "f128_sub_rd.tv", + "f128_sub_rnm.tv" +}; + +string f16mul[] = '{ + "f16_mul_rne.tv", + "f16_mul_rz.tv", + "f16_mul_ru.tv", + "f16_mul_rd.tv", + "f16_mul_rnm.tv" +}; + +string f32mul[] = '{ + "f32_mul_rne.tv", + "f32_mul_rz.tv", + "f32_mul_ru.tv", + "f32_mul_rd.tv", + "f32_mul_rnm.tv" +}; + +string f64mul[] = '{ + "f64_mul_rne.tv", + "f64_mul_rz.tv", + "f64_mul_ru.tv", + "f64_mul_rd.tv", + "f64_mul_rnm.tv" +}; + +string f128mul[] = '{ + "f128_mul_rne.tv", + "f128_mul_rz.tv", + "f128_mul_ru.tv", + "f128_mul_rd.tv", + "f128_mul_rnm.tv" +}; + +string f16div[] = '{ + "f16_div_rne.tv", + "f16_div_rz.tv", + "f16_div_ru.tv", + "f16_div_rd.tv", + "f16_div_rnm.tv" +}; + +string f32div[] = '{ + "f32_div_rne.tv", + "f32_div_rz.tv", + "f32_div_ru.tv", + "f32_div_rd.tv", + "f32_div_rnm.tv" +}; + +string f64div[] = '{ + "f64_div_rne.tv", + "f64_div_rz.tv", + "f64_div_ru.tv", + "f64_div_rd.tv", + "f64_div_rnm.tv" +}; + +string f128div[] = '{ + "f128_div_rne.tv", + "f128_div_rz.tv", + "f128_div_ru.tv", + "f128_div_rd.tv", + "f128_div_rnm.tv" +}; + +string f16sqrt[] = '{ + "f16_sqrt_rne.tv", + "f16_sqrt_rz.tv", + "f16_sqrt_ru.tv", + "f16_sqrt_rd.tv", + "f16_sqrt_rnm.tv" +}; + +string f32sqrt[] = '{ + "f32_sqrt_rne.tv", + "f32_sqrt_rz.tv", + "f32_sqrt_ru.tv", + "f32_sqrt_rd.tv", + "f32_sqrt_rnm.tv" +}; + +string f64sqrt[] = '{ + "f64_sqrt_rne.tv", + "f64_sqrt_rz.tv", + "f64_sqrt_ru.tv", + "f64_sqrt_rd.tv", + "f64_sqrt_rnm.tv" +}; + +string f128sqrt[] = '{ + "f128_sqrt_rne.tv", + "f128_sqrt_rz.tv", + "f128_sqrt_ru.tv", + "f128_sqrt_rd.tv", + "f128_sqrt_rnm.tv" +}; + +string f16cmp[] = '{ + "f16_eq_rne.tv", + "f16_eq_rz.tv", + "f16_eq_ru.tv", + "f16_eq_rd.tv", + "f16_eq_rnm.tv", + "f16_le_rne.tv", + "f16_le_rz.tv", + "f16_le_ru.tv", + "f16_le_rd.tv", + "f16_le_rnm.tv", + "f16_lt_rne.tv", + "f16_lt_rz.tv", + "f16_lt_ru.tv", + "f16_lt_rd.tv", + "f16_lt_rnm.tv" +}; + +string f32cmp[] = '{ + "f32_eq_rne.tv", + "f32_eq_rz.tv", + "f32_eq_ru.tv", + "f32_eq_rd.tv", + "f32_eq_rnm.tv", + "f32_le_rne.tv", + "f32_le_rz.tv", + "f32_le_ru.tv", + "f32_le_rd.tv", + "f32_le_rnm.tv", + "f32_lt_rne.tv", + "f32_lt_rz.tv", + "f32_lt_ru.tv", + "f32_lt_rd.tv", + "f32_lt_rnm.tv" +}; + +string f64cmp[] = '{ + "f64_eq_rne.tv", + "f64_eq_rz.tv", + "f64_eq_ru.tv", + "f64_eq_rd.tv", + "f64_eq_rnm.tv", + "f64_le_rne.tv", + "f64_le_rz.tv", + "f64_le_ru.tv", + "f64_le_rd.tv", + "f64_le_rnm.tv", + "f64_lt_rne.tv", + "f64_lt_rz.tv", + "f64_lt_ru.tv", + "f64_lt_rd.tv", + "f64_lt_rnm.tv" +}; + +string f128cmp[] = '{ + "f128_eq_rne.tv", + "f128_eq_rz.tv", + "f128_eq_ru.tv", + "f128_eq_rd.tv", + "f128_eq_rnm.tv", + "f128_le_rne.tv", + "f128_le_rz.tv", + "f128_le_ru.tv", + "f128_le_rd.tv", + "f128_le_rnm.tv", + "f128_lt_rne.tv", + "f128_lt_rz.tv", + "f128_lt_ru.tv", + "f128_lt_rd.tv", + "f128_lt_rnm.tv" +}; + +string f16fma[] = '{ + "f16_mulAdd_rne.tv", + "f16_mulAdd_rz.tv", + "f16_mulAdd_ru.tv", + "f16_mulAdd_rd.tv", + "f16_mulAdd_rnm.tv" +}; + +string f32fma[] = '{ + "f32_mulAdd_rne.tv", + "f32_mulAdd_rz.tv", + "f32_mulAdd_ru.tv", + "f32_mulAdd_rd.tv", + "f32_mulAdd_rnm.tv" +}; + +string f64fma[] = '{ + "f64_mulAdd_rne.tv", + "f64_mulAdd_rz.tv", + "f64_mulAdd_ru.tv", + "f64_mulAdd_rd.tv", + "f64_mulAdd_rnm.tv" +}; + +string f128fma[] = '{ + "f128_mulAdd_rne.tv", + "f128_mulAdd_rz.tv", + "f128_mulAdd_ru.tv", + "f128_mulAdd_rd.tv", + "f128_mulAdd_rnm.tv" +}; + + + diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 49ff0ff5c..bf443ac6f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -28,1532 +28,1886 @@ `define WALLYTEST "2" `define MYIMPERASTEST "3" `define COREMARK "4" +`define EMBENCH "5" // *** remove MYIMPERASTEST cases when ported string tvpaths[] = '{ "../../addins/imperas-riscv-tests/work/", - "../../addins/riscv-arch-test/work/", - "../../tests/wally-riscv-arch-test/work/", + "../../tests/riscof/work/riscv-arch-test/", + "../../tests/riscof/work/wally-riscv-arch-test/", "../../tests/imperas-riscv-tests/work/", - "../../benchmarks/riscv-coremark/work/" -}; + "../../benchmarks/coremark/work/", + "../../addins/embench-iot/" + }; - // *** make sure these are somewhere string coremark[] = '{ `COREMARK, - "coremark.bare.riscv", "100000" + "coremark.bare.riscv" }; - string wally64a[] = '{ - `WALLYTEST, - "rv64i_m/privilege/WALLY-amo", "2210", - "rv64i_m/privilege/WALLY-lrsc", "2410", - "rv64i_m/privilege/WALLY-status-fp-enabled-01", "50a0" - }; - - string wally32a[] = '{ - `WALLYTEST, - "rv32i_m/privilege/WALLY-amo", "2310", - "rv32i_m/privilege/WALLY-lrsc", "2310", - "rv32i_m/privilege/WALLY-status-fp-enabled-01", "5080" - + string embench[] = '{ + `EMBENCH, + "bd_speedopt_speed/src/aha-mont64/aha-mont64", + "bd_speedopt_speed/src/crc32/crc32", + "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches + "bd_speedopt_speed/src/edn/edn", + "bd_speedopt_speed/src/huffbench/huffbench", + "bd_speedopt_speed/src/matmult-int/matmult-int", + // "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back + "bd_speedopt_speed/src/minver/minver", + "bd_speedopt_speed/src/nbody/nbody", + "bd_speedopt_speed/src/nettle-aes/nettle-aes", + "bd_speedopt_speed/src/nettle-sha256/nettle-sha256", + "bd_speedopt_speed/src/nsichneu/nsichneu", + "bd_speedopt_speed/src/picojpeg/picojpeg", + // "bd_speedopt_speed/src/primecount/primecount", + "bd_speedopt_speed/src/sglib-combined/sglib-combined", + "bd_speedopt_speed/src/slre/slre", + "bd_speedopt_speed/src/st/st", + "bd_speedopt_speed/src/statemate/statemate", + // "bd_speedopt_speed/src/tarfind/tarfind", + "bd_speedopt_speed/src/ud/ud", + "bd_speedopt_speed/src/wikisort/wikisort", + "bd_sizeopt_speed/src/aha-mont64/aha-mont64", + "bd_sizeopt_speed/src/crc32/crc32", + "bd_sizeopt_speed/src/cubic/cubic", + "bd_sizeopt_speed/src/edn/edn", + "bd_sizeopt_speed/src/huffbench/huffbench", + "bd_sizeopt_speed/src/matmult-int/matmult-int", + // "bd_sizeopt_speed/src/md5sum/md5sum", + "bd_sizeopt_speed/src/minver/minver", + "bd_sizeopt_speed/src/nbody/nbody", + "bd_sizeopt_speed/src/nettle-aes/nettle-aes", + "bd_sizeopt_speed/src/nettle-sha256/nettle-sha256", + "bd_sizeopt_speed/src/nsichneu/nsichneu", + "bd_sizeopt_speed/src/picojpeg/picojpeg", + // "bd_sizeopt_speed/src/primecount/primecount", + "bd_sizeopt_speed/src/qrduino/qrduino", + "bd_sizeopt_speed/src/sglib-combined/sglib-combined", + "bd_sizeopt_speed/src/slre/slre", + "bd_sizeopt_speed/src/st/st", + "bd_sizeopt_speed/src/statemate/statemate", + // "bd_sizeopt_speed/src/tarfind/tarfind", + "bd_sizeopt_speed/src/ud/ud", + "bd_sizeopt_speed/src/wikisort/wikisort" }; // *** restore CSR tests from Imperas old - - string extra64i[] = '{ + string extra64i[] = '{ `MYIMPERASTEST, - "rv64i_m/I/WALLY-ADD", "4000", - "rv64i_m/I/WALLY-SUB", "4000", - "rv64i_m/I/WALLY-ADDI", "3000", - "rv64i_m/I/WALLY-ANDI", "3000", - "rv64i_m/I/WALLY-ORI", "3000", - "rv64i_m/I/WALLY-XORI", "3000", - "rv64i_m/I/WALLY-SLTI", "3000", - "rv64i_m/I/WALLY-SLTIU", "3000", - "rv64i_m/I/WALLY-SLLI", "3000", - "rv64i_m/I/WALLY-SRLI", "3000", - "rv64i_m/I/WALLY-SRAI", "3000", - "rv64i_m/I/WALLY-JAL", "4000", - "rv64i_m/I/WALLY-JALR", "3000", - "rv64i_m/I/WALLY-STORE", "3000", - "rv64i_m/I/WALLY-ADDIW", "3000", - "rv64i_m/I/WALLY-SLLIW", "3000", - "rv64i_m/I/WALLY-SRLIW", "3000", - "rv64i_m/I/WALLY-SRAIW", "3000", - "rv64i_m/I/WALLY-ADDW", "4000", - "rv64i_m/I/WALLY-SUBW", "4000", - "rv64i_m/I/WALLY-SLLW", "3000", - "rv64i_m/I/WALLY-SRLW", "3000", - "rv64i_m/I/WALLY-SRAW", "3000", - "rv64i_m/I/WALLY-BEQ" ,"5000", - "rv64i_m/I/WALLY-BNE", "5000 ", - "rv64i_m/I/WALLY-BLTU", "5000 ", - "rv64i_m/I/WALLY-BLT", "5000", - "rv64i_m/I/WALLY-BGE", "5000 ", - "rv64i_m/I/WALLY-BGEU", "5000 ", - "rv64i_m/I/WALLY-CSRRW", "4000", - "rv64i_m/I/WALLY-CSRRS", "4000", - "rv64i_m/I/WALLY-CSRRC", "5000", - "rv64i_m/I/WALLY-CSRRWI", "4000", - "rv64i_m/I/WALLY-CSRRSI", "4000", - "rv64i_m/I/WALLY-CSRRCI", "4000" + "rv64i_m/I/WALLY-ADD", + "rv64i_m/I/WALLY-SUB", + "rv64i_m/I/WALLY-ADDI", + "rv64i_m/I/WALLY-ANDI", + "rv64i_m/I/WALLY-ORI", + "rv64i_m/I/WALLY-XORI", + "rv64i_m/I/WALLY-SLTI", + "rv64i_m/I/WALLY-SLTIU", + "rv64i_m/I/WALLY-SLLI", + "rv64i_m/I/WALLY-SRLI", + "rv64i_m/I/WALLY-SRAI", + "rv64i_m/I/WALLY-JAL", + "rv64i_m/I/WALLY-JALR", + "rv64i_m/I/WALLY-STORE", + "rv64i_m/I/WALLY-ADDIW", + "rv64i_m/I/WALLY-SLLIW", + "rv64i_m/I/WALLY-SRLIW", + "rv64i_m/I/WALLY-SRAIW", + "rv64i_m/I/WALLY-ADDW", + "rv64i_m/I/WALLY-SUBW", + "rv64i_m/I/WALLY-SLLW", + "rv64i_m/I/WALLY-SRLW", + "rv64i_m/I/WALLY-SRAW", + "rv64i_m/I/WALLY-BEQ", + "rv64i_m/I/WALLY-BNE", + "rv64i_m/I/WALLY-BLTU", + "rv64i_m/I/WALLY-BLT", + "rv64i_m/I/WALLY-BGE", + "rv64i_m/I/WALLY-BGEU", + "rv64i_m/I/WALLY-CSRRW", + "rv64i_m/I/WALLY-CSRRS", + "rv64i_m/I/WALLY-CSRRC", + "rv64i_m/I/WALLY-CSRRWI", + "rv64i_m/I/WALLY-CSRRSI", + "rv64i_m/I/WALLY-CSRRCI" }; string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FADD-S-RDN-01", "002010", - "rv32i_m/F/FADD-S-RMM-01", "002010", - "rv32i_m/F/FADD-S-RNE-01", "002010", - "rv32i_m/F/FADD-S-RTZ-01", "002010", - "rv32i_m/F/FADD-S-RUP-01", "002010", - "rv32i_m/F/FCLASS-S-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-W-RDN-01", "002010", - "rv32i_m/F/FCVT-S-W-RMM-01", "002010", - "rv32i_m/F/FCVT-S-W-RNE-01", "002010", - "rv32i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-W-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv32i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv32i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv32i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv32i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-W-S-RDN-01", "002010", - "rv32i_m/F/FCVT-W-S-RMM-01", "002010", - "rv32i_m/F/FCVT-W-S-RNE-01", "002010", - "rv32i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-W-S-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv32i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv32i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv32i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv32i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv32i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FDIV-S-RDN-01", "002010", - // "rv32i_m/F/FDIV-S-RMM-01", "002010", - // "rv32i_m/F/FDIV-S-RNE-01", "002010", - // "rv32i_m/F/FDIV-S-RTZ-01", "002010", - // "rv32i_m/F/FDIV-S-RUP-01", "002010", - "rv32i_m/F/FEQ-S-01", "002010", - "rv32i_m/F/FLE-S-01", "002010", - "rv32i_m/F/FLT-S-01", "002010", - "rv32i_m/F/FLW-01", "002120", - "rv32i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMADD-S-RDN-01", "002010", - "rv32i_m/F/FMADD-S-RMM-01", "002010", - "rv32i_m/F/FMADD-S-RNE-01", "002010", - "rv32i_m/F/FMADD-S-RTZ-01", "002010", - "rv32i_m/F/FMADD-S-RUP-01", "002010", - "rv32i_m/F/FMAX-S-01", "002010", - "rv32i_m/F/FMIN-S-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMSUB-S-RDN-01", "002010", - "rv32i_m/F/FMSUB-S-RMM-01", "002010", - "rv32i_m/F/FMSUB-S-RNE-01", "002010", - "rv32i_m/F/FMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FMSUB-S-RUP-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv32i_m/F/FMUL-S-RDN-01", "002010", - "rv32i_m/F/FMUL-S-RMM-01", "002010", - "rv32i_m/F/FMUL-S-RNE-01", "002010", - "rv32i_m/F/FMUL-S-RTZ-01", "002010", - "rv32i_m/F/FMUL-S-RUP-01", "002010", - "rv32i_m/F/FMV-W-X-01", "002010", - "rv32i_m/F/FMV-X-W-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMADD-S-RDN-01", "002010", - "rv32i_m/F/FNMADD-S-RMM-01", "002010", - "rv32i_m/F/FNMADD-S-RNE-01", "002010", - "rv32i_m/F/FNMADD-S-RTZ-01", "002010", - "rv32i_m/F/FNMADD-S-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FNMSUB-S-RDN-01", "002010", - "rv32i_m/F/FNMSUB-S-RMM-01", "002010", - "rv32i_m/F/FNMSUB-S-RNE-01", "002010", - "rv32i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv32i_m/F/FNMSUB-S-RUP-01", "002010", - "rv32i_m/F/FSGNJN-S-01", "002010", - "rv32i_m/F/FSGNJ-S-01", "002010", - "rv32i_m/F/FSGNJX-S-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv32i_m/F/FSQRT-S-RDN-01", "002010", - // "rv32i_m/F/FSQRT-S-RMM-01", "002010", - // "rv32i_m/F/FSQRT-S-RNE-01", "002010", - // "rv32i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv32i_m/F/FSQRT-S-RUP-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv32i_m/F/FSUB-S-RDN-01", "002010", - "rv32i_m/F/FSUB-S-RMM-01", "002010", - "rv32i_m/F/FSUB-S-RNE-01", "002010", - "rv32i_m/F/FSUB-S-RTZ-01", "002010", - "rv32i_m/F/FSUB-S-RUP-01", "002010", - "rv32i_m/F/FSW-01", "002010" + "rv32i_m/F/FADD-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RMM-01", + "rv32i_m/F/FADD-S-DYN-RNE-01", + "rv32i_m/F/FADD-S-DYN-RTZ-01", + "rv32i_m/F/FADD-S-DYN-RUP-01", + "rv32i_m/F/FADD-S-RDN-01", + "rv32i_m/F/FADD-S-RMM-01", + "rv32i_m/F/FADD-S-RNE-01", + "rv32i_m/F/FADD-S-RTZ-01", + "rv32i_m/F/FADD-S-RUP-01", + "rv32i_m/F/FCLASS-S-01", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", + "rv32i_m/F/FCVT-S-W-RDN-01", + "rv32i_m/F/FCVT-S-W-RMM-01", + "rv32i_m/F/FCVT-S-W-RNE-01", + "rv32i_m/F/FCVT-S-W-RTZ-01", + "rv32i_m/F/FCVT-S-W-RUP-01", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv32i_m/F/FCVT-S-WU-RDN-01", + "rv32i_m/F/FCVT-S-WU-RMM-01", + "rv32i_m/F/FCVT-S-WU-RNE-01", + "rv32i_m/F/FCVT-S-WU-RTZ-01", + "rv32i_m/F/FCVT-S-WU-RUP-01", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", + "rv32i_m/F/FCVT-W-S-RDN-01", + "rv32i_m/F/FCVT-W-S-RMM-01", + "rv32i_m/F/FCVT-W-S-RNE-01", + "rv32i_m/F/FCVT-W-S-RTZ-01", + "rv32i_m/F/FCVT-W-S-RUP-01", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv32i_m/F/FCVT-WU-S-RDN-01", + "rv32i_m/F/FCVT-WU-S-RMM-01", + "rv32i_m/F/FCVT-WU-S-RNE-01", + "rv32i_m/F/FCVT-WU-S-RTZ-01", + "rv32i_m/F/FCVT-WU-S-RUP-01", + "rv32i_m/F/FDIV-S-DYN-RDN-01", + "rv32i_m/F/FDIV-S-DYN-RMM-01", + "rv32i_m/F/FDIV-S-DYN-RNE-01", + "rv32i_m/F/FDIV-S-DYN-RTZ-01", + "rv32i_m/F/FDIV-S-DYN-RUP-01", + "rv32i_m/F/FDIV-S-RDN-01", + "rv32i_m/F/FDIV-S-RMM-01", + "rv32i_m/F/FDIV-S-RNE-01", + "rv32i_m/F/FDIV-S-RTZ-01", + "rv32i_m/F/FDIV-S-RUP-01", + "rv32i_m/F/FEQ-S-01", + "rv32i_m/F/FLE-S-01", + "rv32i_m/F/FLT-S-01", + "rv32i_m/F/FLW-01", + "rv32i_m/F/FMADD-S-DYN-RDN-01", + "rv32i_m/F/FMADD-S-DYN-RMM-01", + "rv32i_m/F/FMADD-S-DYN-RNE-01", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", + "rv32i_m/F/FMADD-S-DYN-RUP-01", + "rv32i_m/F/FMADD-S-RDN-01", + "rv32i_m/F/FMADD-S-RMM-01", + "rv32i_m/F/FMADD-S-RNE-01", + "rv32i_m/F/FMADD-S-RTZ-01", + "rv32i_m/F/FMADD-S-RUP-01", + "rv32i_m/F/FMAX-S-01", + "rv32i_m/F/FMIN-S-01", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", + "rv32i_m/F/FMSUB-S-RDN-01", + "rv32i_m/F/FMSUB-S-RMM-01", + "rv32i_m/F/FMSUB-S-RNE-01", + "rv32i_m/F/FMSUB-S-RTZ-01", + "rv32i_m/F/FMSUB-S-RUP-01", + "rv32i_m/F/FMUL-S-DYN-RDN-01", + "rv32i_m/F/FMUL-S-DYN-RMM-01", + "rv32i_m/F/FMUL-S-DYN-RNE-01", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", + "rv32i_m/F/FMUL-S-DYN-RUP-01", + "rv32i_m/F/FMUL-S-RDN-01", + "rv32i_m/F/FMUL-S-RMM-01", + "rv32i_m/F/FMUL-S-RNE-01", + "rv32i_m/F/FMUL-S-RTZ-01", + "rv32i_m/F/FMUL-S-RUP-01", + "rv32i_m/F/FMV-W-X-01", + "rv32i_m/F/FMV-X-W-01", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", + "rv32i_m/F/FNMADD-S-RDN-01", + "rv32i_m/F/FNMADD-S-RMM-01", + "rv32i_m/F/FNMADD-S-RNE-01", + "rv32i_m/F/FNMADD-S-RTZ-01", + "rv32i_m/F/FNMADD-S-RUP-01", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", + "rv32i_m/F/FNMSUB-S-RDN-01", + "rv32i_m/F/FNMSUB-S-RMM-01", + "rv32i_m/F/FNMSUB-S-RNE-01", + "rv32i_m/F/FNMSUB-S-RTZ-01", + "rv32i_m/F/FNMSUB-S-RUP-01", + "rv32i_m/F/FSGNJN-S-01", + "rv32i_m/F/FSGNJ-S-01", + "rv32i_m/F/FSGNJX-S-01", + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FSQRT-S-DYN-RMM-01", + "rv32i_m/F/FSQRT-S-DYN-RNE-01", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01", + "rv32i_m/F/FSQRT-S-DYN-RUP-01", + "rv32i_m/F/FSQRT-S-RDN-01", + "rv32i_m/F/FSQRT-S-RMM-01", + "rv32i_m/F/FSQRT-S-RNE-01", + "rv32i_m/F/FSQRT-S-RTZ-01", + "rv32i_m/F/FSQRT-S-RUP-01", + "rv32i_m/F/FSUB-S-DYN-RDN-01", + "rv32i_m/F/FSUB-S-DYN-RMM-01", + "rv32i_m/F/FSUB-S-DYN-RNE-01", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", + "rv32i_m/F/FSUB-S-DYN-RUP-01", + "rv32i_m/F/FSUB-S-RDN-01", + "rv32i_m/F/FSUB-S-RMM-01", + "rv32i_m/F/FSUB-S-RNE-01", + "rv32i_m/F/FSUB-S-RTZ-01", + "rv32i_m/F/FSUB-S-RUP-01", + "rv32i_m/F/FSW-01" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FADD-S-RDN-01", "002010", - "rv64i_m/F/FADD-S-RMM-01", "002010", - "rv64i_m/F/FADD-S-RNE-01", "002010", - "rv64i_m/F/FADD-S-RTZ-01", "002010", - "rv64i_m/F/FADD-S-RUP-01", "002010", - "rv64i_m/F/FCLASS-S-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-L-S-RDN-01", "002010", - "rv64i_m/F/FCVT-L-S-RMM-01", "002010", - "rv64i_m/F/FCVT-L-S-RNE-01", "002010", - "rv64i_m/F/FCVT-L-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-L-S-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-LU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-LU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-LU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-LU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-LU-S-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-L-RDN-01", "002010", - "rv64i_m/F/FCVT-S-L-RMM-01", "002010", - "rv64i_m/F/FCVT-S-L-RNE-01", "002010", - "rv64i_m/F/FCVT-S-L-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-L-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-LU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-LU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-LU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-LU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-LU-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-W-RDN-01", "002010", - "rv64i_m/F/FCVT-S-W-RMM-01", "002010", - "rv64i_m/F/FCVT-S-W-RNE-01", "002010", - "rv64i_m/F/FCVT-S-W-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-W-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-S-WU-RDN-01", "002010", - "rv64i_m/F/FCVT-S-WU-RMM-01", "002010", - "rv64i_m/F/FCVT-S-WU-RNE-01", "002010", - "rv64i_m/F/FCVT-S-WU-RTZ-01", "002010", - "rv64i_m/F/FCVT-S-WU-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-W-S-RDN-01", "002010", - "rv64i_m/F/FCVT-W-S-RMM-01", "002010", - "rv64i_m/F/FCVT-W-S-RNE-01", "002010", - "rv64i_m/F/FCVT-W-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-W-S-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", "002010", - "rv64i_m/F/FCVT-WU-S-RDN-01", "002010", - "rv64i_m/F/FCVT-WU-S-RMM-01", "002010", - "rv64i_m/F/FCVT-WU-S-RNE-01", "002010", - "rv64i_m/F/FCVT-WU-S-RTZ-01", "002010", - "rv64i_m/F/FCVT-WU-S-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FDIV-S-RDN-01", "002010", - // "rv64i_m/F/FDIV-S-RMM-01", "002010", - // "rv64i_m/F/FDIV-S-RNE-01", "002010", - // "rv64i_m/F/FDIV-S-RTZ-01", "002010", - // "rv64i_m/F/FDIV-S-RUP-01", "002010", - "rv64i_m/F/FEQ-S-01", "002010", - "rv64i_m/F/FLE-S-01", "002010", - "rv64i_m/F/FLT-S-01", "002010", - "rv64i_m/F/FLW-01", "002210", - "rv64i_m/F/FMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMADD-S-RDN-01", "002010", - "rv64i_m/F/FMADD-S-RMM-01", "002010", - "rv64i_m/F/FMADD-S-RNE-01", "002010", - "rv64i_m/F/FMADD-S-RTZ-01", "002010", - "rv64i_m/F/FMADD-S-RUP-01", "002010", - "rv64i_m/F/FMAX-S-01", "002010", - "rv64i_m/F/FMIN-S-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMSUB-S-RDN-01", "002010", - "rv64i_m/F/FMSUB-S-RMM-01", "002010", - "rv64i_m/F/FMSUB-S-RNE-01", "002010", - "rv64i_m/F/FMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FMSUB-S-RUP-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RDN-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RMM-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RNE-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-DYN-RUP-01", "002010", - "rv64i_m/F/FMUL-S-RDN-01", "002010", - "rv64i_m/F/FMUL-S-RMM-01", "002010", - "rv64i_m/F/FMUL-S-RNE-01", "002010", - "rv64i_m/F/FMUL-S-RTZ-01", "002010", - "rv64i_m/F/FMUL-S-RUP-01", "002010", - "rv64i_m/F/FMV-W-X-01", "002010", - "rv64i_m/F/FMV-X-W-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMADD-S-RDN-01", "002010", - "rv64i_m/F/FNMADD-S-RMM-01", "002010", - "rv64i_m/F/FNMADD-S-RNE-01", "002010", - "rv64i_m/F/FNMADD-S-RTZ-01", "002010", - "rv64i_m/F/FNMADD-S-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FNMSUB-S-RDN-01", "002010", - "rv64i_m/F/FNMSUB-S-RMM-01", "002010", - "rv64i_m/F/FNMSUB-S-RNE-01", "002010", - "rv64i_m/F/FNMSUB-S-RTZ-01", "002010", - "rv64i_m/F/FNMSUB-S-RUP-01", "002010", - "rv64i_m/F/FSGNJN-S-01", "002010", - "rv64i_m/F/FSGNJ-S-01", "002010", - "rv64i_m/F/FSGNJX-S-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-DYN-RUP-01", "002010", - // "rv64i_m/F/FSQRT-S-RDN-01", "002010", - // "rv64i_m/F/FSQRT-S-RMM-01", "002010", - // "rv64i_m/F/FSQRT-S-RNE-01", "002010", - // "rv64i_m/F/FSQRT-S-RTZ-01", "002010", - // "rv64i_m/F/FSQRT-S-RUP-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RDN-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RMM-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RNE-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-DYN-RUP-01", "002010", - "rv64i_m/F/FSUB-S-RDN-01", "002010", - "rv64i_m/F/FSUB-S-RMM-01", "002010", - "rv64i_m/F/FSUB-S-RNE-01", "002010", - "rv64i_m/F/FSUB-S-RTZ-01", "002010", - "rv64i_m/F/FSUB-S-RUP-01", "002010", - "rv64i_m/F/FSW-01", "002010" + "rv64i_m/F/FADD-S-DYN-RDN-01", + "rv64i_m/F/FADD-S-DYN-RMM-01", + "rv64i_m/F/FADD-S-DYN-RNE-01", + "rv64i_m/F/FADD-S-DYN-RTZ-01", + "rv64i_m/F/FADD-S-DYN-RUP-01", + "rv64i_m/F/FADD-S-RDN-01", + "rv64i_m/F/FADD-S-RMM-01", + "rv64i_m/F/FADD-S-RNE-01", + "rv64i_m/F/FADD-S-RTZ-01", + "rv64i_m/F/FADD-S-RUP-01", + "rv64i_m/F/FCLASS-S-01", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", + "rv64i_m/F/FCVT-L-S-RDN-01", + "rv64i_m/F/FCVT-L-S-RMM-01", + "rv64i_m/F/FCVT-L-S-RNE-01", + "rv64i_m/F/FCVT-L-S-RTZ-01", + "rv64i_m/F/FCVT-L-S-RUP-01", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-LU-S-RDN-01", + "rv64i_m/F/FCVT-LU-S-RMM-01", + "rv64i_m/F/FCVT-LU-S-RNE-01", + "rv64i_m/F/FCVT-LU-S-RTZ-01", + "rv64i_m/F/FCVT-LU-S-RUP-01", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", + "rv64i_m/F/FCVT-S-L-RDN-01", + "rv64i_m/F/FCVT-S-L-RMM-01", + "rv64i_m/F/FCVT-S-L-RNE-01", + "rv64i_m/F/FCVT-S-L-RTZ-01", + "rv64i_m/F/FCVT-S-L-RUP-01", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-LU-RDN-01", + "rv64i_m/F/FCVT-S-LU-RMM-01", + "rv64i_m/F/FCVT-S-LU-RNE-01", + "rv64i_m/F/FCVT-S-LU-RTZ-01", + "rv64i_m/F/FCVT-S-LU-RUP-01", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", + "rv64i_m/F/FCVT-S-W-RDN-01", + "rv64i_m/F/FCVT-S-W-RMM-01", + "rv64i_m/F/FCVT-S-W-RNE-01", + "rv64i_m/F/FCVT-S-W-RTZ-01", + "rv64i_m/F/FCVT-S-W-RUP-01", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-WU-RDN-01", + "rv64i_m/F/FCVT-S-WU-RMM-01", + "rv64i_m/F/FCVT-S-WU-RNE-01", + "rv64i_m/F/FCVT-S-WU-RTZ-01", + "rv64i_m/F/FCVT-S-WU-RUP-01", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", + "rv64i_m/F/FCVT-W-S-RDN-01", + "rv64i_m/F/FCVT-W-S-RMM-01", + "rv64i_m/F/FCVT-W-S-RNE-01", + "rv64i_m/F/FCVT-W-S-RTZ-01", + "rv64i_m/F/FCVT-W-S-RUP-01", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-WU-S-RDN-01", + "rv64i_m/F/FCVT-WU-S-RMM-01", + "rv64i_m/F/FCVT-WU-S-RNE-01", + "rv64i_m/F/FCVT-WU-S-RTZ-01", + "rv64i_m/F/FCVT-WU-S-RUP-01", + "rv64i_m/F/FDIV-S-DYN-RDN-01", + "rv64i_m/F/FDIV-S-DYN-RMM-01", + "rv64i_m/F/FDIV-S-DYN-RNE-01", + "rv64i_m/F/FDIV-S-DYN-RTZ-01", + "rv64i_m/F/FDIV-S-DYN-RUP-01", + "rv64i_m/F/FDIV-S-RDN-01", + "rv64i_m/F/FDIV-S-RMM-01", + "rv64i_m/F/FDIV-S-RNE-01", + "rv64i_m/F/FDIV-S-RTZ-01", + "rv64i_m/F/FDIV-S-RUP-01", + "rv64i_m/F/FEQ-S-01", + "rv64i_m/F/FLE-S-01", + "rv64i_m/F/FLT-S-01", + "rv64i_m/F/FLW-01", + "rv64i_m/F/FMADD-S-DYN-RDN-01", + "rv64i_m/F/FMADD-S-DYN-RMM-01", + "rv64i_m/F/FMADD-S-DYN-RNE-01", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", + "rv64i_m/F/FMADD-S-DYN-RUP-01", + "rv64i_m/F/FMADD-S-RDN-01", + "rv64i_m/F/FMADD-S-RMM-01", + "rv64i_m/F/FMADD-S-RNE-01", + "rv64i_m/F/FMADD-S-RTZ-01", + "rv64i_m/F/FMADD-S-RUP-01", + "rv64i_m/F/FMAX-S-01", + "rv64i_m/F/FMIN-S-01", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", + "rv64i_m/F/FMSUB-S-RDN-01", + "rv64i_m/F/FMSUB-S-RMM-01", + "rv64i_m/F/FMSUB-S-RNE-01", + "rv64i_m/F/FMSUB-S-RTZ-01", + "rv64i_m/F/FMSUB-S-RUP-01", + "rv64i_m/F/FMUL-S-DYN-RDN-01", + "rv64i_m/F/FMUL-S-DYN-RMM-01", + "rv64i_m/F/FMUL-S-DYN-RNE-01", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", + "rv64i_m/F/FMUL-S-DYN-RUP-01", + "rv64i_m/F/FMUL-S-RDN-01", + "rv64i_m/F/FMUL-S-RMM-01", + "rv64i_m/F/FMUL-S-RNE-01", + "rv64i_m/F/FMUL-S-RTZ-01", + "rv64i_m/F/FMUL-S-RUP-01", + "rv64i_m/F/FMV-W-X-01", + "rv64i_m/F/FMV-X-W-01", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", + "rv64i_m/F/FNMADD-S-RDN-01", + "rv64i_m/F/FNMADD-S-RMM-01", + "rv64i_m/F/FNMADD-S-RNE-01", + "rv64i_m/F/FNMADD-S-RTZ-01", + "rv64i_m/F/FNMADD-S-RUP-01", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", + "rv64i_m/F/FNMSUB-S-RDN-01", + "rv64i_m/F/FNMSUB-S-RMM-01", + "rv64i_m/F/FNMSUB-S-RNE-01", + "rv64i_m/F/FNMSUB-S-RTZ-01", + "rv64i_m/F/FNMSUB-S-RUP-01", + "rv64i_m/F/FSGNJN-S-01", + "rv64i_m/F/FSGNJ-S-01", + "rv64i_m/F/FSGNJX-S-01", + "rv64i_m/F/FSQRT-S-DYN-RDN-01", + "rv64i_m/F/FSQRT-S-DYN-RMM-01", + "rv64i_m/F/FSQRT-S-DYN-RNE-01", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01", + "rv64i_m/F/FSQRT-S-DYN-RUP-01", + "rv64i_m/F/FSQRT-S-RDN-01", + "rv64i_m/F/FSQRT-S-RMM-01", + "rv64i_m/F/FSQRT-S-RNE-01", + "rv64i_m/F/FSQRT-S-RTZ-01", + "rv64i_m/F/FSQRT-S-RUP-01", + "rv64i_m/F/FSUB-S-DYN-RDN-01", + "rv64i_m/F/FSUB-S-DYN-RMM-01", + "rv64i_m/F/FSUB-S-DYN-RNE-01", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", + "rv64i_m/F/FSUB-S-DYN-RUP-01", + "rv64i_m/F/FSUB-S-RDN-01", + "rv64i_m/F/FSUB-S-RMM-01", + "rv64i_m/F/FSUB-S-RNE-01", + "rv64i_m/F/FSUB-S-RTZ-01", + "rv64i_m/F/FSUB-S-RUP-01", + "rv64i_m/F/FSW-01" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", "002010", - "rv64i_m/D/FADD-D-DYN-RMM-01", "002010", - "rv64i_m/D/FADD-D-DYN-RNE-01", "002010", - "rv64i_m/D/FADD-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FADD-D-DYN-RUP-01", "002010", - "rv64i_m/D/FADD-D-RDN-01", "002010", - "rv64i_m/D/FADD-D-RMM-01", "002010", - "rv64i_m/D/FADD-D-RNE-01", "002010", - "rv64i_m/D/FADD-D-RTZ-01", "002010", - "rv64i_m/D/FADD-D-RUP-01", "002010", - "rv64i_m/D/FCLASS-D-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-L-RDN-01", "002010", - "rv64i_m/D/FCVT-D-L-RMM-01", "002010", - "rv64i_m/D/FCVT-D-L-RNE-01", "002010", - "rv64i_m/D/FCVT-D-L-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-L-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-D-LU-RDN-01", "002010", - "rv64i_m/D/FCVT-D-LU-RMM-01", "002010", - "rv64i_m/D/FCVT-D-LU-RNE-01", "002010", - "rv64i_m/D/FCVT-D-LU-RTZ-01", "002010", - "rv64i_m/D/FCVT-D-LU-RUP-01", "002010", - "rv64i_m/D/FCVT-D-S-01", "002010", - "rv64i_m/D/FCVT-D-W-01", "002010", - "rv64i_m/D/FCVT-D-WU-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-L-D-RDN-01", "002010", - "rv64i_m/D/FCVT-L-D-RMM-01", "002010", - "rv64i_m/D/FCVT-L-D-RNE-01", "002010", - "rv64i_m/D/FCVT-L-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-L-D-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-LU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-LU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-LU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-LU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-LU-D-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-S-D-RDN-01", "002010", - "rv64i_m/D/FCVT-S-D-RMM-01", "002010", - "rv64i_m/D/FCVT-S-D-RNE-01", "002010", - "rv64i_m/D/FCVT-S-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-S-D-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-W-D-RDN-01", "002010", - "rv64i_m/D/FCVT-W-D-RMM-01", "002010", - "rv64i_m/D/FCVT-W-D-RNE-01", "002010", - "rv64i_m/D/FCVT-W-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-W-D-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", "002010", - "rv64i_m/D/FCVT-WU-D-RDN-01", "002010", - "rv64i_m/D/FCVT-WU-D-RMM-01", "002010", - "rv64i_m/D/FCVT-WU-D-RNE-01", "002010", - "rv64i_m/D/FCVT-WU-D-RTZ-01", "002010", - "rv64i_m/D/FCVT-WU-D-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FDIV-D-RDN-01", "002010", - // "rv64i_m/D/FDIV-D-RMM-01", "002010", - // "rv64i_m/D/FDIV-D-RNE-01", "002010", - // "rv64i_m/D/FDIV-D-RTZ-01", "002010", - // "rv64i_m/D/FDIV-D-RUP-01", "002010", - "rv64i_m/D/FEQ-D-01", "002010", - "rv64i_m/D/FLD-01", "002520", - "rv64i_m/D/FLE-D-01", "002010", - "rv64i_m/D/FLT-D-01", "002010", - "rv64i_m/D/FMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMADD-D-RDN-01", "003010", - "rv64i_m/D/FMADD-D-RMM-01", "003010", - "rv64i_m/D/FMADD-D-RNE-01", "003010", - "rv64i_m/D/FMADD-D-RTZ-01", "003010", - "rv64i_m/D/FMADD-D-RUP-01", "003010", - "rv64i_m/D/FMAX-D-01", "002010", - "rv64i_m/D/FMIN-D-01", "002010", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FMSUB-D-RDN-01", "003010", - "rv64i_m/D/FMSUB-D-RMM-01", "003010", - "rv64i_m/D/FMSUB-D-RNE-01", "003010", - "rv64i_m/D/FMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FMSUB-D-RUP-01", "003010", - "rv64i_m/D/FMUL-D-DYN-RDN-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RMM-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RNE-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-DYN-RUP-01", "002010", - "rv64i_m/D/FMUL-D-RDN-01", "002010", - "rv64i_m/D/FMUL-D-RMM-01", "002010", - "rv64i_m/D/FMUL-D-RNE-01", "002010", - "rv64i_m/D/FMUL-D-RTZ-01", "002010", - "rv64i_m/D/FMUL-D-RUP-01", "002010", - "rv64i_m/D/FMV-D-X-01", "002010", - "rv64i_m/D/FMV-X-D-01", "002010", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMADD-D-RDN-01", "003010", - "rv64i_m/D/FNMADD-D-RMM-01", "003010", - "rv64i_m/D/FNMADD-D-RNE-01", "003010", - "rv64i_m/D/FNMADD-D-RTZ-01", "003010", - "rv64i_m/D/FNMADD-D-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", "003010", - "rv64i_m/D/FNMSUB-D-RDN-01", "003010", - "rv64i_m/D/FNMSUB-D-RMM-01", "003010", - "rv64i_m/D/FNMSUB-D-RNE-01", "003010", - "rv64i_m/D/FNMSUB-D-RTZ-01", "003010", - "rv64i_m/D/FNMSUB-D-RUP-01", "003010", - "rv64i_m/D/FSD-01", "002010", - "rv64i_m/D/FSGNJ-D-01", "002010", - "rv64i_m/D/FSGNJN-D-01", "002010", - "rv64i_m/D/FSGNJX-D-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-DYN-RUP-01", "002010", - // "rv64i_m/D/FSQRT-D-RDN-01", "002010", - // "rv64i_m/D/FSQRT-D-RMM-01", "002010", - // "rv64i_m/D/FSQRT-D-RNE-01", "002010", - // "rv64i_m/D/FSQRT-D-RTZ-01", "002010", - // "rv64i_m/D/FSQRT-D-RUP-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RDN-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RMM-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RNE-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-DYN-RUP-01", "002010", - "rv64i_m/D/FSUB-D-RDN-01", "002010", - "rv64i_m/D/FSUB-D-RMM-01", "002010", - "rv64i_m/D/FSUB-D-RNE-01", "002010", - "rv64i_m/D/FSUB-D-RTZ-01", "002010", - "rv64i_m/D/FSUB-D-RUP-01", "002010" + "rv64i_m/D/FADD-D-DYN-RDN-01", + "rv64i_m/D/FADD-D-DYN-RMM-01", + "rv64i_m/D/FADD-D-DYN-RNE-01", + "rv64i_m/D/FADD-D-DYN-RTZ-01", + "rv64i_m/D/FADD-D-DYN-RUP-01", + "rv64i_m/D/FADD-D-RDN-01", + "rv64i_m/D/FADD-D-RMM-01", + "rv64i_m/D/FADD-D-RNE-01", + "rv64i_m/D/FADD-D-RTZ-01", + "rv64i_m/D/FADD-D-RUP-01", + "rv64i_m/D/FCLASS-D-01", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", + "rv64i_m/D/FCVT-D-L-RDN-01", + "rv64i_m/D/FCVT-D-L-RMM-01", + "rv64i_m/D/FCVT-D-L-RNE-01", + "rv64i_m/D/FCVT-D-L-RTZ-01", + "rv64i_m/D/FCVT-D-L-RUP-01", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", + "rv64i_m/D/FCVT-D-LU-RDN-01", + "rv64i_m/D/FCVT-D-LU-RMM-01", + "rv64i_m/D/FCVT-D-LU-RNE-01", + "rv64i_m/D/FCVT-D-LU-RTZ-01", + "rv64i_m/D/FCVT-D-LU-RUP-01", + "rv64i_m/D/FCVT-D-S-01", + "rv64i_m/D/FCVT-D-W-01", + "rv64i_m/D/FCVT-D-WU-01", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", + "rv64i_m/D/FCVT-L-D-RDN-01", + "rv64i_m/D/FCVT-L-D-RMM-01", + "rv64i_m/D/FCVT-L-D-RNE-01", + "rv64i_m/D/FCVT-L-D-RTZ-01", + "rv64i_m/D/FCVT-L-D-RUP-01", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-LU-D-RDN-01", + "rv64i_m/D/FCVT-LU-D-RMM-01", + "rv64i_m/D/FCVT-LU-D-RNE-01", + "rv64i_m/D/FCVT-LU-D-RTZ-01", + "rv64i_m/D/FCVT-LU-D-RUP-01", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", + "rv64i_m/D/FCVT-S-D-RDN-01", + "rv64i_m/D/FCVT-S-D-RMM-01", + "rv64i_m/D/FCVT-S-D-RNE-01", + "rv64i_m/D/FCVT-S-D-RTZ-01", + "rv64i_m/D/FCVT-S-D-RUP-01", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", + "rv64i_m/D/FCVT-W-D-RDN-01", + "rv64i_m/D/FCVT-W-D-RMM-01", + "rv64i_m/D/FCVT-W-D-RNE-01", + "rv64i_m/D/FCVT-W-D-RTZ-01", + "rv64i_m/D/FCVT-W-D-RUP-01", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-WU-D-RDN-01", + "rv64i_m/D/FCVT-WU-D-RMM-01", + "rv64i_m/D/FCVT-WU-D-RNE-01", + "rv64i_m/D/FCVT-WU-D-RTZ-01", + "rv64i_m/D/FCVT-WU-D-RUP-01", + "rv64i_m/D/FDIV-D-DYN-RDN-01", + "rv64i_m/D/FDIV-D-DYN-RMM-01", + "rv64i_m/D/FDIV-D-DYN-RNE-01", + "rv64i_m/D/FDIV-D-DYN-RTZ-01", + "rv64i_m/D/FDIV-D-DYN-RUP-01", + "rv64i_m/D/FDIV-D-RDN-01", + "rv64i_m/D/FDIV-D-RMM-01", + "rv64i_m/D/FDIV-D-RNE-01", + "rv64i_m/D/FDIV-D-RTZ-01", + "rv64i_m/D/FDIV-D-RUP-01", + "rv64i_m/D/FEQ-D-01", + "rv64i_m/D/FLD-01", + "rv64i_m/D/FLE-D-01", + "rv64i_m/D/FLT-D-01", + "rv64i_m/D/FMADD-D-DYN-RDN-01", + "rv64i_m/D/FMADD-D-DYN-RMM-01", + "rv64i_m/D/FMADD-D-DYN-RNE-01", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", + "rv64i_m/D/FMADD-D-DYN-RUP-01", + "rv64i_m/D/FMADD-D-RDN-01", + "rv64i_m/D/FMADD-D-RMM-01", + "rv64i_m/D/FMADD-D-RNE-01", + "rv64i_m/D/FMADD-D-RTZ-01", + "rv64i_m/D/FMADD-D-RUP-01", + "rv64i_m/D/FMAX-D-01", + "rv64i_m/D/FMIN-D-01", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", + "rv64i_m/D/FMSUB-D-RDN-01", + "rv64i_m/D/FMSUB-D-RMM-01", + "rv64i_m/D/FMSUB-D-RNE-01", + "rv64i_m/D/FMSUB-D-RTZ-01", + "rv64i_m/D/FMSUB-D-RUP-01", + "rv64i_m/D/FMUL-D-DYN-RDN-01", + "rv64i_m/D/FMUL-D-DYN-RMM-01", + "rv64i_m/D/FMUL-D-DYN-RNE-01", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", + "rv64i_m/D/FMUL-D-DYN-RUP-01", + "rv64i_m/D/FMUL-D-RDN-01", + "rv64i_m/D/FMUL-D-RMM-01", + "rv64i_m/D/FMUL-D-RNE-01", + "rv64i_m/D/FMUL-D-RTZ-01", + "rv64i_m/D/FMUL-D-RUP-01", + "rv64i_m/D/FMV-D-X-01", + "rv64i_m/D/FMV-X-D-01", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", + "rv64i_m/D/FNMADD-D-RDN-01", + "rv64i_m/D/FNMADD-D-RMM-01", + "rv64i_m/D/FNMADD-D-RNE-01", + "rv64i_m/D/FNMADD-D-RTZ-01", + "rv64i_m/D/FNMADD-D-RUP-01", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", + "rv64i_m/D/FNMSUB-D-RDN-01", + "rv64i_m/D/FNMSUB-D-RMM-01", + "rv64i_m/D/FNMSUB-D-RNE-01", + "rv64i_m/D/FNMSUB-D-RTZ-01", + "rv64i_m/D/FNMSUB-D-RUP-01", + "rv64i_m/D/FSD-01", + "rv64i_m/D/FSGNJ-D-01", + "rv64i_m/D/FSGNJN-D-01", + "rv64i_m/D/FSGNJX-D-01", + "rv64i_m/D/FSQRT-D-DYN-RDN-01", + "rv64i_m/D/FSQRT-D-DYN-RMM-01", + "rv64i_m/D/FSQRT-D-DYN-RNE-01", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01", + "rv64i_m/D/FSQRT-D-DYN-RUP-01", + "rv64i_m/D/FSQRT-D-RDN-01", + "rv64i_m/D/FSQRT-D-RMM-01", + "rv64i_m/D/FSQRT-D-RNE-01", + "rv64i_m/D/FSQRT-D-RTZ-01", + "rv64i_m/D/FSQRT-D-RUP-01", + "rv64i_m/D/FSUB-D-DYN-RDN-01", + "rv64i_m/D/FSUB-D-DYN-RMM-01", + "rv64i_m/D/FSUB-D-DYN-RNE-01", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", + "rv64i_m/D/FSUB-D-DYN-RUP-01", + "rv64i_m/D/FSUB-D-RDN-01", + "rv64i_m/D/FSUB-D-RMM-01", + "rv64i_m/D/FSUB-D-RNE-01", + "rv64i_m/D/FSUB-D-RTZ-01", + "rv64i_m/D/FSUB-D-RUP-01" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", "004010", - "rv64i_m/M/DIVU-01", "004010", - "rv64i_m/M/DIVUW-01", "003010", - "rv64i_m/M/DIVW-01", "003010", - "rv64i_m/M/MUL-01", "004010", - "rv64i_m/M/MULH-01", "004010", - "rv64i_m/M/MULHSU-01", "004010", - "rv64i_m/M/MULHU-01", "004010", - "rv64i_m/M/MULW-01", "003010", - "rv64i_m/M/REM-01", "004010", - "rv64i_m/M/REMU-01", "004010", - "rv64i_m/M/REMUW-01", "003010", - "rv64i_m/M/REMW-01", "003010" + "rv64i_m/M/DIV-01", + "rv64i_m/M/DIVU-01", + "rv64i_m/M/DIVUW-01", + "rv64i_m/M/DIVW-01", + "rv64i_m/M/MUL-01", + "rv64i_m/M/MULH-01", + "rv64i_m/M/MULHSU-01", + "rv64i_m/M/MULHU-01", + "rv64i_m/M/MULW-01", + "rv64i_m/M/REM-01", + "rv64i_m/M/REMU-01", + "rv64i_m/M/REMUW-01", + "rv64i_m/M/REMW-01" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", "003010", - "rv64i_m/C/C-ADDI-01", "003010", - "rv64i_m/C/C-ADDI16SP-01", "003010", - "rv64i_m/C/C-ADDI4SPN-01", "003010", - "rv64i_m/C/C-ADDIW-01", "003010", - "rv64i_m/C/C-ADDW-01", "003010", - "rv64i_m/C/C-AND-01", "003010", - "rv64i_m/C/C-ANDI-01", "003010", - "rv64i_m/C/C-BEQZ-01", "004010", - "rv64i_m/C/C-BNEZ-01", "004010", - "rv64i_m/C/C-J-01", "003010", - "rv64i_m/C/C-JALR-01", "004010", - "rv64i_m/C/C-JR-01", "004010", - "rv64i_m/C/C-LD-01", "003520", - "rv64i_m/C/C-LDSP-01", "003520", - "rv64i_m/C/C-LI-01", "003010", - "rv64i_m/C/C-LUI-01", "002010", - "rv64i_m/C/C-LW-01", "003210", - "rv64i_m/C/C-LWSP-01", "003210", - "rv64i_m/C/C-MV-01", "003010", - "rv64i_m/C/C-OR-01", "003010", - "rv64i_m/C/C-SD-01", "003010", - "rv64i_m/C/C-SDSP-01", "003010", - "rv64i_m/C/C-SLLI-01", "003010", - "rv64i_m/C/C-SRAI-01", "003010", - "rv64i_m/C/C-SRLI-01", "003010", - "rv64i_m/C/C-SUB-01", "003010", - "rv64i_m/C/C-SUBW-01", "003010", - "rv64i_m/C/C-SW-01", "003010", - "rv64i_m/C/C-SWSP-01", "003010", - "rv64i_m/C/C-XOR-01", "003010", - "rv64i_m/C/I-C-EBREAK-01", "002000", - "rv64i_m/C/I-C-NOP-01", "002000" + "rv64i_m/C/C-ADD-01", + "rv64i_m/C/C-ADDI-01", + "rv64i_m/C/C-ADDI16SP-01", + "rv64i_m/C/C-ADDI4SPN-01", + "rv64i_m/C/C-ADDIW-01", + "rv64i_m/C/C-ADDW-01", + "rv64i_m/C/C-AND-01", + "rv64i_m/C/C-ANDI-01", + "rv64i_m/C/C-BEQZ-01", + "rv64i_m/C/C-BNEZ-01", + "rv64i_m/C/C-J-01", + "rv64i_m/C/C-JALR-01", + "rv64i_m/C/C-JR-01", + "rv64i_m/C/C-LD-01", + "rv64i_m/C/C-LDSP-01", + "rv64i_m/C/C-LI-01", + "rv64i_m/C/C-LUI-01", + "rv64i_m/C/C-LW-01", + "rv64i_m/C/C-LWSP-01", + "rv64i_m/C/C-MV-01", + "rv64i_m/C/C-OR-01", + "rv64i_m/C/C-SD-01", + "rv64i_m/C/C-SDSP-01", + "rv64i_m/C/C-SLLI-01", + "rv64i_m/C/C-SRAI-01", + "rv64i_m/C/C-SRLI-01", + "rv64i_m/C/C-SUB-01", + "rv64i_m/C/C-SUBW-01", + "rv64i_m/C/C-SW-01", + "rv64i_m/C/C-SWSP-01", + "rv64i_m/C/C-XOR-01", + "rv64i_m/C/I-C-EBREAK-01", + "rv64i_m/C/I-C-NOP-01" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01", "002000" + "rv64i_m/I/I-MISALIGN_JMP-01" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/ADD-01", "004010", - "rv64i_m/I/ADDI-01", "003010", - "rv64i_m/I/ADDIW-01", "003010", - "rv64i_m/I/ADDW-01", "003010", - "rv64i_m/I/AND-01", "004010", - "rv64i_m/I/ANDI-01", "003010", - "rv64i_m/I/AUIPC-01", "003010", - "rv64i_m/I/BEQ-01", "005010", - "rv64i_m/I/BGE-01", "005010", - "rv64i_m/I/BGEU-01", "005010", - "rv64i_m/I/BLT-01", "005010", - "rv64i_m/I/BLTU-01", "005010", - "rv64i_m/I/BNE-01", "005010", - "rv64i_m/I/I-DELAY_SLOTS-01", "002010", - "rv64i_m/I/I-EBREAK-01", "002010", - "rv64i_m/I/I-ECALL-01", "002010", - "rv64i_m/I/I-ENDIANESS-01", "002010", - "rv64i_m/I/I-IO-01", "002050", -// "rv64i_m/I/I-MISALIGN_JMP-01", "002000", - "rv64i_m/I/I-MISALIGN_LDST-01", "002010", - "rv64i_m/I/I-NOP-01", "002000", - "rv64i_m/I/I-RF_size-01", "002000", - "rv64i_m/I/I-RF_width-01", "002000", - "rv64i_m/I/I-RF_x0-01", "002010", - "rv64i_m/I/JAL-01", "004010", - "rv64i_m/I/JALR-01", "005010", - "rv64i_m/I/LB-01", "004120", - "rv64i_m/I/LBU-01", "004120", - "rv64i_m/I/LD-01", "004520", - "rv64i_m/I/LH-01", "004150", - "rv64i_m/I/LHU-01", "004150", - "rv64i_m/I/LUI-01", "002010", - "rv64i_m/I/LW-01", "004210", - "rv64i_m/I/LWU-01", "004210", - "rv64i_m/I/OR-01", "004010", - "rv64i_m/I/ORI-01", "003010", - "rv64i_m/I/SB-01", "004010", - "rv64i_m/I/SD-01", "004010", - "rv64i_m/I/SH-01", "004010", - "rv64i_m/I/SLL-01", "003010", - "rv64i_m/I/SLLI-01", "003010", - "rv64i_m/I/SLLIW-01", "003010", - "rv64i_m/I/SLLW-01", "003010", - "rv64i_m/I/SLT-01", "004010", - "rv64i_m/I/SLTI-01", "003010", - "rv64i_m/I/SLTIU-01", "003010", - "rv64i_m/I/SLTU-01", "004010", - "rv64i_m/I/SRA-01", "003010", - "rv64i_m/I/SRAI-01", "003010", - "rv64i_m/I/SRAIW-01", "003010", - "rv64i_m/I/SRAW-01", "003010", - "rv64i_m/I/SRL-01", "003010", - "rv64i_m/I/SRLI-01", "003010", - "rv64i_m/I/SRLIW-01", "003010", - "rv64i_m/I/SRLW-01", "003010", - "rv64i_m/I/SUB-01", "004010", - "rv64i_m/I/SUBW-01", "003010", - "rv64i_m/I/SW-01", "004010", - "rv64i_m/I/XOR-01", "004010", - "rv64i_m/I/XORI-01", "003010" + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/ADD-01", + "rv64i_m/I/ADDI-01", + "rv64i_m/I/ADDIW-01", + "rv64i_m/I/ADDW-01", + "rv64i_m/I/AND-01", + "rv64i_m/I/ANDI-01", + "rv64i_m/I/AUIPC-01", + "rv64i_m/I/BEQ-01", + "rv64i_m/I/BGE-01", + "rv64i_m/I/BGEU-01", + "rv64i_m/I/BLT-01", + "rv64i_m/I/BLTU-01", + "rv64i_m/I/BNE-01", + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/I-EBREAK-01", + "rv64i_m/I/I-ECALL-01", + "rv64i_m/I/I-ENDIANESS-01", + "rv64i_m/I/I-IO-01", +// "rv64i_m/I/I-MISALIGN_JMP-01", + "rv64i_m/I/I-MISALIGN_LDST-01", + "rv64i_m/I/I-NOP-01", + "rv64i_m/I/I-RF_size-01", + "rv64i_m/I/I-RF_width-01", + "rv64i_m/I/I-RF_x0-01", + "rv64i_m/I/JAL-01", + "rv64i_m/I/JALR-01", + "rv64i_m/I/LB-01", + "rv64i_m/I/LBU-01", + "rv64i_m/I/LD-01", + "rv64i_m/I/LH-01", + "rv64i_m/I/LHU-01", + "rv64i_m/I/LUI-01", + "rv64i_m/I/LW-01", + "rv64i_m/I/LWU-01", + "rv64i_m/I/OR-01", + "rv64i_m/I/ORI-01", + "rv64i_m/I/SB-01", + "rv64i_m/I/SD-01", + "rv64i_m/I/SH-01", + "rv64i_m/I/SLL-01", + "rv64i_m/I/SLLI-01", + "rv64i_m/I/SLLIW-01", + "rv64i_m/I/SLLW-01", + "rv64i_m/I/SLT-01", + "rv64i_m/I/SLTI-01", + "rv64i_m/I/SLTIU-01", + "rv64i_m/I/SLTU-01", + "rv64i_m/I/SRA-01", + "rv64i_m/I/SRAI-01", + "rv64i_m/I/SRAIW-01", + "rv64i_m/I/SRAW-01", + "rv64i_m/I/SRL-01", + "rv64i_m/I/SRLI-01", + "rv64i_m/I/SRLIW-01", + "rv64i_m/I/SRLW-01", + "rv64i_m/I/SUB-01", + "rv64i_m/I/SUBW-01", + "rv64i_m/I/SW-01", + "rv64i_m/I/XOR-01", + "rv64i_m/I/XORI-01" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", "002010", - "rv32i_m/M/DIVU-01", "002010", - "rv32i_m/M/MUL-01", "002010", - "rv32i_m/M/MULH-01", "002010", - "rv32i_m/M/MULHSU-01", "002010", - "rv32i_m/M/MULHU-01", "002010", - "rv32i_m/M/REM-01", "002010", - "rv32i_m/M/REMU-01", "002010" + "rv32i_m/M/DIV-01", + "rv32i_m/M/DIVU-01", + "rv32i_m/M/MUL-01", + "rv32i_m/M/MULH-01", + "rv32i_m/M/MULHSU-01", + "rv32i_m/M/MULHU-01", + "rv32i_m/M/REM-01", + "rv32i_m/M/REMU-01" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", "002010", - "rv32i_m/C/C-ADDI-01", "002010", - "rv32i_m/C/C-ADDI16SP-01", "002010", - "rv32i_m/C/C-ADDI4SPN-01", "002010", - "rv32i_m/C/C-AND-01", "002010", - "rv32i_m/C/C-ANDI-01", "002010", - "rv32i_m/C/C-BEQZ-01", "003010", - "rv32i_m/C/C-BNEZ-01", "003010", - "rv32i_m/C/C-J-01", "002010", - "rv32i_m/C/C-JAL-01", "002010", - "rv32i_m/C/C-JALR-01", "003010", - "rv32i_m/C/C-JR-01", "003010", - "rv32i_m/C/C-LI-01", "002010", - "rv32i_m/C/C-LUI-01", "002010", - "rv32i_m/C/C-LW-01", "002120", - "rv32i_m/C/C-LWSP-01", "002120", - "rv32i_m/C/C-MV-01", "002010", - "rv32i_m/C/C-OR-01", "002010", - "rv32i_m/C/C-SLLI-01", "002010", - "rv32i_m/C/C-SRAI-01", "002010", - "rv32i_m/C/C-SRLI-01", "002010", - "rv32i_m/C/C-SUB-01", "002010", - "rv32i_m/C/C-SW-01", "002010", - "rv32i_m/C/C-SWSP-01", "002010", - "rv32i_m/C/C-XOR-01", "002010", - "rv32i_m/C/I-C-EBREAK-01", "002000", - "rv32i_m/C/I-C-NOP-01", "002000" + "rv32i_m/C/C-ADD-01", + "rv32i_m/C/C-ADDI-01", + "rv32i_m/C/C-ADDI16SP-01", + "rv32i_m/C/C-ADDI4SPN-01", + "rv32i_m/C/C-AND-01", + "rv32i_m/C/C-ANDI-01", + "rv32i_m/C/C-BEQZ-01", + "rv32i_m/C/C-BNEZ-01", + "rv32i_m/C/C-J-01", + "rv32i_m/C/C-JAL-01", + "rv32i_m/C/C-JALR-01", + "rv32i_m/C/C-JR-01", + "rv32i_m/C/C-LI-01", + "rv32i_m/C/C-LUI-01", + "rv32i_m/C/C-LW-01", + "rv32i_m/C/C-LWSP-01", + "rv32i_m/C/C-MV-01", + "rv32i_m/C/C-OR-01", + "rv32i_m/C/C-SLLI-01", + "rv32i_m/C/C-SRAI-01", + "rv32i_m/C/C-SRLI-01", + "rv32i_m/C/C-SUB-01", + "rv32i_m/C/C-SW-01", + "rv32i_m/C/C-SWSP-01", + "rv32i_m/C/C-XOR-01", + "rv32i_m/C/I-C-EBREAK-01", + "rv32i_m/C/I-C-NOP-01" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01", "002000" + "rv32i_m/I/I-MISALIGN_JMP-01" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", "002010", - "rv32i_m/I/ADDI-01", "002010", - "rv32i_m/I/AND-01", "002010", - "rv32i_m/I/ANDI-01", "002010", - "rv32i_m/I/AUIPC-01", "002010", - "rv32i_m/I/BEQ-01", "003010", - "rv32i_m/I/BGE-01", "003010", - "rv32i_m/I/BGEU-01", "003010", - "rv32i_m/I/BLT-01", "003010", - "rv32i_m/I/BLTU-01", "003010", - "rv32i_m/I/BNE-01", "003010", - "rv32i_m/I/I-DELAY_SLOTS-01", "002010", - "rv32i_m/I/I-EBREAK-01", "002010", - "rv32i_m/I/I-ECALL-01", "002010", - "rv32i_m/I/I-ENDIANESS-01", "002010", - "rv32i_m/I/I-IO-01", "002030", -// "rv32i_m/I/I-MISALIGN_JMP-01", "002000", - "rv32i_m/I/I-MISALIGN_LDST-01", "002010", - "rv32i_m/I/I-NOP-01", "002000", - "rv32i_m/I/I-RF_size-01", "002000", - "rv32i_m/I/I-RF_width-01", "002000", - "rv32i_m/I/I-RF_x0-01", "002010", - "rv32i_m/I/JAL-01", "003010", - "rv32i_m/I/JALR-01", "003010", - "rv32i_m/I/LB-01", "003030", - "rv32i_m/I/LBU-01", "003030", - "rv32i_m/I/LH-01", "003060", - "rv32i_m/I/LHU-01", "003060", - "rv32i_m/I/LUI-01", "002010", - "rv32i_m/I/LW-01", "003120", - "rv32i_m/I/OR-01", "002010", - "rv32i_m/I/ORI-01", "002010", - "rv32i_m/I/SB-01", "003010", - "rv32i_m/I/SH-01", "003010", - "rv32i_m/I/SLL-01", "002010", - "rv32i_m/I/SLLI-01", "002010", - "rv32i_m/I/SLT-01", "002010", - "rv32i_m/I/SLTI-01", "002010", - "rv32i_m/I/SLTIU-01", "002010", - "rv32i_m/I/SLTU-01", "002010", - "rv32i_m/I/SRA-01", "002010", - "rv32i_m/I/SRAI-01", "002010", - "rv32i_m/I/SRL-01", "002010", - "rv32i_m/I/SRLI-01", "002010", - "rv32i_m/I/SUB-01", "002010", - "rv32i_m/I/SW-01", "003010", - "rv32i_m/I/XOR-01", "002010", - "rv32i_m/I/XORI-01", "002010" + "rv32i_m/I/ADD-01", + "rv32i_m/I/ADDI-01", + "rv32i_m/I/AND-01", + "rv32i_m/I/ANDI-01", + "rv32i_m/I/AUIPC-01", + "rv32i_m/I/BEQ-01", + "rv32i_m/I/BGE-01", + "rv32i_m/I/BGEU-01", + "rv32i_m/I/BLT-01", + "rv32i_m/I/BLTU-01", + "rv32i_m/I/BNE-01", + "rv32i_m/I/I-DELAY_SLOTS-01", + "rv32i_m/I/I-EBREAK-01", + "rv32i_m/I/I-ECALL-01", + "rv32i_m/I/I-ENDIANESS-01", + "rv32i_m/I/I-IO-01", +// "rv32i_m/I/I-MISALIGN_JMP-01", + "rv32i_m/I/I-MISALIGN_LDST-01", + "rv32i_m/I/I-NOP-01", + "rv32i_m/I/I-RF_size-01", + "rv32i_m/I/I-RF_width-01", + "rv32i_m/I/I-RF_x0-01", + "rv32i_m/I/JAL-01", + "rv32i_m/I/JALR-01", + "rv32i_m/I/LB-01", + "rv32i_m/I/LBU-01", + "rv32i_m/I/LH-01", + "rv32i_m/I/LHU-01", + "rv32i_m/I/LUI-01", + "rv32i_m/I/LW-01", + "rv32i_m/I/OR-01", + "rv32i_m/I/ORI-01", + "rv32i_m/I/SB-01", + "rv32i_m/I/SH-01", + "rv32i_m/I/SLL-01", + "rv32i_m/I/SLLI-01", + "rv32i_m/I/SLT-01", + "rv32i_m/I/SLTI-01", + "rv32i_m/I/SLTIU-01", + "rv32i_m/I/SLTU-01", + "rv32i_m/I/SRA-01", + "rv32i_m/I/SRAI-01", + "rv32i_m/I/SRL-01", + "rv32i_m/I/SRLI-01", + "rv32i_m/I/SUB-01", + "rv32i_m/I/SW-01", + "rv32i_m/I/XOR-01", + "rv32i_m/I/XORI-01" }; string testsBP64[] = '{ `IMPERASTEST, - "rv64BP/simple", "10000", - "rv64BP/mmm", "1000000", - "rv64BP/linpack_bench", "1000000", - "rv64BP/sieve", "1000000", - "rv64BP/qsort", "1000000", - "rv64BP/dhrystone", "1000000" + "rv64BP/simple", + "rv64BP/mmm", + "rv64BP/linpack_bench", + "rv64BP/sieve", + "rv64BP/qsort", + "rv64BP/dhrystone" }; string imperas32p[] = '{ `MYIMPERASTEST, - "rv32p/WALLY-MSTATUS", "2000", - "rv32p/WALLY-MCAUSE", "3000", - "rv32p/WALLY-SCAUSE", "2000", - "rv32p/WALLY-MEPC", "5000", - "rv32p/WALLY-SEPC", "4000", - "rv32p/WALLY-MTVAL", "5000", - "rv32p/WALLY-STVAL", "4000", - "rv32p/WALLY-MARCHID", "4000", - "rv32p/WALLY-MIMPID", "4000", - "rv32p/WALLY-MHARTID", "4000", - "rv32p/WALLY-MVENDORID", "4000", - "rv32p/WALLY-MTVEC", "2000", - "rv32p/WALLY-STVEC", "2000", - "rv32p/WALLY-MIE", "3000", - "rv32p/WALLY-MEDELEG", "4000", - "rv32p/WALLY-IP", "3000", - "rv32p/WALLY-CSR-PERMISSIONS-M", "5000", - "rv32p/WALLY-CSR-PERMISSIONS-S", "3000" + "rv32p/WALLY-MSTATUS", + "rv32p/WALLY-MCAUSE", + "rv32p/WALLY-SCAUSE", + "rv32p/WALLY-MEPC", + "rv32p/WALLY-SEPC", + "rv32p/WALLY-MTVAL", + "rv32p/WALLY-STVAL", + "rv32p/WALLY-MARCHID", + "rv32p/WALLY-MIMPID", + "rv32p/WALLY-MHARTID", + "rv32p/WALLY-MVENDORID", + "rv32p/WALLY-MTVEC", + "rv32p/WALLY-STVEC", + "rv32p/WALLY-MIE", + "rv32p/WALLY-MEDELEG", + "rv32p/WALLY-IP", + "rv32p/WALLY-CSR-PERMISSIONS-M", + "rv32p/WALLY-CSR-PERMISSIONS-S" }; + string wally64a[] = '{ + `WALLYTEST, + "rv64i_m/privilege/src/WALLY-amo.S", + "rv64i_m/privilege/src/WALLY-lrsc.S", + "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S" + }; + + string wally32a[] = '{ + `WALLYTEST, + "rv32i_m/privilege/src/WALLY-amo.S", + "rv32i_m/privilege/src/WALLY-lrsc.S", + "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S" + }; + string arch64priv[] = '{ `RISCVARCHTEST, - "rv64i_m/privilege/ebreak", "2090", - "rv64i_m/privilege/ecall", "2090", - "rv64i_m/privilege/misalign-beq-01", "20a0", - "rv64i_m/privilege/misalign-bge-01", "20a0", - "rv64i_m/privilege/misalign-bgeu-01", "20a0", - "rv64i_m/privilege/misalign-blt-01", "20a0", - "rv64i_m/privilege/misalign-bltu-01", "20a0", - "rv64i_m/privilege/misalign-bne-01", "20a0", - "rv64i_m/privilege/misalign-jal-01", "20a0", - "rv64i_m/privilege/misalign-ld-01", "20a0", - "rv64i_m/privilege/misalign-lh-01", "20a0", - "rv64i_m/privilege/misalign-lhu-01", "20a0", - "rv64i_m/privilege/misalign-lw-01", "20a0", - "rv64i_m/privilege/misalign-lwu-01", "20a0", - "rv64i_m/privilege/misalign-sd-01", "20a0", - "rv64i_m/privilege/misalign-sh-01", "20a0", - "rv64i_m/privilege/misalign-sw-01", "20a0", - "rv64i_m/privilege/misalign1-jalr-01", "20a0", - "rv64i_m/privilege/misalign2-jalr-01", "20a0" + "rv64i_m/privilege/src/ebreak.S", + "rv64i_m/privilege/src/ecall.S", + "rv64i_m/privilege/src/misalign1-jalr-01.S", + "rv64i_m/privilege/src/misalign2-jalr-01.S", + "rv64i_m/privilege/src/misalign-beq-01.S", + "rv64i_m/privilege/src/misalign-bge-01.S", + "rv64i_m/privilege/src/misalign-bgeu-01.S", + "rv64i_m/privilege/src/misalign-blt-01.S", + "rv64i_m/privilege/src/misalign-bltu-01.S", + "rv64i_m/privilege/src/misalign-bne-01.S", + "rv64i_m/privilege/src/misalign-jal-01.S", + "rv64i_m/privilege/src/misalign-ld-01.S", + "rv64i_m/privilege/src/misalign-lh-01.S", + "rv64i_m/privilege/src/misalign-lhu-01.S", + "rv64i_m/privilege/src/misalign-lw-01.S", + "rv64i_m/privilege/src/misalign-lwu-01.S", + "rv64i_m/privilege/src/misalign-sd-01.S", + "rv64i_m/privilege/src/misalign-sh-01.S", + "rv64i_m/privilege/src/misalign-sw-01.S" }; string arch64m[] = '{ `RISCVARCHTEST, - "rv64i_m/M/div-01", "9010", - "rv64i_m/M/divu-01", "a010", - "rv64i_m/M/divuw-01", "a010", - "rv64i_m/M/divw-01", "9010", - "rv64i_m/M/mul-01", "9010", - "rv64i_m/M/mulh-01", "9010", - "rv64i_m/M/mulhsu-01", "9010", - "rv64i_m/M/mulhu-01", "a010", - "rv64i_m/M/mulw-01", "9010", - "rv64i_m/M/rem-01", "9010", - "rv64i_m/M/remu-01", "a010", - "rv64i_m/M/remuw-01", "a010", - "rv64i_m/M/remw-01", "9010" + "rv64i_m/M/src/div-01.S", + "rv64i_m/M/src/divu-01.S", + "rv64i_m/M/src/divuw-01.S", + "rv64i_m/M/src/divw-01.S", + "rv64i_m/M/src/mul-01.S", + "rv64i_m/M/src/mulh-01.S", + "rv64i_m/M/src/mulhsu-01.S", + "rv64i_m/M/src/mulhu-01.S", + "rv64i_m/M/src/mulw-01.S", + "rv64i_m/M/src/rem-01.S", + "rv64i_m/M/src/remu-01.S", + "rv64i_m/M/src/remuw-01.S", + "rv64i_m/M/src/remw-01.S" }; string arch64c[] = '{ `RISCVARCHTEST, - "rv64i_m/C/cadd-01", "8010", - "rv64i_m/C/caddi-01", "4010", - "rv64i_m/C/caddi16sp-01", "2010", - "rv64i_m/C/caddi4spn-01", "2010", - "rv64i_m/C/caddiw-01", "4010", - "rv64i_m/C/caddw-01", "8010", - "rv64i_m/C/cand-01", "8010", - "rv64i_m/C/candi-01", "4010", - "rv64i_m/C/cbeqz-01", "4010", - "rv64i_m/C/cbnez-01", "5010", - "rv64i_m/C/cj-01", "3010", - "rv64i_m/C/cjalr-01", "2010", - "rv64i_m/C/cjr-01", "2010", - "rv64i_m/C/cld-01", "2010", - "rv64i_m/C/cldsp-01", "2010", - "rv64i_m/C/cli-01", "2010", - "rv64i_m/C/clui-01", "2010", - "rv64i_m/C/clw-01", "2010", - "rv64i_m/C/clwsp-01", "2010", - "rv64i_m/C/cmv-01", "2010", - "rv64i_m/C/cnop-01", "2010", - "rv64i_m/C/cor-01", "8010", - "rv64i_m/C/csd-01", "3010", - "rv64i_m/C/csdsp-01", "3010", - "rv64i_m/C/cslli-01", "2010", - "rv64i_m/C/csrai-01", "2010", - "rv64i_m/C/csrli-01", "2010", - "rv64i_m/C/csub-01", "8010", - "rv64i_m/C/csubw-01", "8010", - "rv64i_m/C/csw-01", "3010", - "rv64i_m/C/cswsp-01", "3010", - "rv64i_m/C/cxor-01", "8010" + "rv64i_m/C/src/cadd-01.S", + "rv64i_m/C/src/caddi-01.S", + "rv64i_m/C/src/caddi16sp-01.S", + "rv64i_m/C/src/caddi4spn-01.S", + "rv64i_m/C/src/caddiw-01.S", + "rv64i_m/C/src/caddw-01.S", + "rv64i_m/C/src/cand-01.S", + "rv64i_m/C/src/candi-01.S", + "rv64i_m/C/src/cbeqz-01.S", + "rv64i_m/C/src/cbnez-01.S", + "rv64i_m/C/src/cj-01.S", + "rv64i_m/C/src/cjalr-01.S", + "rv64i_m/C/src/cjr-01.S", + "rv64i_m/C/src/cld-01.S", + "rv64i_m/C/src/cldsp-01.S", + "rv64i_m/C/src/cli-01.S", + "rv64i_m/C/src/clui-01.S", + "rv64i_m/C/src/clw-01.S", + "rv64i_m/C/src/clwsp-01.S", + "rv64i_m/C/src/cmv-01.S", + "rv64i_m/C/src/cnop-01.S", + "rv64i_m/C/src/cor-01.S", + "rv64i_m/C/src/csd-01.S", + "rv64i_m/C/src/csdsp-01.S", + "rv64i_m/C/src/cslli-01.S", + "rv64i_m/C/src/csrai-01.S", + "rv64i_m/C/src/csrli-01.S", + "rv64i_m/C/src/csub-01.S", + "rv64i_m/C/src/csubw-01.S", + "rv64i_m/C/src/csw-01.S", + "rv64i_m/C/src/cswsp-01.S", + "rv64i_m/C/src/cxor-01.S" }; string arch64cpriv[] = '{ // `RISCVARCHTEST, - "rv64i_m/C/cebreak-01", "2070" + "rv64i_m/C/src/cebreak-01.S" }; string arch64i[] = '{ `RISCVARCHTEST, - "rv64i_m/I/add-01", "9010", - "rv64i_m/I/addi-01", "6010", - "rv64i_m/I/addiw-01", "6010", - "rv64i_m/I/addw-01", "9010", - "rv64i_m/I/and-01", "9010", - "rv64i_m/I/andi-01", "6010", - "rv64i_m/I/auipc-01", "2010", - "rv64i_m/I/beq-01", "47010", - "rv64i_m/I/bge-01", "46010", - "rv64i_m/I/bgeu-01", "56010", - "rv64i_m/I/blt-01", "4d010", - "rv64i_m/I/bltu-01", "57010", - "rv64i_m/I/bne-01", "43010", - "rv64i_m/I/fence-01", "2010", - "rv64i_m/I/jal-01", "122010", - "rv64i_m/I/jalr-01", "2010", - "rv64i_m/I/lb-align-01", "2010", - "rv64i_m/I/lbu-align-01", "2010", - "rv64i_m/I/ld-align-01", "2010", - "rv64i_m/I/lh-align-01", "2010", - "rv64i_m/I/lhu-align-01", "2010", - "rv64i_m/I/lui-01", "2010", - "rv64i_m/I/lw-align-01", "2010", - "rv64i_m/I/lwu-align-01", "2010", - "rv64i_m/I/or-01", "9010", - "rv64i_m/I/ori-01", "6010", - "rv64i_m/I/sb-align-01", "3010", - "rv64i_m/I/sd-align-01", "3010", - "rv64i_m/I/sh-align-01", "3010", - "rv64i_m/I/sll-01", "3010", - "rv64i_m/I/slli-01", "2010", - "rv64i_m/I/slliw-01", "2010", - "rv64i_m/I/sllw-01", "3010", - "rv64i_m/I/slt-01", "9010", - "rv64i_m/I/slti-01", "6010", - "rv64i_m/I/sltiu-01", "6010", - "rv64i_m/I/sltu-01", "a010", - "rv64i_m/I/sra-01", "3010", - "rv64i_m/I/srai-01", "2010", - "rv64i_m/I/sraiw-01", "2010", - "rv64i_m/I/sraw-01", "3010", - "rv64i_m/I/srl-01", "3010", - "rv64i_m/I/srli-01", "2010", - "rv64i_m/I/srliw-01", "2010", - "rv64i_m/I/srlw-01", "3010", - "rv64i_m/I/sub-01", "9010", - "rv64i_m/I/subw-01", "9010", - "rv64i_m/I/sw-align-01", "3010", - "rv64i_m/I/xor-01", "9010", - "rv64i_m/I/xori-01", "6010" + "rv64i_m/I/src/add-01.S", + "rv64i_m/I/src/addi-01.S", + "rv64i_m/I/src/addiw-01.S", + "rv64i_m/I/src/addw-01.S", + "rv64i_m/I/src/and-01.S", + "rv64i_m/I/src/andi-01.S", + "rv64i_m/I/src/auipc-01.S", + "rv64i_m/I/src/beq-01.S", + "rv64i_m/I/src/bge-01.S", + "rv64i_m/I/src/bgeu-01.S", + "rv64i_m/I/src/blt-01.S", + "rv64i_m/I/src/bltu-01.S", + "rv64i_m/I/src/bne-01.S", + "rv64i_m/I/src/fence-01.S", + "rv64i_m/I/src/jal-01.S", + "rv64i_m/I/src/jalr-01.S", + "rv64i_m/I/src/lb-align-01.S", + "rv64i_m/I/src/lbu-align-01.S", + "rv64i_m/I/src/ld-align-01.S", + "rv64i_m/I/src/lh-align-01.S", + "rv64i_m/I/src/lhu-align-01.S", + "rv64i_m/I/src/lui-01.S", + "rv64i_m/I/src/lw-align-01.S", + "rv64i_m/I/src/lwu-align-01.S", + "rv64i_m/I/src/or-01.S", + "rv64i_m/I/src/ori-01.S", + "rv64i_m/I/src/sb-align-01.S", + "rv64i_m/I/src/sd-align-01.S", + "rv64i_m/I/src/sh-align-01.S", + "rv64i_m/I/src/sll-01.S", + "rv64i_m/I/src/slli-01.S", + "rv64i_m/I/src/slliw-01.S", + "rv64i_m/I/src/sllw-01.S", + "rv64i_m/I/src/slt-01.S", + "rv64i_m/I/src/slti-01.S", + "rv64i_m/I/src/sltiu-01.S", + "rv64i_m/I/src/sltu-01.S", + "rv64i_m/I/src/sra-01.S", + "rv64i_m/I/src/srai-01.S", + "rv64i_m/I/src/sraiw-01.S", + "rv64i_m/I/src/sraw-01.S", + "rv64i_m/I/src/srl-01.S", + "rv64i_m/I/src/srli-01.S", + "rv64i_m/I/src/srliw-01.S", + "rv64i_m/I/src/srlw-01.S", + "rv64i_m/I/src/sub-01.S", + "rv64i_m/I/src/subw-01.S", + "rv64i_m/I/src/sw-align-01.S", + "rv64i_m/I/src/xor-01.S", + "rv64i_m/I/src/xori-01.S" }; + string arch64f[] = '{ + `RISCVARCHTEST, + "rv64i_m/F/src/fadd_b10-01.S", + "rv64i_m/F/src/fadd_b1-01.S", + "rv64i_m/F/src/fadd_b11-01.S", + "rv64i_m/F/src/fadd_b12-01.S", + "rv64i_m/F/src/fadd_b13-01.S", + "rv64i_m/F/src/fadd_b2-01.S", + "rv64i_m/F/src/fadd_b3-01.S", + "rv64i_m/F/src/fadd_b4-01.S", + "rv64i_m/F/src/fadd_b5-01.S", + "rv64i_m/F/src/fadd_b7-01.S", + "rv64i_m/F/src/fadd_b8-01.S", + "rv64i_m/F/src/fclass_b1-01.S", + "rv64i_m/F/src/fcvt.s.w_b25-01.S", + "rv64i_m/F/src/fcvt.s.w_b26-01.S", + "rv64i_m/F/src/fcvt.s.wu_b25-01.S", + "rv64i_m/F/src/fcvt.s.wu_b26-01.S", + "rv64i_m/F/src/fcvt.w.s_b1-01.S", + "rv64i_m/F/src/fcvt.w.s_b22-01.S", + "rv64i_m/F/src/fcvt.w.s_b23-01.S", + "rv64i_m/F/src/fcvt.w.s_b24-01.S", + "rv64i_m/F/src/fcvt.w.s_b27-01.S", + "rv64i_m/F/src/fcvt.w.s_b28-01.S", + "rv64i_m/F/src/fcvt.w.s_b29-01.S", + "rv64i_m/F/src/fcvt.wu.s_b1-01.S", + "rv64i_m/F/src/fcvt.wu.s_b22-01.S", + "rv64i_m/F/src/fcvt.wu.s_b23-01.S", + "rv64i_m/F/src/fcvt.wu.s_b24-01.S", + "rv64i_m/F/src/fcvt.wu.s_b27-01.S", + "rv64i_m/F/src/fcvt.wu.s_b28-01.S", + "rv64i_m/F/src/fcvt.wu.s_b29-01.S", + "rv64i_m/F/src/fdiv_b1-01.S", + "rv64i_m/F/src/fdiv_b20-01.S", + "rv64i_m/F/src/fdiv_b2-01.S", + "rv64i_m/F/src/fdiv_b21-01.S", + "rv64i_m/F/src/fdiv_b3-01.S", + "rv64i_m/F/src/fdiv_b4-01.S", + "rv64i_m/F/src/fdiv_b5-01.S", + "rv64i_m/F/src/fdiv_b6-01.S", + "rv64i_m/F/src/fdiv_b7-01.S", + "rv64i_m/F/src/fdiv_b8-01.S", + "rv64i_m/F/src/fdiv_b9-01.S", + "rv64i_m/F/src/feq_b1-01.S", + "rv64i_m/F/src/feq_b19-01.S", + "rv64i_m/F/src/fle_b1-01.S", + "rv64i_m/F/src/fle_b19-01.S", + "rv64i_m/F/src/flt_b1-01.S", + "rv64i_m/F/src/flt_b19-01.S", + // "rv64i_m/F/src/flw-align-01.S", + "rv64i_m/F/src/fmadd_b1-01.S", + "rv64i_m/F/src/fmadd_b14-01.S", + // "rv64i_m/F/src/fmadd_b15-01.S", + "rv64i_m/F/src/fmadd_b16-01.S", + "rv64i_m/F/src/fmadd_b17-01.S", + "rv64i_m/F/src/fmadd_b18-01.S", + "rv64i_m/F/src/fmadd_b2-01.S", + "rv64i_m/F/src/fmadd_b3-01.S", + "rv64i_m/F/src/fmadd_b4-01.S", + "rv64i_m/F/src/fmadd_b5-01.S", + "rv64i_m/F/src/fmadd_b6-01.S", + "rv64i_m/F/src/fmadd_b7-01.S", + "rv64i_m/F/src/fmadd_b8-01.S", + "rv64i_m/F/src/fmax_b1-01.S", + "rv64i_m/F/src/fmax_b19-01.S", + "rv64i_m/F/src/fmin_b1-01.S", + "rv64i_m/F/src/fmin_b19-01.S", + "rv64i_m/F/src/fmsub_b1-01.S", + "rv64i_m/F/src/fmsub_b14-01.S", + "rv64i_m/F/src/fmsub_b15-01.S", + "rv64i_m/F/src/fmsub_b16-01.S", + "rv64i_m/F/src/fmsub_b17-01.S", + "rv64i_m/F/src/fmsub_b18-01.S", + "rv64i_m/F/src/fmsub_b2-01.S", + "rv64i_m/F/src/fmsub_b3-01.S", + "rv64i_m/F/src/fmsub_b4-01.S", + "rv64i_m/F/src/fmsub_b5-01.S", + "rv64i_m/F/src/fmsub_b6-01.S", + "rv64i_m/F/src/fmsub_b7-01.S", + "rv64i_m/F/src/fmsub_b8-01.S", + "rv64i_m/F/src/fmul_b1-01.S", + "rv64i_m/F/src/fmul_b2-01.S", + "rv64i_m/F/src/fmul_b3-01.S", + "rv64i_m/F/src/fmul_b4-01.S", + "rv64i_m/F/src/fmul_b5-01.S", + "rv64i_m/F/src/fmul_b6-01.S", + "rv64i_m/F/src/fmul_b7-01.S", + "rv64i_m/F/src/fmul_b8-01.S", + "rv64i_m/F/src/fmul_b9-01.S", + "rv64i_m/F/src/fmv.w.x_b25-01.S", + "rv64i_m/F/src/fmv.w.x_b26-01.S", + "rv64i_m/F/src/fmv.x.w_b1-01.S", + "rv64i_m/F/src/fmv.x.w_b22-01.S", + "rv64i_m/F/src/fmv.x.w_b23-01.S", + "rv64i_m/F/src/fmv.x.w_b24-01.S", + "rv64i_m/F/src/fmv.x.w_b27-01.S", + "rv64i_m/F/src/fmv.x.w_b28-01.S", + "rv64i_m/F/src/fmv.x.w_b29-01.S", + "rv64i_m/F/src/fnmadd_b1-01.S", + "rv64i_m/F/src/fnmadd_b14-01.S", + // "rv64i_m/F/src/fnmadd_b15-01.S", + "rv64i_m/F/src/fnmadd_b16-01.S", + "rv64i_m/F/src/fnmadd_b17-01.S", + "rv64i_m/F/src/fnmadd_b18-01.S", + "rv64i_m/F/src/fnmadd_b2-01.S", + "rv64i_m/F/src/fnmadd_b3-01.S", + "rv64i_m/F/src/fnmadd_b4-01.S", + "rv64i_m/F/src/fnmadd_b5-01.S", + "rv64i_m/F/src/fnmadd_b6-01.S", + "rv64i_m/F/src/fnmadd_b7-01.S", + "rv64i_m/F/src/fnmadd_b8-01.S", + "rv64i_m/F/src/fnmsub_b1-01.S", + "rv64i_m/F/src/fnmsub_b14-01.S", + // "rv64i_m/F/src/fnmsub_b15-01.S", + "rv64i_m/F/src/fnmsub_b16-01.S", + "rv64i_m/F/src/fnmsub_b17-01.S", + "rv64i_m/F/src/fnmsub_b18-01.S", + "rv64i_m/F/src/fnmsub_b2-01.S", + "rv64i_m/F/src/fnmsub_b3-01.S", + "rv64i_m/F/src/fnmsub_b4-01.S", + "rv64i_m/F/src/fnmsub_b5-01.S", + "rv64i_m/F/src/fnmsub_b6-01.S", + "rv64i_m/F/src/fnmsub_b7-01.S", + "rv64i_m/F/src/fnmsub_b8-01.S", + "rv64i_m/F/src/fsgnj_b1-01.S", + "rv64i_m/F/src/fsgnjn_b1-01.S", + "rv64i_m/F/src/fsgnjx_b1-01.S", + "rv64i_m/F/src/fsqrt_b1-01.S", + "rv64i_m/F/src/fsqrt_b20-01.S", + "rv64i_m/F/src/fsqrt_b2-01.S", + "rv64i_m/F/src/fsqrt_b3-01.S", + "rv64i_m/F/src/fsqrt_b4-01.S", + "rv64i_m/F/src/fsqrt_b5-01.S", + "rv64i_m/F/src/fsqrt_b7-01.S", + "rv64i_m/F/src/fsqrt_b8-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S", + "rv64i_m/F/src/fsub_b10-01.S", + "rv64i_m/F/src/fsub_b1-01.S", + "rv64i_m/F/src/fsub_b11-01.S", + "rv64i_m/F/src/fsub_b12-01.S", + "rv64i_m/F/src/fsub_b13-01.S", + "rv64i_m/F/src/fsub_b2-01.S", + "rv64i_m/F/src/fsub_b3-01.S", + "rv64i_m/F/src/fsub_b4-01.S", + "rv64i_m/F/src/fsub_b5-01.S", + "rv64i_m/F/src/fsub_b7-01.S", + "rv64i_m/F/src/fsub_b8-01.S" + // "rv64i_m/F/src/fsw-align-01.S" + }; + string arch64d[] = '{ `RISCVARCHTEST, - "rv64i_m/D/d_fadd_b10-01", "8690", - "rv64i_m/D/d_fadd_b1-01", "8430", - "rv64i_m/D/d_fadd_b11-01", "74da0", - "rv64i_m/D/d_fadd_b12-01", "2350", - "rv64i_m/D/d_fadd_b13-01", "3cb0", - "rv64i_m/D/d_fadd_b2-01", "5160", - "rv64i_m/D/d_fadd_b3-01", "d640", - "rv64i_m/D/d_fadd_b4-01", "3900", - "rv64i_m/D/d_fadd_b5-01", "3d50", - "rv64i_m/D/d_fadd_b7-01", "5530", - "rv64i_m/D/d_fadd_b8-01", "11c10", - "rv64i_m/D/d_fclass_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.l_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.lu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.lu_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.s_b1-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b22-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b23-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b24-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b27-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b28-01", "2110", - "rv64i_m/D/d_fcvt.d.s_b29-01", "2110", - "rv64i_m/D/d_fcvt.d.w_b25-01", "2120", - "rv64i_m/D/d_fcvt.d.w_b26-01", "2220", - "rv64i_m/D/d_fcvt.d.wu_b25-01", "2110", - "rv64i_m/D/d_fcvt.d.wu_b26-01", "2220", - "rv64i_m/D/d_fcvt.l.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.l.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.l.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.l.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.l.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.l.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.lu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b22-01", "2260", - "rv64i_m/D/d_fcvt.lu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.lu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.lu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.lu.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.s.d_b1-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b22-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.s.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.s.d_b27-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b28-01", "2110", - "rv64i_m/D/d_fcvt.s.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.w.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.w.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.w.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.w.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.w.d_b29-01", "22a0", - "rv64i_m/D/d_fcvt.wu.d_b1-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b22-01", "2160", - "rv64i_m/D/d_fcvt.wu.d_b23-01", "2180", - "rv64i_m/D/d_fcvt.wu.d_b24-01", "2360", - "rv64i_m/D/d_fcvt.wu.d_b27-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b28-01", "2120", - "rv64i_m/D/d_fcvt.wu.d_b29-01", "22a0", - // "rv64i_m/D/d_fdiv_b1-01", "8430", // RV NaNs need to be positive - // "rv64i_m/D/d_fdiv_b20-01", "3fa0", // looks like flags - // "rv64i_m/D/d_fdiv_b2-01", "5170", // also flags - // "rv64i_m/D/d_fdiv_b21-01", "8a70", // positive NaNs again - "rv64i_m/D/d_fdiv_b3-01", "d630", - // "rv64i_m/D/d_fdiv_b4-01", "38f0", // flags - "rv64i_m/D/d_fdiv_b5-01", "3d50", - // "rv64i_m/D/d_fdiv_b6-01", "38f0", // flags - "rv64i_m/D/d_fdiv_b7-01", "5530", - // "rv64i_m/D/d_fdiv_b8-01", "11c10", // flags - // "rv64i_m/D/d_fdiv_b9-01", "1b0f0", might be a flag too - "rv64i_m/D/d_feq_b1-01", "7430", - "rv64i_m/D/d_feq_b19-01", "c4c0", - "rv64i_m/D/d_fld-align-01", "2010", - "rv64i_m/D/d_fle_b1-01", "7430", - "rv64i_m/D/d_fle_b19-01", "c4c0", - "rv64i_m/D/d_flt_b1-01", "7430", - "rv64i_m/D/d_flt_b19-01", "d800", - "rv64i_m/D/d_fmadd_b14-01", "3fd0", - "rv64i_m/D/d_fmadd_b16-01", "43b0", - "rv64i_m/D/d_fmadd_b17-01", "43b0", - "rv64i_m/D/d_fmadd_b18-01", "5a20", - "rv64i_m/D/d_fmadd_b2-01", "5ab0", - "rv64i_m/D/d_fmadd_b3-01", "119d0", - "rv64i_m/D/d_fmadd_b4-01", "3df0", - "rv64i_m/D/d_fmadd_b5-01", "4480", - "rv64i_m/D/d_fmadd_b6-01", "3df0", - "rv64i_m/D/d_fmadd_b7-01", "6050", - "rv64i_m/D/d_fmadd_b8-01", "15aa0", - "rv64i_m/D/d_fmax_b1-01", "8430", - "rv64i_m/D/d_fmax_b19-01", "d5c0", - "rv64i_m/D/d_fmin_b1-01", "8430", - "rv64i_m/D/d_fmin_b19-01", "d4b0", - "rv64i_m/D/d_fmsub_b14-01", "3fd0", - "rv64i_m/D/d_fmsub_b16-01", "43b0", - "rv64i_m/D/d_fmsub_b17-01", "43b0", - "rv64i_m/D/d_fmsub_b18-01", "5a20", - "rv64i_m/D/d_fmsub_b2-01", "5ab0", - "rv64i_m/D/d_fmsub_b3-01", "119f0", - "rv64i_m/D/d_fmsub_b4-01", "3df0", - "rv64i_m/D/d_fmsub_b5-01", "4480", - "rv64i_m/D/d_fmsub_b6-01", "3df0", - "rv64i_m/D/d_fmsub_b7-01", "6050", - "rv64i_m/D/d_fmsub_b8-01", "15aa0", - "rv64i_m/D/d_fmul_b1-01", "8430", - "rv64i_m/D/d_fmul_b2-01", "5180", - "rv64i_m/D/d_fmul_b3-01", "d640", - "rv64i_m/D/d_fmul_b4-01", "38f0", - "rv64i_m/D/d_fmul_b5-01", "3d50", - "rv64i_m/D/d_fmul_b6-01", "38f0", - "rv64i_m/D/d_fmul_b7-01", "5540", - "rv64i_m/D/d_fmul_b8-01", "11c10", - "rv64i_m/D/d_fmul_b9-01", "1b0f0", - "rv64i_m/D/d_fmv.d.x_b25-01", "2110", - "rv64i_m/D/d_fmv.d.x_b26-01", "2220", - "rv64i_m/D/d_fmv.x.d_b1-01", "2120", - "rv64i_m/D/d_fmv.x.d_b22-01", "2110", - "rv64i_m/D/d_fmv.x.d_b23-01", "2110", - "rv64i_m/D/d_fmv.x.d_b24-01", "2120", - "rv64i_m/D/d_fmv.x.d_b27-01", "2120", - "rv64i_m/D/d_fmv.x.d_b28-01", "2110", - "rv64i_m/D/d_fmv.x.d_b29-01", "2120", - "rv64i_m/D/d_fnmadd_b14-01", "3fd0", - "rv64i_m/D/d_fnmadd_b16-01", "4390", - "rv64i_m/D/d_fnmadd_b17-01", "4390", - "rv64i_m/D/d_fnmadd_b18-01", "5a20", - "rv64i_m/D/d_fnmadd_b2-01", "5ab0", - "rv64i_m/D/d_fnmadd_b3-01", "119d0", - "rv64i_m/D/d_fnmadd_b4-01", "3df0", - "rv64i_m/D/d_fnmadd_b5-01", "4480", - "rv64i_m/D/d_fnmadd_b6-01", "3df0", - "rv64i_m/D/d_fnmadd_b7-01", "6050", - "rv64i_m/D/d_fnmadd_b8-01", "15aa0", - "rv64i_m/D/d_fnmsub_b14-01", "3fd0", - "rv64i_m/D/d_fnmsub_b16-01", "4390", - "rv64i_m/D/d_fnmsub_b17-01", "4390", - "rv64i_m/D/d_fnmsub_b18-01", "5a20", - "rv64i_m/D/d_fnmsub_b2-01", "5aa0", - "rv64i_m/D/d_fnmsub_b3-01", "119d0", - "rv64i_m/D/d_fnmsub_b4-01", "3e20", - "rv64i_m/D/d_fnmsub_b5-01", "4480", - "rv64i_m/D/d_fnmsub_b6-01", "3e10", - "rv64i_m/D/d_fnmsub_b7-01", "6050", - "rv64i_m/D/d_fnmsub_b8-01", "15aa0", - "rv64i_m/D/d_fsd-align-01", "2010", - "rv64i_m/D/d_fsgnj_b1-01", "8430", - "rv64i_m/D/d_fsgnjn_b1-01", "8430", - "rv64i_m/D/d_fsgnjx_b1-01", "8430", - // "rv64i_m/D/d_fsqrt_b1-01", "2110", // flg - // "rv64i_m/D/d_fsqrt_b20-01", "3460", // flg - // "rv64i_m/D/d_fsqrt_b2-01", "2190", // flg - I'm going to stop here with the sqrt - // "rv64i_m/D/d_fsqrt_b3-01", "2120", - // "rv64i_m/D/d_fsqrt_b4-01", "2110", - // "rv64i_m/D/d_fsqrt_b5-01", "2110", - // "rv64i_m/D/d_fsqrt_b7-01", "2110", - // "rv64i_m/D/d_fsqrt_b8-01", "2110", - // "rv64i_m/D/d_fsqrt_b9-01", "4c10", - "rv64i_m/D/d_fsub_b10-01", "8660", - "rv64i_m/D/d_fsub_b1-01", "8440", - "rv64i_m/D/d_fsub_b11-01", "74da0", - "rv64i_m/D/d_fsub_b12-01", "2350", - "rv64i_m/D/d_fsub_b13-01", "3cb0", - "rv64i_m/D/d_fsub_b2-01", "5160", - "rv64i_m/D/d_fsub_b3-01", "d630", - "rv64i_m/D/d_fsub_b4-01", "38f0", - "rv64i_m/D/d_fsub_b5-01", "3d50", - "rv64i_m/D/d_fsub_b7-01", "5530", - "rv64i_m/D/d_fsub_b8-01", "11c10" - }; + "rv64i_m/D/src/fadd.d_b10-01.S", + "rv64i_m/D/src/fadd.d_b1-01.S", + "rv64i_m/D/src/fadd.d_b11-01.S", + "rv64i_m/D/src/fadd.d_b12-01.S", + "rv64i_m/D/src/fadd.d_b13-01.S", + "rv64i_m/D/src/fadd.d_b2-01.S", + "rv64i_m/D/src/fadd.d_b3-01.S", + "rv64i_m/D/src/fadd.d_b4-01.S", + "rv64i_m/D/src/fadd.d_b5-01.S", + "rv64i_m/D/src/fadd.d_b7-01.S", + "rv64i_m/D/src/fadd.d_b8-01.S", + "rv64i_m/D/src/fclass.d_b1-01.S", + "rv64i_m/D/src/fcvt.d.l_b25-01.S", + "rv64i_m/D/src/fcvt.d.l_b26-01.S", + "rv64i_m/D/src/fcvt.d.lu_b25-01.S", + "rv64i_m/D/src/fcvt.d.lu_b26-01.S", + "rv64i_m/D/src/fcvt.d.s_b1-01.S", + "rv64i_m/D/src/fcvt.d.s_b22-01.S", + "rv64i_m/D/src/fcvt.d.s_b23-01.S", + "rv64i_m/D/src/fcvt.d.s_b24-01.S", + "rv64i_m/D/src/fcvt.d.s_b27-01.S", + "rv64i_m/D/src/fcvt.d.s_b28-01.S", + "rv64i_m/D/src/fcvt.d.s_b29-01.S", + "rv64i_m/D/src/fcvt.d.w_b25-01.S", + "rv64i_m/D/src/fcvt.d.w_b26-01.S", + "rv64i_m/D/src/fcvt.d.wu_b25-01.S", + "rv64i_m/D/src/fcvt.d.wu_b26-01.S", + "rv64i_m/D/src/fcvt.l.d_b1-01.S", + "rv64i_m/D/src/fcvt.l.d_b22-01.S", + "rv64i_m/D/src/fcvt.l.d_b23-01.S", + "rv64i_m/D/src/fcvt.l.d_b24-01.S", + "rv64i_m/D/src/fcvt.l.d_b27-01.S", + "rv64i_m/D/src/fcvt.l.d_b28-01.S", + "rv64i_m/D/src/fcvt.l.d_b29-01.S", + "rv64i_m/D/src/fcvt.lu.d_b1-01.S", + "rv64i_m/D/src/fcvt.lu.d_b22-01.S", + "rv64i_m/D/src/fcvt.lu.d_b23-01.S", + "rv64i_m/D/src/fcvt.lu.d_b24-01.S", + "rv64i_m/D/src/fcvt.lu.d_b27-01.S", + "rv64i_m/D/src/fcvt.lu.d_b28-01.S", + "rv64i_m/D/src/fcvt.lu.d_b29-01.S", + "rv64i_m/D/src/fcvt.s.d_b1-01.S", + "rv64i_m/D/src/fcvt.s.d_b22-01.S", + "rv64i_m/D/src/fcvt.s.d_b23-01.S", + "rv64i_m/D/src/fcvt.s.d_b24-01.S", + "rv64i_m/D/src/fcvt.s.d_b27-01.S", + "rv64i_m/D/src/fcvt.s.d_b28-01.S", + "rv64i_m/D/src/fcvt.s.d_b29-01.S", + "rv64i_m/D/src/fcvt.w.d_b1-01.S", + "rv64i_m/D/src/fcvt.w.d_b22-01.S", + "rv64i_m/D/src/fcvt.w.d_b23-01.S", + "rv64i_m/D/src/fcvt.w.d_b24-01.S", + "rv64i_m/D/src/fcvt.w.d_b27-01.S", + "rv64i_m/D/src/fcvt.w.d_b28-01.S", + "rv64i_m/D/src/fcvt.w.d_b29-01.S", + "rv64i_m/D/src/fcvt.wu.d_b1-01.S", + "rv64i_m/D/src/fcvt.wu.d_b22-01.S", + "rv64i_m/D/src/fcvt.wu.d_b23-01.S", + "rv64i_m/D/src/fcvt.wu.d_b24-01.S", + "rv64i_m/D/src/fcvt.wu.d_b27-01.S", + "rv64i_m/D/src/fcvt.wu.d_b28-01.S", + "rv64i_m/D/src/fcvt.wu.d_b29-01.S", + "rv64i_m/D/src/fdiv.d_b1-01.S", + "rv64i_m/D/src/fdiv.d_b20-01.S", + "rv64i_m/D/src/fdiv.d_b2-01.S", + "rv64i_m/D/src/fdiv.d_b21-01.S", + "rv64i_m/D/src/fdiv.d_b3-01.S", + "rv64i_m/D/src/fdiv.d_b4-01.S", + "rv64i_m/D/src/fdiv.d_b5-01.S", + "rv64i_m/D/src/fdiv.d_b6-01.S", + "rv64i_m/D/src/fdiv.d_b7-01.S", + "rv64i_m/D/src/fdiv.d_b8-01.S", + "rv64i_m/D/src/fdiv.d_b9-01.S", + "rv64i_m/D/src/feq.d_b1-01.S", + "rv64i_m/D/src/feq.d_b19-01.S", + "rv64i_m/D/src/fle.d_b1-01.S", + "rv64i_m/D/src/fle.d_b19-01.S", + "rv64i_m/D/src/flt.d_b1-01.S", + "rv64i_m/D/src/flt.d_b19-01.S", + // "rv64i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back + // "rv64i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266 + "rv64i_m/D/src/fmadd.d_b14-01.S", + "rv64i_m/D/src/fmadd.d_b16-01.S", + "rv64i_m/D/src/fmadd.d_b17-01.S", + "rv64i_m/D/src/fmadd.d_b18-01.S", + "rv64i_m/D/src/fmadd.d_b2-01.S", + "rv64i_m/D/src/fmadd.d_b3-01.S", + "rv64i_m/D/src/fmadd.d_b4-01.S", + "rv64i_m/D/src/fmadd.d_b5-01.S", + "rv64i_m/D/src/fmadd.d_b6-01.S", + "rv64i_m/D/src/fmadd.d_b7-01.S", + "rv64i_m/D/src/fmadd.d_b8-01.S", + "rv64i_m/D/src/fmax.d_b1-01.S", + "rv64i_m/D/src/fmax.d_b19-01.S", + "rv64i_m/D/src/fmin.d_b1-01.S", + "rv64i_m/D/src/fmin.d_b19-01.S", + "rv64i_m/D/src/fmsub.d_b14-01.S", + "rv64i_m/D/src/fmsub.d_b16-01.S", + "rv64i_m/D/src/fmsub.d_b17-01.S", + "rv64i_m/D/src/fmsub.d_b18-01.S", + "rv64i_m/D/src/fmsub.d_b2-01.S", + "rv64i_m/D/src/fmsub.d_b3-01.S", + "rv64i_m/D/src/fmsub.d_b4-01.S", + "rv64i_m/D/src/fmsub.d_b5-01.S", + "rv64i_m/D/src/fmsub.d_b6-01.S", + "rv64i_m/D/src/fmsub.d_b7-01.S", + "rv64i_m/D/src/fmsub.d_b8-01.S", + "rv64i_m/D/src/fmul.d_b1-01.S", + "rv64i_m/D/src/fmul.d_b2-01.S", + "rv64i_m/D/src/fmul.d_b3-01.S", + "rv64i_m/D/src/fmul.d_b4-01.S", + "rv64i_m/D/src/fmul.d_b5-01.S", + "rv64i_m/D/src/fmul.d_b6-01.S", + "rv64i_m/D/src/fmul.d_b7-01.S", + "rv64i_m/D/src/fmul.d_b8-01.S", + "rv64i_m/D/src/fmul.d_b9-01.S", + "rv64i_m/D/src/fmv.d.x_b25-01.S", + "rv64i_m/D/src/fmv.d.x_b26-01.S", + "rv64i_m/D/src/fmv.x.d_b1-01.S", + "rv64i_m/D/src/fmv.x.d_b22-01.S", + "rv64i_m/D/src/fmv.x.d_b23-01.S", + "rv64i_m/D/src/fmv.x.d_b24-01.S", + "rv64i_m/D/src/fmv.x.d_b27-01.S", + "rv64i_m/D/src/fmv.x.d_b28-01.S", + "rv64i_m/D/src/fmv.x.d_b29-01.S", + "rv64i_m/D/src/fnmadd.d_b14-01.S", + "rv64i_m/D/src/fnmadd.d_b16-01.S", + "rv64i_m/D/src/fnmadd.d_b17-01.S", + "rv64i_m/D/src/fnmadd.d_b18-01.S", + "rv64i_m/D/src/fnmadd.d_b2-01.S", + "rv64i_m/D/src/fnmadd.d_b3-01.S", + "rv64i_m/D/src/fnmadd.d_b4-01.S", + "rv64i_m/D/src/fnmadd.d_b5-01.S", + "rv64i_m/D/src/fnmadd.d_b6-01.S", + "rv64i_m/D/src/fnmadd.d_b7-01.S", + "rv64i_m/D/src/fnmadd.d_b8-01.S", + "rv64i_m/D/src/fnmsub.d_b14-01.S", + "rv64i_m/D/src/fnmsub.d_b16-01.S", + "rv64i_m/D/src/fnmsub.d_b17-01.S", + "rv64i_m/D/src/fnmsub.d_b18-01.S", + "rv64i_m/D/src/fnmsub.d_b2-01.S", + "rv64i_m/D/src/fnmsub.d_b3-01.S", + "rv64i_m/D/src/fnmsub.d_b4-01.S", + "rv64i_m/D/src/fnmsub.d_b5-01.S", + "rv64i_m/D/src/fnmsub.d_b6-01.S", + "rv64i_m/D/src/fnmsub.d_b7-01.S", + "rv64i_m/D/src/fnmsub.d_b8-01.S", + "rv64i_m/D/src/fsgnj.d_b1-01.S", + "rv64i_m/D/src/fsgnjn.d_b1-01.S", + "rv64i_m/D/src/fsgnjx.d_b1-01.S", + "rv64i_m/D/src/fsqrt.d_b1-01.S", + "rv64i_m/D/src/fsqrt.d_b20-01.S", + "rv64i_m/D/src/fsqrt.d_b2-01.S", + "rv64i_m/D/src/fsqrt.d_b3-01.S", + "rv64i_m/D/src/fsqrt.d_b4-01.S", + "rv64i_m/D/src/fsqrt.d_b5-01.S", + "rv64i_m/D/src/fsqrt.d_b7-01.S", + "rv64i_m/D/src/fsqrt.d_b8-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S", + "rv64i_m/D/src/fssub.d_b10-01.S", + "rv64i_m/D/src/fssub.d_b1-01.S", + "rv64i_m/D/src/fssub.d_b11-01.S", + "rv64i_m/D/src/fssub.d_b12-01.S", + "rv64i_m/D/src/fssub.d_b13-01.S", + "rv64i_m/D/src/fssub.d_b2-01.S", + "rv64i_m/D/src/fssub.d_b3-01.S", + "rv64i_m/D/src/fssub.d_b4-01.S", + "rv64i_m/D/src/fssub.d_b5-01.S", + "rv64i_m/D/src/fssub.d_b7-01.S", + "rv64i_m/D/src/fssub.d_b8-01.S" +}; string arch32priv[] = '{ `RISCVARCHTEST, - "rv32i_m/privilege/ebreak", "2070", - "rv32i_m/privilege/ecall", "2070", - "rv32i_m/privilege/misalign-beq-01", "2080", - "rv32i_m/privilege/misalign-bge-01", "2080", - "rv32i_m/privilege/misalign-bgeu-01", "2080", - "rv32i_m/privilege/misalign-blt-01", "2080", - "rv32i_m/privilege/misalign-bltu-01", "2080", - "rv32i_m/privilege/misalign-bne-01", "2080", - "rv32i_m/privilege/misalign-jal-01", "2080", - "rv32i_m/privilege/misalign-lh-01", "2080", - "rv32i_m/privilege/misalign-lhu-01", "2080", - "rv32i_m/privilege/misalign-lw-01", "2080", - "rv32i_m/privilege/misalign-sh-01", "2080", - "rv32i_m/privilege/misalign-sw-01", "2080", - "rv32i_m/privilege/misalign1-jalr-01", "2080", - "rv32i_m/privilege/misalign2-jalr-01", "2080" + "rv32i_m/privilege/src/ebreak.S", + "rv32i_m/privilege/src/ecall.S", + "rv32i_m/privilege/src/misalign1-jalr-01.S", + "rv32i_m/privilege/src/misalign2-jalr-01.S", + "rv32i_m/privilege/src/misalign-beq-01.S", + "rv32i_m/privilege/src/misalign-bge-01.S", + "rv32i_m/privilege/src/misalign-bgeu-01.S", + "rv32i_m/privilege/src/misalign-blt-01.S", + "rv32i_m/privilege/src/misalign-bltu-01.S", + "rv32i_m/privilege/src/misalign-bne-01.S", + "rv32i_m/privilege/src/misalign-jal-01.S", + "rv32i_m/privilege/src/misalign-lh-01.S", + "rv32i_m/privilege/src/misalign-lhu-01.S", + "rv32i_m/privilege/src/misalign-lw-01.S", + "rv32i_m/privilege/src/misalign-sh-01.S", + "rv32i_m/privilege/src/misalign-sw-01.S" }; string arch32m[] = '{ `RISCVARCHTEST, - "rv32i_m/M/div-01", "5010", - "rv32i_m/M/divu-01", "5010", - "rv32i_m/M/mul-01", "5010", - "rv32i_m/M/mulh-01", "5010", - "rv32i_m/M/mulhsu-01", "5010", - "rv32i_m/M/mulhu-01", "5010", - "rv32i_m/M/rem-01", "5010", - "rv32i_m/M/remu-01", "5010" + "rv32i_m/M/src/div-01.S", + "rv32i_m/M/src/divu-01.S", + "rv32i_m/M/src/mul-01.S", + "rv32i_m/M/src/mulh-01.S", + "rv32i_m/M/src/mulhsu-01.S", + "rv32i_m/M/src/mulhu-01.S", + "rv32i_m/M/src/rem-01.S", + "rv32i_m/M/src/remu-01.S" }; string arch32f[] = '{ `RISCVARCHTEST, - "rv32i_m/F/fadd_b1-01", "7220", - "rv32i_m/F/fadd_b10-01", "2270", - "rv32i_m/F/fadd_b11-01", "3fb40", - "rv32i_m/F/fadd_b12-01", "21b0", - "rv32i_m/F/fadd_b13-01", "3660", - "rv32i_m/F/fadd_b2-01", "38b0", - "rv32i_m/F/fadd_b3-01", "b320", - "rv32i_m/F/fadd_b4-01", "3480", - "rv32i_m/F/fadd_b5-01", "3700", - "rv32i_m/F/fadd_b7-01", "3520", - "rv32i_m/F/fadd_b8-01", "104a0", - "rv32i_m/F/fclass_b1-01", "2090", - "rv32i_m/F/fcvt.s.w_b25-01", "20a0", - "rv32i_m/F/fcvt.s.w_b26-01", "3290", - "rv32i_m/F/fcvt.s.wu_b25-01", "20a0", - "rv32i_m/F/fcvt.s.wu_b26-01", "3290", - "rv32i_m/F/fcvt.w.s_b1-01", "2090", - "rv32i_m/F/fcvt.w.s_b22-01", "20b0", - "rv32i_m/F/fcvt.w.s_b23-01", "20c0", - "rv32i_m/F/fcvt.w.s_b24-01", "21b0", - "rv32i_m/F/fcvt.w.s_b27-01", "2090", - "rv32i_m/F/fcvt.w.s_b28-01", "2090", - "rv32i_m/F/fcvt.w.s_b29-01", "2150", - "rv32i_m/F/fcvt.wu.s_b1-01", "2090", - "rv32i_m/F/fcvt.wu.s_b22-01", "20b0", - "rv32i_m/F/fcvt.wu.s_b23-01", "20c0", - "rv32i_m/F/fcvt.wu.s_b24-01", "21b0", - "rv32i_m/F/fcvt.wu.s_b27-01", "2090", - "rv32i_m/F/fcvt.wu.s_b28-01", "2090", - "rv32i_m/F/fcvt.wu.s_b29-01", "2150", - // "rv32i_m/F/fdiv_b1-01", "7220", // NaN i'm going to skip div, probably the same problems as the double version - // "rv32i_m/F/fdiv_b2-01", "2350", - // "rv32i_m/F/fdiv_b20-01", "38c0", - // "rv32i_m/F/fdiv_b21-01", "7540", - // "rv32i_m/F/fdiv_b3-01", "b320", - // "rv32i_m/F/fdiv_b4-01", "3480", - // "rv32i_m/F/fdiv_b5-01", "3700", - // "rv32i_m/F/fdiv_b6-01", "3480", - // "rv32i_m/F/fdiv_b7-01", "3520", - // "rv32i_m/F/fdiv_b8-01", "104a0", - // "rv32i_m/F/fdiv_b9-01", "d960", - "rv32i_m/F/feq_b1-01", "6220", - "rv32i_m/F/feq_b19-01", "a190", - "rv32i_m/F/fle_b1-01", "6220", - "rv32i_m/F/fle_b19-01", "a190", - "rv32i_m/F/flt_b1-01", "6220", - "rv32i_m/F/flt_b19-01", "8ee0", - "rv32i_m/F/flw-align-01", "2010", - "rv32i_m/F/fmadd_b1-01", "96860", - "rv32i_m/F/fmadd_b14-01", "23d0", -// --passes but is timeconsuming "rv32i_m/F/fmadd_b15-01", "19bb30", - "rv32i_m/F/fmadd_b16-01", "39d0", - "rv32i_m/F/fmadd_b17-01", "39d0", - "rv32i_m/F/fmadd_b18-01", "4d10", - "rv32i_m/F/fmadd_b2-01", "4d60", - "rv32i_m/F/fmadd_b3-01", "d4f0", - "rv32i_m/F/fmadd_b4-01", "3700", - "rv32i_m/F/fmadd_b5-01", "3ac0", - "rv32i_m/F/fmadd_b6-01", "3700", - "rv32i_m/F/fmadd_b7-01", "37f0", - "rv32i_m/F/fmadd_b8-01", "13f30", - "rv32i_m/F/fmax_b1-01", "7220", - "rv32i_m/F/fmax_b19-01", "9e00", - "rv32i_m/F/fmin_b1-01", "7220", - "rv32i_m/F/fmin_b19-01", "9f20", - "rv32i_m/F/fmsub_b1-01", "96860", - "rv32i_m/F/fmsub_b14-01", "23d0", - "rv32i_m/F/fmsub_b15-01", "19bb30", - "rv32i_m/F/fmsub_b16-01", "39d0", - "rv32i_m/F/fmsub_b17-01", "39d0", - "rv32i_m/F/fmsub_b18-01", "4d20", - "rv32i_m/F/fmsub_b2-01", "4d60", - "rv32i_m/F/fmsub_b3-01", "d4f0", - "rv32i_m/F/fmsub_b4-01", "3700", - "rv32i_m/F/fmsub_b5-01", "3ac0", - "rv32i_m/F/fmsub_b6-01", "3700", - "rv32i_m/F/fmsub_b7-01", "37f0", - "rv32i_m/F/fmsub_b8-01", "13f30", - "rv32i_m/F/fmul_b1-01", "7220", - "rv32i_m/F/fmul_b2-01", "38c0", - "rv32i_m/F/fmul_b3-01", "b320", - "rv32i_m/F/fmul_b4-01", "3480", - "rv32i_m/F/fmul_b5-01", "3700", - "rv32i_m/F/fmul_b6-01", "3480", - "rv32i_m/F/fmul_b7-01", "3520", - "rv32i_m/F/fmul_b8-01", "104a0", - "rv32i_m/F/fmul_b9-01", "d960", - "rv32i_m/F/fmv.w.x_b25-01", "2090", - "rv32i_m/F/fmv.w.x_b26-01", "2090", - "rv32i_m/F/fmv.x.w_b1-01", "2090", - "rv32i_m/F/fmv.x.w_b22-01", "2090", - "rv32i_m/F/fmv.x.w_b23-01", "2090", - "rv32i_m/F/fmv.x.w_b24-01", "2090", - "rv32i_m/F/fmv.x.w_b27-01", "2090", - "rv32i_m/F/fmv.x.w_b28-01", "2090", - "rv32i_m/F/fmv.x.w_b29-01", "2090", - "rv32i_m/F/fnmadd_b1-01", "96870", - "rv32i_m/F/fnmadd_b14-01", "23d0", -// timeconsuming "rv32i_m/F/fnmadd_b15-01", "19bb40", - "rv32i_m/F/fnmadd_b16-01", "39d0", - "rv32i_m/F/fnmadd_b17-01", "39d0", - "rv32i_m/F/fnmadd_b18-01", "4d10", - "rv32i_m/F/fnmadd_b2-01", "4d60", - "rv32i_m/F/fnmadd_b3-01", "d4f0", - "rv32i_m/F/fnmadd_b4-01", "3700", - "rv32i_m/F/fnmadd_b5-01", "3ac0", - "rv32i_m/F/fnmadd_b6-01", "3700", - "rv32i_m/F/fnmadd_b7-01", "37f0", - "rv32i_m/F/fnmadd_b8-01", "13f30", - "rv32i_m/F/fnmsub_b1-01", "96870", - "rv32i_m/F/fnmsub_b14-01", "23d0", -// timeconsuming "rv32i_m/F/fnmsub_b15-01", "19bb30", - "rv32i_m/F/fnmsub_b16-01", "39d0", - "rv32i_m/F/fnmsub_b17-01", "39d0", - "rv32i_m/F/fnmsub_b18-01", "4d10", - "rv32i_m/F/fnmsub_b2-01", "4d60", - "rv32i_m/F/fnmsub_b3-01", "d4f0", - "rv32i_m/F/fnmsub_b4-01", "3700", - "rv32i_m/F/fnmsub_b5-01", "3ac0", - "rv32i_m/F/fnmsub_b6-01", "3700", - "rv32i_m/F/fnmsub_b7-01", "37f0", - "rv32i_m/F/fnmsub_b8-01", "13f30", - "rv32i_m/F/fsgnj_b1-01", "7220", - "rv32i_m/F/fsgnjn_b1-01", "7220", - "rv32i_m/F/fsgnjx_b1-01", "7220", - // "rv32i_m/F/fsqrt_b1-01", "2090", // flag i am skiping sqrt - // "rv32i_m/F/fsqrt_b2-01", "2090", - // "rv32i_m/F/fsqrt_b20-01", "2090", - // "rv32i_m/F/fsqrt_b3-01", "2090", - // "rv32i_m/F/fsqrt_b4-01", "2090", - // "rv32i_m/F/fsqrt_b5-01", "2090", - // "rv32i_m/F/fsqrt_b7-01", "2090", - // "rv32i_m/F/fsqrt_b8-01", "2090", - // "rv32i_m/F/fsqrt_b9-01", "3310", - "rv32i_m/F/fsub_b1-01", "7220", - "rv32i_m/F/fsub_b10-01", "2250", - "rv32i_m/F/fsub_b11-01", "3fb40", - "rv32i_m/F/fsub_b12-01", "21b0", - "rv32i_m/F/fsub_b13-01", "3660", - "rv32i_m/F/fsub_b2-01", "38b0", - "rv32i_m/F/fsub_b3-01", "b320", - "rv32i_m/F/fsub_b4-01", "3480", - "rv32i_m/F/fsub_b5-01", "3700", - "rv32i_m/F/fsub_b7-01", "3520", - "rv32i_m/F/fsub_b8-01", "104a0", - "rv32i_m/F/fsw-align-01", "2010" + "rv32i_m/F/src/fadd_b10-01.S", + "rv32i_m/F/src/fadd_b1-01.S", + "rv32i_m/F/src/fadd_b11-01.S", + "rv32i_m/F/src/fadd_b12-01.S", + "rv32i_m/F/src/fadd_b13-01.S", + "rv32i_m/F/src/fadd_b2-01.S", + "rv32i_m/F/src/fadd_b3-01.S", + "rv32i_m/F/src/fadd_b4-01.S", + "rv32i_m/F/src/fadd_b5-01.S", + "rv32i_m/F/src/fadd_b7-01.S", + "rv32i_m/F/src/fadd_b8-01.S", + "rv32i_m/F/src/fclass_b1-01.S", + "rv32i_m/F/src/fcvt.s.w_b25-01.S", + "rv32i_m/F/src/fcvt.s.w_b26-01.S", + "rv32i_m/F/src/fcvt.s.wu_b25-01.S", + "rv32i_m/F/src/fcvt.s.wu_b26-01.S", + "rv32i_m/F/src/fcvt.w.s_b1-01.S", + "rv32i_m/F/src/fcvt.w.s_b22-01.S", + "rv32i_m/F/src/fcvt.w.s_b23-01.S", + "rv32i_m/F/src/fcvt.w.s_b24-01.S", + "rv32i_m/F/src/fcvt.w.s_b27-01.S", + "rv32i_m/F/src/fcvt.w.s_b28-01.S", + "rv32i_m/F/src/fcvt.w.s_b29-01.S", + "rv32i_m/F/src/fcvt.wu.s_b1-01.S", + "rv32i_m/F/src/fcvt.wu.s_b22-01.S", + "rv32i_m/F/src/fcvt.wu.s_b23-01.S", + "rv32i_m/F/src/fcvt.wu.s_b24-01.S", + "rv32i_m/F/src/fcvt.wu.s_b27-01.S", + "rv32i_m/F/src/fcvt.wu.s_b28-01.S", + "rv32i_m/F/src/fcvt.wu.s_b29-01.S", + "rv32i_m/F/src/fdiv_b1-01.S", + "rv32i_m/F/src/fdiv_b20-01.S", + "rv32i_m/F/src/fdiv_b2-01.S", + "rv32i_m/F/src/fdiv_b21-01.S", + "rv32i_m/F/src/fdiv_b3-01.S", + "rv32i_m/F/src/fdiv_b4-01.S", + "rv32i_m/F/src/fdiv_b5-01.S", + "rv32i_m/F/src/fdiv_b6-01.S", + "rv32i_m/F/src/fdiv_b7-01.S", + "rv32i_m/F/src/fdiv_b8-01.S", + "rv32i_m/F/src/fdiv_b9-01.S", + "rv32i_m/F/src/feq_b1-01.S", + "rv32i_m/F/src/feq_b19-01.S", + "rv32i_m/F/src/fle_b1-01.S", + "rv32i_m/F/src/fle_b19-01.S", + "rv32i_m/F/src/flt_b1-01.S", + "rv32i_m/F/src/flt_b19-01.S", + // "rv32i_m/F/src/flw-align-01.S", + "rv32i_m/F/src/fmadd_b1-01.S", + "rv32i_m/F/src/fmadd_b14-01.S", + // "rv32i_m/F/src/fmadd_b15-01.S", + "rv32i_m/F/src/fmadd_b16-01.S", + "rv32i_m/F/src/fmadd_b17-01.S", + "rv32i_m/F/src/fmadd_b18-01.S", + "rv32i_m/F/src/fmadd_b2-01.S", + "rv32i_m/F/src/fmadd_b3-01.S", + "rv32i_m/F/src/fmadd_b4-01.S", + "rv32i_m/F/src/fmadd_b5-01.S", + "rv32i_m/F/src/fmadd_b6-01.S", + "rv32i_m/F/src/fmadd_b7-01.S", + "rv32i_m/F/src/fmadd_b8-01.S", + "rv32i_m/F/src/fmax_b1-01.S", + "rv32i_m/F/src/fmax_b19-01.S", + "rv32i_m/F/src/fmin_b1-01.S", + "rv32i_m/F/src/fmin_b19-01.S", + "rv32i_m/F/src/fmsub_b1-01.S", + "rv32i_m/F/src/fmsub_b14-01.S", + "rv32i_m/F/src/fmsub_b15-01.S", + "rv32i_m/F/src/fmsub_b16-01.S", + "rv32i_m/F/src/fmsub_b17-01.S", + "rv32i_m/F/src/fmsub_b18-01.S", + "rv32i_m/F/src/fmsub_b2-01.S", + "rv32i_m/F/src/fmsub_b3-01.S", + "rv32i_m/F/src/fmsub_b4-01.S", + "rv32i_m/F/src/fmsub_b5-01.S", + "rv32i_m/F/src/fmsub_b6-01.S", + "rv32i_m/F/src/fmsub_b7-01.S", + "rv32i_m/F/src/fmsub_b8-01.S", + "rv32i_m/F/src/fmul_b1-01.S", + "rv32i_m/F/src/fmul_b2-01.S", + "rv32i_m/F/src/fmul_b3-01.S", + "rv32i_m/F/src/fmul_b4-01.S", + "rv32i_m/F/src/fmul_b5-01.S", + "rv32i_m/F/src/fmul_b6-01.S", + "rv32i_m/F/src/fmul_b7-01.S", + "rv32i_m/F/src/fmul_b8-01.S", + "rv32i_m/F/src/fmul_b9-01.S", + "rv32i_m/F/src/fmv.w.x_b25-01.S", + "rv32i_m/F/src/fmv.w.x_b26-01.S", + "rv32i_m/F/src/fmv.x.w_b1-01.S", + "rv32i_m/F/src/fmv.x.w_b22-01.S", + "rv32i_m/F/src/fmv.x.w_b23-01.S", + "rv32i_m/F/src/fmv.x.w_b24-01.S", + "rv32i_m/F/src/fmv.x.w_b27-01.S", + "rv32i_m/F/src/fmv.x.w_b28-01.S", + "rv32i_m/F/src/fmv.x.w_b29-01.S", + "rv32i_m/F/src/fnmadd_b1-01.S", + "rv32i_m/F/src/fnmadd_b14-01.S", + // "rv32i_m/F/src/fnmadd_b15-01.S", + "rv32i_m/F/src/fnmadd_b16-01.S", + "rv32i_m/F/src/fnmadd_b17-01.S", + "rv32i_m/F/src/fnmadd_b18-01.S", + "rv32i_m/F/src/fnmadd_b2-01.S", + "rv32i_m/F/src/fnmadd_b3-01.S", + "rv32i_m/F/src/fnmadd_b4-01.S", + "rv32i_m/F/src/fnmadd_b5-01.S", + "rv32i_m/F/src/fnmadd_b6-01.S", + "rv32i_m/F/src/fnmadd_b7-01.S", + "rv32i_m/F/src/fnmadd_b8-01.S", + "rv32i_m/F/src/fnmsub_b1-01.S", + "rv32i_m/F/src/fnmsub_b14-01.S", + // "rv32i_m/F/src/fnmsub_b15-01.S", + "rv32i_m/F/src/fnmsub_b16-01.S", + "rv32i_m/F/src/fnmsub_b17-01.S", + "rv32i_m/F/src/fnmsub_b18-01.S", + "rv32i_m/F/src/fnmsub_b2-01.S", + "rv32i_m/F/src/fnmsub_b3-01.S", + "rv32i_m/F/src/fnmsub_b4-01.S", + "rv32i_m/F/src/fnmsub_b5-01.S", + "rv32i_m/F/src/fnmsub_b6-01.S", + "rv32i_m/F/src/fnmsub_b7-01.S", + "rv32i_m/F/src/fnmsub_b8-01.S", + "rv32i_m/F/src/fsgnj_b1-01.S", + "rv32i_m/F/src/fsgnjn_b1-01.S", + "rv32i_m/F/src/fsgnjx_b1-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S", + "rv32i_m/F/src/fsub_b10-01.S", + "rv32i_m/F/src/fsub_b1-01.S", + "rv32i_m/F/src/fsub_b11-01.S", + "rv32i_m/F/src/fsub_b12-01.S", + "rv32i_m/F/src/fsub_b13-01.S", + "rv32i_m/F/src/fsub_b2-01.S", + "rv32i_m/F/src/fsub_b3-01.S", + "rv32i_m/F/src/fsub_b4-01.S", + "rv32i_m/F/src/fsub_b5-01.S", + "rv32i_m/F/src/fsub_b7-01.S", + "rv32i_m/F/src/fsub_b8-01.S" + // "rv32i_m/F/src/fsw-align-01.S" + }; + + string arch32d[] = '{ + `RISCVARCHTEST, + "rv32i_m/D/src/fadd.d_b10-01.S", + "rv32i_m/D/src/fadd.d_b1-01.S", + "rv32i_m/D/src/fadd.d_b11-01.S", + "rv32i_m/D/src/fadd.d_b12-01.S", + "rv32i_m/D/src/fadd.d_b13-01.S", + "rv32i_m/D/src/fadd.d_b2-01.S", + "rv32i_m/D/src/fadd.d_b3-01.S", + "rv32i_m/D/src/fadd.d_b4-01.S", + "rv32i_m/D/src/fadd.d_b5-01.S", + "rv32i_m/D/src/fadd.d_b7-01.S", + "rv32i_m/D/src/fadd.d_b8-01.S", + "rv32i_m/D/src/fclass.d_b1-01.S", + "rv32i_m/D/src/fcvt.d.s_b1-01.S", + "rv32i_m/D/src/fcvt.d.s_b22-01.S", + "rv32i_m/D/src/fcvt.d.s_b23-01.S", + "rv32i_m/D/src/fcvt.d.s_b24-01.S", + "rv32i_m/D/src/fcvt.d.s_b27-01.S", + "rv32i_m/D/src/fcvt.d.s_b28-01.S", + "rv32i_m/D/src/fcvt.d.s_b29-01.S", + "rv32i_m/D/src/fcvt.d.w_b25-01.S", + "rv32i_m/D/src/fcvt.d.w_b26-01.S", + "rv32i_m/D/src/fcvt.d.wu_b25-01.S", + "rv32i_m/D/src/fcvt.d.wu_b26-01.S", + "rv32i_m/D/src/fcvt.s.d_b1-01.S", + "rv32i_m/D/src/fcvt.s.d_b22-01.S", + "rv32i_m/D/src/fcvt.s.d_b23-01.S", + "rv32i_m/D/src/fcvt.s.d_b24-01.S", + "rv32i_m/D/src/fcvt.s.d_b27-01.S", + "rv32i_m/D/src/fcvt.s.d_b28-01.S", + "rv32i_m/D/src/fcvt.s.d_b29-01.S", + "rv32i_m/D/src/fcvt.w.d_b1-01.S", + "rv32i_m/D/src/fcvt.w.d_b22-01.S", + "rv32i_m/D/src/fcvt.w.d_b23-01.S", + "rv32i_m/D/src/fcvt.w.d_b24-01.S", + "rv32i_m/D/src/fcvt.w.d_b27-01.S", + "rv32i_m/D/src/fcvt.w.d_b28-01.S", + "rv32i_m/D/src/fcvt.w.d_b29-01.S", + "rv32i_m/D/src/fcvt.wu.d_b1-01.S", + "rv32i_m/D/src/fcvt.wu.d_b22-01.S", + "rv32i_m/D/src/fcvt.wu.d_b23-01.S", + "rv32i_m/D/src/fcvt.wu.d_b24-01.S", + "rv32i_m/D/src/fcvt.wu.d_b27-01.S", + "rv32i_m/D/src/fcvt.wu.d_b28-01.S", + "rv32i_m/D/src/fcvt.wu.d_b29-01.S", + "rv32i_m/D/src/fdiv.d_b1-01.S", + "rv32i_m/D/src/fdiv.d_b20-01.S", + "rv32i_m/D/src/fdiv.d_b2-01.S", + "rv32i_m/D/src/fdiv.d_b21-01.S", + "rv32i_m/D/src/fdiv.d_b3-01.S", + "rv32i_m/D/src/fdiv.d_b4-01.S", + "rv32i_m/D/src/fdiv.d_b5-01.S", + "rv32i_m/D/src/fdiv.d_b6-01.S", + "rv32i_m/D/src/fdiv.d_b7-01.S", + "rv32i_m/D/src/fdiv.d_b8-01.S", + "rv32i_m/D/src/fdiv.d_b9-01.S", + "rv32i_m/D/src/feq.d_b1-01.S", + "rv32i_m/D/src/feq.d_b19-01.S", + "rv32i_m/D/src/fle.d_b1-01.S", + "rv32i_m/D/src/fle.d_b19-01.S", + "rv32i_m/D/src/flt.d_b1-01.S", + "rv32i_m/D/src/flt.d_b19-01.S", + // "rv32i_m/D/src/fld-align-01.S", //missing right now from top of tree, should be returned when it comes back + // "rv32i_m/D/src/fsd-align-01.S", //https://github.com/riscv-non-isa/riscv-arch-test/issues/266 + "rv32i_m/D/src/fmadd.d_b14-01.S", + "rv32i_m/D/src/fmadd.d_b16-01.S", + "rv32i_m/D/src/fmadd.d_b17-01.S", + "rv32i_m/D/src/fmadd.d_b18-01.S", + "rv32i_m/D/src/fmadd.d_b2-01.S", + "rv32i_m/D/src/fmadd.d_b3-01.S", + "rv32i_m/D/src/fmadd.d_b4-01.S", + "rv32i_m/D/src/fmadd.d_b5-01.S", + "rv32i_m/D/src/fmadd.d_b6-01.S", + "rv32i_m/D/src/fmadd.d_b7-01.S", + "rv32i_m/D/src/fmadd.d_b8-01.S", + "rv32i_m/D/src/fmax.d_b1-01.S", + "rv32i_m/D/src/fmax.d_b19-01.S", + "rv32i_m/D/src/fmin.d_b1-01.S", + "rv32i_m/D/src/fmin.d_b19-01.S", + "rv32i_m/D/src/fmsub.d_b14-01.S", + "rv32i_m/D/src/fmsub.d_b16-01.S", + "rv32i_m/D/src/fmsub.d_b17-01.S", + "rv32i_m/D/src/fmsub.d_b18-01.S", + "rv32i_m/D/src/fmsub.d_b2-01.S", + "rv32i_m/D/src/fmsub.d_b3-01.S", + "rv32i_m/D/src/fmsub.d_b4-01.S", + "rv32i_m/D/src/fmsub.d_b5-01.S", + "rv32i_m/D/src/fmsub.d_b6-01.S", + "rv32i_m/D/src/fmsub.d_b7-01.S", + "rv32i_m/D/src/fmsub.d_b8-01.S", + "rv32i_m/D/src/fmul.d_b1-01.S", + "rv32i_m/D/src/fmul.d_b2-01.S", + "rv32i_m/D/src/fmul.d_b3-01.S", + "rv32i_m/D/src/fmul.d_b4-01.S", + "rv32i_m/D/src/fmul.d_b5-01.S", + "rv32i_m/D/src/fmul.d_b6-01.S", + "rv32i_m/D/src/fmul.d_b7-01.S", + "rv32i_m/D/src/fmul.d_b8-01.S", + "rv32i_m/D/src/fmul.d_b9-01.S", + "rv32i_m/D/src/fnmadd.d_b14-01.S", + "rv32i_m/D/src/fnmadd.d_b16-01.S", + "rv32i_m/D/src/fnmadd.d_b17-01.S", + "rv32i_m/D/src/fnmadd.d_b18-01.S", + "rv32i_m/D/src/fnmadd.d_b2-01.S", + "rv32i_m/D/src/fnmadd.d_b3-01.S", + "rv32i_m/D/src/fnmadd.d_b4-01.S", + "rv32i_m/D/src/fnmadd.d_b5-01.S", + "rv32i_m/D/src/fnmadd.d_b6-01.S", + "rv32i_m/D/src/fnmadd.d_b7-01.S", + "rv32i_m/D/src/fnmadd.d_b8-01.S", + "rv32i_m/D/src/fnmsub.d_b14-01.S", + "rv32i_m/D/src/fnmsub.d_b16-01.S", + "rv32i_m/D/src/fnmsub.d_b17-01.S", + "rv32i_m/D/src/fnmsub.d_b18-01.S", + "rv32i_m/D/src/fnmsub.d_b2-01.S", + "rv32i_m/D/src/fnmsub.d_b3-01.S", + "rv32i_m/D/src/fnmsub.d_b4-01.S", + "rv32i_m/D/src/fnmsub.d_b5-01.S", + "rv32i_m/D/src/fnmsub.d_b6-01.S", + "rv32i_m/D/src/fnmsub.d_b7-01.S", + "rv32i_m/D/src/fnmsub.d_b8-01.S", + "rv32i_m/D/src/fsgnj.d_b1-01.S", + "rv32i_m/D/src/fsgnjn.d_b1-01.S", + "rv32i_m/D/src/fsgnjx.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S", + "rv32i_m/D/src/fssub.d_b10-01.S", + "rv32i_m/D/src/fssub.d_b1-01.S", + "rv32i_m/D/src/fssub.d_b11-01.S", + "rv32i_m/D/src/fssub.d_b12-01.S", + "rv32i_m/D/src/fssub.d_b13-01.S", + "rv32i_m/D/src/fssub.d_b2-01.S", + "rv32i_m/D/src/fssub.d_b3-01.S", + "rv32i_m/D/src/fssub.d_b4-01.S", + "rv32i_m/D/src/fssub.d_b5-01.S", + "rv32i_m/D/src/fssub.d_b7-01.S", + "rv32i_m/D/src/fssub.d_b8-01.S" }; string arch32c[] = '{ `RISCVARCHTEST, - "rv32i_m/C/cadd-01", "4010", - "rv32i_m/C/caddi-01", "3010", - "rv32i_m/C/caddi16sp-01", "2010", - "rv32i_m/C/caddi4spn-01", "2010", - "rv32i_m/C/cand-01", "4010", - "rv32i_m/C/candi-01", "3010", - "rv32i_m/C/cbeqz-01", "3010", - "rv32i_m/C/cbnez-01", "3010", - "rv32i_m/C/cj-01", "3010", - "rv32i_m/C/cjal-01", "3010", - "rv32i_m/C/cjalr-01", "2010", - "rv32i_m/C/cjr-01", "2010", - "rv32i_m/C/cli-01", "2010", - "rv32i_m/C/clui-01", "2010", - "rv32i_m/C/clw-01", "2010", - "rv32i_m/C/clwsp-01", "2010", - "rv32i_m/C/cmv-01", "2010", - "rv32i_m/C/cnop-01", "2010", - "rv32i_m/C/cor-01", "4010", - "rv32i_m/C/cslli-01", "2010", - "rv32i_m/C/csrai-01", "2010", - "rv32i_m/C/csrli-01", "2010", - "rv32i_m/C/csub-01", "4010", - "rv32i_m/C/csw-01", "2010", - "rv32i_m/C/cswsp-01", "2010", - "rv32i_m/C/cxor-01", "4010" + "rv32i_m/C/src/cadd-01.S", + "rv32i_m/C/src/caddi-01.S", + "rv32i_m/C/src/caddi16sp-01.S", + "rv32i_m/C/src/caddi4spn-01.S", + "rv32i_m/C/src/cand-01.S", + "rv32i_m/C/src/candi-01.S", + "rv32i_m/C/src/cbeqz-01.S", + "rv32i_m/C/src/cbnez-01.S", + "rv32i_m/C/src/cj-01.S", + "rv32i_m/C/src/cjal-01.S", + "rv32i_m/C/src/cjalr-01.S", + "rv32i_m/C/src/cjr-01.S", + "rv32i_m/C/src/cli-01.S", + "rv32i_m/C/src/clui-01.S", + "rv32i_m/C/src/clw-01.S", + "rv32i_m/C/src/clwsp-01.S", + "rv32i_m/C/src/cmv-01.S", + "rv32i_m/C/src/cnop-01.S", + "rv32i_m/C/src/cor-01.S", + "rv32i_m/C/src/cslli-01.S", + "rv32i_m/C/src/csrai-01.S", + "rv32i_m/C/src/csrli-01.S", + "rv32i_m/C/src/csub-01.S", + "rv32i_m/C/src/csw-01.S", + "rv32i_m/C/src/cswsp-01.S", + "rv32i_m/C/src/cxor-01.S" }; string arch32cpriv[] = '{ // `RISCVARCHTEST, - "rv32i_m/C/cebreak-01", "2050" + "rv32i_m/C/src/cebreak-01.S" }; string arch32i[] = '{ `RISCVARCHTEST, - "rv32i_m/I/add-01", "5010", - "rv32i_m/I/addi-01", "4010", - "rv32i_m/I/and-01", "5010", - "rv32i_m/I/andi-01", "4010", - "rv32i_m/I/auipc-01", "2010", - "rv32i_m/I/beq-01", "39010", - "rv32i_m/I/bge-01", "3a010", - "rv32i_m/I/bgeu-01", "4a010", - "rv32i_m/I/blt-01", "38010", - "rv32i_m/I/bltu-01", "4b010", - "rv32i_m/I/bne-01", "39010", - "rv32i_m/I/fence-01", "2010", - "rv32i_m/I/jal-01", "1ad010", - "rv32i_m/I/jalr-01", "2010", - "rv32i_m/I/lb-align-01", "2010", - "rv32i_m/I/lbu-align-01", "2010", - "rv32i_m/I/lh-align-01", "2010", - "rv32i_m/I/lhu-align-01", "2010", - "rv32i_m/I/lui-01", "2010", - "rv32i_m/I/lw-align-01", "2010", - "rv32i_m/I/or-01", "5010", - "rv32i_m/I/ori-01", "4010", - "rv32i_m/I/sb-align-01", "2010", - "rv32i_m/I/sh-align-01", "2010", - "rv32i_m/I/sll-01", "2010", - "rv32i_m/I/slli-01", "2010", - "rv32i_m/I/slt-01", "5010", - "rv32i_m/I/slti-01", "4010", - "rv32i_m/I/sltiu-01", "4010", - "rv32i_m/I/sltu-01", "5010", - "rv32i_m/I/sra-01", "2010", - "rv32i_m/I/srai-01", "2010", - "rv32i_m/I/srl-01", "2010", - "rv32i_m/I/srli-01", "2010", - "rv32i_m/I/sub-01", "5010", - "rv32i_m/I/sw-align-01", "2010", - "rv32i_m/I/xor-01", "5010", - "rv32i_m/I/xori-01", "4010" + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S" }; string wally64i[] = '{ `WALLYTEST, - "rv64i_m/I/WALLY-ADD", "002010", - "rv64i_m/I/WALLY-SLT", "002010", - "rv64i_m/I/WALLY-SLTU", "002010", - "rv64i_m/I/WALLY-SUB", "002010", - "rv64i_m/I/WALLY-XOR", "002010" + "rv64i_m/I/src/WALLY-ADD.S", + "rv64i_m/I/src/WALLY-SLT.S", + "rv64i_m/I/src/WALLY-SLTU.S", + "rv64i_m/I/src/WALLY-SUB.S", + "rv64i_m/I/src/WALLY-XOR.S" }; + string wally64priv[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-status-tw-01", "0050a0", - "rv64i_m/privilege/WALLY-csr-permission-s-01", "0060a0", - "rv64i_m/privilege/WALLY-csr-permission-u-01", "0060a0", - "rv64i_m/privilege/WALLY-minfo-01", "0050a0", - "rv64i_m/privilege/WALLY-misa-01", "0050a0", - "rv64i_m/privilege/WALLY-mmu-sv39", "0050a0", - "rv64i_m/privilege/WALLY-mmu-sv48", "0050a0", - "rv64i_m/privilege/WALLY-pma", "0050a0", - "rv64i_m/privilege/WALLY-pmp", "0050a0", - "rv64i_m/privilege/WALLY-trap-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-s-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-u-01", "0050a0", - "rv64i_m/privilege/WALLY-mie-01", "0050a0", - "rv64i_m/privilege/WALLY-sie-01", "0050a0", - "rv64i_m/privilege/WALLY-mtvec-01", "0050a0", - "rv64i_m/privilege/WALLY-stvec-01", "0050a0", - "rv64i_m/privilege/WALLY-status-mie-01", "0050a0", - "rv64i_m/privilege/WALLY-status-sie-01", "0050a0", - "rv64i_m/privilege/WALLY-trap-sret-01", "0050a0", - "rv64i_m/privilege/WALLY-status-tw-01", "0050a0", - "rv64i_m/privilege/WALLY-wfi-01", "0050a0" + "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", + "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", + "rv64i_m/privilege/src/WALLY-mie-01.S", + "rv64i_m/privilege/src/WALLY-minfo-01.S", + "rv64i_m/privilege/src/WALLY-misa-01.S", + "rv64i_m/privilege/src/WALLY-mmu-sv39.S", + "rv64i_m/privilege/src/WALLY-mmu-sv48.S", + "rv64i_m/privilege/src/WALLY-mtvec-01.S", + "rv64i_m/privilege/src/WALLY-pma.S", + "rv64i_m/privilege/src/WALLY-pmp.S", + "rv64i_m/privilege/src/WALLY-sie-01.S", + "rv64i_m/privilege/src/WALLY-status-mie-01.S", + "rv64i_m/privilege/src/WALLY-status-sie-01.S", + "rv64i_m/privilege/src/WALLY-status-tw-01.S", + "rv64i_m/privilege/src/WALLY-stvec-01.S", + "rv64i_m/privilege/src/WALLY-trap-01.S", + "rv64i_m/privilege/src/WALLY-trap-s-01.S", + "rv64i_m/privilege/src/WALLY-trap-sret-01.S", + "rv64i_m/privilege/src/WALLY-trap-u-01.S", + "rv64i_m/privilege/src/WALLY-wfi-01.S" }; string wally64periph[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-periph", "3310" + "rv64i_m/privilege/src/WALLY-periph.S" }; string wally32e[] = '{ `WALLYTEST, - "rv32i_m/I/E-add-01", "005010", - "rv32i_m/I/E-addi-01", "004010", - "rv32i_m/I/E-and-01", "005010", - "rv32i_m/I/E-andi-01", "004010", - "rv32i_m/I/E-auipc-01", "002010", - "rv32i_m/I/E-bge-01", "034010", - "rv32i_m/I/E-bgeu-01", "047010", - "rv32i_m/I/E-blt-01", "038010", - "rv32i_m/I/E-bltu-01", "03e010", - "rv32i_m/I/E-bne-01", "038010", - "rv32i_m/I/E-jal-01", "e02010", - "rv32i_m/I/E-jalr-01", "002010", - "rv32i_m/I/E-lb-align-01", "002010", - "rv32i_m/I/E-lbu-align-01", "002010", - "rv32i_m/I/E-lh-align-01", "002010", - "rv32i_m/I/E-lhu-align-01", "002010", - "rv32i_m/I/E-lui-01", "002010", - "rv32i_m/I/E-lw-align-01", "002010", - "rv32i_m/I/E-or-01", "005010", - "rv32i_m/I/E-ori-01", "004010", - "rv32i_m/I/E-sb-align-01", "002010", - "rv32i_m/I/E-sh-align-01", "002010", - "rv32i_m/I/E-sll-01", "002010", - "rv32i_m/I/E-slli-01", "002010", - "rv32i_m/I/E-slt-01", "005010", - "rv32i_m/I/E-slti-01", "004010", - "rv32i_m/I/E-sltiu-01", "004010", - "rv32i_m/I/E-sltu-01", "005010", - "rv32i_m/I/E-sra-01", "002010", - "rv32i_m/I/E-srai-01", "002010", - "rv32i_m/I/E-srl-01", "002010", - "rv32i_m/I/E-srli-01", "002010", - "rv32i_m/I/E-sub-01", "005010", - "rv32i_m/I/E-sw-align-01", "002010", - "rv32i_m/I/E-xor-01", "005010", - "rv32i_m/I/E-xori-01", "004010" + "rv32i_m/I/src/E-add-01.S", + "rv32i_m/I/src/E-addi-01.S", + "rv32i_m/I/src/E-and-01.S", + "rv32i_m/I/src/E-andi-01.S", + "rv32i_m/I/src/E-auipc-01.S", + "rv32i_m/I/src/E-bge-01.S", + "rv32i_m/I/src/E-bgeu-01.S", + "rv32i_m/I/src/E-blt-01.S", + "rv32i_m/I/src/E-bltu-01.S", + "rv32i_m/I/src/E-bne-01.S", + "rv32i_m/I/src/E-jal-01.S", + "rv32i_m/I/src/E-jalr-01.S", + "rv32i_m/I/src/E-lb-align-01.S", + "rv32i_m/I/src/E-lbu-align-01.S", + "rv32i_m/I/src/E-lh-align-01.S", + "rv32i_m/I/src/E-lhu-align-01.S", + "rv32i_m/I/src/E-lui-01.S", + "rv32i_m/I/src/E-lw-align-01.S", + "rv32i_m/I/src/E-or-01.S", + "rv32i_m/I/src/E-ori-01.S", + "rv32i_m/I/src/E-sb-align-01.S", + "rv32i_m/I/src/E-sh-align-01.S", + "rv32i_m/I/src/E-sll-01.S", + "rv32i_m/I/src/E-slli-01.S", + "rv32i_m/I/src/E-slt-01.S", + "rv32i_m/I/src/E-slti-01.S", + "rv32i_m/I/src/E-sltiu-01.S", + "rv32i_m/I/src/E-sltu-01.S", + "rv32i_m/I/src/E-sra-01.S", + "rv32i_m/I/src/E-srai-01.S", + "rv32i_m/I/src/E-srl-01.S", + "rv32i_m/I/src/E-srli-01.S", + "rv32i_m/I/src/E-sub-01.S", + "rv32i_m/I/src/E-sw-align-01.S", + "rv32i_m/I/src/E-xor-01.S", + "rv32i_m/I/src/E-xori-01.S" }; -string wally32i[] = '{ + string wally32i[] = '{ `WALLYTEST, - "rv32i_m/I/WALLY-ADD", "002010", - "rv32i_m/I/WALLY-SLT", "002010", - "rv32i_m/I/WALLY-SLTU", "002010", - "rv32i_m/I/WALLY-SUB", "002010", - "rv32i_m/I/WALLY-XOR", "002010" + "rv32i_m/I/src/WALLY-ADD.S", + "rv32i_m/I/src/WALLY-SLT.S", + "rv32i_m/I/src/WALLY-SLTU.S", + "rv32i_m/I/src/WALLY-SUB.S", + "rv32i_m/I/src/WALLY-XOR.S" }; + string wally32priv[] = '{ `WALLYTEST, - "rv32i_m/privilege/WALLY-csr-permission-s-01", "6080", - "rv32i_m/privilege/WALLY-csr-permission-u-01", "6080", - "rv32i_m/privilege/WALLY-minfo-01", "5080", - "rv32i_m/privilege/WALLY-misa-01", "5080", - "rv32i_m/privilege/WALLY-mmu-sv32", "5080", - "rv32i_m/privilege/WALLY-pma", "5080", - "rv32i_m/privilege/WALLY-pmp", "5080", - "rv32i_m/privilege/WALLY-trap-01", "5080", - "rv32i_m/privilege/WALLY-trap-s-01", "5080", - "rv32i_m/privilege/WALLY-trap-u-01", "5080", - "rv32i_m/privilege/WALLY-mie-01", "5080", - "rv32i_m/privilege/WALLY-sie-01", "5080", - "rv32i_m/privilege/WALLY-mtvec-01", "5080", - "rv32i_m/privilege/WALLY-stvec-01", "5080", - "rv32i_m/privilege/WALLY-status-mie-01", "5080", - "rv32i_m/privilege/WALLY-status-sie-01", "5080", - "rv32i_m/privilege/WALLY-trap-sret-01", "5080", - "rv32i_m/privilege/WALLY-status-tw-01", "5080", - "rv32i_m/privilege/WALLY-wfi-01", "5080" + "rv32i_m/privilege/src/WALLY-csr-permission-s-01.S", + "rv32i_m/privilege/src/WALLY-csr-permission-u-01.S", + "rv32i_m/privilege/src/WALLY-mie-01.S", + "rv32i_m/privilege/src/WALLY-minfo-01.S", + "rv32i_m/privilege/src/WALLY-misa-01.S", + "rv32i_m/privilege/src/WALLY-mmu-sv32.S", + "rv32i_m/privilege/src/WALLY-mtvec-01.S", + "rv32i_m/privilege/src/WALLY-pma.S", + "rv32i_m/privilege/src/WALLY-pmp.S", + "rv32i_m/privilege/src/WALLY-sie-01.S", + "rv32i_m/privilege/src/WALLY-status-mie-01.S", + "rv32i_m/privilege/src/WALLY-status-sie-01.S", + "rv32i_m/privilege/src/WALLY-status-tw-01.S", + "rv32i_m/privilege/src/WALLY-stvec-01.S", + "rv32i_m/privilege/src/WALLY-trap-01.S", + "rv32i_m/privilege/src/WALLY-trap-s-01.S", + "rv32i_m/privilege/src/WALLY-trap-sret-01.S", + "rv32i_m/privilege/src/WALLY-trap-u-01.S", + "rv32i_m/privilege/src/WALLY-wfi-01.S" }; string wally32periph[] = '{ - `WALLYTEST + `WALLYTEST, + "rv32i_m/privilege/src/WALLY-gpio-01.S", + "rv32i_m/privilege/src/WALLY-clint-01.S", + "rv32i_m/privilege/src/WALLY-uart-01.S", + "rv32i_m/privilege/src/WALLY-plic-01.S", + "rv32i_m/privilege/src/WALLY-plic-s-01.S" }; + + string wally32d[] = '{ + `WALLYTEST, + "rv32i_m/D/src/WALLY-fld.S" + }; diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 95b39b13f..2490e5647 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -17,6 +17,9 @@ if {$tech == "sky130"} { } elseif {$tech == "sky90"} { set s9lib $timing_lib/sky90/sky90_sc/V1.7.4/lib lappend search_path $s9lib +} elseif {$tech == "tsmc28"} { + set s10lib /proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a + lappend search_path $s10lib } # Synthetic libraries @@ -30,6 +33,8 @@ if {$tech == "sky130"} { lappend target_library $s8lib/sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db } elseif {$tech == "sky90"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db +} elseif {$tech == "tsmc28"} { + lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db } # Set Link Library @@ -46,7 +51,7 @@ lappend search_path ./mapped # Set up User Information set company "Oklahoma State University" -set user "James E. Stine" +set user "Prof. James E. Stine" # Alias alias ra report_area diff --git a/synthDC/Makefile b/synthDC/Makefile index b8a79fbdf..a77720248 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,37 +1,37 @@ # -# Makefile for synthesis +# Makefile for synthesis # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 +# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 7/8/2022 NAME := synth # defaults export DESIGN ?= wallypipelinedcore -export FREQ ?= 500 +export FREQ ?= 3000 export CONFIG ?= rv32e -# sky130 and sky90 presently supported -export TECH ?= sky130 +# title to add a note in the synth's directory name +TITLE = +# tsmc28, sky130, and sky90 presently supported +export TECH ?= sky90 # MAXCORES allows parallel compilation, which is faster but less CPU-efficient # Avoid when doing sweeps of many optimization points in parallel -export MAXCORES ?= 4 +export MAXCORES ?= 1 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 +export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 -CONFIGDIR ?= ${WALLY}/pipelined/config +configAsList := $(subst _, ,$(CONFIG)) +BASECONFIG := $(word 1, $(configAsList)) +OLDCONFIGDIR ?= ${WALLY}/pipelined/config +CONFIGDIR ?= $(OUTPUTDIR)/hdl/config CONFIGFILES ?= $(shell find $(CONFIGDIR) -name rv*_*) CONFIGFILESTRIM = $(notdir $(CONFIGFILES)) -# FREQS = 25 50 100 150 200 250 300 350 400 -k = 3 6 - -ifeq ($(TECH), sky130) - FREQS = 25 50 100 150 200 250 300 350 400 -else - FREQS = 500 550 600 650 700 750 800 850 900 950 1000 -endif +# k = 3 6 print: @echo $(FREQS) @@ -39,92 +39,85 @@ print: default: - @echo "Basic synthesis procedure for Wally:" - @echo " Invoke with make synth" - -test: rv% - echo "Running test on $<" - -rv%.log: rv% - echo $< + @echo " Basic synthesis procedure for Wally:" + @echo " Invoke with make synth" + @echo "Use wallySynth.py to run a concurrent sweep " -DIRS = rv64gc rv32e rv32gc rv64ic rv32ic -# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic -# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig +DIRS32 = rv32e rv32gc rv32ic +DIRS64 = rv64ic rv64gc +DIRS = $(DIRS32) $(DIRS64) + # bpred: # @$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);) # @$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;) # @$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;) -copy: - @$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;) - @$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) - @$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;) - @$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;) +configs: $(BASECONFIG) +$(BASECONFIG): + cp -r $(OLDCONFIGDIR)/$(BASECONFIG) $(CONFIGDIR)/$(BASECONFIG)_orig + sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh + sed -i 's/BPRED_SIZE.*/BPRED_SIZE 4/g' $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh -del: - rm -rf $(CONFIGDIR)/*_* - -configs: $(DIRS) -$(DIRS): - #turn off FPU - rm -rf $(CONFIGDIR)/$@_FPUoff +ifneq ($(filter $ $(BASECONFIG), $(DIRS32)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 34\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else ifneq ($(filter $ $(BASECONFIG), $(DIRS64)),) + sed -i "s/RAM_RANGE.*/RAM_RANGE 56\'h01FF/g" $(CONFIGDIR)/$(BASECONFIG)_orig/wally-config.vh +else + $(info $(BASECONFIG) does not exist in $(DIRS32) or $(DIRS64)) + @echo "Config not in list, RAM_RANGE will be unmodified" +endif + + # turn off FPU cp -r $(CONFIGDIR)/$@_orig $(CONFIGDIR)/$@_FPUoff sed -i 's/1 *<< *3/0 << 3/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh sed -i 's/1 *<< *5/0 << 5/' $(CONFIGDIR)/$@_FPUoff/wally-config.vh # PMP 16 - rm -rf $(CONFIGDIR)/$@_PMP16 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP16 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 16/' $(CONFIGDIR)/$@_PMP16/wally-config.vh # PMP 0 - rm -rf $(CONFIGDIR)/$@_PMP0 cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0 sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh - #no muldiv - rm -rf $(CONFIGDIR)/$@_noMulDiv + # no muldiv cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh - #no priv - rm -rf $(CONFIGDIR)/$@_noPriv + # no priv cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif + freqs: @$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;) -allsynth: $(CONFIGFILESTRIM) - -$(CONFIGFILESTRIM): - make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=1000 MAXCORES=1 - - -synth: +mkdirecs: @echo "DC Synthesis" - @mkdir -p hdl/ @mkdir -p $(OUTPUTDIR) + @mkdir -p $(OUTPUTDIR)/hdl/config @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped -ifeq ($(SAIFPOWER), 1) - cp -f ../pipelined/regression/power.saif . -endif - dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out +synth: mkdirecs configs rundc clean + +rundc: + dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out + clean: - rm -rf alib-52 WORK analyzed $(NAME).out - rm -f hdl/* + rm -rf $(OUTPUTDIR)/hdl + rm -rf $(OUTPUTDIR)/WORK + rm -rf $(OUTPUTDIR)/alib-52 rm -f default.svf rm -f command.log rm -f filenames*.log rm -f power.saif - - - + rm -f Synopsys_stack_trace_*.txt + rm -f crte_*.txt \ No newline at end of file diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 85ab99ec6..2587bf103 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -1,29 +1,265 @@ #!/usr/bin/python3 -# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 -import glob +# Madeleine Masser-Frye (mmmasserfrye@hmc.edu) 06/2022 +from collections import namedtuple import re import csv - -field_names = [ 'Name', 'Critical Path Length', 'Cell Area', 'Synth Time'] -data = [] -for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): - f = open(name, 'r') - # trimName = re.search("runs\/(.*?)\/reports", name).group(1) - trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) - for line in f: - if "Critical Path Length" in line: - pathLen = re.search("Length: *(.*?)\\n", line).group(1) - if "Cell Area" in line: - area = re.search("Area: *(.*?)\\n", line).group(1) - if "Overall Compile Time" in line: - time = re.search("Time: *(.*?)\\n", line).group(1) - data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area, 'Synth Time' :time}] - -with open('Summary.csv', 'w') as csvfile: - writer = csv.DictWriter(csvfile, fieldnames=field_names) - writer.writeheader() - writer.writerows(data) +import subprocess +from matplotlib.cbook import flatten +import matplotlib.pyplot as plt +import matplotlib.lines as lines +import numpy as np +from ppa.ppaAnalyze import noOutliers +from matplotlib import ticker +import argparse +import os +def synthsintocsv(): + ''' writes a CSV with one line for every available synthesis + each line contains the module, tech, width, target freq, and resulting metrics + ''' + print("This takes a moment...") + bashCommand = "find . -path '*runs/wallypipelinedcore_*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] - \ No newline at end of file + specReg = re.compile('[a-zA-Z0-9]+') + metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*') + + file = open("Summary.csv", "w") + writer = csv.writer(file) + writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) + + for oneSynth in allSynths: + descrip = specReg.findall(oneSynth) + width = descrip[2][:4] + config = descrip[2][4:] + if descrip[3][-2:] == 'nm': + special = '' + else: + special = descrip[3] + descrip = descrip[1:] + tech = descrip[3][:-2] + freq = descrip[4] + metrics = [] + for phrase in ['Path Slack', 'Design Area']: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*' + bashCommand = bashCommand.format(phrase) + try: + output = subprocess.check_output(['bash','-c', bashCommand]) + nums = metricReg.findall(str(output)) + nums = [float(m) for m in nums] + metrics += nums + except: + print(width + config + tech + '_' + freq + " doesn't have reports") + if metrics == []: + pass + else: + delay = 1000/int(freq) - metrics[0] + area = metrics[1] + writer.writerow([width, config, special, tech, freq, delay, area]) + file.close() + + +def synthsfromcsv(filename): + Synth = namedtuple("Synth", "width config special tech freq delay area") + with open(filename, newline='') as csvfile: + csvreader = csv.reader(csvfile) + global allSynths + allSynths = list(csvreader)[1:] + for i in range(len(allSynths)): + for j in range(len(allSynths[0])): + try: allSynths[i][j] = int(allSynths[i][j]) + except: + try: allSynths[i][j] = float(allSynths[i][j]) + except: pass + allSynths[i] = Synth(*allSynths[i]) + return allSynths + + +def freqPlot(tech, width, config): + ''' plots delay, area for syntheses with specified tech, module, width + ''' + + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'plots/wally') + if not os.path.exists(final_directory): + os.makedirs(final_directory) + + freqsL, delaysL, areasL = ([[], []] for i in range(3)) + for oneSynth in allSynths: + if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('' == oneSynth.special): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] + + fig, (ax1, ax2) = plt.subplots(2, 1, sharex=True) + allFreqs = list(flatten(freqsL)) + if allFreqs != []: + median = np.median(allFreqs) + else: + median = 0 + + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + freqs = freqsL[ind] + freqs, delays, areas = noOutliers(median, freqs, delays, areas) + + c = 'blue' if ind else 'green' + targs = [1000/f for f in freqs] + + ax1.scatter(targs, delays, color=c) + ax2.scatter(targs, areas, color=c) + + freqs = list(flatten(freqsL)) + delays = list(flatten(delaysL)) + areas = list(flatten(areasL)) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] + + ax1.legend(handles=legend_elements) + ytop = ax2.get_ylim()[1] + ax2.set_ylim(ymin=0, ymax=1.1*ytop) + ax2.set_xlabel("Target Cycle Time (ns)") + ax1.set_ylabel('Cycle Time Achieved (ns)') + ax2.set_ylabel('Area (sq microns)') + ax1.set_title(tech + ' ' + width + config) + ax2.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) + addFO4axis(fig, ax1, tech) + + plt.savefig('./plots/wally/freqSweep_' + tech + '_' + width + config + '.png') + + +def areaDelay(tech, delays, areas, labels, fig, ax, norm=False): + + plt.subplots_adjust(left=0.18) + + fo4 = techdict[tech].fo4 + add32area = techdict[tech].add32area + marker = techdict[tech].shape + color = techdict[tech].color + + if norm: + delays = [d/fo4 for d in delays] + areas = [a/add32area for a in areas] + + plt.scatter(delays, areas, marker=marker, color=color) + plt.xlabel('Cycle time (ns)') + plt.ylabel('Area (sq microns)') + ytop = ax.get_ylim()[1] + plt.ylim(ymin=0, ymax=1.1*ytop) + + ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}')) + + for i in range(len(labels)): + plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center') + + return fig + + +def plotFeatures(tech, width, config): + delays, areas, labels = ([] for i in range(3)) + freq = techdict[tech].targfreq + for oneSynth in allSynths: + if (tech == oneSynth.tech) & (freq == oneSynth.freq): + if (oneSynth.config == config) & (width == oneSynth.width): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.special] + + fig, (ax) = plt.subplots(1, 1) + + fig = areaDelay(tech, delays, areas, labels, fig, ax) + + titlestr = tech+'_'+width+config + plt.title(titlestr) + plt.savefig('./plots/wally/features_'+titlestr+'.png') + + +def plotConfigs(tech, special=''): + delays, areas, labels = ([] for i in range(3)) + freq = techdict[tech].targfreq + for oneSynth in allSynths: + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] + + fig, (ax) = plt.subplots(1, 1) + + fig = areaDelay(tech, delays, areas, labels, fig, ax) + + titleStr = tech+'_'+special + plt.title(titleStr) + plt.savefig('./plots/wally/configs_' + titleStr + '.png') + + +def normAreaDelay(special=''): + fig, (ax) = plt.subplots(1, 1) + fullLeg = [] + for tech in list(techdict.keys()): + delays, areas, labels = ([] for i in range(3)) + spec = techdict[tech] + freq = spec.targfreq + for oneSynth in allSynths: + if (tech == oneSynth.tech) & (freq == oneSynth.freq) & (oneSynth.special == special): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.width + oneSynth.config] + areaDelay(tech, delays, areas, labels, fig, ax, norm=True) + fullLeg += [lines.Line2D([0], [0], markerfacecolor=spec.color, label=tech, marker=spec.shape, markersize=10, color='w')] + + ax.set_title('Normalized Area & Cycle Time by Configuration') + ax.set_xlabel('Cycle Time (FO4)') + ax.set_ylabel('Area (add32)') + ax.legend(handles = fullLeg, loc='upper left') + plt.savefig('./plots/wally/normAreaDelay.png') + + +def addFO4axis(fig, ax, tech): + fo4 = techdict[tech].fo4 + + ax3 = fig.add_axes((0.125,0.14,0.775,0.0)) + ax3.yaxis.set_visible(False) # hide the yaxis + + fo4Range = [x/fo4 for x in ax.get_xlim()] + dif = fo4Range[1] - fo4Range[0] + for n in [0.02, 0.05, 0.1, 0.25, 0.5, 1, 2, 5, 10, 20, 50, 100, 200, 500, 1000]: + d = dif/n + if d > 3 and d < 10: + r = [int(x/n) for x in fo4Range] + nsTicks = [round(x*n, 2) for x in range(r[0], r[1]+1)] + break + new_tick_locations = [fo4*float(x) for x in nsTicks] + + ax3.set_xticks(new_tick_locations) + ax3.set_xticklabels(nsTicks) + ax3.set_xlim(ax.get_xlim()) + ax3.set_xlabel("FO4 delays") + plt.subplots_adjust(left=0.125, bottom=0.25, right=0.9, top=0.9) + + +if __name__ == '__main__': + + parser = argparse.ArgumentParser() + parser.add_argument("-s", "--skyfreq", type=int, default=3000, help = "Target frequency used for sky90 syntheses") + parser.add_argument("-t", "--tsmcfreq", type=int, default=10000, help = "Target frequency used for tsmc28 syntheses") + args = parser.parse_args() + + TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy") + techdict = {} + techdict['sky90'] = TechSpec('green', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023) + techdict['tsmc28'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533) + + synthsintocsv() + synthsfromcsv('Summary.csv') + freqPlot('tsmc28', 'rv32', 'e') + freqPlot('sky90', 'rv32', 'e') + plotFeatures('sky90', 'rv64', 'gc') + plotFeatures('tsmc28', 'rv64', 'gc') + plotConfigs('sky90', special='orig') + plotConfigs('tsmc28', special='orig') + normAreaDelay(special='orig') diff --git a/synthDC/ppa/README b/synthDC/ppa/README new file mode 100644 index 000000000..2bdf2edae --- /dev/null +++ b/synthDC/ppa/README @@ -0,0 +1,32 @@ +Wally PPA Study +July 8, 2022 +Madeleine Masser-Frye +mmasserfrye@hmc.edu +___________________ +Apologies for issues in this folder, code was written originally for individual use and documentation was compiled in haste. Please feel free to contact the author with questions. + +------------------- +ppaSynth.py + +Run to synthesize datapath modules from src/ppa. +To run a specific combination of widths, modules, techs, and freqs, +modify those lists and use allCombos() to generate synthsToRun (comment out freqSweep). +To run a sweep of frequencies around the best delay found in existing syntheses (according to bestSynths.csv), modify the parameters and use freqSweep to generate synthsToRun. +To remove synths to be run that already exist in /runs from synthsToRun, use filterRedundant(). +Syntheses run in parallel but you may encounter issues doing more than a dozen or so at once. +------------------- +ppaAnalyze.py + +Run to plot results of PPA syntheses. See docstrings for individual function info. +------------------- +bestSynths.csv + +Results of the synthesis for each combination of module, width, and tech with the best achievable delay. Generated by csvOfBest() in ppaAnalyze.py +------------------- +ppaFitting.csv & ppaEquations.csv + +Representations of the regression fit for each module and metric. Generated in ppaAnalyze.py by makeCoefTable() and makeEqTable(). +------------------- +ppaData.csv + +Results from all synthesis runs. Generated by synthsintocsv() and used by synthsfromcsv in ppaAnalyze.py. diff --git a/synthDC/ppa/bestSynths.csv b/synthDC/ppa/bestSynths.csv new file mode 100644 index 000000000..7e3d35569 --- /dev/null +++ b/synthDC/ppa/bestSynths.csv @@ -0,0 +1,101 @@ +Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (nJ) +priorityencoder,sky90,8,7683,0.12508649056358195,50.960001,24.761,0.010685929975270078 +priorityencoder,sky90,16,5773,0.16977016282695304,136.220003,77.243,0.021773774467348 +priorityencoder,sky90,32,4500,0.2218912222222222,372.400007,189.626,0.04371111111111111 +priorityencoder,sky90,64,4098,0.2439914738897023,797.720015,382.205,0.07393850658857981 +priorityencoder,sky90,128,3409,0.2933331557641537,1602.300031,610.009,0.1261366969785861 +add,sky90,8,3658,0.27337042810278844,253.820005,154.438,0.10825587752870422 +add,sky90,16,2942,0.3393218266485384,722.260013,485.109,0.32460910944935417 +add,sky90,32,2468,0.40496338573743923,1440.600027,714.057,0.6580226904376014 +add,sky90,64,2139,0.4674681813931744,2781.240054,1050.0,0.9392239364188874 +add,sky90,128,1885,0.5304949787798409,6186.740118,2230.0,2.1480106100795755 +csa,sky90,8,5758,0.16536141368530738,266.560005,154.202,0.13650573115665163 +csa,sky90,16,5931,0.1654056314280897,533.12001,308.404,0.27263530601922104 +csa,sky90,32,5758,0.16536141368530738,1066.240021,616.808,0.5448072247308093 +csa,sky90,64,5931,0.1654056314280897,2132.480042,1230.0,1.0905412240768841 +csa,sky90,128,5931,0.1654056314280897,4264.960083,2470.0,2.178553363682347 +shiftleft,sky90,8,4327,0.23025600254217704,259.700005,196.451,0.07534088282874972 +shiftleft,sky90,16,3355,0.29803959314456036,666.400006,558.433,0.19552906110283155 +shiftleft,sky90,32,2503,0.39951757530962845,1475.880027,768.262,0.3807431082700759 +shiftleft,sky90,64,2203,0.45385946391284615,3914.120062,2680.0,1.144802541988198 +shiftleft,sky90,128,1907,0.5242938489774515,9192.400136,6080.0,2.9008914525432616 +comparator,sky90,8,4839,0.20629126741062204,200.900004,136.6,0.05001033271337053 +comparator,sky90,16,4018,0.24806303982080635,358.680007,189.253,0.06321553011448482 +comparator,sky90,32,3602,0.276293542476402,690.900013,315.709,0.10771793448084398 +comparator,sky90,64,3129,0.31954192361776923,1372.980026,508.393,0.2048577820389901 +comparator,sky90,128,2791,0.35824651809387315,2744.980052,796.047,0.34396273737011823 +flop,sky90,8,10,0.1143419999999935,133.279999,64.8145,0.193835 +flop,sky90,16,10,0.1143419999999935,266.5599975,129.629,0.38715000000000005 +flop,sky90,32,10,0.1143419999999935,533.119995,259.258,0.7723000000000001 +flop,sky90,64,10,0.1143419999999935,1066.23999,520.0,1.54955 +flop,sky90,128,10,0.1143419999999935,2132.4799805,1035.0,3.094 +mux2,sky90,8,5299,0.1883518518588413,63.700001,21.541,0.01932440083034535 +mux2,sky90,16,4850,0.20207356701030926,119.560002,32.354,0.03884536082474227 +mux2,sky90,32,5003,0.19908807195682593,375.340008,259.372,0.13671796921846893 +mux2,sky90,64,4073,0.24517727326295113,479.220009,115.22,0.15148539160324087 +mux2,sky90,128,4004,0.24974824975024976,1302.420025,767.078,0.4665334665334665 +mux4,sky90,8,4726,0.21123742953872196,148.960002,66.984,0.04026661024121879 +mux4,sky90,16,4455,0.2231388911335578,392.0,398.313,0.1037037037037037 +mux4,sky90,32,4118,0.24283532831471588,594.860011,331.197,0.131617289946576 +mux4,sky90,64,3710,0.26931477897574124,899.640016,344.331,0.2862533692722372 +mux4,sky90,128,3249,0.3077210113881194,2013.900038,818.249,0.6094182825484764 +mux8,sky90,8,3585,0.2789170278940028,287.140006,116.648,0.06089260808926081 +mux8,sky90,16,3362,0.295237998810232,582.120003,282.366,0.14455681142177274 +mux8,sky90,32,3178,0.3140553102580239,1319.079995,670.683,0.35777218376337316 +mux8,sky90,64,2906,0.3440756228492774,2132.48004,808.482,0.44287680660701995 +mux8,sky90,128,2667,0.3749401308586427,4575.620089,1830.0,0.9786276715410572 +mult,sky90,8,1310,0.7631557786259543,2194.220041,1440.0,1.421374045801527 +mult,sky90,16,997,1.0029260270812437,7519.540137,4940.0,6.376128385155466 +mult,sky90,32,763,1.3106129895150722,25200.700446,14900.0,24.931847968545217 +mult,sky90,64,632,1.5822664810126583,86011.661365,42600.0,88.84651898734177 +mult,sky90,128,524,1.9083759465648855,296198.144128,114000.0,273.3148854961832 +priorityencoder,tsmc28,8,31335,0.031912196106590074,8.316,34.836,0.001716929950534546 +priorityencoder,tsmc28,16,21253,0.04703118086858326,21.672,78.026,0.004008845810003294 +priorityencoder,tsmc28,32,16464,0.06071258114674442,61.614,207.499,0.009323372206025266 +priorityencoder,tsmc28,64,13804,0.07239877021153289,137.466,425.592,0.01847290640394089 +priorityencoder,tsmc28,128,11440,0.0874065874125874,317.646,973.649,0.041171328671328666 +add,tsmc28,8,13838,0.07207477814713109,34.272,187.089,0.013311172134701546 +add,tsmc28,16,11521,0.08678002100512108,90.972001,475.207,0.03367763214998698 +add,tsmc28,32,9812,0.1018860211985324,209.286002,1060.0,0.08153281695882594 +add,tsmc28,64,8206,0.12185605215695831,388.836003,1770.0,0.1409943943456008 +add,tsmc28,128,7354,0.13597341881968997,907.452008,4360.0,0.3451183029643731 +csa,tsmc28,8,24524,0.040663382319360626,52.416,482.462,0.02173381177621921 +csa,tsmc28,16,24524,0.040663382319360626,104.832,964.99,0.04346762355243842 +csa,tsmc28,32,24524,0.040663382319360626,209.664,1930.0,0.08677214157559941 +csa,tsmc28,64,24524,0.040663382319360626,419.327999,3860.0,0.17342195400424076 +csa,tsmc28,128,24524,0.040663382319360626,838.655998,7720.0,0.3471701190670363 +shiftleft,tsmc28,8,15202,0.0656078183133798,50.652,367.074,0.016991185370346006 +shiftleft,tsmc28,16,11804,0.08465604506946797,127.511999,602.29,0.03388681802778719 +shiftleft,tsmc28,32,9587,0.10430391697089808,384.803997,1940.0,0.10180452696359654 +shiftleft,tsmc28,64,8272,0.12086674854932303,1041.263998,5460.0,0.2895309477756286 +shiftleft,tsmc28,128,7023,0.14238329232521713,1836.953994,8670.0,0.566566994162039 +comparator,tsmc28,8,17422,0.05733769130983814,35.784,170.595,0.009488003673516243 +comparator,tsmc28,16,13736,0.07273839778683751,54.558,250.167,0.014349155503785673 +comparator,tsmc28,32,12139,0.08236710865804432,145.782,622.975,0.03567015404893319 +comparator,tsmc28,64,11080,0.09024670758122744,294.21,1250.0,0.0684115523465704 +comparator,tsmc28,128,9371,0.10671119720414043,558.432,2400.0,0.12794792444776437 +flop,tsmc28,8,10,0.048889000000002625,15.12,78.6345,0.027246000000000003 +flop,tsmc28,16,10,0.048889000000002625,30.24,157.29,0.054290000000000005 +flop,tsmc28,32,10,0.048889000000002625,60.4799995,314.5805,0.10908000000000001 +flop,tsmc28,64,10,0.048889000000002625,120.959999,630.0,0.21765500000000004 +flop,tsmc28,128,10,0.048889000000002625,241.919998,1260.0,0.43579999999999997 +mux2,tsmc28,8,29614,0.03374481252110488,16.758,114.564,0.005436617815897886 +mux2,tsmc28,16,18767,0.053046021580433735,15.75,88.025,0.005142004582511856 +mux2,tsmc28,32,17903,0.05585556035301346,32.130001,171.146,0.009897782494553985 +mux2,tsmc28,64,18568,0.05371109651012495,91.35,523.884,0.027574321413183972 +mux2,tsmc28,128,16637,0.05991099044298852,176.525999,941.106,0.05012923002945243 +mux4,tsmc28,8,18151,0.055092383284667513,27.971999,133.963,0.008032615282904523 +mux4,tsmc28,16,16486,0.06057952759917506,39.438,186.231,0.012556108213029236 +mux4,tsmc28,32,15196,0.06580579126085812,69.174,324.969,0.023229797315082915 +mux4,tsmc28,64,13926,0.07180612868016659,137.465999,648.086,0.04574177796926612 +mux4,tsmc28,128,13090,0.07636619404125286,294.335997,1420.0,0.09358288770053477 +mux8,tsmc28,8,12902,0.07750336319950395,44.604,214.286,0.0117501162610448 +mux8,tsmc28,16,12264,0.08147446510110894,128.771998,548.714,0.02666340508806262 +mux8,tsmc28,32,11713,0.08517122410996329,172.115999,823.633,0.046956373260479814 +mux8,tsmc28,64,11014,0.09067453550027238,304.163999,1460.0,0.08498274922825495 +mux8,tsmc28,128,10474,0.09542350830628223,683.045996,2820.0,0.15705556616383426 +mult,tsmc28,8,5200,0.1922996923076923,577.206,4340.0,0.37769230769230766 +mult,tsmc28,16,3819,0.26184265147944485,1634.472002,11800.0,1.4553548049227547 +mult,tsmc28,32,3033,0.3295775611605671,6343.721998,47200.0,6.303330036267723 +mult,tsmc28,64,2390,0.4184090418410042,16045.092071,109000.0,18.54602510460251 +mult,tsmc28,128,1868,0.5353279057815846,44272.49428,262000.0,50.01177730192719 diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py new file mode 100755 index 000000000..2dce62ae5 --- /dev/null +++ b/synthDC/ppa/ppaAnalyze.py @@ -0,0 +1,737 @@ +#!/usr/bin/python3 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 5/22 + +import scipy.optimize as opt +import subprocess +import csv +import re +from matplotlib.cbook import flatten +import matplotlib.pyplot as plt +import matplotlib.lines as lines +import matplotlib as mpl +import numpy as np +from collections import namedtuple +import sklearn.metrics as skm +import os + +def synthsfromcsv(filename): + Synth = namedtuple("Synth", "module tech width freq delay area lpower denergy") + with open(filename, newline='') as csvfile: + csvreader = csv.reader(csvfile) + global allSynths + allSynths = list(csvreader)[1:] + for i in range(len(allSynths)): + for j in range(len(allSynths[0])): + try: allSynths[i][j] = int(allSynths[i][j]) + except: + try: allSynths[i][j] = float(allSynths[i][j]) + except: pass + allSynths[i] = Synth(*allSynths[i]) + return allSynths + +def synthsintocsv(): + ''' writes a CSV with one line for every available synthesis + each line contains the module, tech, width, target freq, and resulting metrics + ''' + print("This takes a moment...") + bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + + specReg = re.compile('[a-zA-Z0-9]+') + metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*') + + file = open("ppaData.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (nJ)']) + + for oneSynth in allSynths: + module, width, risc, tech, freq = specReg.findall(oneSynth)[2:7] + tech = tech[:-2] + metrics = [] + for phrase in [['Path Slack', 'qor'], ['Design Area', 'qor'], ['100', 'power']]: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*' + bashCommand = bashCommand.format(*phrase) + try: output = subprocess.check_output(['bash','-c', bashCommand]) + except: + print(module + width + tech + freq + " doesn't have reports") + print("Consider running cleanup() first") + nums = metricReg.findall(str(output)) + nums = [float(m) for m in nums] + metrics += nums + delay = 1000/int(freq) - metrics[0] + area = metrics[1] + lpower = metrics[4] + denergy = (metrics[2] + metrics[3])/int(freq)*1000 # (switching + internal powers)*delay, more practical units for regression coefs + + if ('flop' in module): # since two flops in each module + [area, lpower, denergy] = [n/2 for n in [area, lpower, denergy]] + + writer.writerow([module, tech, width, freq, delay, area, lpower, denergy]) + file.close() + +def cleanup(): + ''' removes runs that didn't work + ''' + bashCommand = 'grep -r "Error" runs/ppa*/reports/*qor*' + try: + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + for run in allSynths: + run = run.split('MHz')[0] + bc = 'rm -r '+ run + '*' + output = subprocess.check_output(['bash','-c', bc]) + except: pass + + bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + for oneSynth in allSynths: + for phrase in [['Path Length', 'qor']]: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*{}*' + bashCommand = bashCommand.format(*phrase) + try: output = subprocess.check_output(['bash','-c', bashCommand]) + except: + bc = 'rm -r '+ oneSynth[2:] + output = subprocess.check_output(['bash','-c', bc]) + print("All cleaned up!") + +def getVals(tech, module, var, freq=None, width=None): + ''' for a specified tech, module, and variable/metric + returns a list of values for that metric in ascending width order + works at a specified target frequency or if none is given, uses the synthesis with the best achievable delay for each width + ''' + + if width != None: + widthsToGet = width + else: + widthsToGet = widths + + metric = [] + widthL = [] + + if (freq != None): + for oneSynth in allSynths: + if (oneSynth.freq == freq) & (oneSynth.tech == tech) & (oneSynth.module == module) & (oneSynth.width != 1): + widthL += [oneSynth.width] + osdict = oneSynth._asdict() + metric += [osdict[var]] + metric = [x for _, x in sorted(zip(widthL, metric))] # ordering + else: + for w in widthsToGet: + for oneSynth in bestSynths: + if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == module): + osdict = oneSynth._asdict() + met = osdict[var] + metric += [met] + return metric + +def csvOfBest(filename): + bestSynths = [] + for tech in [x.tech for x in techSpecs]: + for mod in modules: + for w in widths: + m = np.Inf # large number to start + best = None + for oneSynth in allSynths: # best achievable, rightmost green + if (oneSynth.width == w) & (oneSynth.tech == tech) & (oneSynth.module == mod): + if (oneSynth.delay < m) & (1000/oneSynth.delay > oneSynth.freq): + m = oneSynth.delay + best = oneSynth + + if (best != None) & (best not in bestSynths): + bestSynths += [best] + + file = open(filename, "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Tech', 'Width', 'Target Freq', 'Delay', 'Area', 'L Power (nW)', 'D energy (nJ)']) + for synth in bestSynths: + writer.writerow(list(synth)) + file.close() + return bestSynths + +def genLegend(fits, coefs, r2=None, spec=None, ale=False): + ''' generates a list of two legend elements (or just an equation if no r2 or spec) + labels line with fit equation and dots with r squared of the fit + ''' + + coefsr = [str(sigfig(c, 2)) for c in coefs] + if ale: + if (normAddWidth == 32): + sub = 'S' + elif normAddWidth != 1: + print('Equations are wrong, check normAddWidth') + else: + sub = 'N' + + eqDict = {'c': '', 'l': sub, 's': '$'+sub+'^2$', 'g': '$log_2$('+sub+')', 'n': ''+sub+'$log_2$('+sub+')'} + eq = '' + ind = 0 + + for k in eqDict.keys(): + if k in fits: + if str(coefsr[ind]) != '0': eq += " + " + coefsr[ind] + eqDict[k] + ind += 1 + + eq = eq[3:] # chop off leading ' + ' + + if (r2==None) or (spec==None): + return eq + else: + legend_elements = [lines.Line2D([0], [0], color=spec.color, label=eq)] + legend_elements += [lines.Line2D([0], [0], color=spec.color, ls='', marker=spec.shape, label='$R^2$='+ str(round(r2, 4)))] + return legend_elements + +def oneMetricPlot(module, var, freq=None, ax=None, fits='clsgn', norm=True, color=None): + ''' module: string module name + freq: int freq (MHz) + var: string delay, area, lpower, or denergy + fits: constant, linear, square, log2, Nlog2 + plots given variable vs width for all matching syntheses with regression + ''' + singlePlot = True + if ax or (freq == 10): + singlePlot = False + if ax is None: + ax = plt.gca() + + fullLeg = [] + allWidths = [] + allMetrics = [] + + ale = (var != 'delay') # if not delay, must be area, leakage, or energy + modFit = fitDict[module] + fits = modFit[ale] + + if freq: + ls = '--' + else: + ls = '-' + + for spec in techSpecs: + metric = getVals(spec.tech, module, var, freq=freq) + + if norm: + techdict = spec._asdict() + norm = techdict[var] + metric = [m/norm for m in metric] + + if len(metric) == 5: # don't include the spec if we don't have points for all widths + xp, pred, coefs, r2 = regress(widths, metric, fits, ale) + fullLeg += genLegend(fits, coefs, r2, spec, ale=ale) + c = color if color else spec.color + ax.scatter(widths, metric, color=c, marker=spec.shape) + ax.plot(xp, pred, color=c, linestyle=ls) + allWidths += widths + allMetrics += metric + + xp, pred, coefs, r2 = regress(allWidths, allMetrics, fits) + ax.plot(xp, pred, color='red', linestyle=ls) + + if norm: + ylabeldic = {"lpower": "Leakage Power (add32)", "denergy": "Energy/Op (add32)", "area": "Area (add32)", "delay": "Delay (FO4)"} + else: + ylabeldic = {"lpower": "Leakage Power (nW)", "denergy": "Dynamic Energy (nJ)", "area": "Area (sq microns)", "delay": "Delay (ns)"} + + ax.set_ylabel(ylabeldic[var]) + ax.set_xticks(widths) + + if singlePlot or (var == 'lpower') or (var == 'denergy'): + ax.set_xlabel("Width (bits)") + if not singlePlot and ((var == 'delay') or (var == 'area')): + ax.tick_params(labelbottom=False) + + if singlePlot: + fullLeg += genLegend(fits, coefs, r2, combined, ale=ale) + legLoc = 'upper left' if ale else 'center right' + ax.add_artist(ax.legend(handles=fullLeg, loc=legLoc)) + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else " (best achievable delay)" + ax.set_title(module + titleStr) + plt.savefig('.plots/'+ module + '_' + var + '.png') + # plt.show() + return r2 + +def regress(widths, var, fits='clsgn', ale=False): + ''' fits a curve to the given points + returns lists of x and y values to plot that curve and coefs for the eq with r2 + ''' + + funcArr = genFuncs(fits) + xp = np.linspace(min(widths)/2, max(widths)*1.1, 200) + xpToCalc = xp + + if ale: + widths = [w/normAddWidth for w in widths] + xpToCalc = [x/normAddWidth for x in xp] + + mat = [] + for w in widths: + row = [] + for func in funcArr: + row += [func(w)] + mat += [row] + + y = np.array(var, dtype=np.float) + coefs = opt.nnls(mat, y)[0] + + yp = [] + for w in widths: + n = [func(w) for func in funcArr] + yp += [sum(np.multiply(coefs, n))] + r2 = skm.r2_score(y, yp) + + pred = [] + for x in xpToCalc: + n = [func(x) for func in funcArr] + pred += [sum(np.multiply(coefs, n))] + + return xp, pred, coefs, r2 + +def makeCoefTable(): + ''' writes CSV with each line containing the coefficients for a regression fit + to a particular combination of module, metric (including both techs, normalized) + ''' + file = open("ppaFitting.csv", "w") + writer = csv.writer(file) + writer.writerow(['Module', 'Metric', 'Target', '1', 'N', 'N^2', 'log2(N)', 'Nlog2(N)', 'R^2']) + + for module in modules: + for freq in [10, None]: + target = 'easy' if freq else 'hard' + for var in ['delay', 'area', 'lpower', 'denergy']: + ale = (var != 'delay') + metL = [] + modFit = fitDict[module] + fits = modFit[ale] + + for spec in techSpecs: + metric = getVals(spec.tech, module, var, freq=freq) + techdict = spec._asdict() + norm = techdict[var] + metL += [m/norm for m in metric] + + xp, pred, coefs, r2 = regress(widths*2, metL, fits, ale) + coefs = np.ndarray.tolist(coefs) + coefsToWrite = [None]*5 + fitTerms = 'clsgn' + ind = 0 + for i in range(len(fitTerms)): + if fitTerms[i] in fits: + coefsToWrite[i] = coefs[ind] + ind += 1 + row = [module, var, target] + coefsToWrite + [r2] + writer.writerow(row) + + file.close() + +def sigfig(num, figs): + return '{:g}'.format(float('{:.{p}g}'.format(num, p=figs))) + +def makeEqTable(): + ''' writes CSV with each line containing the equations for fits for each metric + to a particular module (including both techs, normalized) + ''' + file = open("ppaEquations.csv", "w") + writer = csv.writer(file) + writer.writerow(['Element', 'Best delay', 'Fast area', 'Fast leakage', 'Fast energy', 'Small area', 'Small leakage', 'Small energy']) + + for module in modules: + eqs = [] + for freq in [None, 10]: + for var in ['delay', 'area', 'lpower', 'denergy']: + if (var == 'delay') and (freq == 10): + pass + else: + ale = (var != 'delay') + metL = [] + modFit = fitDict[module] + fits = modFit[ale] + + for spec in techSpecs: + metric = getVals(spec.tech, module, var, freq=freq) + techdict = spec._asdict() + norm = techdict[var] + metL += [m/norm for m in metric] + + xp, pred, coefs, r2 = regress(widths*2, metL, fits, ale) + coefs = np.ndarray.tolist(coefs) + eqs += [genLegend(fits, coefs, ale=ale)] + row = [module] + eqs + writer.writerow(row) + + file.close() + +def genFuncs(fits='clsgn'): + ''' helper function for regress() + returns array of functions with one for each term desired in the regression fit + ''' + funcArr = [] + if 'c' in fits: + funcArr += [lambda x: 1] + if 'l' in fits: + funcArr += [lambda x: x] + if 's' in fits: + funcArr += [lambda x: x**2] + if 'g' in fits: + funcArr += [lambda x: np.log2(x)] + if 'n' in fits: + funcArr += [lambda x: x*np.log2(x)] + return funcArr + +def noOutliers(median, freqs, delays, areas): + ''' returns a pared down list of freqs, delays, and areas + cuts out any syntheses in which target freq isn't within 75% of the min delay target to focus on interesting area + helper function to freqPlot() + ''' + f=[] + d=[] + a=[] + for i in range(len(freqs)): + norm = freqs[i]/median + if (norm > 0.4) & (norm<1.4): + f += [freqs[i]] + d += [delays[i]] + a += [areas[i]] + + return f, d, a + +def freqPlot(tech, mod, width): + ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width + ''' + + freqsL, delaysL, areasL = ([[], []] for i in range(3)) + for oneSynth in allSynths: + if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] + + median = np.median(list(flatten(freqsL))) + + f, (ax1, ax2) = plt.subplots(2, 1, sharex=True) + for ax in (ax1, ax2): + ax.ticklabel_format(useOffset=False, style='plain') + + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + freqs = freqsL[ind] + + freqs, delays, areas = noOutliers(median, freqs, delays, areas) # comment out to see all syntheses + + c = 'blue' if ind else 'green' + ax1.scatter(freqs, delays, color=c) + ax2.scatter(freqs, areas, color=c) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] + + ax1.legend(handles=legend_elements) + width = str(width) + + ax2.set_xlabel("Target Freq (MHz)") + ax1.set_ylabel('Delay (ns)') + ax2.set_ylabel('Area (sq microns)') + ax1.set_title(mod + '_' + width) + if ('mux' in mod) & ('d' in mod): + width = mod + mod = 'muxd' + plt.savefig('./plots/freqBuckshot/' + tech + '/' + mod + '/' + width + '.png') + # plt.show() + +def squareAreaDelay(tech, mod, width): + ''' plots delay, area, area*delay, and area*delay^2 for syntheses with specified tech, module, width + ''' + global allSynths + freqsL, delaysL, areasL = ([[], []] for i in range(3)) + for oneSynth in allSynths: + if (mod == oneSynth.module) & (width == oneSynth.width) & (tech == oneSynth.tech): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] + + f, (ax1) = plt.subplots(1, 1) + ax2 = ax1.twinx() + + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + targets = freqsL[ind] + targets = [1000/f for f in targets] + + targets, delays, areas = noOutliers(targets, delays, areas) # comment out to see all + + if not ind: + achievedDelays = delays + + c = 'blue' if ind else 'green' + ax1.scatter(targets, delays, marker='^', color=c) + ax2.scatter(targets, areas, marker='s', color=c) + + bestAchieved = min(achievedDelays) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='^', label='delay (timing achieved)'), + lines.Line2D([0], [0], color='green', ls='', marker='s', label='area (timing achieved)'), + lines.Line2D([0], [0], color='blue', ls='', marker='^', label='delay (timing violated)'), + lines.Line2D([0], [0], color='blue', ls='', marker='s', label='area (timing violated)')] + + ax2.legend(handles=legend_elements, loc='upper left') + + ax1.set_xlabel("Delay Targeted (ns)") + ax1.set_ylabel("Delay Achieved (ns)") + ax2.set_ylabel('Area (sq microns)') + ax1.set_title(mod + '_' + str(width)) + + squarify(f) + + xvals = np.array(ax1.get_xlim()) + frac = (min(flatten(delaysL))-xvals[0])/(xvals[1]-xvals[0]) + areaLowerLim = min(flatten(areasL))-100 + areaUpperLim = max(flatten(areasL))/frac + areaLowerLim + ax2.set_ylim([areaLowerLim, areaUpperLim]) + ax1.plot(xvals, xvals, ls="--", c=".3") + ax1.hlines(y=bestAchieved, xmin=xvals[0], xmax=xvals[1], color="black", ls='--') + + plt.savefig('./plots/squareareadelay_' + mod + '_' + str(width) + '.png') + # plt.show() + +def squarify(fig): + ''' helper function for squareAreaDelay() + forces matplotlib figure to be a square + ''' + w, h = fig.get_size_inches() + if w > h: + t = fig.subplotpars.top + b = fig.subplotpars.bottom + axs = h*(t-b) + l = (1.-axs/w)/2 + fig.subplots_adjust(left=l, right=1-l) + else: + t = fig.subplotpars.right + b = fig.subplotpars.left + axs = w*(t-b) + l = (1.-axs/h)/2 + fig.subplots_adjust(bottom=l, top=1-l) + +def plotPPA(mod, freq=None, norm=True, aleOpt=False): + ''' for the module specified, plots width vs delay, area, leakage power, and dynamic energy with fits + if no freq specified, uses the synthesis with best achievable delay for each width + overlays data from both techs + ''' + with mpl.rc_context({"figure.figsize": (7,3.46)}): + fig, axs = plt.subplots(2, 2) + + arr = [['delay', 'area'], ['lpower', 'denergy']] + + freqs = [freq] + if aleOpt: freqs += [10] + + for i in [0, 1]: + for j in [0, 1]: + leg = [] + for f in freqs: + if (arr[i][j]=='delay') and (f==10): + pass + else: + r2 = oneMetricPlot(mod, arr[i][j], ax=axs[i, j], freq=f, norm=norm) + ls = '--' if f else '-' + leg += [lines.Line2D([0], [0], color='red', label='$R^2$='+str(round(r2, 4)), linestyle=ls)] + + if (mod in ['flop', 'csa']) & (arr[i][j] == 'delay'): + axs[i, j].set_ylim(ymin=0) + ytop = axs[i, j].get_ylim()[1] + axs[i, j].set_ylim(ymax=1.1*ytop) + else: + axs[i, j].legend(handles=leg, handlelength=1.5) + + titleStr = " (target " + str(freq)+ "MHz)" if freq != None else "" + plt.suptitle(mod + titleStr) + plt.tight_layout(pad=0.05, w_pad=1, h_pad=0.5, rect=(0,0,1,0.97)) + + if freq != 10: + n = 'normalized' if norm else 'unnormalized' + saveStr = './plots/'+ n + '/' + mod + '.png' + plt.savefig(saveStr) + # plt.show() + +def makeLineLegend(): + ''' generates legend to accompany normalized plots + ''' + plt.rcParams["figure.figsize"] = (5.5,0.3) + fig = plt.figure() + fullLeg = [lines.Line2D([0], [0], color='black', label='fastest', linestyle='-')] + fullLeg += [lines.Line2D([0], [0], color='black', label='smallest', linestyle='--')] + fullLeg += [lines.Line2D([0], [0], color='blue', label='tsmc28', marker='^')] + fullLeg += [lines.Line2D([0], [0], color='green', label='sky90', marker='o')] + fullLeg += [lines.Line2D([0], [0], color='red', label='combined', marker='_')] + fig.legend(handles=fullLeg, ncol=5, handlelength=1.4, loc='center') + saveStr = './plots/legend.png' + plt.savefig(saveStr) + +def muxPlot(fits='clsgn', norm=True): + ''' module: string module name + freq: int freq (MHz) + var: string delay, area, lpower, or denergy + fits: constant, linear, square, log2, Nlog2 + plots given variable vs width for all matching syntheses with regression + ''' + ax = plt.gca() + + inputs = [2, 4, 8] + allInputs = inputs*2 + fullLeg = [] + + for crit in ['data', 'control']: + allMetrics = [] + muxes = ['mux2', 'mux4', 'mux8'] + + if crit == 'data': + ls = '--' + muxes = [m + 'd' for m in muxes] + elif crit == 'control': + ls = '-' + + for spec in techSpecs: + metric = [] + for module in muxes: + metric += getVals(spec.tech, module, 'delay', width=[1]) + + if norm: + techdict = spec._asdict() + norm = techdict['delay'] + metric = [m/norm for m in metric] + # print(spec.tech, ' ', metric) + + if len(metric) == 3: # don't include the spec if we don't have points for all + xp, pred, coefs, r2 = regress(inputs, metric, fits, ale=False) + ax.scatter(inputs, metric, color=spec.color, marker=spec.shape) + ax.plot(xp, pred, color=spec.color, linestyle=ls) + allMetrics += metric + + xp, pred, coefs, r2 = regress(allInputs, allMetrics, fits) + ax.plot(xp, pred, color='red', linestyle=ls) + fullLeg += [lines.Line2D([0], [0], color='red', label=crit, linestyle=ls)] + + ax.set_ylabel('Delay (FO4)') + ax.set_xticks(inputs) + ax.set_xlabel("Number of inputs") + ax.set_title('mux timing') + + ax.legend(handles = fullLeg) + plt.savefig('./plots/mux.png') + +def stdDevError(): + ''' calculates std deviation and error for paper-writing purposes + ''' + for var in ['delay', 'area', 'lpower', 'denergy']: + errlist = [] + for module in modules: + ale = (var != 'delay') + metL = [] + modFit = fitDict[module] + fits = modFit[ale] + funcArr = genFuncs(fits) + + for spec in techSpecs: + metric = getVals(spec.tech, module, var) + techdict = spec._asdict() + norm = techdict[var] + metL += [m/norm for m in metric] + + if ale: + ws = [w/normAddWidth for w in widths] + else: + ws = widths + ws = ws*2 + mat = [] + for w in ws: + row = [] + for func in funcArr: + row += [func(w)] + mat += [row] + + y = np.array(metL, dtype=np.float) + coefs = opt.nnls(mat, y)[0] + + yp = [] + for w in ws: + n = [func(w) for func in funcArr] + yp += [sum(np.multiply(coefs, n))] + + if (var == 'delay') & (module == 'flop'): + pass + elif (module == 'mult') & ale: + pass + else: + for i in range(len(y)): + errlist += [abs(y[i]/yp[i]-1)] + # print(module, ' ', var, ' ', np.mean(errlist[-10:])) + + avgErr = np.mean(errlist) + stdv = np.std(errlist) + + print(var, ' ', avgErr, ' ', stdv) + +def makePlotDirectory(): + ''' creates plots directory in same level as this script to store plots in + ''' + current_directory = os.getcwd() + final_directory = os.path.join(current_directory, 'plots') + if not os.path.exists(final_directory): + os.makedirs(final_directory) + os.chdir(final_directory) + + for folder in ['freqBuckshot', 'normalized', 'unnormalized']: + new_directory = os.path.join(final_directory, folder) + if not os.path.exists(new_directory): + os.makedirs(new_directory) + os.chdir(new_directory) + if 'freq' in folder: + for tech in ['sky90', 'tsmc28']: + for mod in modules: + tech_directory = os.path.join(new_directory, tech) + mod_directory = os.path.join(tech_directory, mod) + if not os.path.exists(mod_directory): + os.makedirs(mod_directory) + os.chdir('..') + + os.chdir(current_directory) + +if __name__ == '__main__': + ############################## + # set up stuff, global variables + widths = [8, 16, 32, 64, 128] + modules = ['priorityencoder', 'add', 'csa', 'shiftleft', 'comparator', 'flop', 'mux2', 'mux4', 'mux8', 'mult'] #, 'mux2d', 'mux4d', 'mux8d'] + normAddWidth = 32 # divisor to use with N since normalizing to add_32 + + fitDict = {'add': ['cg', 'l', 'l'], 'mult': ['cg', 's', 's'], 'comparator': ['cg', 'l', 'l'], 'csa': ['c', 'l', 'l'], 'shiftleft': ['cg', 'l', 'ln'], 'flop': ['c', 'l', 'l'], 'priorityencoder': ['cg', 'l', 'l']} + fitDict.update(dict.fromkeys(['mux2', 'mux4', 'mux8'], ['cg', 'l', 'l'])) + + TechSpec = namedtuple("TechSpec", "tech color shape delay area lpower denergy") + techSpecs = [['sky90', 'green', 'o', 43.2e-3, 1440.600027, 714.057, 0.658022690438], ['tsmc28', 'blue', '^', 12.2e-3, 209.286002, 1060.0, .08153281695882594]] + techSpecs = [TechSpec(*t) for t in techSpecs] + combined = TechSpec('combined fit', 'red', '_', 0, 0, 0, 0) + ############################## + + # cleanup() # run to remove garbage synth runs + synthsintocsv() # slow, run only when new synth runs to add to csv + + allSynths = synthsfromcsv('ppaData.csv') # your csv here! + bestSynths = csvOfBest('bestSynths.csv') + makePlotDirectory() + + # ### other functions + # makeCoefTable() + # makeEqTable() + # muxPlot() + # stdDevError() + + for mod in modules: + for w in widths: + freqPlot('sky90', mod, w) + freqPlot('tsmc28', mod, w) + plotPPA(mod, norm=False) + plotPPA(mod, aleOpt=True) + plt.close('all') \ No newline at end of file diff --git a/synthDC/ppa/ppaData.csv b/synthDC/ppa/ppaData.csv new file mode 100644 index 000000000..601e74652 --- /dev/null +++ b/synthDC/ppa/ppaData.csv @@ -0,0 +1,1221 @@ +Module,Tech,Width,Target Freq,Delay,Area,L Power (nW),D energy (nJ) +mux2,sky90,1,12770,0.08300853563038371,13.72,12.3,0.0039075959279561475 +comparator,sky90,32,3674,0.2733739069134458,699.720013,330.048,0.108056614044638 +mux4,tsmc28,16,15167,0.0651646168655634,32.886,134.911,0.010127249950550539 +priorityencoder,sky90,8,7522,0.1322263661260303,47.040001,18.57,0.010276522201542142 +add,tsmc28,64,8534,0.12049834544176237,447.300003,2220.0,0.1683852823998125 +mux4,sky90,16,4529,0.263597293442261,358.680007,100.453,0.07948774563921396 +mux8,tsmc28,1,17693,0.060110527496750124,9.072,57.908,0.002797716611089131 +mult,sky90,8,1389,0.7681404046076313,2209.900042,1430.0,1.470842332613391 +add,sky90,8,3439,0.2897002041291073,243.040005,146.139,0.11805757487641758 +priorityencoder,tsmc28,32,17451,0.058905306400779324,66.15,236.198,0.009907741676694747 +shiftleft,tsmc28,16,10,0.16585499999999342,43.722,137.701,0.01291 +mux8d,sky90,1,10,0.22809599999999364,34.300001,4.606,0.00609 +comparator,sky90,32,3890,0.2804184087403599,745.780014,371.064,0.12262210796915168 +mux2,sky90,8,5299,0.1883518518588413,63.700001,21.541,0.01932440083034535 +flop,sky90,8,9270,0.11434386515641856,133.279999,64.8145,0.19360302049622438 +mult,tsmc28,32,2973,0.3363555785401951,5141.430011,36900.0,5.416414396232761 +mux4,tsmc28,64,13926,0.07180612868016659,137.465999,648.086,0.04574177796926612 +csa,sky90,32,5998,0.16643624074691563,1178.940023,650.306,0.6495498499499833 +flop,sky90,32,8921,0.11434405660800359,533.119995,259.258,0.7742405559914808 +mux8,sky90,128,2453,0.40739008479412964,3629.920071,818.07,0.7240114145943742 +csa,tsmc28,32,24524,0.040663382319360626,209.664,1930.0,0.08677214157559941 +mult,tsmc28,128,1943,0.525260039114771,48676.82422,299000.0,55.878023674729796 +priorityencoder,tsmc28,16,20828,0.048207291146533514,20.79,73.76,0.003797772229690801 +csa,tsmc28,8,22562,0.04244531185178619,31.248001,240.54,0.013850722453683184 +mux8,sky90,16,3636,0.28388450275027505,608.580012,247.862,0.13091309130913092 +mult,tsmc28,8,5301,0.19483965214110546,531.468,3930.0,0.35106583663459723 +csa,sky90,128,6294,0.16536147442008264,6117.160119,3640.0,2.729583730537019 +mux8,sky90,128,2667,0.3749401308586427,4575.620089,1830.0,0.9786276715410572 +shiftleft,tsmc28,16,12748,0.08287467743959838,125.243999,615.906,0.03451521807342328 +add,tsmc28,32,10597,0.10036333009342267,240.030002,1260.0,0.09266773615174106 +flop,sky90,64,8221,0.1143447031991242,1066.23999,520.0,1.5482909621700522 +csa,tsmc28,32,24034,0.04077672239327619,197.567999,1890.0,0.08558708496296911 +flop,sky90,32,8571,0.11434450029168125,533.119995,259.258,0.774180375685451 +mux4d,tsmc28,1,30585,0.03259276589831617,2.898,17.893,0.0008850743828674187 +mux8,tsmc28,128,9636,0.10367850103777501,559.943997,2620.0,0.14061851390618516 +csa,tsmc28,32,23543,0.04244547041583485,124.992002,962.249,0.05509068512933781 +flop,sky90,8,8746,0.11434398307797851,133.279999,64.8145,0.19362565744340268 +mux4,sky90,128,3231,0.3096037022593624,2019.780039,760.934,0.6196224079232435 +mux2,tsmc28,128,15972,0.06228256674179814,173.502,1060.0,0.055033809166040566 +mux2,sky90,64,4396,0.24216452684258416,487.060007,132.876,0.16014558689717925 +csa,tsmc28,16,25995,0.040894936333910364,100.799999,947.479,0.0430467397576457 +priorityencoder,sky90,32,4596,0.2183225047867711,367.500007,196.77,0.04564838990426458 +flop,tsmc28,128,20454,0.04889119262735895,241.919998,1260.0,0.43563606140608185 +mux8d,sky90,1,7754,0.13242769512509672,89.180001,45.284,0.015991746195511993 +mult,tsmc28,16,4125,0.25523324242424245,2007.432002,15100.0,1.7086060606060607 +mux2,sky90,32,4702,0.21088845725223307,368.480007,245.044,0.1344108889834113 +comparator,tsmc28,128,10,0.6097180000000009,256.787999,853.776,0.0566 +csa,sky90,32,5518,0.1796730815512867,1150.520022,813.107,0.5889815150416817 +add,tsmc28,32,10,0.9349590000000063,67.157999,230.644,0.0324 +csa,sky90,64,5931,0.1654056314280897,2132.480042,1230.0,1.0905412240768841 +comparator,sky90,32,3314,0.30097215087507545,694.820014,185.626,0.09897404948702472 +mux8,sky90,32,10,0.9133680000000055,822.220016,56.003,0.1386 +mux4,sky90,128,3324,0.30201935860409146,2346.12003,1140.0,0.7806859205776172 +add,tsmc28,8,13561,0.07281987456677236,31.878,172.3,0.012683430425484846 +mux2,sky90,64,4059,0.2456681000246366,514.50001,165.954,0.164079822616408 +mux8,sky90,16,3293,0.30339846097783174,678.160006,347.764,0.17096872153051929 +mult,tsmc28,16,3743,0.2671573753673524,1399.734003,9840.0,1.2831952978893935 +csa,tsmc28,8,10,0.06758100000000411,17.136,57.229,0.00721 +comparator,sky90,64,2942,0.33983282664853837,1331.820026,241.079,0.1947654656696125 +csa,sky90,16,5810,0.1707250395869191,572.320011,399.957,0.2900172117039587 +mux4,sky90,16,4486,0.22884773785109228,436.100003,418.878,0.10365581810075791 +add,tsmc28,8,13838,0.07207477814713109,34.272,187.089,0.013311172134701546 +add,tsmc28,64,8041,0.12432664146250468,391.860003,1880.0,0.14911080711354308 +mux4,sky90,64,3710,0.26931477897574124,899.640016,344.331,0.2862533692722372 +mux8,sky90,128,2560,0.390515,4343.360071,1680.0,0.93203125 +shiftleft,sky90,32,2353,0.4249323752656184,1232.840023,566.074,0.32171695707607306 +csa,sky90,16,5931,0.1654056314280897,533.12001,308.404,0.27263530601922104 +mux2,sky90,64,3826,0.25709657658128593,462.560009,162.042,0.16989022477783589 +mult,sky90,32,794,1.3013988438287152,26529.580464,17000.0,26.575566750629722 +mult,tsmc28,128,1905,0.5249343832020997,47318.418271,290000.0,54.71338582677165 +mux2,sky90,64,4543,0.2432308641866608,491.96001,108.197,0.14990094651111602 +add,sky90,16,2883,0.351801908775581,694.82001,489.311,0.3315990287894554 +csa,tsmc28,128,25505,0.04036599843168006,806.399994,7610.0,0.3412272103509115 +mux8,tsmc28,128,9846,0.10152608693885842,674.477993,2900.0,0.1568149502335974 +mux2,sky90,8,4981,0.1993458990162618,59.780001,23.364,0.021702469383657903 +mux2,sky90,32,3700,0.2533642702702703,227.360004,74.563,0.08324324324324324 +shiftleft,tsmc28,128,6883,0.1452804859799506,1687.769984,7890.0,0.49716693302339093 +mux4,sky90,16,4750,0.25584431578947364,359.660007,120.182,0.07389473684210526 +mux8,tsmc28,32,10,0.16755700000000218,105.713999,407.748,0.01928 +mux2,tsmc28,64,17825,0.055663981767180924,83.033999,417.316,0.023338008415147268 +shiftleft,sky90,64,2247,0.4693798282153983,3562.300063,1920.0,0.9403649310191367 +mux2,tsmc28,8,30798,0.0337446408857718,16.758,114.743,0.005454899668809662 +mux4,sky90,16,4427,0.224217604924328,359.659999,419.855,0.10074542579625027 +csa,sky90,128,6415,0.1639816453624318,5895.680054,3630.0,2.7976617303195637 +comparator,tsmc28,8,18446,0.058025295348585054,37.548,189.059,0.009611839965304132 +mux8,tsmc28,32,11713,0.08517122410996329,172.115999,823.633,0.046956373260479814 +mux8,sky90,128,2507,0.3981901272437176,3752.420073,821.695,0.6968488232947746 +flop,sky90,128,10,0.1143419999999935,2132.4799805,1035.0,3.094 +priorityencoder,sky90,64,4426,0.25084764121102576,804.580015,353.584,0.07162223226389516 +flop,tsmc28,16,22091,0.048891303426734874,30.24,157.29,0.05447693630890407 +mult,sky90,64,607,1.6473724579901154,75321.821095,29500.0,72.59637561779242 +mux4,sky90,16,4226,0.24670538334122102,318.500005,131.356,0.08305726455276859 +add,sky90,128,1923,0.5214358008320333,6239.660121,2280.0,2.12532501300052 +mux2,sky90,64,3989,0.24961239583855604,479.220007,148.175,0.16570569064928556 +mux2,tsmc28,32,18261,0.05585551360823613,32.130001,171.146,0.009900881660369093 +mux4,sky90,128,2977,0.3352126328518643,2350.040007,969.13,0.8307020490426603 +mux2,sky90,64,4127,0.248457760358614,479.220009,106.14,0.15144172522413374 +add,sky90,64,2139,0.4674681813931744,2781.240054,1050.0,0.9392239364188874 +mux4,sky90,128,3260,0.3103584662576687,2170.700039,1040.0,0.694478527607362 +add,tsmc28,8,13284,0.07456053056308341,33.264,180.682,0.01306082505269497 +csa,sky90,64,5568,0.17497270114942529,2314.760045,1640.0,1.1876795977011494 +mux4,sky90,8,5287,0.22075118138831096,203.840004,102.281,0.046718365802912803 +mux4,tsmc28,1,24680,0.04009963857374392,2.898,17.89,0.0008812803889789302 +csa,tsmc28,16,25014,0.04049261253697929,104.832,964.99,0.043495642440233476 +mux2,tsmc28,64,18568,0.05371109651012495,91.35,523.884,0.027574321413183972 +csa,sky90,16,5568,0.17497270114942529,574.280011,400.9,0.292205459770115 +mux8,tsmc28,64,11234,0.08957548869503294,446.795996,2070.0,0.09337724764108954 +mux8d,sky90,1,7008,0.14061306392694065,110.740002,96.387,0.025470890410958902 +mux8,tsmc28,1,15690,0.06278186297004462,11.718,79.753,0.0036966220522625876 +mux4,tsmc28,128,10,0.3817059999999941,212.561998,731.833,0.07329999999999999 +mux4,sky90,8,4568,0.21942118563922944,136.220003,45.945,0.038507005253940456 +mux4,sky90,8,4693,0.21214331557639038,145.040003,64.775,0.0389729384189218 +comparator,tsmc28,16,14010,0.07188958743754462,52.92,242.622,0.014039971448965025 +priorityencoder,tsmc28,32,15146,0.06594503274792025,47.502,151.098,0.007295655618645188 +priorityencoder,tsmc28,32,17122,0.059302392010279176,59.598001,207.143,0.008871627146361406 +priorityencoder,sky90,128,3273,0.30545509471432936,1551.340029,539.05,0.10785212343415826 +mux4d,sky90,1,9701,0.10307715647871353,51.940001,49.18,0.013627461086485928 +mux2,tsmc28,16,18001,0.05470446930726071,14.994,80.805,0.004971946002999833 +add,sky90,8,3512,0.2841480410022779,244.020004,156.809,0.13069476082004555 +comparator,tsmc28,32,11896,0.08406186953597848,140.238,622.659,0.034045057162071284 +comparator,sky90,32,3530,0.28273311898016995,722.260014,318.387,0.11784702549575071 +mux2,sky90,8,4875,0.20357220512820512,60.760001,22.812,0.021271794871794873 +mux8,tsmc28,8,11869,0.08421509630128908,59.094,255.901,0.01325301204819277 +mux4d,sky90,1,10,0.188477000000006,13.72,1.708,0.00325 +priorityencoder,tsmc28,128,11211,0.08919110900008921,283.248002,843.21,0.03559004549103559 +mux4,tsmc28,128,12043,0.08302378842481109,260.315998,1150.0,0.08394918209748403 +flop,tsmc28,64,20454,0.04889119262735895,120.959999,630.0,0.21783025325119781 +mult,sky90,32,824,1.2735492330097087,28626.780516,20200.0,29.580097087378643 +mux8,tsmc28,32,11245,0.08892641262783459,215.837997,958.69,0.048999555357936854 +mux4,sky90,32,4283,0.24468120476301655,847.700016,518.861,0.18001400887228577 +csa,tsmc28,64,22562,0.04244531185178619,249.984005,1920.0,0.11022958957539225 +mux2,tsmc28,8,28429,0.03986434911533997,11.466,61.225,0.0031622638854690633 +shiftleft,sky90,32,2553,0.39648804386995695,1666.980028,1060.0,0.4888366627497062 +csa,sky90,8,6238,0.1653617909586406,338.100007,209.02,0.15581917281179863 +priorityencoder,sky90,8,7683,0.12508649056358195,50.960001,24.761,0.010685929975270078 +mux2,sky90,128,3956,0.2642535864509606,1007.440002,394.624,0.3660262891809909 +flop,tsmc28,16,20864,0.048891447852760735,30.24,157.289,0.054469421012269946 +mux2,tsmc28,128,16637,0.05991099044298852,176.525999,941.106,0.05012923002945243 +mux4,sky90,128,3303,0.3069780711474417,2001.160038,779.991,0.5818952467453831 +shiftleft,tsmc28,64,8603,0.1211845214460072,1153.529997,6100.0,0.3193072184121818 +csa,tsmc28,64,25505,0.04036599843168006,403.199997,3800.0,0.17047637718094488 +shiftleft,sky90,128,1831,0.5460426450027308,8026.200142,4230.0,2.3042053522665213 +shiftleft,tsmc28,16,10860,0.09202503130755064,79.632,346.968,0.02283609576427256 +comparator,tsmc28,32,13110,0.08841365064836003,147.798,653.398,0.03607932875667429 +shiftleft,tsmc28,8,15202,0.0656078183133798,50.652,367.074,0.016991185370346006 +mult,tsmc28,64,2486,0.41838261464199517,17830.386041,123000.0,20.405068382944492 +mux4,sky90,16,3827,0.25013328037627386,234.220005,65.786,0.06731120982492814 +mux4,sky90,32,3953,0.2646354260055654,694.820013,302.215,0.17227422210979004 +add,sky90,32,10,3.640808000000007,456.679995,55.753,0.1603 +priorityencoder,sky90,32,5171,0.20654319222587508,394.940008,211.398,0.04892670663314639 +comparator,tsmc28,16,13461,0.07416968583314762,48.888,209.064,0.012599361117301833 +add,sky90,8,3365,0.2960748202080238,240.100004,135.697,0.12124814264487371 +flop,tsmc28,32,19636,0.04889186901609289,60.4799995,314.5785,0.10893257282542271 +mux4,tsmc28,32,14285,0.06951250017500875,70.056,308.062,0.021701085054252712 +mux4,tsmc28,32,15196,0.06580579126085812,69.174,324.969,0.023229797315082915 +add,sky90,64,2096,0.4770132366412214,2851.800056,1100.0,0.9990458015267174 +mux4,tsmc28,128,12304,0.08125338231469441,292.949997,1310.0,0.08566319895968791 +flop,tsmc28,64,19636,0.04889186901609289,120.959999,630.0,0.21783968221633732 +mux8,sky90,8,3585,0.2789170278940028,287.140006,116.648,0.06089260808926081 +mux2,sky90,64,4088,0.2460983953033268,482.160008,124.422,0.15557729941291584 +mux2d,sky90,1,12160,0.07841884210526316,18.62,16.576,0.005921052631578948 +mult,tsmc28,32,10,2.1397929999999974,1770.426003,6970.0,1.456 +mux2,sky90,128,3652,0.2735615629791895,942.760018,230.203,0.3044906900328587 +mux8,sky90,64,3027,0.33226909250082587,2210.880042,855.564,0.4800132144037 +priorityencoder,sky90,32,4979,0.2094015428800964,372.400007,230.625,0.04500903795942961 +comparator,sky90,8,5226,0.20861193761959435,224.420003,142.569,0.05778798316111749 +mux8,sky90,128,2720,0.37196705882352943,4226.740078,1240.0,0.8011029411764705 +mux4,sky90,128,3663,0.306884273000273,2294.180044,743.289,0.5511875511875511 +comparator,tsmc28,128,8621,0.11599382415033059,419.705999,1440.0,0.09163670107876117 +mux4,sky90,128,3256,0.3071863071253071,2184.420042,693.138,0.5810810810810811 +flop,tsmc28,128,10,0.048889000000002625,241.919998,1260.0,0.43579999999999997 +mult,tsmc28,128,1719,0.5817325660267597,38214.666162,205000.0,39.616055846422334 +mux4,sky90,1,7478,0.1283835950788981,28.420001,21.808,0.006338593206739769 +flop,tsmc28,16,10,0.048889000000002625,30.24,157.29,0.054290000000000005 +comparator,sky90,8,4645,0.21420925296017224,196.000004,116.123,0.04736275565123789 +mux2,sky90,64,3980,0.25226428140703516,526.259999,203.192,0.19095477386934673 +shiftleft,sky90,16,3288,0.30390325304136256,618.380008,475.055,0.1648418491484185 +mult,sky90,64,594,1.6834886835016836,71780.100958,24600.0,63.42255892255892 +mux4,sky90,1,7322,0.13543670636438132,32.340001,22.173,0.006787762906309752 +mux2,tsmc28,8,31391,0.03374526453442069,16.758,114.743,0.005456978114746265 +mux4,tsmc28,32,10,0.12346599999999341,54.431999,199.177,0.01354 +csa,sky90,32,5758,0.16536141368530738,1066.240021,616.808,0.5448072247308093 +mux8d,sky90,1,7605,0.13242743918474686,89.180001,45.284,0.01604207758053912 +priorityencoder,tsmc28,32,15805,0.06325111673521037,49.896,157.04,0.007586206896551723 +mux4,tsmc28,64,13369,0.07450691024010771,136.331999,609.938,0.043832747400703115 +flop,tsmc28,128,22091,0.048891303426734874,241.919998,1260.0,0.43565252817889644 +comparator,sky90,8,4452,0.22251914914645105,175.420003,102.05,0.044609164420485174 +mux2d,sky90,1,12688,0.07841862799495587,18.62,16.576,0.005918978562421185 +csa,tsmc28,16,25505,0.04036599843168006,100.799999,950.751,0.04277592628896295 +mux4,sky90,16,4213,0.2508225506764776,283.220006,87.245,0.07239496795632566 +flop,sky90,32,9096,0.11434443447669304,533.119995,259.258,0.7742414248021108 +priorityencoder,tsmc28,64,14080,0.07119772727272727,165.312001,544.165,0.02166193181818182 +mux4,tsmc28,32,16108,0.06632995356344673,93.239999,437.954,0.02675689098584554 +priorityencoder,tsmc28,16,20403,0.048862400137234724,20.412,65.051,0.0036612262902514328 +mux8,sky90,8,3729,0.2746434097613301,422.380008,228.3,0.09680879592384017 +priorityencoder,sky90,64,3852,0.25960539979231567,720.300014,251.028,0.059449636552440295 +mux4,sky90,8,4661,0.21448923471358078,164.640002,88.494,0.0431452478009011 +mux4,sky90,32,3813,0.25986668712300026,471.380009,153.367,0.14030946761080512 +priorityencoder,tsmc28,128,10982,0.09105009506465125,249.984,708.42,0.031050810417046076 +mux4,sky90,64,3488,0.29027124770642204,1076.04002,336.513,0.28526376146788995 +mux2,sky90,1,11324,0.08482301836806781,11.76,9.281,0.0037265983751324622 +flop,sky90,64,8571,0.11434450029168125,1066.23999,520.0,1.548302415120756 +flop,sky90,64,9270,0.11434386515641856,1066.23999,520.0,1.5483279395900755 +flop,tsmc28,128,20864,0.048891447852760735,241.919998,1260.0,0.43563075153374237 +flop,sky90,8,8396,0.11434433539780849,133.279999,64.8145,0.19359218675559792 +mux4d,tsmc28,1,33909,0.02948569568551122,6.426,53.381,0.001967029402223598 +mux4,tsmc28,64,14483,0.07128446827314783,225.287996,1000.0,0.05792998688117103 +shiftleft,sky90,64,2336,0.4500001917808219,4441.360059,3810.0,1.3458904109589043 +csa,sky90,32,6238,0.1653617909586406,1349.460026,801.907,0.6146200705354279 +mux2,tsmc28,1,49852,0.019658375752226592,2.142,15.112,0.0006017812725667977 +comparator,tsmc28,16,12912,0.07736533581164808,50.4,200.11,0.012732342007434944 +mux8,sky90,64,2906,0.3440756228492774,2132.48004,808.482,0.44287680660701995 +mux8,sky90,32,3242,0.32156957310302287,1071.14002,340.021,0.22270203578038247 +flop,tsmc28,32,20045,0.04889175255674732,60.4799995,314.5785,0.10893739087054129 +mux4,sky90,64,3933,0.30270983549453345,1673.840027,1300.0,0.4558860920416985 +mux4,sky90,16,4571,0.26359750973528767,358.680007,100.453,0.07941369503390942 +comparator,sky90,128,2522,0.3958217057890563,2654.820052,488.071,0.3370340999206979 +mux2,sky90,32,3400,0.29179964705882355,223.440004,42.391,0.07158823529411765 +add,tsmc28,16,11290,0.08851795925597875,85.428,437.897,0.03153232949512843 +mux4,sky90,16,4500,0.2284882222222222,437.080003,420.382,0.10422222222222222 +flop,sky90,8,8921,0.11434405660800359,133.279999,64.8145,0.19361058177334378 +add,sky90,8,3585,0.2792020278940028,268.520005,182.205,0.13361227336122733 +priorityencoder,sky90,128,3341,0.29916058335827594,1694.420031,709.89,0.1343909009278659 +comparator,tsmc28,16,12637,0.07900370554720265,43.218,177.517,0.011403022869351903 +mux4,sky90,64,3414,0.2928525407147042,1048.60002,252.076,0.2685998828353837 +csa,tsmc28,32,25995,0.040894936333910364,201.599998,1900.0,0.08578572802462012 +add,tsmc28,8,12731,0.07846142510407667,28.98,157.91,0.011994344513392508 +mux4,tsmc28,8,10,0.07530199999999354,15.12,54.869,0.00356 +flop,sky90,16,8046,0.11434435918468804,266.5599975,129.629,0.38714889386030327 +mux2,tsmc28,128,17636,0.05977820004536176,201.347999,1400.0,0.06707870265366295 +mux4,sky90,16,4484,0.22884816503122213,436.100003,418.878,0.10347903657448705 +mux4d,sky90,1,9507,0.10386665267697485,50.960001,47.194,0.013484800673188175 +mux4,tsmc28,128,13875,0.07613907207207207,305.927997,1490.0,0.09643243243243244 +mux4,tsmc28,1,27305,0.03808832906061161,5.292,41.928,0.0017103094671305622 +shiftleft,tsmc28,32,9012,0.11093316023080337,245.951999,1140.0,0.06746560142032845 +priorityencoder,tsmc28,16,22954,0.04644439165287096,26.712,104.46,0.004752984229328221 +mux2,tsmc28,32,17545,0.05664229524080935,30.366001,167.377,0.009905956112852665 +mult,sky90,8,1337,0.7566541563201197,2445.100044,1850.0,1.6222887060583395 +priorityencoder,sky90,32,5075,0.20628333497536946,382.200007,257.609,0.05142857142857143 +comparator,sky90,16,10,0.9970469999999949,252.840005,31.402,0.0261 +mult,sky90,16,1057,1.005271793755913,8161.440151,5800.0,7.126773888363293 +priorityencoder,tsmc28,128,12355,0.08705389113719142,300.006001,970.795,0.0405503844597329 +mux4,tsmc28,16,16816,0.06093117411988582,41.202,195.667,0.012725975261655566 +shiftleft,sky90,16,3154,0.3167537045022194,546.840011,299.663,0.12682308180088775 +csa,tsmc28,32,25014,0.04049261253697929,209.664,1930.0,0.08675141920524505 +mux2,tsmc28,32,10,0.17166100000000029,28.728001,146.078,0.00979 +mux4,tsmc28,1,26255,0.03808798324128737,5.292,41.928,0.0017101504475338031 +mux2d,tsmc28,1,50709,0.019658365221163897,2.142,15.112,0.0006014711392454988 +add,tsmc28,8,14945,0.07161801070592172,40.068,231.181,0.015396453663432584 +mux8,sky90,16,3705,0.2855275330634278,599.760012,190.243,0.1214574898785425 +mult,sky90,128,534,1.9193641760299625,301809.624151,125000.0,289.23595505617976 +mux2,tsmc28,16,17618,0.054704131683505505,14.994,80.805,0.004972187535475082 +add,tsmc28,128,7787,0.1333521601386927,1023.246011,5130.0,0.38153332477205604 +add,tsmc28,16,10829,0.0922426301597562,72.45,357.027,0.027241665897128085 +shiftleft,tsmc28,64,7942,0.12590886829513975,745.289994,3610.0,0.21191135734072022 +mux4,sky90,32,3889,0.2611895104139882,714.420014,328.777,0.19002314219593724 +mux2,tsmc28,1,46800,0.021009521367521367,1.89,12.344,0.0005767094017094016 +mux4,sky90,1,8412,0.12749279362815027,28.420001,25.098,0.0064907275320970036 +mult,sky90,64,10,15.014533999999998,46801.860227,5460.0,19.459999999999997 +mult,sky90,64,632,1.5822664810126583,86011.661365,42600.0,88.84651898734177 +mux4,sky90,16,4840,0.2558435702479339,359.660007,120.182,0.0737603305785124 +mult,sky90,8,1310,0.7631557786259543,2194.220041,1440.0,1.421374045801527 +mux8,tsmc28,64,11675,0.09174310492505353,303.407999,1480.0,0.0835117773019272 +mux2,tsmc28,128,16970,0.05955851915144372,179.045998,924.038,0.04908662345315262 +shiftleft,sky90,16,3087,0.32345509944930356,604.660009,407.488,0.16747651441528993 +flop,tsmc28,16,19636,0.04889186901609289,30.24,157.289,0.054466286412711354 +shiftleft,tsmc28,16,11804,0.08465604506946797,127.511999,602.29,0.03388681802778719 +csa,sky90,64,5810,0.16922003958691909,2696.960052,1950.0,1.3139414802065403 +mux2,sky90,1,11565,0.0848227907479464,11.76,9.281,0.0037267617812364894 +priorityencoder,tsmc28,128,10754,0.09298165538404315,237.636,654.025,0.029105449135205505 +mux2,sky90,128,4032,0.24862387301587302,1305.360024,778.01,0.45907738095238093 +shiftleft,tsmc28,64,8934,0.12338694537721065,1131.605996,5920.0,0.3117304678755317 +mux4,sky90,16,4123,0.24214683846713558,291.060006,99.813,0.0720834343924327 +shiftleft,tsmc28,16,12276,0.08213775887911372,128.771999,599.581,0.033154121863799284 +mux2,sky90,64,3954,0.25284044714213455,482.160009,158.571,0.16514921598381385 +mux4,tsmc28,128,14137,0.07497236556553724,331.505997,1600.0,0.09705029355591709 +mux2,tsmc28,16,19533,0.052470412891004965,15.372,84.373,0.00504274816976399 +mux4,sky90,128,3237,0.30838301977139326,2062.900036,880.935,0.6774791473586654 +mux4,sky90,128,3249,0.3077210113881194,2013.900038,818.249,0.6094182825484764 +flop,tsmc28,64,20864,0.048891447852760735,120.959999,630.0,0.21783934049079753 +shiftleft,sky90,32,2503,0.39951757530962845,1475.880027,768.262,0.3807431082700759 +csa,tsmc28,128,22562,0.04244531185178619,499.96801,3850.0,0.2204591791507845 +flop,tsmc28,8,21273,0.0488919443425939,15.12,78.6345,0.027236402952098903 +mux2d,tsmc28,1,55991,0.01893201321640978,3.276,26.574,0.0009269346859316676 +csa,sky90,32,10,0.2641830000000027,470.399994,55.245,0.1684 +shiftleft,sky90,8,4154,0.2387968247472316,217.560004,130.113,0.0530091478093404 +mux8,tsmc28,8,12644,0.07905289591901297,44.352,215.422,0.011839607719076242 +mux2,tsmc28,1,54939,0.019658005861045887,2.142,15.112,0.0006006661934145144 +flop,tsmc28,128,20045,0.04889175255674732,241.919998,1260.0,0.43564479920179594 +flop,tsmc28,16,20454,0.04889119262735895,30.24,157.289,0.054471008115771984 +mux2,sky90,32,4903,0.20096176116663267,374.360008,257.036,0.1366510299816439 +shiftleft,tsmc28,32,9204,0.10864541373315949,288.539999,1370.0,0.08192090395480227 +comparator,tsmc28,64,10645,0.09393481728511037,278.712,1140.0,0.06519492719586659 +mux4,sky90,32,3737,0.26718032700026756,447.860009,138.381,0.1364731067701365 +csa,sky90,16,6415,0.1639816453624318,736.960007,453.967,0.3499610288386594 +add,sky90,128,1847,0.5413075165132648,6010.340117,1930.0,2.0184082295614507 +csa,tsmc28,8,26486,0.040226795514611495,52.416,489.192,0.021860605602960055 +flop,tsmc28,64,19227,0.048891193998023615,120.959999,630.0,0.2178186924637229 +flop,tsmc28,32,19227,0.048891193998023615,60.4799995,314.5785,0.10892754979976076 +mux4,sky90,32,3584,0.27880885714285714,450.800009,134.823,0.138671875 +mux8,tsmc28,8,13934,0.07549890110521028,46.494,225.202,0.012243433328548874 +csa,sky90,16,10,0.2641830000000027,235.199997,27.622,0.0846 +mux2,sky90,8,5617,0.18835097739006587,64.680001,21.541,0.019316361046822147 +mux2,sky90,32,3550,0.26887414084507044,226.380004,71.139,0.07999999999999999 +mux2,sky90,16,4751,0.20207400378867607,119.560002,32.354,0.03896021890128394 +mux4,sky90,16,3668,0.26406813522355504,238.140005,68.275,0.0723009814612868 +shiftleft,tsmc28,16,11568,0.08636336652835408,114.407998,555.079,0.032244121715076075 +mux2,tsmc28,128,10,0.31761899999999343,113.274004,578.362,0.0475 +add,sky90,8,3731,0.2784306582685607,282.240005,170.25,0.14312516751541143 +mux2,sky90,128,4004,0.24974824975024976,1302.420025,767.078,0.4665334665334665 +add,sky90,32,2226,0.44901729829290205,1172.080023,417.603,0.44923629829290207 +mux2d,tsmc28,1,57047,0.018932405577856855,3.276,26.574,0.0009273055550686277 +mux2,tsmc28,16,10,0.08560900000000515,14.49,74.123,0.00485 +mux4,sky90,32,3871,0.26118918057349527,714.420014,329.878,0.19064841126323948 +mux4,sky90,128,10,1.923141000000001,1662.080032,111.431,0.439 +comparator,sky90,16,4179,0.24596069657812875,417.480006,278.291,0.08542713567839195 +shiftleft,sky90,32,2704,0.3823014852071006,1741.460027,1220.0,0.47928994082840237 +mux4,tsmc28,128,13351,0.07571775649764062,330.245998,1650.0,0.10074151748932667 +comparator,sky90,32,3746,0.2740004148424987,769.300014,392.725,0.12786972770955685 +comparator,tsmc28,32,11653,0.08639581163648846,133.308,567.495,0.03226636917531966 +shiftleft,sky90,128,1984,0.5263342580645162,9846.060141,7380.0,3.1139112903225805 +flop,sky90,16,8396,0.11434433539780849,266.5599975,129.629,0.38708909004287756 +flop,tsmc28,64,20045,0.04889175255674732,120.959999,630.0,0.21780992766275878 +add,sky90,16,3177,0.3287743544224111,734.020014,502.145,0.32892666037141954 +mux8,tsmc28,32,11947,0.08545102167908261,294.588,1430.0,0.06068469071733489 +add,tsmc28,32,10401,0.10034260148062688,236.250002,1260.0,0.09133737140659552 +mult,tsmc28,32,3151,0.330004568390987,6357.077997,47200.0,6.3624246271025084 +comparator,tsmc28,64,11514,0.09154979034219211,276.192001,1270.0,0.06513809275664408 +csa,tsmc28,8,25014,0.04049261253697929,52.416,482.462,0.02170784360757975 +priorityencoder,sky90,64,4098,0.2439914738897023,797.720015,382.205,0.07393850658857981 +csa,tsmc28,64,25995,0.040894936333910364,403.199997,3790.0,0.17187920753991154 +add,sky90,8,3951,0.26842548089091367,271.460005,148.556,0.12401923563654771 +priorityencoder,sky90,64,10,1.535827999999995,436.100008,29.529,0.02269 +mux2,sky90,64,4315,0.2418707103128621,485.100007,130.641,0.159675550405562 +csa,tsmc28,128,24524,0.040663382319360626,838.655998,7720.0,0.3471701190670363 +add,tsmc28,128,7210,0.13869425520110956,868.140006,4090.0,0.33134535367545076 +mux8,sky90,32,3432,0.3320732913752914,899.640018,274.871,0.17424242424242425 +mux8,sky90,8,3872,0.2781554628099173,312.620006,98.575,0.05661157024793389 +add,sky90,16,10,1.9208679999999987,221.479998,28.13,0.07880000000000001 +priorityencoder,tsmc28,64,14908,0.07170007888382077,148.932001,495.463,0.020056345586262413 +csa,tsmc28,128,24034,0.04077672239327619,790.271996,7570.0,0.3422651244070899 +add,tsmc28,64,7713,0.12962723816932453,359.478003,1670.0,0.1358744976014521 +csa,sky90,8,6478,0.16536163229391787,375.340007,216.172,0.15930842852732327 +mux8,sky90,128,2827,0.37011887124159887,4557.000083,1680.0,0.9458790237000354 +comparator,sky90,128,2469,0.4048802762251924,2907.660056,623.203,0.317942486836776 +comparator,tsmc28,64,9994,0.10003003602161296,225.54,848.556,0.0517310386231739 +add,sky90,64,2310,0.4818804329004329,2896.880056,1140.0,1.0454545454545454 +csa,tsmc28,128,23543,0.04244547041583485,499.96801,3850.0,0.22049016692859874 +mux2,sky90,128,3880,0.25698395876288654,1652.280032,1290.0,0.5945876288659794 +mux4,tsmc28,32,15804,0.06679512022272842,75.221999,360.596,0.02372817008352316 +mux2,tsmc28,1,51887,0.019658650182126546,2.142,15.112,0.0006013066856823482 +add,sky90,64,2268,0.46467410758377425,2989.000058,1150.0,1.0533509700176367 +flop,sky90,128,8921,0.11434405660800359,2132.4799805,1035.0,3.096457796211187 +shiftleft,tsmc28,16,11096,0.09008356669069935,82.907999,376.563,0.02406272530641673 +mux4,tsmc28,64,12812,0.07728182641273805,113.399999,453.176,0.03660630658757415 +comparator,tsmc28,128,8809,0.11351826336701101,441.503999,1580.0,0.09774094675899647 +comparator,tsmc28,32,12381,0.082321920119538,163.044,743.896,0.03941523301833454 +flop,sky90,128,9270,0.11434386515641856,2132.4799805,1035.0,3.0964940668824164 +mux2,sky90,64,4032,0.24874687301587303,475.300009,113.443,0.1515376984126984 +mux4,sky90,128,3167,0.31575023618566467,2016.840039,722.109,0.5917271866119356 +comparator,sky90,32,10,1.0165939999999978,495.88001,66.41,0.0424 +comparator,sky90,16,3938,0.25292600812595223,388.080008,208.857,0.07719654647028949 +priorityencoder,sky90,16,6244,0.1666287475976938,185.220003,132.902,0.03294362588084561 +flop,tsmc28,16,21682,0.04889120653076284,30.24,157.29,0.05447606309381053 +mux4d,sky90,1,10284,0.10307742862699339,51.940001,49.18,0.01364255153636717 +comparator,tsmc28,8,16055,0.062218892245406415,26.208,124.888,0.007144191840548115 +mux2,tsmc28,1,52905,0.01965880512238919,2.142,15.112,0.0006010774028919763 +mux4,sky90,128,3357,0.3042110163836759,2132.480041,762.467,0.5895144474232946 +shiftleft,sky90,8,4414,0.25993588038060716,218.540004,115.4,0.05822383325781604 +add,tsmc28,64,7549,0.13246087653993907,330.372002,1490.0,0.1241224003179229 +add,tsmc28,8,14668,0.07161662039814562,39.06,231.044,0.015387237523861466 +comparator,sky90,128,2791,0.35824651809387315,2744.980052,796.047,0.34396273737011823 +shiftleft,tsmc28,32,10163,0.10229014287119945,394.632001,2000.0,0.11040047230148578 +priorityencoder,sky90,8,7362,0.1356376541700625,49.980001,33.776,0.009277370279815267 +mult,sky90,32,763,1.3106129895150722,25200.700446,14900.0,24.931847968545217 +mux2,sky90,8,10,0.41516099999999767,58.800001,10.206,0.01786 +mult,sky90,32,10,8.063384999999997,12417.580067,1180.0,4.64 +mux4,tsmc28,8,17425,0.05691080918220947,19.782,89.585,0.006134863701578192 +mult,sky90,128,514,1.9488052918287937,289359.703832,109000.0,263.0311284046693 +flop,tsmc28,128,19227,0.048891193998023615,241.919998,1260.0,0.4356113798304468 +priorityencoder,sky90,8,10,0.47602799999999945,34.300001,2.489,0.004279 +add,tsmc28,32,9616,0.10391334442595675,202.104002,1010.0,0.07945091514143095 +add,tsmc28,32,9223,0.10841559069717012,174.132001,855.479,0.07090968231594924 +priorityencoder,sky90,16,10,0.660728000000006,85.260002,5.247,0.00692 +csa,sky90,64,6294,0.16398147442008262,3136.000061,1970.0,1.448363520813473 +mux4,tsmc28,64,14205,0.0709287472720873,145.655999,671.083,0.046180922210489264 +mux2,tsmc28,128,17968,0.05788449688334818,210.924,1240.0,0.06077471059661621 +mux4,sky90,8,4726,0.21123742953872196,148.960002,66.984,0.04026661024121879 +mux8,tsmc28,16,11282,0.08828276653075696,76.356,313.906,0.019553270696684985 +mult,tsmc28,128,10,8.397948999999997,26059.445743,91700.0,25.69 +mux4,sky90,128,3391,0.3066542601002654,2248.120044,733.383,0.5682689472132114 +mux4,sky90,8,4288,0.2311609552238806,120.540002,34.353,0.03362873134328358 +priorityencoder,sky90,32,4500,0.2218912222222222,372.400007,189.626,0.04371111111111111 +add,tsmc28,8,14391,0.07025787436592315,37.422,203.854,0.014008755472170106 +csa,tsmc28,64,10,0.06758100000000411,137.087997,458.434,0.05770000000000001 +mux2d,tsmc28,1,48596,0.019658825335418552,2.142,15.112,0.0006029302823277636 +mux8,tsmc28,8,13160,0.07636884194528876,46.494,227.561,0.01222644376899696 +mux8,tsmc28,32,12416,0.08657423711340206,248.723997,1220.0,0.054043170103092786 +mux4,sky90,8,5091,0.22075106383814574,203.840004,102.281,0.046768807699862504 +mux8,sky90,16,3362,0.295237998810232,582.120003,282.366,0.14455681142177274 +mux4,tsmc28,16,10,0.092804000000001,28.224,102.974,0.0069 +mult,sky90,128,524,1.9083759465648855,296198.144128,114000.0,273.3148854961832 +flop,tsmc28,32,20864,0.048891447852760735,60.4799995,314.5785,0.10891487730061351 +csa,sky90,16,6294,0.16398147442008262,784.000015,491.595,0.36272640610104856 +mux8,tsmc28,16,11528,0.08572431575294935,77.994,322.722,0.01940492713393477 +comparator,sky90,8,10,0.7786030000000039,118.580002,16.053,0.013359999999999999 +mux2,sky90,128,3764,0.26554481402763014,1265.179998,702.615,0.4766206163655685 +csa,tsmc28,16,22562,0.04244531185178619,62.496001,481.11,0.02765712259551458 +comparator,tsmc28,128,10121,0.10600846596186148,551.376001,2560.0,0.12597569410137338 +priorityencoder,sky90,64,3770,0.2649169893899205,720.300013,283.102,0.06100795755968169 +mult,sky90,8,1232,0.8116313116883117,1834.560034,953.397,1.1055194805194806 +add,tsmc28,128,10,3.638641000000007,272.789995,918.55,0.1339 +add,tsmc28,16,12212,0.08589166885031116,99.792001,541.144,0.03807730101539469 +mux2,sky90,16,4652,0.21329230696474635,115.640002,41.725,0.04312123817712812 +priorityencoder,sky90,8,8483,0.12521182447247436,64.680001,49.589,0.01462925851703407 +mult,tsmc28,32,2795,0.35777975313059035,3901.212023,26100.0,4.221466905187835 +mux2,tsmc28,8,27245,0.03986398238208846,11.466,61.225,0.0031602128830978157 +mult,sky90,64,619,1.6154428852988691,82141.641305,36600.0,84.04200323101776 +add,sky90,32,2420,0.4132191404958678,1330.840024,582.809,0.5206611570247934 +mux2,sky90,64,4071,0.25437589191844756,466.480009,106.771,0.15131417342176368 +mux2,sky90,1,12288,0.08300820833333333,13.72,12.3,0.00390625 +priorityencoder,sky90,16,5537,0.1802842147372223,126.420002,65.822,0.018945277225934625 +mux8,sky90,1,6114,0.17152604481517827,86.240001,79.616,0.01625776905462872 +comparator,sky90,64,3004,0.33252048069241014,1401.400026,500.904,0.2097203728362184 +mult,tsmc28,64,2581,0.41287172607516465,18964.008028,134000.0,21.443626501356064 +mux8,tsmc28,1,15356,0.06469512529304507,6.804,32.934,0.0018566032821047149 +priorityencoder,sky90,64,4262,0.24266362834350072,888.860015,460.967,0.08305959643359925 +flop,sky90,8,8046,0.11434435918468804,133.279999,64.8145,0.19361794680586625 +mux2d,sky90,1,13482,0.07565897136923305,19.6,18.562,0.006037679869455571 +mux2,sky90,32,10,0.9805759999999992,222.460004,38.896,0.08660000000000001 +add,tsmc28,16,11751,0.08525914049868095,95.382001,501.111,0.03625223385243809 +mux4,sky90,8,4895,0.21053709193054138,164.640002,96.679,0.04439223697650664 +flop,sky90,32,9270,0.11434386515641856,533.119995,259.258,0.7742718446601942 +mux2,sky90,64,4459,0.24442353038797937,564.480008,225.034,0.1910742318905584 +shiftleft,tsmc28,32,10,0.2576830000000001,108.108,362.436,0.0312 +csa,tsmc28,8,25995,0.040894936333910364,50.4,473.705,0.02154260434698981 +csa,tsmc28,64,25014,0.04049261253697929,419.327999,3860.0,0.17346286079795317 +comparator,tsmc28,32,12139,0.08236710865804432,145.782,622.975,0.03567015404893319 +mult,tsmc28,64,2533,0.4110307879984208,19456.542013,137000.0,22.258981444926967 +csa,tsmc28,64,26486,0.040226795514611495,419.327997,3910.0,0.17428075209544666 +comparator,tsmc28,64,10863,0.09205360158335635,281.736,1150.0,0.06526742152259966 +mux8,tsmc28,32,11479,0.08648460240439063,162.288,783.316,0.045648575659900686 +shiftleft,sky90,16,3489,0.3163680759529951,644.840009,367.22,0.18515333906563486 +csa,tsmc28,64,23053,0.04244530217325294,249.984005,1920.0,0.11022426582223571 +mux4,sky90,8,4993,0.2106033925495694,159.740002,79.159,0.04195874223913479 +mux4,tsmc28,128,13613,0.07641319341805627,307.943996,1470.0,0.09696613531183428 +add,tsmc28,64,10,1.836310999999995,135.701998,459.885,0.06620000000000001 +mux2,sky90,128,10,0.9859239999999971,882.000017,273.775,0.41000000000000003 +mux2,sky90,64,4152,0.24532878420038537,472.360009,114.673,0.15221579961464354 +mux2,sky90,128,3576,0.2794420581655481,939.820018,331.591,0.34004474272930646 +mux2,tsmc28,128,16305,0.0613148800981294,190.008,1070.0,0.05636307881018093 +mux4,sky90,16,4392,0.22421770309653916,359.659999,419.855,0.1006375227686703 +shiftleft,sky90,64,2291,0.44757461545176774,3929.800064,2900.0,1.0781318201658665 +comparator,sky90,16,4340,0.2460047465437788,415.520007,287.169,0.08801843317972351 +mux2d,sky90,1,14275,0.07565853940455342,19.6,18.562,0.006038528896672504 +flop,sky90,32,8746,0.11434398307797851,533.119995,259.258,0.7742396524125315 +flop,tsmc28,8,18818,0.04889161005420342,15.12,78.634,0.027231905622276543 +flop,tsmc28,32,22091,0.048891303426734874,60.4799995,314.581,0.1089312389660948 +shiftleft,sky90,16,3221,0.3100215892579944,568.400009,361.777,0.15088481837938528 +flop,tsmc28,16,20045,0.04889175255674732,30.24,157.289,0.05446994262908456 +mux8,tsmc28,16,10,0.1332400000000007,55.314,209.828,0.00977 +add,sky90,64,2011,0.4972310422675286,2600.920051,698.518,0.7419194430631526 +mux4,tsmc28,16,17146,0.06054764084917765,41.454,196.466,0.01294762626851744 +mux2,sky90,64,4046,0.24701768660405338,470.400009,113.216,0.15076618882847256 +mux8,tsmc28,32,12650,0.08457538339920949,166.194,848.034,0.045138339920948616 +mux8d,tsmc28,1,21936,0.045586162654996355,20.664,171.151,0.0066146973012399714 +shiftleft,sky90,32,2654,0.37915475131876414,1722.840029,1260.0,0.48342125094197436 +add,sky90,8,3658,0.27337042810278844,253.820005,154.438,0.10825587752870422 +mult,sky90,32,732,1.366111218579235,22404.76038,10600.0,21.352459016393443 +mult,sky90,16,1077,1.0042961067780873,8138.90015,5900.0,7.317548746518106 +add,sky90,16,3118,0.3282264092366902,736.960014,480.371,0.340602950609365 +shiftleft,tsmc28,8,10,0.12195599999999729,15.624,50.976,0.00468 +shiftleft,sky90,128,2022,0.5271028417408506,10014.620149,7320.0,3.1434223541048465 +shiftleft,sky90,64,2380,0.45773406722689075,3919.020064,2710.0,1.1453781512605041 +add,sky90,64,1968,0.5080270813008131,2562.700049,727.43,0.8257113821138212 +mux4,tsmc28,16,17476,0.06042933211261158,44.603999,221.905,0.013962005035477227 +mux4,tsmc28,16,17805,0.060904998876720025,41.454,205.138,0.012580735748385285 +mult,sky90,64,657,1.5743890152207,91424.201493,51700.0,99.10806697108069 +add,sky90,16,3060,0.33280138562091505,654.640013,402.982,0.30130718954248364 +shiftleft,tsmc28,16,12512,0.083927273657289,133.055999,664.296,0.0356457800511509 +mux8,sky90,16,3499,0.2878559416976279,651.700012,325.896,0.1434695627322092 +mux4,sky90,1,7633,0.12838308777675883,28.420001,22.994,0.006406393292283505 +shiftleft,tsmc28,8,14290,0.06990600629811056,40.95,293.744,0.013638908327501751 +mux8,sky90,1,6349,0.1691041189163648,77.420002,50.656,0.012364151834934636 +priorityencoder,tsmc28,8,31962,0.035221153494775045,9.198,37.469,0.0018521994868906828 +mux4,sky90,8,4709,0.21214331195582928,145.040003,60.946,0.03909534933106817 +shiftleft,sky90,16,3355,0.29803959314456036,666.400006,558.433,0.19552906110283155 +mux4,tsmc28,8,17062,0.05850077611065526,19.53,84.328,0.00568514828273356 +comparator,tsmc28,128,9746,0.10437919741432382,625.338001,2880.0,0.1468294684998974 +add,tsmc28,16,12442,0.08824893039704226,113.274001,694.899,0.04436585757916734 +priorityencoder,tsmc28,64,14632,0.0725743570256971,137.214,427.879,0.017974302897758337 +mux8d,tsmc28,1,23253,0.04558620362963919,20.664,171.151,0.006596998236786652 +mux2,sky90,32,4602,0.21088882746631898,368.480007,245.044,0.13450673620165146 +flop,tsmc28,16,19227,0.048891193998023615,30.24,157.289,0.054465075154730334 +flop,sky90,16,9096,0.11434443447669304,266.5599975,129.629,0.3871481970096746 +flop,sky90,128,8221,0.1143447031991242,2132.4799805,1035.0,3.096338644933706 +mult,tsmc28,8,5000,0.19998100000000002,444.150001,3260.0,0.307 +mult,sky90,16,977,1.0235154534288637,7283.360133,4580.0,6.243602865916069 +flop,tsmc28,128,19636,0.04889186901609289,241.919998,1260.0,0.4356284375636586 +shiftleft,sky90,128,1945,0.5336378174807198,8909.180133,5830.0,2.820051413881748 +comparator,sky90,64,3192,0.3360462080200501,1335.740026,391.156,0.1779448621553885 +mux4,sky90,8,4700,0.2121439574468085,145.040003,64.775,0.03893617021276596 +comparator,sky90,8,4742,0.21876148460565162,196.980003,82.494,0.03829607760438633 +mux2d,tsmc28,1,10,0.029228000000003362,0.882,4.502,0.000264 +flop,tsmc28,64,21682,0.04889120653076284,120.959999,630.0,0.2178535190480583 +mux4d,sky90,1,9895,0.1030771419909045,51.940001,49.18,0.013633148054573016 +flop,tsmc28,32,21682,0.04889120653076284,60.4799995,314.581,0.10892675952402915 +mult,sky90,8,1206,0.8280323963515754,1868.860035,988.885,1.1044776119402984 +priorityencoder,tsmc28,64,12975,0.07704429094412331,114.912,326.132,0.015221579961464355 +mux8,sky90,16,3430,0.2957901895043732,640.920012,234.96,0.12128279883381925 +mux4,sky90,1,7945,0.12749332410320954,28.420001,23.453,0.006419131529263688 +mux2,tsmc28,8,27837,0.039864411287135824,11.466,61.225,0.0031612601932679524 +mult,sky90,64,670,1.561193313432836,92421.841521,53500.0,101.42388059701491 +priorityencoder,tsmc28,8,33842,0.033048081023580166,11.34,48.981,0.002095029844571834 +shiftleft,sky90,8,10,0.705528000000001,130.340003,10.712,0.024439999999999996 +comparator,sky90,128,2737,0.3784935367190354,2763.600053,937.534,0.3624406284252832 +priorityencoder,tsmc28,128,11440,0.0874065874125874,317.646,973.649,0.041171328671328666 +mult,tsmc28,64,2390,0.4184090418410042,16045.092071,109000.0,18.54602510460251 +mux2d,tsmc28,1,54934,0.018931662576910473,3.276,26.574,0.0009265664251647431 +csa,sky90,128,5931,0.1654056314280897,4264.960083,2470.0,2.178553363682347 +csa,sky90,8,5878,0.16847689316093908,282.240005,197.88,0.1439265056141545 +mux4,sky90,16,10,0.5659639999999939,219.520004,14.317,0.049400000000000006 +csa,tsmc28,64,24524,0.040663382319360626,419.327999,3860.0,0.17342195400424076 +mux4,sky90,128,3221,0.31600558925799443,2300.060044,812.053,0.6184414778019248 +shiftleft,sky90,32,2604,0.38592357757296464,1571.920027,1010.0,0.4178187403993856 +shiftleft,tsmc28,64,7611,0.1313867793982394,518.489997,2380.0,0.16371041913020629 +shiftleft,sky90,128,2060,0.5385058932038835,10222.380152,7230.0,3.1378640776699034 +csa,tsmc28,64,24034,0.04077672239327619,395.135998,3790.0,0.17113256220354495 +priorityencoder,sky90,8,8163,0.12799298137939483,56.840001,37.422,0.011674629425456327 +mux2,sky90,64,4112,0.2462356614785992,484.120009,110.88,0.15126459143968873 +priorityencoder,sky90,128,3545,0.30223844710860365,1650.320031,568.632,0.1156558533145275 +mux4,sky90,16,4661,0.2587782347135808,443.940009,202.299,0.10319673889723234 +mux8d,tsmc28,1,10,0.06624600000000669,5.04,17.289,0.001224 +mux2d,sky90,1,14010,0.07565858743754461,19.6,18.562,0.006038543897216275 +mux8,sky90,16,3225,0.30794551937984493,805.560013,497.282,0.18387596899224806 +priorityencoder,tsmc28,8,33216,0.033047973025048166,11.34,48.981,0.0020953757225433524 +mux8,sky90,128,10,1.955451999999994,3207.540062,224.085,0.5810000000000001 +mux8,tsmc28,8,13676,0.07518479555425563,51.281999,237.31,0.013044749926879203 +mult,sky90,16,1037,1.0221291542912248,7597.940137,5000.0,6.758919961427194 +mux2,sky90,8,5723,0.18835053136466887,64.680001,21.541,0.01930805521579591 +flop,tsmc28,32,20454,0.04889119262735895,60.4799995,314.5785,0.10891757113523029 +mux4,sky90,32,3965,0.26433580958385877,694.820013,296.704,0.17225725094577554 +priorityencoder,sky90,8,8323,0.12521198474107895,62.720001,47.365,0.013949297128439266 +mux4d,tsmc28,1,32579,0.030080619233248413,4.158,30.464,0.0012799656220264589 +mux2,sky90,16,5246,0.20207342584826535,119.560002,32.354,0.038810522302706825 +mux2,sky90,128,3684,0.2709390825190011,1077.020021,395.706,0.3564060803474485 +shiftleft,tsmc28,128,6602,0.1514602517418964,1247.021993,5430.0,0.39003332323538326 +mux4,sky90,128,3270,0.3079683975535168,2259.880041,888.365,0.6391437308868501 +add,tsmc28,16,10,0.4766620000000046,32.886,116.238,0.01565 +comparator,sky90,8,4548,0.2197028689533861,190.120003,121.871,0.04243623570800352 +mult,tsmc28,16,3895,0.26150940949935814,1844.136,13600.0,1.5527599486521182 +csa,tsmc28,8,23543,0.04244547041583485,31.248001,240.54,0.013859745996686912 +shiftleft,tsmc28,8,14594,0.06865231012744964,34.398,218.032,0.011299164040016445 +priorityencoder,tsmc28,32,17781,0.06230780653506551,56.826,201.644,0.008762161858163208 +mux2,sky90,64,3908,0.25440036335721594,471.380009,138.856,0.15916069600818833 +flop,sky90,32,8396,0.11434433539780849,533.119995,259.258,0.7741781800857551 +mult,tsmc28,32,2735,0.3656287129798903,3643.290023,23700.0,3.8815356489945154 +shiftleft,tsmc28,8,15810,0.06615910689437064,48.762,352.527,0.016299810246679317 +csa,sky90,32,5638,0.16671386094359703,1160.320023,826.559,0.5954239091876552 +add,sky90,8,3878,0.26842487880350696,273.420005,147.185,0.12325941206807632 +csa,sky90,128,5568,0.17497270114942529,4635.40009,3290.0,2.380387931034483 +mux2,sky90,128,4084,0.2551629823702253,1146.600021,479.203,0.3868756121449559 +mux4,sky90,64,10,1.1701199999999972,834.960016,55.508,0.2097 +priorityencoder,tsmc28,8,30709,0.032285743527955976,8.19,32.782,0.0016770327916897328 +priorityencoder,sky90,16,5773,0.16977016282695304,136.220003,77.243,0.021773774467348 +comparator,tsmc28,128,9559,0.10898145329009311,543.06,2390.0,0.12511769013495136 +priorityencoder,tsmc28,16,22529,0.04496223423143504,30.114,121.215,0.0053974876825425 +mux8,tsmc28,8,12902,0.07750336319950395,44.604,214.286,0.0117501162610448 +shiftleft,sky90,32,2403,0.4160544835622139,1370.040025,695.62,0.3807740324594257 +mult,tsmc28,8,5100,0.19653543137254903,514.458001,3810.0,0.3413725490196079 +comparator,tsmc28,8,10,0.138023000000004,14.994,49.297,0.00345 +comparator,sky90,64,3380,0.3280749881656805,1322.020025,392.984,0.1804733727810651 +mux4,sky90,8,4797,0.20979962309776945,163.660002,93.256,0.043923285386700026 +comparator,sky90,128,2576,0.38793975776397516,2632.280051,550.607,0.3796583850931677 +comparator,tsmc28,8,17763,0.05672979671226708,37.296,188.549,0.00990260654168778 +mux8d,sky90,1,7158,0.13412482788488406,85.260001,40.078,0.015129924559932943 +flop,tsmc28,128,21682,0.04889120653076284,241.919998,1260.0,0.4356378562863204 +shiftleft,tsmc28,128,7023,0.14238329232521713,1836.953994,8670.0,0.566566994162039 +mux8,sky90,32,3305,0.32156986081694405,1068.20002,336.387,0.22208774583963692 +priorityencoder,tsmc28,128,11669,0.08626314628502871,290.808,928.813,0.038906504413403036 +mux2,sky90,64,3870,0.25809293281653745,474.320009,156.263,0.1684754521963824 +flop,tsmc28,32,10,0.048889000000002625,60.4799995,314.5805,0.10908000000000001 +add,tsmc28,64,8206,0.12185605215695831,388.836003,1770.0,0.1409943943456008 +priorityencoder,tsmc28,64,10,0.4980240000000009,55.313999,146.464,0.00796 +mux4,sky90,8,4771,0.2097996646405366,162.680002,90.237,0.04353385034583944 +mult,tsmc28,64,2199,0.45474816007276037,12441.870079,76300.0,13.95543428831287 +flop,sky90,64,9445,0.11434412493382742,1066.23999,520.0,1.5483324510322922 +mult,tsmc28,8,4900,0.20404963265306122,402.318001,2820.0,0.273265306122449 +mux2,sky90,128,4244,0.255888767200754,1307.320024,674.031,0.42412818096135724 +shiftleft,sky90,16,3422,0.30792076797194623,625.240012,393.788,0.1604324956165985 +add,sky90,8,10,1.0608979999999946,103.879999,14.319,0.0376 +mult,sky90,16,937,1.0669988591248665,6421.94011,3210.0,5.136606189967982 +mux8,sky90,8,3800,0.2700248947368421,316.540006,115.77,0.061394736842105266 +csa,sky90,8,10,0.2641830000000027,117.599998,13.811,0.0423 +add,sky90,32,2517,0.4132753710766786,1551.340027,760.812,0.6495828367103694 +mult,sky90,32,717,1.394444139470014,21700.140365,9390.0,18.78103207810321 +mux4,sky90,16,4067,0.24427448512417016,245.000004,71.922,0.07489550036882223 +shiftleft,sky90,8,4500,0.23008222222222222,262.640004,204.113,0.07422222222222222 +mux4,sky90,32,4036,0.26555906937561946,686.980013,310.401,0.1749256689791873 +mux8,tsmc28,64,11014,0.09067453550027238,304.163999,1460.0,0.08498274922825495 +shiftleft,tsmc28,128,6742,0.14831493948383268,1348.955989,6120.0,0.40418273509344405 +comparator,tsmc28,16,14560,0.07291231868131869,65.394,294.431,0.017046703296703294 +shiftleft,sky90,32,2303,0.4341202396873643,1227.940022,465.632,0.30916196265740337 +mux8,tsmc28,1,17359,0.06011100501180944,9.072,57.908,0.002793939743072758 +flop,sky90,8,9096,0.11434443447669304,133.279999,64.8145,0.19359608619173263 +mux8d,tsmc28,1,22814,0.045585734285964755,20.664,171.151,0.006601209783466293 +priorityencoder,tsmc28,32,16793,0.06043762144941345,66.654,245.564,0.01027213720002382 +mux2,tsmc28,16,18767,0.053046021580433735,15.75,88.025,0.005142004582511856 +priorityencoder,tsmc28,8,30082,0.033050470580413535,8.946,35.541,0.0018349843760388273 +mux2d,sky90,1,13217,0.07565913467503972,19.6,18.562,0.006037678747068169 +add,tsmc28,128,7643,0.13338867591259976,1025.51401,5130.0,0.3834881590998299 +mux2,sky90,64,4291,0.24377191004427873,497.840007,137.147,0.1610347238405966 +mux2,tsmc28,32,19336,0.055856004551096405,32.130001,171.146,0.009898634671079851 +shiftleft,tsmc28,32,9587,0.10430391697089808,384.803997,1940.0,0.10180452696359654 +mux8,sky90,8,3370,0.29463590504451037,279.300005,102.669,0.05480712166172106 +mux2,tsmc28,8,30206,0.03374500542938489,16.758,114.743,0.005459180295305568 +priorityencoder,sky90,32,4883,0.2067641359819783,376.320006,232.357,0.04872004915011264 +mux4,tsmc28,16,16486,0.06057952759917506,39.438,186.231,0.012556108213029236 +mux8,tsmc28,128,10055,0.09943300845350571,719.333996,3300.0,0.1648930880159125 +mux4,tsmc28,16,16157,0.06161267809618122,39.06,181.31,0.012428049761713189 +mux8,sky90,128,2613,0.3825318752391887,4084.640077,1310.0,0.8308457711442787 +mux2,sky90,16,5147,0.20207393471925392,119.560002,32.354,0.03891587332426656 +shiftleft,sky90,8,4587,0.22936441225201656,246.960005,191.922,0.06562023108785697 +mux8,tsmc28,128,11312,0.0964546973125884,642.473997,3330.0,0.17494695898161244 +mult,sky90,64,645,1.552430596899225,92630.581541,51300.0,97.67906976744187 +csa,sky90,64,5689,0.16671381683951486,2320.640045,1650.0,1.1935313763403057 +mux4,sky90,32,4042,0.2655582761009401,686.980013,310.401,0.17491340920336468 +mult,tsmc28,32,2854,0.35038242396636304,4257.414022,28900.0,4.601261387526279 +shiftleft,sky90,16,10,0.8858720000000062,350.840007,23.053,0.0551 +mux8,sky90,32,3178,0.3140553102580239,1319.079995,670.683,0.35777218376337316 +flop,sky90,32,10,0.1143419999999935,533.119995,259.258,0.7723000000000001 +add,sky90,32,2323,0.43015783039173483,1235.780024,448.937,0.4567369780456306 +priorityencoder,tsmc28,64,13528,0.07389375694855116,136.584,433.326,0.01848018923713779 +shiftleft,tsmc28,32,8820,0.11336868480725625,202.986,923.446,0.060204081632653055 +mux4,sky90,8,5189,0.2207513594141453,203.840004,102.281,0.046733474657930235 +mux4,sky90,16,4302,0.23042302324500233,358.679999,417.161,0.09972105997210601 +shiftleft,tsmc28,32,9971,0.10217084344599339,306.179999,1470.0,0.08785477885869021 +mux8,tsmc28,128,10683,0.09720766479453338,908.333989,4170.0,0.18440512964523076 +mult,sky90,8,10,2.0858690000000024,1009.399998,188.656,0.28900000000000003 +shiftleft,sky90,16,3624,0.3116181898454746,610.540011,408.291,0.1705298013245033 +csa,tsmc28,128,10,0.06758100000000411,274.175995,917.068,0.1156 +mux2,sky90,64,4100,0.24623543902439024,485.100009,111.924,0.15146341463414634 +mux8,tsmc28,32,11010,0.09082652134423251,200.717998,917.695,0.04695731153496821 +mux2,sky90,8,5405,0.18835087604070305,64.680001,21.541,0.019315448658649398 +mux4,sky90,128,3190,0.31594562382445146,2003.120039,751.54,0.5626959247648903 +add,sky90,16,2765,0.3615926528028933,553.70001,272.075,0.24267631103074144 +add,tsmc28,16,11060,0.09034091320072332,70.434,348.689,0.02631103074141049 +priorityencoder,tsmc28,16,22104,0.04620368041983351,25.956,96.244,0.0045466883821932685 +add,sky90,32,2468,0.40496338573743923,1440.600027,714.057,0.6580226904376014 +priorityencoder,tsmc28,16,19978,0.04995306056662329,17.514,56.066,0.0032535789368305134 +mux2,sky90,16,4949,0.2020740224287735,119.560002,32.354,0.03893715902202465 +comparator,sky90,64,3129,0.31954192361776923,1372.980026,508.393,0.2048577820389901 +mux4,sky90,16,4396,0.22421752684258417,359.659999,419.855,0.10077343039126477 +priorityencoder,tsmc28,32,16464,0.06071258114674442,61.614,207.499,0.009323372206025266 +mux2,tsmc28,32,18978,0.05585559142164612,32.130001,171.146,0.009900937928127306 +priorityencoder,tsmc28,8,31335,0.031912196106590074,8.316,34.836,0.001716929950534546 +priorityencoder,sky90,16,6362,0.1666292756994656,185.220003,132.902,0.03325998113800692 +shiftleft,tsmc28,16,11332,0.08822167596187787,107.603999,530.934,0.03132721496646664 +mult,tsmc28,32,2914,0.3431698991077557,4572.666019,32100.0,4.94818119423473 +mux8,sky90,8,10,0.5354459999999932,234.220005,15.482,0.03289 +comparator,sky90,32,3818,0.27776223415400736,694.820013,315.258,0.10371922472498692 +flop,sky90,8,9445,0.11434412493382742,133.279999,64.8145,0.19358920063525675 +mux4d,sky90,1,9313,0.10687378513905293,53.900001,55.277,0.014087834210243745 +mux4,tsmc28,128,13090,0.07636619404125286,294.335997,1420.0,0.09358288770053477 +priorityencoder,sky90,128,3205,0.31198348049922,1572.900029,499.236,0.10826833073322932 +shiftleft,tsmc28,128,7164,0.14037182300390844,2240.027998,10800.0,0.6394472361809045 +mux8,sky90,8,3298,0.29833006913280774,249.900005,75.262,0.049939357186173434 +mux8,sky90,8,3514,0.28218398178713716,245.980005,77.05,0.04951622083096187 +mux4,sky90,128,3527,0.31660207683583785,2254.980037,793.173,0.6024950382761554 +shiftleft,sky90,128,1907,0.5242938489774515,9192.400136,6080.0,2.9008914525432616 +mult,tsmc28,16,3514,0.2845729817871372,1120.014004,7380.0,1.008537279453614 +csa,sky90,8,5758,0.16536141368530738,266.560005,154.202,0.13650573115665163 +shiftleft,sky90,8,3981,0.25095116754584273,259.700005,172.787,0.07309721175584023 +mux4,sky90,128,3595,0.31559411682892907,2224.600043,699.898,0.5652294853963838 +mux4,sky90,128,3210,0.3111464797507788,1931.580038,685.348,0.5700934579439252 +priorityencoder,sky90,64,4180,0.25021144976076554,817.320015,379.7,0.07320574162679426 +mux4d,sky90,1,10090,0.10307702775024777,51.940001,49.18,0.013637264618434094 +comparator,tsmc28,64,10,0.28591199999999617,134.946,464.047,0.0294 +csa,sky90,64,10,0.2641830000000027,940.799988,110.49,0.3369 +flop,tsmc28,8,21682,0.04889120653076284,15.12,78.635,0.027239184577068535 +mult,tsmc28,128,1756,0.5694750820045558,38955.924167,213000.0,41.384965831435075 +mux2,sky90,32,5303,0.21904050612860645,233.240005,55.502,0.07542900245144259 +priorityencoder,sky90,128,10,2.830100999999999,891.800017,56.107,0.0424 +mux8,tsmc28,16,12264,0.08147446510110894,128.771998,548.714,0.02666340508806262 +shiftleft,tsmc28,64,8438,0.12204549561507466,993.761998,5040.0,0.2788575491822707 +mux4,tsmc28,32,16412,0.06514902607847917,89.837999,413.021,0.025834755057275165 +mux4,sky90,128,3179,0.31437432840515883,1886.500037,637.622,0.5533186536646744 +mux8,tsmc28,64,10133,0.09847845682423764,312.353999,1540.0,0.08516727523931708 +mux2,tsmc28,64,19682,0.0517638447312265,99.036,577.742,0.029976628391423635 +mux8,sky90,1,5409,0.18314205675725645,69.580001,41.904,0.01212793492327602 +mux2,tsmc28,1,47818,0.020583627044209293,2.016,13.728,0.0005876448199422811 +add,tsmc28,64,8862,0.12251134506883322,461.034004,2360.0,0.17659670503272398 +mux4,tsmc28,1,27830,0.038088446999640674,5.292,41.928,0.0017103844771828962 +shiftleft,tsmc28,32,10354,0.10129703148541626,390.725998,1980.0,0.10633571566544331 +mux4,sky90,64,3785,0.2729937926023778,919.240018,338.811,0.2808454425363276 +mux4,tsmc28,128,12566,0.07951181855801369,277.199998,1300.0,0.08952729587776541 +mult,sky90,128,493,2.028396565922921,264363.823149,77300.0,208.79107505070994 +priorityencoder,tsmc28,128,10525,0.09499787648456057,223.902,621.526,0.028883610451306413 +mux4,sky90,128,3459,0.3162518962127782,2229.500043,871.583,0.6551026308181555 +priorityencoder,tsmc28,8,10,0.05780799999999431,4.284,14.558,0.000862 +flop,sky90,128,8571,0.11434450029168125,2132.4799805,1035.0,3.0963131489907827 +comparator,tsmc28,128,9184,0.10887901742160278,507.15,2030.0,0.11378484320557491 +add,tsmc28,16,10599,0.09414852344560808,71.064001,359.005,0.02887064817435607 +mux4,sky90,1,7166,0.13686586491766678,26.460001,19.975,0.005456321518280769 +mux4,sky90,8,10,0.3993300000000062,116.620002,9.077,0.02394 +mux4d,tsmc28,1,33244,0.030080616051016723,4.158,30.464,0.0012811334376128022 +priorityencoder,tsmc28,16,21253,0.04703118086858326,21.672,78.026,0.004008845810003294 +priorityencoder,sky90,8,7843,0.12626623128904757,49.980001,32.378,0.010850439882697946 +mux4,sky90,8,4740,0.2126584641350211,145.040003,62.861,0.03919831223628691 +mux4d,sky90,1,9119,0.1094081470555982,48.020001,46.22,0.013071608729027306 +mux2,tsmc28,64,17082,0.05841015443156539,84.041999,419.594,0.023650626390352418 +mult,sky90,16,997,1.0029260270812437,7519.540137,4940.0,6.376128385155466 +add,sky90,32,2614,0.42499447054322875,1406.300027,636.339,0.598699311400153 +mult,sky90,8,1258,0.794436559618442,1926.680037,1050.0,1.279014308426073 +mux2,sky90,8,5087,0.19261551641438962,70.560001,12.959,0.018812659720857085 +csa,tsmc28,32,23053,0.04244530217325294,124.992002,962.249,0.055133822062204484 +mult,tsmc28,8,10,0.5050959999999947,142.631998,499.628,0.0635 +priorityencoder,tsmc28,32,16134,0.06174490987975703,54.054,163.63,0.008478988471550762 +mux8,tsmc28,64,10,0.24052399999999352,206.513999,803.317,0.0404 +add,sky90,8,3804,0.2758531777076761,257.740005,154.606,0.12381703470031545 +csa,tsmc28,8,25505,0.04036599843168006,50.4,475.36,0.02136835914526563 +mux8d,sky90,1,7903,0.13242722750854108,89.180001,45.284,0.016031886625332153 +mux4,sky90,64,3562,0.28061815665356543,1076.040021,276.31,0.27681078046041546 +mux4d,sky90,1,8925,0.11149681792717087,50.960001,49.104,0.013602240896358544 +mux8,sky90,32,3369,0.3275659833778569,1058.400021,328.34,0.2143069159988127 +flop,sky90,16,8221,0.1143447031991242,266.5599975,129.629,0.38711835543121276 +shiftleft,sky90,64,10,1.4229579999999942,2117.780041,153.751,0.36299999999999993 +flop,sky90,128,9096,0.11434443447669304,2132.4799805,1035.0,3.096470976253298 +mux4,sky90,16,3748,0.26579596478121664,232.260005,65.645,0.0672358591248666 +mux2,tsmc28,8,29614,0.03374481252110488,16.758,114.564,0.005436617815897886 +shiftleft,sky90,128,10,2.072533000000007,4988.200097,311.979,0.956 +priorityencoder,sky90,32,4692,0.21690972975277067,370.440007,198.644,0.04471440750213128 +comparator,sky90,8,5129,0.20861177968414896,224.420003,142.569,0.05790602456619224 +add,sky90,32,2372,0.42075916020236087,1269.100024,537.997,0.5189713322091062 +mux2,sky90,32,5203,0.21903980953296176,237.160005,57.793,0.0768787238131847 +shiftleft,sky90,64,2203,0.45385946391284615,3914.120062,2680.0,1.144802541988198 +mult,tsmc28,8,5401,0.1935488979818552,545.076,3950.0,0.3588224402888354 +mult,sky90,32,809,1.2962689431396788,27029.380482,17800.0,27.053152039555005 +mult,tsmc28,32,3033,0.3295775611605671,6343.721998,47200.0,6.303330036267723 +mux4,sky90,32,10,0.8744200000000006,423.360008,27.792,0.1045 +flop,sky90,64,8746,0.11434398307797851,1066.23999,520.0,1.548364966841985 +flop,tsmc28,16,18818,0.04889161005420342,30.24,157.289,0.05446115421405038 +mux4,sky90,16,4455,0.2231388911335578,392.0,398.313,0.1037037037037037 +priorityencoder,sky90,16,5419,0.18031289223103894,125.440002,50.563,0.018305960509319066 +mult,sky90,64,581,1.721128395869191,68673.500832,21700.0,57.345955249569705 +priorityencoder,sky90,64,4344,0.2409075782688766,890.820015,461.143,0.09231123388581954 +comparator,sky90,64,3067,0.36997951613955005,1251.460024,221.953,0.14150635800456474 +mux2,tsmc28,16,19150,0.05221932114882506,15.75,88.448,0.005159268929503916 +mux8,sky90,1,6232,0.16910413093709886,77.420002,50.656,0.01235558408215661 +priorityencoder,sky90,32,10,0.8791959999999932,196.980004,12.728,0.011870000000000002 +comparator,tsmc28,16,13736,0.07273839778683751,54.558,250.167,0.014349155503785673 +comparator,sky90,8,5032,0.2153801399046105,244.020004,169.251,0.06279809220985691 +comparator,tsmc28,64,11732,0.09292495874531197,284.886,1320.0,0.06657006478008863 +mult,tsmc28,64,10,4.225143000000003,6729.029936,23600.0,6.0600000000000005 +shiftleft,tsmc28,64,8272,0.12086674854932303,1041.263998,5460.0,0.2895309477756286 +csa,sky90,128,6173,0.16536178810950916,5394.900105,3330.0,2.4791835412279286 +mux8,tsmc28,1,16357,0.059911905117075254,7.182,38.342,0.0018878767500152837 +mux8d,tsmc28,1,21059,0.04721963559523244,6.804,34.408,0.0018092027161783562 +mux8d,sky90,1,8052,0.1324277471435668,91.140001,43.658,0.016008445106805762 +mux2,tsmc28,8,29021,0.03376780641604355,16.884,113.726,0.005440887633093278 +comparator,tsmc28,16,10,0.16839600000000132,29.736,97.848,0.0068000000000000005 +add,tsmc28,64,7877,0.12692688523549575,367.920002,1700.0,0.1405357369556938 +mux4,sky90,128,3294,0.3065102707953855,2226.560042,1070.0,0.6715239829993928 +priorityencoder,tsmc28,16,10,0.11891900000000533,10.962,32.132,0.00191 +csa,sky90,8,5518,0.1796730815512867,280.280005,194.202,0.14244291409931137 +mux2,sky90,1,12529,0.08300882959533881,13.72,12.3,0.0039029451672120677 +shiftleft,sky90,8,4674,0.2294615079161318,243.040005,191.378,0.06546854942233632 +mux2,tsmc28,16,19916,0.0524708857200241,15.372,84.373,0.005046194014862422 +flop,sky90,128,8046,0.11434435918468804,2132.4799805,1035.0,3.0963211533681334 +add,tsmc28,8,13007,0.07612567909587145,30.366,161.839,0.011855154916583378 +mult,sky90,16,10,5.005561999999998,3869.040009,641.517,1.6879999999999997 +comparator,tsmc28,64,10428,0.09588966551591867,260.82,1030.0,0.05974299961641734 +mux2,sky90,32,5003,0.19908807195682593,375.340008,259.372,0.13671796921846893 +mult,tsmc28,16,10,1.0536270000000059,539.405992,1830.0,0.368 +priorityencoder,tsmc28,64,12699,0.07861935798094338,104.706,306.577,0.01392235609103079 +mux2,sky90,1,13011,0.08300904319422028,13.72,12.3,0.0039043885942663895 +mult,sky90,128,555,1.9449018018018018,305166.124288,139000.0,316.31891891891894 +mux2,sky90,16,4850,0.20207356701030926,119.560002,32.354,0.03884536082474227 +shiftleft,sky90,8,4327,0.23025600254217704,259.700005,196.451,0.07534088282874972 +comparator,tsmc28,8,18105,0.058020360950013804,35.154,195.216,0.00964374482187241 +mux8,sky90,1,5879,0.16984595526450078,75.460001,60.639,0.014237115155638714 +comparator,sky90,64,10,1.1199110000000019,1008.42002,127.626,0.0831 +priorityencoder,sky90,32,4405,0.22696975595913735,348.880006,159.17,0.040794551645856984 +mux8,sky90,64,3088,0.3305971968911917,2143.260041,777.3,0.4740932642487046 +mux2,sky90,8,5511,0.18835127127563056,64.680001,21.541,0.019306840863727092 +mult,tsmc28,16,3590,0.2785115320334262,1216.278005,8230.0,1.1376044568245125 +mux2,sky90,128,3728,0.26636334334763945,934.920018,235.084,0.3076716738197425 +flop,tsmc28,8,19227,0.048891193998023615,15.12,78.634,0.027232537577365167 +mux2,sky90,1,12047,0.08300821781356355,13.72,12.3,0.003909687059018843 +priorityencoder,tsmc28,16,19553,0.05112504710274639,17.136,56.184,0.003283383623996318 +mux8,tsmc28,128,10,0.39436299999999846,411.011997,1610.0,0.0853 +add,sky90,128,1810,0.552345187845304,5897.640112,1960.0,1.8342541436464088 +mux2,sky90,16,10,0.6069949999999977,113.680002,19.729,0.0386 +mux2,sky90,16,5345,0.20207373900841907,119.560002,32.354,0.03889616463985033 +mult,sky90,8,1284,0.778472199376947,2067.800038,1220.0,1.2710280373831777 +mux4d,sky90,1,10478,0.10307706069860662,51.940001,49.18,0.013638098873830882 +mux4,sky90,16,4411,0.22421796236681027,359.659999,419.855,0.10088415325323055 +shiftleft,sky90,64,2027,0.492941911198816,2849.840051,1050.0,0.6729156388751849 +csa,tsmc28,32,26486,0.040226795514611495,209.663999,1960.0,0.08717813184323794 +mux4,tsmc28,128,12828,0.07792147458684127,296.603998,1450.0,0.09588400374181479 +flop,tsmc28,128,18818,0.04889161005420342,241.919998,1260.0,0.43562015091933254 +mux2,tsmc28,8,10,0.08170300000000452,7.56,38.026,0.00241 +flop,sky90,16,8571,0.11434450029168125,266.5599975,129.629,0.3871193559677984 +mux2,sky90,64,4020,0.25170921890547265,533.119997,224.115,0.2 +mux8d,tsmc28,1,21498,0.04628595497255559,17.514,137.759,0.005730765652618848 +priorityencoder,sky90,16,5655,0.1753866595932803,133.280002,84.414,0.020176834659593284 +mux2,tsmc28,64,17454,0.057247457087200644,79.254,433.639,0.023719491234101067 +mux4,sky90,128,2914,0.34151589910775565,1962.940038,488.841,0.5243651338366507 +comparator,sky90,32,3602,0.276293542476402,690.900013,315.709,0.10771793448084398 +add,sky90,128,1960,0.5343460816326531,6824.72013,2820.0,2.4168367346938777 +mux8d,tsmc28,1,23691,0.04558612198725254,20.664,171.151,0.006631210164197375 +mux2,tsmc28,8,31983,0.03374461038676797,16.758,114.743,0.0054497701904136575 +mux4,sky90,128,3120,0.32006682051282054,2008.020039,557.55,0.5423076923076923 +mux2,sky90,64,3745,0.26633369692923897,459.620009,146.5,0.16555407209612816 +mux2,sky90,32,4802,0.20550356393169514,369.460007,247.031,0.13473552686380677 +shiftleft,tsmc28,128,7585,0.14153315622940013,2560.949989,13000.0,0.7444957152274226 +comparator,sky90,64,3255,0.32338666205837174,1354.360026,436.796,0.18525345622119815 +mux2,tsmc28,16,20299,0.0524705105177595,15.372,84.373,0.005039657125966796 +shiftleft,tsmc28,8,16418,0.06592875867949811,61.488,451.858,0.02028261664027287 +shiftleft,sky90,64,2159,0.4631083969430292,3537.800054,2160.0,1.0490968040759612 +mux4,tsmc28,1,28355,0.038088148651031564,5.292,41.928,0.0017069299947099275 +add,sky90,64,2225,0.466599202247191,2894.920056,1040.0,0.9842696629213483 +csa,tsmc28,16,10,0.06758100000000411,34.271999,114.459,0.014410000000000001 +comparator,sky90,128,2898,0.39185256245686684,2667.560051,751.018,0.31573498964803315 +comparator,tsmc28,64,10211,0.09791160101850946,246.708,1010.0,0.057389090196846536 +mux4,tsmc28,64,10,0.17948199999999304,106.847999,391.422,0.027700000000000002 +mux2,sky90,128,4108,0.25670645861733205,1104.460019,443.391,0.37000973709834467 +priorityencoder,tsmc28,64,14356,0.07864628615213151,128.268,410.848,0.01699637782112009 +mux8d,sky90,1,7456,0.13268717167381974,88.200001,42.371,0.01636266094420601 +mux2,sky90,32,5103,0.2190401589261219,237.160005,57.793,0.07681755829903977 +mux8,tsmc28,16,12999,0.07783899453804138,166.823999,864.695,0.033387183629509966 +comparator,tsmc28,32,11410,0.08759541893076249,133.056,523.589,0.03242769500438212 +add,tsmc28,128,7499,0.13434411348179756,1029.54601,5030.0,0.3831177490332045 +mult,sky90,16,957,1.044805079414838,6996.220129,4080.0,5.647857889237199 +csa,sky90,8,5998,0.16669324074691563,332.220006,234.084,0.17305768589529844 +csa,sky90,16,5689,0.16671381683951486,580.160011,413.956,0.2984707329934962 +add,tsmc28,128,6922,0.1444319170759896,814.212006,3770.0,0.3185495521525571 +flop,sky90,64,8046,0.11434435918468804,1066.23999,520.0,1.5482848620432514 +mux8,sky90,32,3115,0.32077628731942215,1099.560021,345.681,0.20513643659711076 +mult,sky90,16,1017,1.006137169124877,7719.460138,5170.0,6.812192723697148 +comparator,tsmc28,128,9933,0.10677251927917045,498.834,2190.0,0.1120507399577167 +add,sky90,16,2824,0.35254064872521246,562.520011,272.42,0.22839943342776206 +mux2,sky90,128,4324,0.2587083450508788,1099.560018,533.373,0.3878353376503238 +mux4,tsmc28,8,16699,0.05960982537876519,20.16,94.804,0.005976405772800767 +comparator,tsmc28,8,16738,0.0595542944198829,34.524,177.167,0.009355956506153663 +mux4,sky90,128,3168,0.3155825656565656,1988.420039,716.011,0.5792297979797979 +comparator,sky90,32,3458,0.2884604997108155,709.520014,223.226,0.0948525159051475 +csa,sky90,64,6537,0.1653613709652746,2947.840057,1740.0,1.271837234205293 +mux2,tsmc28,64,18939,0.05314609826284387,84.797999,432.492,0.023971698611331114 +mux2,sky90,64,10,0.9630970000000048,444.920009,77.207,0.168 +flop,tsmc28,8,10,0.048889000000002625,15.12,78.6345,0.027246000000000003 +comparator,tsmc28,8,17422,0.05733769130983814,35.784,170.595,0.009488003673516243 +flop,tsmc28,8,20864,0.048891447852760735,15.12,78.634,0.02723590874233129 +mult,tsmc28,128,1868,0.5353279057815846,44272.49428,262000.0,50.01177730192719 +add,sky90,128,10,13.960425999999998,1867.879976,221.488,0.653 +mux2,tsmc28,64,10,0.18685899999999833,56.826002,290.226,0.02082 +flop,sky90,32,8046,0.11434435918468804,533.119995,259.258,0.7741735023614218 +priorityencoder,tsmc28,8,28829,0.03459129404419161,6.174,23.212,0.0013423982795102154 +mux2d,tsmc28,1,49652,0.019658175622331426,2.142,15.112,0.0006021912511077097 +mux2,sky90,32,4150,0.23922785542168676,230.300004,85.432,0.08602409638554216 +mux8d,sky90,1,6859,0.1408138474996355,110.740002,89.514,0.024901589152937748 +mux8,tsmc28,128,10893,0.09798407472688883,830.591987,3990.0,0.1872762324428532 +csa,sky90,16,6537,0.1653613709652746,736.960014,439.259,0.31910662383356275 +mult,sky90,128,482,2.0746737966804982,251002.502634,63000.0,174.44190871369292 +mux8,sky90,32,3051,0.32773938970829236,1253.419994,557.88,0.3352999016715831 +mux2,sky90,1,11806,0.08300869354565475,13.72,12.3,0.0038963239031001187 +priorityencoder,sky90,128,3409,0.2933331557641537,1602.300031,610.009,0.1261366969785861 +mux2,tsmc28,32,16471,0.060023767895088335,29.484001,155.318,0.009586546050634446 +mux2,sky90,8,5193,0.19048991700365878,59.780001,16.177,0.01919892162526478 +mux2,sky90,64,4038,0.24874735017335314,475.300009,113.443,0.15156017830609214 +mux4,sky90,16,4469,0.23470170552696354,411.600005,351.781,0.09599462967106737 +add,sky90,64,2182,0.463233142071494,2916.480057,1140.0,1.0664527956003667 +mux2,sky90,1,11083,0.08482327754218172,11.76,9.281,0.0037264278624921056 +mux8,tsmc28,1,18027,0.06011034703500305,9.072,57.908,0.0027958062905641535 +mux4d,tsmc28,1,35239,0.029485649763046625,6.426,53.388,0.0019552200686739126 +mux4,sky90,8,4847,0.21051618341242007,160.720002,75.759,0.04120074272746029 +mux8,sky90,64,3269,0.3220959461609055,2250.080042,750.807,0.4717038849801162 +flop,tsmc28,64,18818,0.04889161005420342,120.959999,630.0,0.21784993091720692 +flop,tsmc28,128,21273,0.0488919443425939,241.919998,1260.0,0.43564612419498894 +mult,tsmc28,64,2247,0.44503082821539836,13239.198086,83600.0,15.089452603471296 +mux4,sky90,8,4754,0.2126581796381994,145.040003,62.861,0.03910391249474127 +mux2,sky90,64,4060,0.24566741871921183,514.50001,165.954,0.16403940886699508 +mux4d,tsmc28,1,31250,0.03008,4.158,30.468,0.00128192 +shiftleft,tsmc28,128,10,0.6244959999999935,621.683997,1970.0,0.22 +comparator,sky90,128,2844,0.3556604402250352,2858.660053,1040.0,0.37095639943741204 +flop,tsmc28,32,18818,0.04889161005420342,60.4799995,314.5785,0.10892230842810076 +mux4,sky90,128,3421,0.30357918941829876,2183.440041,857.282,0.6033323589593687 +add,sky90,128,2036,0.5260351355599214,6531.700127,2540.0,2.2264243614931236 +mult,sky90,8,1415,0.7822477809187279,2212.840039,1440.0,1.542049469964664 +mult,tsmc28,64,2294,0.43591579075850045,14614.866081,95200.0,16.97384481255449 +mux4,tsmc28,64,14762,0.06852549844194553,305.42399,1370.0,0.07119631486248477 +flop,tsmc28,8,22091,0.048891303426734874,15.12,78.635,0.027239599837037706 +mux4,sky90,64,3859,0.3036454908007256,1512.140028,861.823,0.411764705882353 +flop,sky90,32,9445,0.11434412493382742,533.119995,259.258,0.7742191635786131 +mux8,sky90,1,5526,0.17846672167933406,70.560001,50.725,0.014115092290988058 +mux8,tsmc28,16,12018,0.08288952055250458,91.728,436.205,0.025212181727408887 +flop,sky90,8,10,0.1143419999999935,133.279999,64.8145,0.193835 +mux8,tsmc28,8,10,0.11437999999999704,30.114,111.042,0.00512 +add,sky90,32,2275,0.4382754395604396,1143.660022,372.681,0.43208791208791214 +mux4,sky90,1,8257,0.12749336175366355,28.420001,25.098,0.006479350853821 +csa,tsmc28,16,24034,0.04077672239327619,98.783999,946.879,0.04289756178746776 +mux8,sky90,64,2967,0.34396478193461405,1982.540038,605.952,0.3788338388945063 +mult,sky90,16,917,1.0904565408942202,6101.480106,2770.0,4.877862595419847 +csa,tsmc28,16,23543,0.04244547041583485,62.496001,481.11,0.027609055770292656 +add,sky90,16,2707,0.3688706339120798,554.68001,193.792,0.23125230882896194 +mult,tsmc28,16,4048,0.25795957312252965,1922.886,14300.0,1.6385869565217392 +mux2,tsmc28,1,53922,0.01965830618300508,2.142,15.112,0.0006008679203293645 +mux2d,tsmc28,1,51765,0.01893207205640877,3.276,26.574,0.000927267458707621 +shiftleft,sky90,128,1755,0.5695325698005698,7463.680134,3390.0,1.932763532763533 +mult,tsmc28,64,2342,0.4269854824935952,15405.390085,103000.0,17.771562766865927 +mux2d,sky90,1,12953,0.0756591925422682,19.6,18.562,0.006029491237551147 +mux4d,tsmc28,1,35904,0.02948604991087344,6.426,53.388,0.0019579991087344028 +mult,tsmc28,64,2438,0.41469727235438886,17618.832028,122000.0,20.132895816242826 +csa,tsmc28,16,23053,0.04244530217325294,62.496001,481.11,0.02763197848436212 +mux2,tsmc28,32,17903,0.05585556035301346,32.130001,171.146,0.009897782494553985 +mult,tsmc28,128,2017,0.521343820525533,50239.728229,312000.0,57.93257312840853 +priorityencoder,sky90,16,6126,0.16939465491348352,166.600002,113.104,0.028778974861247145 +csa,tsmc28,16,24524,0.040663382319360626,104.832,964.99,0.04346762355243842 +mux2,tsmc28,32,18619,0.05585557725978839,32.130001,171.146,0.009898490788979 +comparator,tsmc28,32,12867,0.08809919382917542,147.924,654.69,0.035672650967591514 +mux4,tsmc28,32,14588,0.06829549273375377,76.103999,363.48,0.02495201535508637 +flop,tsmc28,64,21273,0.0488919443425939,120.959999,630.0,0.21783481408358013 +add,sky90,64,2054,0.48669491723466407,2674.420052,957.825,0.952288218111003 +mult,tsmc28,16,3972,0.2571083363544814,2139.101998,16200.0,1.7797079556898288 +mult,sky90,128,566,1.9132164522968198,301979.16406,136000.0,308.3144876325089 +mux4,sky90,32,4118,0.24283532831471588,594.860011,331.197,0.131617289946576 +mux4,sky90,16,4471,0.2374716099306643,392.980007,336.716,0.09349138895101766 +shiftleft,tsmc28,128,7304,0.14135928148959476,2368.547985,11900.0,0.6592278203723987 +mult,tsmc28,8,4700,0.21274895744680852,334.404002,2220.0,0.22914893617021276 +mux8,sky90,16,3156,0.31606278073510774,523.32001,180.283,0.10963244613434726 +flop,tsmc28,32,21273,0.0488919443425939,60.4799995,314.5805,0.10892210783622433 +mult,sky90,32,702,1.4242284245014245,19874.400305,7550.0,16.801994301994302 +shiftleft,sky90,128,1869,0.5349974788657036,8478.960135,5130.0,2.594970572498662 +mux4,sky90,16,3907,0.2556648574353724,232.260005,65.86,0.0664704376759662 +comparator,sky90,128,2683,0.37266110771524413,2825.340055,784.95,0.462541930674618 +mux8,sky90,32,2924,0.34153726402188783,1064.280021,239.507,0.19220246238030098 +mux8d,sky90,1,7307,0.1341250704803613,85.260001,40.078,0.01506774325988778 +mux4,sky90,8,5034,0.2207511855383393,203.840004,102.281,0.0467222884386174 +priorityencoder,sky90,128,3682,0.28672152634437803,1864.940032,910.869,0.1719174361759913 +mult,sky90,128,10,29.683678,180759.040854,18000.0,78.1 +mult,sky90,128,545,1.924225385321101,300240.644153,129000.0,302.308256880734 +mux4,sky90,8,4474,0.22174063433169425,122.500002,39.907,0.03520339740724184 +shiftleft,sky90,64,2115,0.47275823877068557,3320.240051,2040.0,0.9394799054373523 +flop,sky90,16,9270,0.11434386515641856,266.5599975,129.629,0.38710895361380804 +mux4,tsmc28,1,24155,0.0400992962119644,2.898,17.89,0.0008818050093148417 +mux4,tsmc28,16,15827,0.06317816800404372,33.894,142.636,0.010412586087066406 +mux4,sky90,128,3104,0.32191194845360827,2060.94004,567.296,0.5341494845360825 +flop,sky90,64,8396,0.11434433539780849,1066.23999,520.0,1.5482968080038113 +comparator,tsmc28,8,17080,0.058468009367681505,32.256,148.439,0.008588992974238877 +mux2,sky90,64,4008,0.249340998003992,509.600006,173.87,0.17190618762475052 +mux8,tsmc28,16,12754,0.07864877434530344,105.21,501.447,0.027755998118237413 +comparator,sky90,16,4099,0.2462409419370578,410.620007,284.523,0.08587460356184434 +mux4,sky90,8,4504,0.22543886678507993,168.560003,60.445,0.04054174067495559 +mux4,tsmc28,64,13648,0.07299580890973037,141.623999,661.956,0.04645369284876905 +mult,sky90,128,503,1.9880695705765408,271535.463355,88700.0,235.36978131212723 +priorityencoder,tsmc28,8,32589,0.03304820052778545,11.592,49.654,0.002138758476786646 +mux8,tsmc28,64,11455,0.09107112309035356,312.353999,1550.0,0.0857267568747272 +mux4,sky90,128,3291,0.3176560094196293,2053.100039,760.125,0.5870556061987238 +mux4,sky90,128,3232,0.3149519405940594,2190.300041,889.429,0.651299504950495 +flop,tsmc28,8,20045,0.04889175255674732,15.12,78.634,0.0272362185083562 +mux8d,tsmc28,1,22375,0.0455857374301676,20.664,171.151,0.0066100558659217875 +mux8,tsmc28,8,12128,0.08243582585751978,41.706,181.866,0.010183047493403694 +comparator,sky90,32,3386,0.2947787271116361,655.620013,173.527,0.0767867690490254 +add,tsmc28,128,6777,0.14755591648221927,813.960006,3780.0,0.3209384683488269 +csa,sky90,128,6052,0.16536163317911434,5269.460103,3280.0,2.4631526768010574 +csa,sky90,8,6118,0.16536210853220007,330.260006,208.877,0.15495259888852567 +mult,sky90,32,778,1.2898160437017996,26921.580481,17200.0,26.807197943444734 +add,tsmc28,32,9812,0.1018860211985324,209.286002,1060.0,0.08153281695882594 +mux4,sky90,32,3508,0.28452071379703536,449.820009,129.665,0.13768529076396807 +mux4,sky90,64,3636,0.27624650275027507,889.840016,304.841,0.2714521452145215 +comparator,sky90,16,4018,0.24806303982080635,358.680007,189.253,0.06321553011448482 +mux8,sky90,1,5761,0.17009697552508246,70.560001,49.874,0.01256726262801597 +mux2,sky90,32,5403,0.21904036165093466,233.240005,55.502,0.07551360355358135 +shiftleft,tsmc28,128,7445,0.14241033445265278,2676.617983,13800.0,0.7658831430490262 +mux2,tsmc28,1,48835,0.01965811682195147,2.142,15.112,0.0006020272345653731 +mux4,sky90,16,4306,0.2304230919647004,358.679999,417.161,0.09962842545285648 +mux8,tsmc28,128,10264,0.09738990335151988,700.937992,3100.0,0.16017147310989868 +csa,sky90,32,6118,0.16536210853220007,1318.100026,832.166,0.6181758744687806 +comparator,tsmc28,16,14285,0.07632350017500876,54.054,235.74,0.013860693034651733 +mux2,tsmc28,16,18384,0.053569126196692775,15.246,84.024,0.0050641862489120976 +mux2d,sky90,1,12424,0.07841937540244688,18.62,16.576,0.005924018029620091 +mux4,tsmc28,64,13091,0.07627735841417768,132.551999,603.132,0.04529829653960736 +mux8,tsmc28,8,13418,0.07609875510508272,46.368,224.828,0.012132955731107469 +mult,tsmc28,16,3666,0.2727758685215494,1281.546006,8860.0,1.188761593016912 +add,tsmc28,64,8370,0.11969531302270012,439.488003,2130.0,0.16439665471923534 +mux4,tsmc28,8,18877,0.05756651925623775,22.302,111.045,0.006383429570376648 +flop,sky90,128,8396,0.11434433539780849,2132.4799805,1035.0,3.0962958551691284 +mux8,sky90,1,5644,0.1749683054571226,70.560001,47.501,0.012331679659815733 +comparator,sky90,16,4259,0.24596490068091104,414.540007,269.17,0.08499647804648978 +mux4,sky90,16,4514,0.22817500841825433,462.560009,352.002,0.11541869738591051 +mux4,sky90,128,3041,0.32867219763235783,1891.400037,563.999,0.5004932587964486 +comparator,sky90,16,3697,0.2704605861509332,354.760007,114.334,0.05923721936705437 +comparator,tsmc28,32,12624,0.08578519518377693,146.412,662.137,0.035487959442332066 +comparator,tsmc28,32,11168,0.08951854727793697,114.408,448.212,0.027489255014326645 +priorityencoder,sky90,32,4788,0.21353147201336675,384.160007,267.54,0.052631578947368425 +priorityencoder,sky90,128,3614,0.30526071555063644,1695.400033,611.905,0.13198671831765357 +mux4,tsmc28,32,13981,0.07113564194263644,68.04,282.367,0.020813961805307205 +mux4,sky90,8,4381,0.22772738849577723,120.540002,34.353,0.03362246062542799 +mux4,tsmc28,32,15500,0.06548612903225806,73.961999,360.628,0.024322580645161292 +mux2d,sky90,1,13746,0.07565843590862796,19.6,18.562,0.006030845336825259 +mux2,tsmc28,64,20053,0.05297485019697801,87.318,456.882,0.024634717997307137 +csa,sky90,128,6537,0.1653613709652746,5895.680115,3510.0,2.548569680281475 +mux4,sky90,1,7789,0.12838318564642445,28.420001,22.994,0.006406470663756579 +mux8,sky90,64,2846,0.35130134434293747,2092.30004,580.155,0.392832044975404 +csa,tsmc28,32,10,0.06758100000000411,68.543999,229.117,0.028800000000000003 +mult,sky90,8,1363,0.7637627153338225,2251.060042,1540.0,1.5766691122523844 +priorityencoder,tsmc28,32,15476,0.06460917989144482,52.164,168.016,0.008516412509692426 +add,tsmc28,32,10008,0.10399206394884093,207.900002,1070.0,0.08363309352517985 +priorityencoder,sky90,16,6008,0.16939474034620508,166.600002,115.018,0.029061251664447403 +mux8d,tsmc28,1,20620,0.04721960523763336,6.804,34.356,0.0018234723569350146 +shiftleft,tsmc28,8,13986,0.0711090715000715,27.468,148.616,0.008336908336908337 +mux4d,tsmc28,1,10,0.044273000000004004,2.268,8.147,0.000485 +csa,tsmc28,128,23053,0.04244530217325294,499.96801,3850.0,0.2204919099466447 +mux2,sky90,32,4450,0.2224351011235955,230.300004,63.574,0.07730337078651685 +add,tsmc28,16,11521,0.08678002100512108,90.972001,475.207,0.03367763214998698 +priorityencoder,sky90,64,4016,0.248852984063745,788.900013,356.748,0.07246015936254982 +shiftleft,sky90,32,2453,0.40740408479412965,1381.800025,768.035,0.3530370974317163 +csa,sky90,8,6358,0.16398216420257944,392.000008,245.798,0.1818181818181818 +add,tsmc28,8,10,0.25532499999999914,15.75,58.809,0.007129999999999999 +shiftleft,tsmc28,32,9779,0.10537294477962983,359.604,1700.0,0.09990796604969833 +mux2,sky90,32,3850,0.2503912597402597,226.380004,76.383,0.08337662337662337 +comparator,tsmc28,32,10,0.21334099999999978,64.26,218.094,0.01492 +mux2,sky90,64,4141,0.2484585633904854,479.220009,102.601,0.1504467519922724 +csa,sky90,16,6052,0.16536163317911434,659.540013,409.513,0.30799735624586916 +mux2d,tsmc28,1,53878,0.01893245139017781,3.276,26.574,0.0009280225695088904 +priorityencoder,tsmc28,32,10,0.24741400000000624,25.326,69.772,0.003940000000000001 +add,tsmc28,32,10204,0.10141978400627205,225.792002,1180.0,0.08653469227753822 +mux2,sky90,32,4000,0.246172,228.340004,80.334,0.08449999999999999 +mux2,tsmc28,128,15639,0.06391170733422853,145.782001,1020.0,0.05204936377006203 +add,tsmc28,16,11981,0.08588248702111677,95.886001,511.735,0.03722560721141808 +mux2,tsmc28,16,20682,0.05247022328594913,15.372,84.373,0.005043032588724495 +csa,sky90,16,6173,0.16536178810950916,675.220013,421.312,0.31119390895836707 +flop,sky90,8,8571,0.11434450029168125,133.279999,64.8145,0.1936355151090888 +comparator,sky90,64,2879,0.3470918273706148,1519.98003,422.272,0.21778395276137547 +mux4,tsmc28,64,15041,0.07022094116082707,145.277999,710.673,0.047337278106508875 +mux4,sky90,32,3789,0.26225787912377935,459.620009,152.167,0.1419899709685933 +add,tsmc28,8,14114,0.07275363667280714,35.028001,197.931,0.0138869207878702 +add,tsmc28,128,7354,0.13597341881968997,907.452008,4360.0,0.3451183029643731 +mux8,tsmc28,128,11102,0.09522286056566384,640.079998,3170.0,0.17096018735362997 +add,tsmc28,128,7066,0.1415187851684121,858.942007,3940.0,0.3235210868949901 +comparator,sky90,64,3317,0.3259782384684956,1324.960026,375.296,0.17244498040397951 +shiftleft,tsmc28,8,14898,0.06690610377231844,51.912,383.207,0.018042690293999193 +priorityencoder,tsmc28,128,10,0.9983220000000017,114.533999,291.024,0.01597 +mux4,tsmc28,1,26780,0.0380882994772218,5.292,41.928,0.0017102315160567587 +comparator,tsmc28,16,13186,0.07577501001061733,47.754,197.671,0.012619444865766721 +mux2,sky90,64,3994,0.24961056334501755,479.220007,139.961,0.16399599399098647 +add,sky90,64,10,7.080673000000004,927.079988,110.998,0.3249 +flop,sky90,32,8221,0.1143447031991242,533.119995,259.258,0.774175891010826 +comparator,sky90,8,4839,0.20629126741062204,200.900004,136.6,0.05001033271337053 +comparator,tsmc28,8,16397,0.06087376587180582,27.846,124.214,0.007355003964139782 +csa,sky90,64,6173,0.16536178810950916,2697.940053,1670.0,1.2418597116474974 +mult,tsmc28,8,4600,0.2172923043478261,316.512001,2070.0,0.21195652173913043 +mux2,sky90,64,4207,0.2429750729736154,517.44001,134.725,0.157594485381507 +shiftleft,sky90,64,2071,0.4824885224529213,3215.380053,1760.0,0.8614196040560116 +shiftleft,sky90,16,3557,0.297124788585887,608.58001,422.656,0.15434354793365193 +mux8,tsmc28,1,17025,0.06011015124816446,9.072,57.908,0.0027958883994126287 +shiftleft,tsmc28,8,15506,0.06589716471043468,44.856,300.094,0.014413775312782148 +flop,sky90,64,8921,0.11434405660800359,1066.23999,520.0,1.5483690169263535 +priorityencoder,tsmc28,16,21678,0.04626771676353907,23.688,87.326,0.00417935233877664 +mux4,tsmc28,8,18514,0.055939179215728635,24.066,117.217,0.007232364696986064 +mux8,tsmc28,64,11895,0.08861193652795293,585.647993,2900.0,0.11197982345523327 +comparator,tsmc28,128,8996,0.11113551578479325,480.438,1900.0,0.10704757670075589 +mux4,sky90,64,4007,0.2932652642874969,1421.980024,895.196,0.35338158223109556 +mux4d,tsmc28,1,34574,0.0294854685023428,6.426,53.388,0.0019581188176086076 +csa,sky90,128,5689,0.16671381683951486,4641.28009,3300.0,2.386183863596414 +priorityencoder,sky90,16,5890,0.1697722869269949,136.220003,75.053,0.020950764006791172 +mux4,tsmc28,1,25730,0.0384481379712398,4.158,30.449,0.0012922658375437233 +mux4,sky90,16,4146,0.251916333815726,245.000004,80.791,0.06343463579353595 +mux4,sky90,16,4545,0.26359700220022003,358.680007,100.453,0.07942794279427942 +csa,sky90,32,6478,0.16536163229391787,1499.400029,862.282,0.6336832355665329 +mux2,sky90,64,4073,0.24517727326295113,479.220009,115.22,0.15148539160324087 +csa,sky90,32,6358,0.16398216420257944,1568.000031,983.19,0.7239698018244731 +flop,sky90,64,10,0.1143419999999935,1066.23999,520.0,1.54955 +flop,sky90,16,9445,0.11434412493382742,266.5599975,129.629,0.38713605082054 +csa,tsmc28,128,25014,0.04049261253697929,838.655998,7720.0,0.34720556488366516 +mux8,sky90,64,10,1.3133009999999956,1610.140031,110.909,0.27999999999999997 +add,sky90,16,2942,0.3393218266485384,722.260013,485.109,0.32460910944935417 +comparator,tsmc28,128,9371,0.10671119720414043,558.432,2400.0,0.12794792444776437 +mux8,sky90,64,2785,0.3587524272890485,2023.700038,635.117,0.40430879712746853 +mux4,tsmc28,32,14892,0.066647147730325,77.238,364.152,0.025248455546602204 +shiftleft,tsmc28,32,9396,0.10641326734780758,311.723998,1470.0,0.08343976160068114 +mux8,tsmc28,32,10776,0.09256081217520415,171.989999,780.419,0.04101707498144023 +mux2,sky90,64,4122,0.248458679281902,479.220009,106.14,0.15138282387190685 +priorityencoder,sky90,128,3136,0.31840255102040815,1579.760031,453.063,0.10427295918367345 +mux8,sky90,32,2987,0.33436006427854037,1412.180011,763.713,0.34181452962838965 +mux8,sky90,16,3568,0.2891280582959641,618.380012,225.209,0.12780269058295965 +mux4,sky90,128,3280,0.3066450487804878,2166.780041,981.943,0.6625 +mux8,tsmc28,16,11773,0.08486411721736176,83.664,357.291,0.021404909538775163 +add,tsmc28,128,6633,0.15075334479119554,792.414006,3640.0,0.3086084727875773 +mux4,tsmc28,8,17788,0.05615667483696874,23.814,113.824,0.007252080053968968 +add,sky90,32,2565,0.41661854775828455,1395.520026,647.273,0.5734892787524366 +csa,tsmc28,128,26486,0.040226795514611495,838.655994,7830.0,0.3485615041908933 +mux8,sky90,128,2773,0.36877026685899744,4476.640087,1520.0,0.8755860079336458 +mux2,tsmc28,64,18196,0.05494513343591998,83.285999,419.089,0.023411738843701915 +priorityencoder,sky90,64,3934,0.2539222043721403,760.480014,316.203,0.06507371631926792 +priorityencoder,tsmc28,128,12126,0.08674642536698005,321.048001,1060.0,0.04395513772060037 +mult,tsmc28,32,3211,0.33017946122703207,6265.475998,46700.0,6.259732170663345 +csa,sky90,128,10,0.2641830000000027,1881.599976,220.98,0.675 +mux4,sky90,16,3987,0.2507101492350138,273.420005,78.903,0.07123150238274392 +mux4,sky90,32,4365,0.2416230744558992,755.580015,452.834,0.1628865979381443 +mult,tsmc28,128,1793,0.5577244841048522,40469.058207,229000.0,43.65476854433909 +mult,tsmc28,128,1831,0.5461486450027307,42969.906237,251000.0,47.86892408519934 +comparator,sky90,16,3777,0.27152939184537994,360.640007,157.74,0.059571088165210485 +mux2d,tsmc28,1,52822,0.018931505811972286,3.276,26.574,0.0009276437847866419 +flop,tsmc28,64,22091,0.048891303426734874,120.959999,630.0,0.21782626408944816 +priorityencoder,sky90,8,8003,0.12495914257153568,60.760001,44.346,0.013444958140697238 +comparator,sky90,128,2630,0.38016313688212927,2700.880053,641.273,0.41711026615969576 +priorityencoder,tsmc28,8,29455,0.033933093362756746,8.316,36.118,0.0018095399762349347 +flop,sky90,16,8921,0.11434405660800359,266.5599975,129.629,0.3871202779957404 +csa,sky90,128,5810,0.16922003958691909,4700.080091,3350.0,2.4051635111876077 +mux2,sky90,16,5048,0.20207425673534074,119.560002,32.354,0.03882725832012678 +shiftleft,sky90,8,4241,0.23524044494223062,255.780005,194.529,0.06908747936807356 +mux8d,tsmc28,1,20182,0.049365103161232785,11.718,79.832,0.0037260925577247057 +comparator,sky90,128,10,1.136650000000003,1997.240039,243.506,0.1572 +mux8,tsmc28,64,10353,0.09590236028204385,266.615998,1150.0,0.06799961363855887 +mux4d,tsmc28,1,31914,0.030080210691232692,4.158,30.468,0.0012831359278059787 +csa,tsmc28,8,24524,0.040663382319360626,52.416,482.462,0.02173381177621921 +flop,sky90,8,8221,0.1143447031991242,133.279999,64.8145,0.19360175161172608 +mux2,tsmc28,128,15306,0.06522285600418137,160.02,948.941,0.05017640141121129 +csa,sky90,32,5878,0.1696478931609391,1365.140027,921.68,0.6731881592378359 +csa,tsmc28,32,22562,0.04244531185178619,124.992002,962.249,0.05509263363177023 +mux8,tsmc28,8,12386,0.08048931519457453,41.832,167.156,0.010229291135152592 +mux2,tsmc28,32,16829,0.058776237150157465,29.736001,158.536,0.009673777408045637 +csa,tsmc28,8,23053,0.04244530217325294,31.248001,240.54,0.013855029714136989 +mux8,tsmc28,32,12182,0.08988432703989492,202.104,984.173,0.04703661139385979 +shiftleft,sky90,128,1793,0.5575724841048522,7695.940136,3730.0,2.007250418293363 +priorityencoder,tsmc28,64,13252,0.07544330787805614,123.228,381.105,0.01619378207063085 +shiftleft,tsmc28,64,8107,0.12333419119279634,757.385999,3630.0,0.21438263229308005 +csa,tsmc28,32,25505,0.04036599843168006,201.599998,1900.0,0.08519898059204077 +mux2,sky90,64,4233,0.24139207394283013,486.080007,135.616,0.16182376565083867 +csa,sky90,64,6052,0.16536163317911434,2631.300051,1640.0,1.232154659616656 +mux8,tsmc28,16,13245,0.08118818875047187,86.814,421.512,0.023556058890147225 +mux2,tsmc28,1,50870,0.01965795164143896,2.142,15.112,0.0006034991153921761 +mux8,sky90,64,3148,0.3316140076238882,2234.400043,750.071,0.4453621346886913 +mux4,sky90,128,3200,0.317297,2058.00004,772.668,0.5843750000000001 +csa,tsmc28,8,24034,0.04077672239327619,49.392,473.393,0.02151119247732379 +priorityencoder,tsmc28,64,13804,0.07239877021153289,137.466,425.592,0.01847290640394089 +mux8,sky90,8,3657,0.27529718156959254,447.860008,277.646,0.09625375991249657 +csa,sky90,8,5638,0.16671386094359703,290.080006,207.654,0.1493437389145087 +mux8,tsmc28,128,10474,0.09542350830628223,683.045996,2820.0,0.15705556616383426 +mux8,tsmc28,1,16691,0.05956652770954406,10.206,62.604,0.0032173027380025163 +flop,sky90,16,8746,0.11434398307797851,266.5599975,129.629,0.3871484107020352 +add,sky90,128,1734,0.5763442687427912,5613.440109,1880.0,1.7687427912341407 +csa,sky90,64,6415,0.1639816453624318,2947.840027,1820.0,1.3995323460639129 +comparator,sky90,16,3857,0.26124686180969664,392.000008,180.236,0.07311381903033447 +add,sky90,128,1885,0.5304949787798409,6186.740118,2230.0,2.1480106100795755 +mux4,tsmc28,8,18151,0.055092383284667513,27.971999,133.963,0.008032615282904523 +mux4,sky90,1,8101,0.12749355042587335,28.420001,25.098,0.006493025552400939 +mux2,sky90,128,3804,0.2615571777076761,1302.420012,772.39,0.48291272344900105 +comparator,tsmc28,16,14835,0.07291515638692282,54.18,251.929,0.013050219076508256 +priorityencoder,sky90,8,8643,0.12521256693277796,64.680001,49.589,0.014636121716996414 +csa,tsmc28,64,23543,0.04244547041583485,249.984005,1920.0,0.11022384572909145 +add,sky90,16,3001,0.3504502592469177,648.760012,358.879,0.2715761412862379 +comparator,sky90,8,4935,0.21438524518743668,196.980003,103.039,0.04137791286727457 +add,tsmc28,32,9027,0.11067877478675085,180.054001,870.864,0.07411100033233632 +priorityencoder,tsmc28,128,11898,0.08643973911581779,300.636001,944.678,0.038914103210623635 +mux2,tsmc28,128,17303,0.05864344622319829,177.785999,958.338,0.050684852337744904 +mux4,sky90,32,4447,0.24214169934787497,752.640015,483.31,0.16820328311221047 +mux4,tsmc28,16,15497,0.06397261844227915,33.768,141.323,0.01046008904949345 +shiftleft,tsmc28,16,12040,0.08349647840531561,122.093999,588.646,0.031727574750830566 +csa,tsmc28,16,26486,0.040226795514611495,104.831999,978.516,0.043683455410405504 +mux8,tsmc28,1,16024,0.06212039041437843,8.568,46.793,0.0021779830254618072 +add,tsmc28,32,9419,0.10615638305552606,183.834001,912.393,0.07357468945747957 +flop,sky90,128,9445,0.11434412493382742,2132.4799805,1035.0,3.0964531498147165 +mux2d,sky90,1,10,0.16890700000000436,6.86,1.19,0.001981 +mux4,sky90,8,4787,0.20980010173386257,163.660002,93.256,0.043451013160643405 +mux8,sky90,128,2880,0.3583902222222222,4552.100084,1800.0,0.9871527777777778 +mux4,tsmc28,8,19240,0.05756705197505198,22.302,111.045,0.006382536382536383 +mux2,sky90,128,3500,0.2797142857142857,1177.960023,654.082,0.3911428571428572 +mux2,sky90,64,4375,0.24280542857142856,490.980007,134.477,0.16045714285714283 +mult,tsmc28,16,3819,0.26184265147944485,1634.472002,11800.0,1.4553548049227547 +mux4,tsmc28,8,19604,0.05756699795960008,22.302,111.045,0.00638135074474597 +mult,tsmc28,8,4800,0.20832833333333334,367.416001,2600.0,0.26166666666666666 +mult,tsmc28,128,1980,0.5215165050505051,50452.794237,316000.0,58.41464646464647 +add,tsmc28,64,8698,0.12149495838123707,434.448005,2180.0,0.16360082777650037 +flop,tsmc28,8,19636,0.04889186901609289,15.12,78.634,0.027233143206355677 +mux8,sky90,16,10,0.7726059999999961,430.220008,28.957,0.0688 +shiftleft,tsmc28,64,10,0.40777599999999836,270.395999,887.005,0.07880000000000001 +mux8,sky90,1,5997,0.16975504168751043,72.520001,56.57,0.013206603301650825 +mux8,sky90,8,3442,0.2903377623474724,275.380005,60.636,0.049535153980244044 +mult,sky90,32,748,1.357571395721925,22731.100368,11200.0,21.080213903743317 +mux2,sky90,32,4300,0.23126713953488373,230.300004,88.215,0.08534883720930232 +mux4,sky90,32,4200,0.2820362380952381,735.980014,257.203,0.17547619047619048 +mux4,sky90,32,3660,0.272303043715847,453.740008,144.844,0.14262295081967213 +mux8,tsmc28,64,10794,0.09243606151565685,301.77,1480.0,0.0845840281637947 +shiftleft,tsmc28,128,6461,0.15476280266212658,1215.647996,5280.0,0.36867357994118555 +add,sky90,128,1772,0.5643280857787811,5611.480109,1710.0,1.696388261851016 +comparator,tsmc28,8,15714,0.06352952068219422,25.578,121.375,0.0067837597047219035 +priorityencoder,sky90,128,3477,0.3124412565429968,1500.380028,438.268,0.0986482599942479 +comparator,tsmc28,64,11297,0.09384907586084801,291.06,1290.0,0.0684252456404355 +shiftleft,tsmc28,64,7776,0.12859482304526748,654.695996,3090.0,0.1949588477366255 +shiftleft,sky90,32,10,1.1897809999999964,882.980017,61.087,0.1489 +mux8,tsmc28,16,12509,0.08081944144216165,99.036,498.654,0.027260372531777117 +flop,sky90,16,10,0.1143419999999935,266.5599975,129.629,0.38715000000000005 +flop,tsmc28,64,10,0.048889000000002625,120.959999,630.0,0.21765500000000004 +mux2,sky90,16,4553,0.21640140522732265,114.660002,40.216,0.04256534153305513 +shiftleft,sky90,8,4068,0.24550304228121925,232.260005,140.797,0.06052114060963618 +shiftleft,tsmc28,64,8769,0.11943108872163302,1183.769998,6450.0,0.3350439046641578 +mux2,tsmc28,32,17187,0.05813651079304125,29.862001,160.059,0.009699191249199978 +mux2,tsmc28,64,19310,0.05253463904712584,123.858,794.333,0.03702744691869498 +flop,tsmc28,16,21273,0.0488919443425939,30.24,157.29,0.054472805904197806 +flop,sky90,64,9096,0.11434443447669304,1066.23999,520.0,1.5483179419525066 +mux2,sky90,128,3924,0.258784997961264,955.500018,279.611,0.30937818552497454 +mult,tsmc28,8,5200,0.1922996923076923,577.206,4340.0,0.37769230769230766 +shiftleft,tsmc28,8,16114,0.0664628379049274,49.392,346.537,0.016277770882462454 +mux2,sky90,128,4164,0.2565836983669548,1165.220021,656.972,0.4205091258405379 +mux8,tsmc28,64,10573,0.09440153532582994,294.965999,1460.0,0.08256880733944953 +mux4,sky90,8,4602,0.21713182746631898,134.260003,42.968,0.036701434159061276 +mux4,tsmc28,1,25205,0.038448667724657805,4.158,30.449,0.0012933941678238445 +mux8,sky90,64,3209,0.3308795587410408,2240.280042,852.73,0.49236522281084455 +flop,sky90,128,8746,0.11434398307797851,2132.4799805,1035.0,3.0964440887262747 +add,sky90,128,1998,0.5428695005005005,6510.140126,2360.0,2.3248248248248244 +csa,tsmc28,128,25995,0.040894936333910364,806.399994,7580.0,0.34383535295249085 +mult,sky90,64,683,1.5572078433382137,95922.401617,59200.0,108.05124450951685 +comparator,tsmc28,64,11080,0.09024670758122744,294.21,1250.0,0.0684115523465704 +mux4,sky90,8,4941,0.21053718053025702,164.640002,96.679,0.04430277271807326 +mult,tsmc28,32,3092,0.32732826520051744,6660.989998,50100.0,6.573091849935317 +flop,tsmc28,8,20454,0.04889119262735895,15.12,78.6345,0.027236726312701676 +mux4,sky90,16,4482,0.22884868094600624,436.100003,418.878,0.10352521195894689 +mux2,sky90,128,3844,0.26160968158168574,1387.680005,841.057,0.49349635796045777 diff --git a/synthDC/ppa/ppaEquations.csv b/synthDC/ppa/ppaEquations.csv new file mode 100644 index 000000000..5c52db0bb --- /dev/null +++ b/synthDC/ppa/ppaEquations.csv @@ -0,0 +1,11 @@ +Element,Best delay,Fast area,Fast leakage,Fast energy,Small area,Small leakage,Small energy +priorityencoder,0.98$log_2$(N),0.32S,0.22S,0.087S,0.14S,0.044S,0.033S +add,1.9 + 1.4$log_2$(N),1S,0.89S,0.91S,0.32S,0.15S,0.33S +csa,3.6,0.87S,1.3S,0.95S,0.33S,0.15S,0.31S +shiftleft,0.46 + 1.6$log_2$(N),1.9S,2.1S,1.4S,0.77S,0.28S,0.48S +comparator,2.1 + 0.91$log_2$(N),0.58S,0.44S,0.27S,0.33S,0.15S,0.12S +flop,3.3,0.33S,0.33S,1.3S,0.33S,0.33S,1.3S +mux2,2.6 + 0.41$log_2$(N),0.21S,0.23S,0.16S,0.14S,0.11S,0.14S +mux4,3.1 + 0.5$log_2$(N),0.35S,0.31S,0.26S,0.27S,0.11S,0.19S +mux8,4.9 + 0.46$log_2$(N),0.8S,0.66S,0.43S,0.53S,0.23S,0.24S +mult,6$log_2$(N),13$S^2$,13$S^2$,33$S^2$,7.8$S^2$,3.5$S^2$,14$S^2$ diff --git a/synthDC/ppa/ppaFitting.csv b/synthDC/ppa/ppaFitting.csv new file mode 100644 index 000000000..ef4159ecf --- /dev/null +++ b/synthDC/ppa/ppaFitting.csv @@ -0,0 +1,81 @@ +Module,Metric,Target,1,N,N^2,log2(N),Nlog2(N),R^2 +priorityencoder,delay,easy,0.0,,,6.815655848737334,,0.5471505976585844 +priorityencoder,area,easy,,0.14996313076366272,,,,0.9751246139683207 +priorityencoder,lpower,easy,,0.04628232776780845,,,,0.6646449382421588 +priorityencoder,denergy,easy,,0.00046338953826781273,,,,0.8843605490100168 +priorityencoder,delay,hard,0.0,,,0.9775747670327015,,0.987274834491306 +priorityencoder,area,hard,,0.3296349181169891,,,,0.9718942704677337 +priorityencoder,lpower,hard,,0.2508481588069769,,,,0.9418329012771585 +priorityencoder,denergy,hard,,0.09327161156406552,,,,0.8065924672945542 +add,delay,easy,0.0,,,27.820556626526365,,0.5330240516496716 +add,area,easy,,0.33740563909904386,,,,0.9968636684818916 +add,lpower,easy,,0.1559461482654009,,,,0.7403794995975848 +add,denergy,easy,,0.025219887569037786,,,,0.6462978476180771 +add,delay,hard,1.8060844241506506,,,1.4310340215065525,,0.9564367595740637 +add,area,hard,,1.0710989265923485,,,,0.988580182173048 +add,lpower,hard,,0.9470245397661955,,,,0.9951383820581323 +add,denergy,hard,,0.9954952282287014,,,,0.9928308616130285 +csa,delay,easy,5.827386725865409,,,,,0.0 +csa,area,easy,,0.3404841239399024,,,,0.9966821820865757 +csa,lpower,easy,,0.1555300133584381,,,,0.7410756093594764 +csa,denergy,easy,,0.0005478126632729184,,,,0.5798854696439455 +csa,delay,hard,3.590384717869601,,,,,0.0 +csa,area,hard,,0.9312877569527923,,,,0.9993939428598292 +csa,lpower,hard,,1.5320774877598933,,,,0.9400384192534433 +csa,denergy,hard,,1.1454135769936609,,,,0.9735205275004183 +shiftleft,delay,easy,0.0,,,5.744537363106859,,0.7778961884907117 +shiftleft,area,easy,,0.8000093911038876,,,,0.9576897492378456 +shiftleft,lpower,easy,,0.28913702096331206,,,,0.623995386847899 +shiftleft,denergy,easy,,0.005924456057944899,,,,0.7200057939838627 +shiftleft,delay,hard,0.48433873118517795,,,1.635171191349943,,0.9873681453602638 +shiftleft,area,hard,,1.9102134686740575,,,,0.9466461680123697 +shiftleft,lpower,hard,,2.277088275290811,,,,0.9624044038708768 +shiftleft,denergy,hard,,1.4931073444617051,,,,0.9454881696599784 +comparator,delay,easy,0.0,,,4.706704191403,,0.5450694752498024 +comparator,area,easy,,0.3425601443761704,,,,0.978537426983507 +comparator,lpower,easy,,0.15525826941742596,,,,0.8078417286943447 +comparator,denergy,easy,,0.0008896717814426517,,,,0.9267090446396561 +comparator,delay,hard,1.9818442635987938,,,0.9397668550976329,,0.9878932660337799 +comparator,area,hard,,0.6003877936704982,,,,0.9672416909621802 +comparator,lpower,hard,,0.46756802348373877,,,,0.8609362596824635 +comparator,denergy,hard,,0.3089180049610159,,,,0.8267293340232036 +flop,delay,easy,3.3270503187614153,,,,,0.0 +flop,area,easy,,0.34478305655859876,,,,0.9433629202566682 +flop,lpower,easy,,0.3707856336608904,,,,0.9170347531086821 +flop,denergy,easy,,0.0011765517257429892,,,,0.688648230209356 +flop,delay,hard,3.3270503187614153,,,,,0.0 +flop,area,hard,,0.34478305655859876,,,,0.9433629202566682 +flop,lpower,hard,,0.3707856336608904,,,,0.9170347531086821 +flop,denergy,hard,,0.0011765517257429892,,,,0.688648230209356 +mux2,delay,easy,0.0,,,3.276654474184255,,0.7130397298335213 +mux2,area,easy,,0.15083561354737726,,,,0.976644158286422 +mux2,lpower,easy,,0.12067626255418841,,,,0.9344813545348312 +mux2,denergy,easy,,0.0011206170933885473,,,,0.5565267433319017 +mux2,delay,hard,2.539326242287272,,,0.4143154417811283,,0.550540330173853 +mux2,area,hard,,0.2261714754439734,,,,0.9792793539936671 +mux2,lpower,hard,,0.27830936017352714,,,,0.9042661125086188 +mux2,denergy,hard,,0.19333666277894856,,,,0.9525189311701613 +mux4,delay,easy,0.0,,,3.934462222278399,,0.5700865267151127 +mux4,area,easy,,0.2839183647889992,,,,0.9755791039549218 +mux4,lpower,easy,,0.11187597259171647,,,,0.5559362399863286 +mux4,denergy,easy,,0.0021483489610266407,,,,0.5348528431713737 +mux4,delay,hard,3.1369448764435073,,,0.5081925137582488,,0.8316415055210026 +mux4,area,hard,,0.35778033738856435,,,,0.9880049722019894 +mux4,lpower,hard,,0.32236674794207065,,,,0.8279138454959137 +mux4,denergy,hard,,0.28073375091037084,,,,0.9943662618662574 +mux8,delay,easy,0.0,,,4.439779694843578,,0.6601108415004824 +mux8,area,easy,,0.5486426664163658,,,,0.9756934275959698 +mux8,lpower,easy,,0.2380559585648822,,,,0.5468728724048277 +mux8,denergy,easy,,0.0029053391137917966,,,,0.5231276299250225 +mux8,delay,hard,4.9490961359025585,,,0.45254210999717775,,0.8846872287553096 +mux8,area,hard,,0.7645051946159651,,,,0.9834986761377894 +mux8,lpower,hard,,0.6697504633436362,,,,0.9599639296705227 +mux8,denergy,hard,,0.4542825975429124,,,,0.9698068520398291 +mult,delay,easy,0.0,,,61.777235436483835,,0.539191885251039 +mult,area,easy,,1.1322969325198273,7.852086512913157,,,0.997120506119588 +mult,lpower,easy,,1.0320514230056876,3.411671281132248,,,0.7465081509218953 +mult,denergy,easy,,0.0,2.146924193738219,,,0.8988257654810033 +mult,delay,hard,0.0,,,5.971649009143529,,0.9704083045351518 +mult,area,hard,,13.296909763669026,10.2773763878058,,,0.9969630019304513 +mult,lpower,hard,,26.397088944265164,7.310137358727654,,,0.9703772416232848 +mult,denergy,hard,,41.5120348723692,25.39500777044283,,,0.9849195751440497 diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py new file mode 100755 index 000000000..cbfd52538 --- /dev/null +++ b/synthDC/ppa/ppaSynth.py @@ -0,0 +1,73 @@ +#!/usr/bin/python3 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22 + +import subprocess +import re +from multiprocessing import Pool +from ppaAnalyze import synthsfromcsv + +def runCommand(module, width, tech, freq): + command = "make synth DESIGN=ppa_{}_{} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1".format(module, width, tech, freq) + subprocess.Popen(command, shell=True) + +def deleteRedundant(synthsToRun): + '''removes any previous runs for the current synthesis specifications''' + synthStr = "rm -rf runs/ppa_{}_{}_rv32e_{}nm_{}_*" + for synth in synthsToRun: + bashCommand = synthStr.format(*synth) + outputCPL = subprocess.check_output(['bash','-c', bashCommand]) + +def freqSweep(module, width, tech): + synthsToRun = [] + arr = [-8, -6, -4, -2, 0, 2, 4, 6, 8] + allSynths = synthsfromcsv('bestSynths.csv') + for synth in allSynths: + if (synth.module == module) & (synth.tech == tech) & (synth.width == width): + f = 1000/synth.delay + for freq in [round(f+f*x/100) for x in arr]: + synthsToRun += [[synth.module, str(synth.width), synth.tech, str(freq)]] + return synthsToRun + +def filterRedundant(synthsToRun): + bashCommand = "find . -path '*runs/ppa*rv32e*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + specReg = re.compile('[a-zA-Z0-9]+') + allSynths = output.decode("utf-8").split('\n')[:-1] + allSynths = [specReg.findall(oneSynth)[2:7] for oneSynth in allSynths] + allSynths = [oneSynth[0:2] + [oneSynth[3][:-2]] + [oneSynth[4]] for oneSynth in allSynths] + output = [] + for synth in synthsToRun: + if (synth not in allSynths): + output += [synth] + return output + +def allCombos(widths, modules, techs, freqs): + synthsToRun = [] + for w in widths: + for module in modules: + for tech in techs: + for freq in freqs: + synthsToRun += [[module, str(w), tech, str(freq)]] + return synthsToRun + + +if __name__ == '__main__': + + ##### Run specific syntheses + widths = [8, 16, 32, 64, 128] + modules = ['mult', 'add', 'shiftleft', 'flop', 'comparator', 'priorityencoder', 'add', 'csa', 'mux2', 'mux4', 'mux8'] + techs = ['sky90', 'tsmc28'] + freqs = [5000] + synthsToRun = allCombos(widths, modules, techs, freqs) + + ##### Run a sweep based on best delay found in existing syntheses + module = 'add' + width = 32 + tech = 'sky90' + synthsToRun = freqSweep(module, width, tech) + + ##### Only do syntheses for which a run doesn't already exist + synthsToRun = filterRedundant(synthsToRun) + + pool = Pool(processes=25) + pool.starmap(print, synthsToRun) \ No newline at end of file diff --git a/synthDC/runConfigsSynth.sh b/synthDC/runConfigsSynth.sh deleted file mode 100755 index 40c4b6a8f..000000000 --- a/synthDC/runConfigsSynth.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/usr/bin/bash -rm -r runs/* -make clean -make del -make copy -make configs -make allsynth -scripts/extractSummary.py -make del \ No newline at end of file diff --git a/synthDC/runFrequencySynth.sh b/synthDC/runFrequencySynth.sh deleted file mode 100755 index cf603cfd3..000000000 --- a/synthDC/runFrequencySynth.sh +++ /dev/null @@ -1,7 +0,0 @@ -#!/usr/bin/bash -rm -r runs/* -make clean -make del -make freqs TECH=$1 -scripts/extractSummary.py -make del diff --git a/synthDC/scripts/extractSummary.py b/synthDC/scripts/extractSummary.py deleted file mode 100755 index c9ec53494..000000000 --- a/synthDC/scripts/extractSummary.py +++ /dev/null @@ -1,50 +0,0 @@ -#!/usr/bin/python3 -# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 -import glob -import re -import csv -import linecache -import os - - -def main(): - data = [] - curr_dir = os.path.dirname(os.path.abspath(__file__)) - output_file = os.path.join(curr_dir,"..","Summary.csv") - runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep") - # cruns_dir = "/home/ssanghai/Desktop/cleanRun/*/reports/wallypipelinedcore_qor.rep" - search_strings = [ - "Critical Path Length:", "Cell Area:", "Overall Compile Time:", - "Critical Path Clk Period:", "Critical Path Slack:" - ] - for name in glob.glob(runs_dir): - f = open(name, 'r') - trimName = re.search("wallypipelinedcore_(.*?)_sky",name).group(1) - - output = {'Name':trimName} - num_lines = len(f.readlines()) - curr_line_index = 0 - - while curr_line_index < num_lines: - line = linecache.getline(name, curr_line_index) - for search_string in search_strings: - if search_string in line: - val = getVal(name,search_string,line,curr_line_index) - output[search_string] = val - curr_line_index +=1 - data += [output] - - with open(output_file, 'w') as csvfile: - writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings) - writer.writeheader() - writer.writerows(data) - -def getVal(filename, search_string, line, line_index): - data = re.search(f"{search_string} *(.*?)\\n", line).group(1) - if data == '': #sometimes data is stored in two line - data = linecache.getline(filename, line_index+1).strip() - return data - -if __name__=="__main__": - main() - \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index d79009fe1..cbf07dbc6 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -3,6 +3,9 @@ # james.stine@okstate.edu 27 Sep 2015 # +# start run clock +set t1 [clock seconds] + # Ignore unnecessary warnings: # intraassignment delays for nonblocking assignments are ignored suppress_message {VER-130} @@ -18,18 +21,19 @@ set outputDir $::env(OUTPUTDIR) set cfgName $::env(CONFIG) # Config set hdl_src "../pipelined/src" -set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" +set cfg "$outputDir/hdl/config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) +set drive $::env(DRIVE) -eval file copy -force ${cfg} {hdl/} -eval file copy -force ${cfg} $outputDir -eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} -eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} -eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} +eval file copy -force ${cfg} {$outputDir/hdl/} +#eval file copy -force ${cfg} $outputDir +eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} +eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {$outputDir/hdl/} # Only for FMA class project; comment out when done -eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} +# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/} # Enables name mapping if { $saifpower == 1 } { @@ -37,7 +41,7 @@ if { $saifpower == 1 } { } # Verilog files -set my_verilog_files [glob hdl/*] +set my_verilog_files [glob $outputDir/hdl/*] # Set toplevel set my_toplevel $::env(DESIGN) @@ -52,7 +56,8 @@ set vhdlout_show_unconnected_pins "true" # Due to parameterized Verilog must use analyze/elaborate and not # read_verilog/vhdl (change to pull in Verilog and/or VHDL) # -define_design_lib WORK -path ./WORK +#set alib_library_analysis_path ./$outputDir +define_design_lib WORK -path ./$outputDir/WORK analyze -f sverilog -lib WORK $my_verilog_files elaborate $my_toplevel -lib WORK @@ -70,7 +75,12 @@ if { $saifpower == 1 } { } # Set reset false path -set_false_path -from [get_ports reset] +if {$drive != "INV"} { + set_false_path -from [get_ports reset] +} +if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} { + set_false_path -from {s} +} # Set Frequency in [MHz] or period in [ns] set my_clock_pin clk @@ -96,7 +106,7 @@ set_critical_range [expr $my_period*0.05] $current_design # Partitioning - flatten or hierarchically synthesize if { $maxopt == 1 } { - ungroup -all -flatten -simple_names + ungroup -all -simple_names -flatten } # Set input pins except clock @@ -111,23 +121,52 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] if {$tech == "sky130"} { set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk } elseif {$tech == "sky90"} { - set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk + if {$drive == "INV"} { + set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk + } +} elseif {$tech == "tsmc28"} { + if {$drive == "INV"} { + set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk + } } # Set input/output delay -set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk -set_output_delay 0.1 -max -clock $my_clk [all_outputs] +if {$drive == "FLOP"} { + set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.1 -max -clock $my_clk [all_outputs] +} else { + set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk + set_output_delay 0.0 -max -clock $my_clk [all_outputs] +} # Setting load constraint on output ports if {$tech == "sky130"} { set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] } elseif {$tech == "sky90"} { - set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] + if {$drive == "INV"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] + } +} elseif {$tech == "tsmc28"} { + if {$drive == "INV"} { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs] + } } # Set the wire load model set_wire_load_mode "top" +# Set switching activities +# default activity factors are 1 for clocks, 0.1 for others +# static probability of 0.5 is used for leakage + # Attempt Area Recovery - if looking for minimal area # set_max_area 2000 @@ -146,8 +185,8 @@ set_fix_multiple_port_nets -all -buffer_constants # group_path -name COMBO -from [all_inputs] -to [all_outputs] # Save Unmapped Design -#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] -#write_file -format ddc -hierarchy -o $filename +# set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] +# write_file -format ddc -hierarchy -o $filename # Compile statements if { $maxopt == 1 } { @@ -302,21 +341,15 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"] redirect -append $filename { echo "\n\n\n//// Critical paths through fma ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fma1 ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fma/fma1/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fma2 ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {postprocess/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical paths through fpdiv ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through faddcvt ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FMAResM ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FDivResM ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through FResE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through fma/SumE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical paths through fma/ProdExpE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {divsqrt/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical paths through fcvt ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fcvt/*} -nworst 1 } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"] redirect -append $filename { echo "\n\n\n//// Critical paths through immu/physicaladdress ////\n\n\n" } @@ -350,4 +383,9 @@ redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] # redirect $filename { report_hierarchy } +# end run clock and echo run time in minutes +set t2 [clock seconds] +set t [expr $t2 - $t1] +echo [expr $t/60] + quit diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py new file mode 100755 index 000000000..b35a40cf4 --- /dev/null +++ b/synthDC/wallySynth.py @@ -0,0 +1,55 @@ +#!/usr/bin/python3 +# Madeleine Masser-Frye mmasserfrye@hmc.edu 6/22 + +import subprocess +from multiprocessing import Pool +import argparse + +def runSynth(config, tech, freq, maxopt): + global pool + command = "make synth DESIGN=wallypipelinedcore CONFIG={} TECH={} DRIVE=FLOP FREQ={} MAXOPT={} MAXCORES=1".format(config, tech, freq, maxopt) + pool.map(mask, [command]) + +def mask(command): + subprocess.Popen(command, shell=True) + + +if __name__ == '__main__': + + techs = ['sky90', 'tsmc28'] + allConfigs = ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e', 'rv32i', 'rv64i'] + freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] + + pool = Pool() + + parser = argparse.ArgumentParser() + + parser.add_argument("-s", "--freqsweep", type=int, help = "Synthesize wally with target frequencies at given MHz and +/- 2, 4, 6, 8 %%") + parser.add_argument("-c", "--configsweep", action='store_true', help = "Synthesize wally with configurations 32e, 32ic, 64ic, 32gc, and 64gc") + parser.add_argument("-f", "--featuresweep", action='store_true', help = "Synthesize wally with features turned off progressively to visualize critical path") + + parser.add_argument("-v", "--version", choices=allConfigs, help = "Configuration of wally") + parser.add_argument("-t", "--targetfreq", type=int, help = "Target frequncy") + parser.add_argument("-e", "--tech", choices=techs, help = "Technology") + parser.add_argument("-o", "--maxopt", action='store_true', help = "Turn on MAXOPT") + + args = parser.parse_args() + + freq = args.targetfreq if args.targetfreq else 3000 + tech = args.tech if args.tech else 'sky90' + maxopt = int(args.maxopt) + + if args.freqsweep: + sc = args.freqsweep + config = args.version if args.version else 'rv32e' + for freq in [round(sc+sc*x/100) for x in freqVaryPct]: # rv32e freq sweep + runSynth(config, tech, freq, maxopt) + if args.configsweep: + for config in ['rv32gc', 'rv32ic', 'rv64gc', 'rv64ic', 'rv32e']: # configs + config = config + '_orig' # until memory integrated + runSynth(config, tech, freq, maxopt) + if args.featuresweep: + v = args.version if args.version else 'rv64gc' + for mod in ['orig', 'FPUoff', 'noMulDiv', 'noPriv', 'PMP0', 'PMP16']: # rv64gc path variations + config = v + '_' + mod + runSynth(config, tech, freq, maxopt) diff --git a/tests/fp/append_ctrlSig.sh b/tests/fp/append_ctrlSig.sh deleted file mode 100755 index 2cf1dc17a..000000000 --- a/tests/fp/append_ctrlSig.sh +++ /dev/null @@ -1,484 +0,0 @@ -#!/bin/sh -BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" -OUTPUT="./vectors" -echo "Editing ui32_to_f16 test vectors" -sed -ie 's/$/_0_2_2/' $OUTPUT/ui32_to_f16_rne.tv -sed -ie 's/$/_1_2_2/' $OUTPUT/ui32_to_f16_rz.tv -sed -ie 's/$/_3_2_2/' $OUTPUT/ui32_to_f16_ru.tv -sed -ie 's/$/_2_2_2/' $OUTPUT/ui32_to_f16_rd.tv -sed -ie 's/$/_4_2_2/' $OUTPUT/ui32_to_f16_rnm.tv -echo "Editing ui32_to_f32 test vectors" -sed -ie 's/$/_0_0_2/' $OUTPUT/ui32_to_f32_rne.tv -sed -ie 's/$/_1_0_2/' $OUTPUT/ui32_to_f32_rz.tv -sed -ie 's/$/_3_0_2/' $OUTPUT/ui32_to_f32_ru.tv -sed -ie 's/$/_2_0_2/' $OUTPUT/ui32_to_f32_rd.tv -sed -ie 's/$/_4_0_2/' $OUTPUT/ui32_to_f32_rnm.tv -echo "Editing ui32_to_f64 test vectors" -sed -ie 's/$/_0_1_2/' $OUTPUT/ui32_to_f64_rne.tv -sed -ie 's/$/_1_1_2/' $OUTPUT/ui32_to_f64_rz.tv -sed -ie 's/$/_3_1_2/' $OUTPUT/ui32_to_f64_ru.tv -sed -ie 's/$/_2_1_2/' $OUTPUT/ui32_to_f64_rd.tv -sed -ie 's/$/_4_1_2/' $OUTPUT/ui32_to_f64_rnm.tv -echo "Editing ui32_to_f128 test vectors" -sed -ie 's/$/_0_3_2/' $OUTPUT/ui32_to_f128_rne.tv -sed -ie 's/$/_1_3_2/' $OUTPUT/ui32_to_f128_rz.tv -sed -ie 's/$/_3_3_2/' $OUTPUT/ui32_to_f128_ru.tv -sed -ie 's/$/_2_3_2/' $OUTPUT/ui32_to_f128_rd.tv -sed -ie 's/$/_4_3_2/' $OUTPUT/ui32_to_f128_rnm.tv -echo "Editing ui64_to_f16 test vectors" -sed -ie 's/$/_0_2_6/' $OUTPUT/ui64_to_f16_rne.tv -sed -ie 's/$/_1_2_6/' $OUTPUT/ui64_to_f16_rz.tv -sed -ie 's/$/_3_2_6/' $OUTPUT/ui64_to_f16_ru.tv -sed -ie 's/$/_2_2_6/' $OUTPUT/ui64_to_f16_rd.tv -sed -ie 's/$/_4_2_6/' $OUTPUT/ui64_to_f16_rnm.tv -echo "Editing ui64_to_f32 test vectors" -sed -ie 's/$/_0_0_6/' $OUTPUT/ui64_to_f32_rne.tv -sed -ie 's/$/_1_0_6/' $OUTPUT/ui64_to_f32_rz.tv -sed -ie 's/$/_3_0_6/' $OUTPUT/ui64_to_f32_ru.tv -sed -ie 's/$/_2_0_6/' $OUTPUT/ui64_to_f32_rd.tv -sed -ie 's/$/_4_0_6/' $OUTPUT/ui64_to_f32_rnm.tv -echo "Editing ui64_to_f64 test vectors" -sed -ie 's/$/_0_1_6/' $OUTPUT/ui64_to_f64_rne.tv -sed -ie 's/$/_1_1_6/' $OUTPUT/ui64_to_f64_rz.tv -sed -ie 's/$/_3_1_6/' $OUTPUT/ui64_to_f64_ru.tv -sed -ie 's/$/_2_1_6/' $OUTPUT/ui64_to_f64_rd.tv -sed -ie 's/$/_4_1_6/' $OUTPUT/ui64_to_f64_rnm.tv -echo "Editing ui64_to_f128 test vectors" -sed -ie 's/$/_0_3_6/' $OUTPUT/ui64_to_f128_rne.tv -sed -ie 's/$/_1_3_6/' $OUTPUT/ui64_to_f128_rz.tv -sed -ie 's/$/_3_3_6/' $OUTPUT/ui64_to_f128_ru.tv -sed -ie 's/$/_2_3_6/' $OUTPUT/ui64_to_f128_rd.tv -sed -ie 's/$/_4_3_6/' $OUTPUT/ui64_to_f128_rnm.tv -echo "Editing i32_to_f16 test vectors" -sed -ie 's/$/_0_2_0/' $OUTPUT/i32_to_f16_rne.tv -sed -ie 's/$/_1_2_0/' $OUTPUT/i32_to_f16_rz.tv -sed -ie 's/$/_3_2_0/' $OUTPUT/i32_to_f16_ru.tv -sed -ie 's/$/_2_2_0/' $OUTPUT/i32_to_f16_rd.tv -sed -ie 's/$/_4_2_0/' $OUTPUT/i32_to_f16_rnm.tv -echo "Editing i32_to_f32 test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/i32_to_f32_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/i32_to_f32_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/i32_to_f32_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/i32_to_f32_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/i32_to_f32_rnm.tv -echo "Editing i32_to_f64 test vectors" -sed -ie 's/$/_0_1_0/' $OUTPUT/i32_to_f64_rne.tv -sed -ie 's/$/_1_1_0/' $OUTPUT/i32_to_f64_rz.tv -sed -ie 's/$/_3_1_0/' $OUTPUT/i32_to_f64_ru.tv -sed -ie 's/$/_2_1_0/' $OUTPUT/i32_to_f64_rd.tv -sed -ie 's/$/_4_1_0/' $OUTPUT/i32_to_f64_rnm.tv -echo "Editing i32_to_f128 test vectors" -sed -ie 's/$/_0_3_0/' $OUTPUT/i32_to_f128_rne.tv -sed -ie 's/$/_1_3_0/' $OUTPUT/i32_to_f128_rz.tv -sed -ie 's/$/_3_3_0/' $OUTPUT/i32_to_f128_ru.tv -sed -ie 's/$/_2_3_0/' $OUTPUT/i32_to_f128_rd.tv -sed -ie 's/$/_4_3_0/' $OUTPUT/i32_to_f128_rnm.tv -echo "Editing i64_to_f16 test vectors" -sed -ie 's/$/_0_2_4/' $OUTPUT/i64_to_f16_rne.tv -sed -ie 's/$/_1_2_4/' $OUTPUT/i64_to_f16_rz.tv -sed -ie 's/$/_3_2_4/' $OUTPUT/i64_to_f16_ru.tv -sed -ie 's/$/_2_2_4/' $OUTPUT/i64_to_f16_rd.tv -sed -ie 's/$/_4_2_4/' $OUTPUT/i64_to_f16_rnm.tv -echo "Editing i64_to_f32 test vectors" -sed -ie 's/$/_0_0_4/' $OUTPUT/i64_to_f32_rne.tv -sed -ie 's/$/_1_0_4/' $OUTPUT/i64_to_f32_rz.tv -sed -ie 's/$/_3_0_4/' $OUTPUT/i64_to_f32_ru.tv -sed -ie 's/$/_2_0_4/' $OUTPUT/i64_to_f32_rd.tv -sed -ie 's/$/_4_0_4/' $OUTPUT/i64_to_f32_rnm.tv -echo "Editing i64_to_f64 test vectors" -sed -ie 's/$/_0_1_4/' $OUTPUT/i64_to_f64_rne.tv -sed -ie 's/$/_1_1_4/' $OUTPUT/i64_to_f64_rz.tv -sed -ie 's/$/_3_1_4/' $OUTPUT/i64_to_f64_ru.tv -sed -ie 's/$/_2_1_4/' $OUTPUT/i64_to_f64_rd.tv -sed -ie 's/$/_4_1_4/' $OUTPUT/i64_to_f64_rnm.tv -echo "Editing i64_to_f128 test vectors" -sed -ie 's/$/_0_3_4/' $OUTPUT/i64_to_f128_rne.tv -sed -ie 's/$/_1_3_4/' $OUTPUT/i64_to_f128_rz.tv -sed -ie 's/$/_3_3_4/' $OUTPUT/i64_to_f128_ru.tv -sed -ie 's/$/_2_3_4/' $OUTPUT/i64_to_f128_rd.tv -sed -ie 's/$/_4_3_4/' $OUTPUT/i64_to_f128_rnm.tv -echo "Editing f16_to_ui32 test vectors" -sed -ie 's/$/_0_2_3/' $OUTPUT/f16_to_ui32_rne.tv -sed -ie 's/$/_1_2_3/' $OUTPUT/f16_to_ui32_rz.tv -sed -ie 's/$/_3_2_3/' $OUTPUT/f16_to_ui32_ru.tv -sed -ie 's/$/_2_2_3/' $OUTPUT/f16_to_ui32_rd.tv -sed -ie 's/$/_4_2_3/' $OUTPUT/f16_to_ui32_rnm.tv -echo "Editing f32_to_ui32 test vectors" -sed -ie 's/$/_0_0_3/' $OUTPUT/f32_to_ui32_rne.tv -sed -ie 's/$/_1_0_3/' $OUTPUT/f32_to_ui32_rz.tv -sed -ie 's/$/_3_0_3/' $OUTPUT/f32_to_ui32_ru.tv -sed -ie 's/$/_2_0_3/' $OUTPUT/f32_to_ui32_rd.tv -sed -ie 's/$/_4_0_3/' $OUTPUT/f32_to_ui32_rnm.tv -echo "Editing f64_to_ui32 test vectors" -sed -ie 's/$/_0_1_3/' $OUTPUT/f64_to_ui32_rne.tv -sed -ie 's/$/_1_1_3/' $OUTPUT/f64_to_ui32_rz.tv -sed -ie 's/$/_3_1_3/' $OUTPUT/f64_to_ui32_ru.tv -sed -ie 's/$/_2_1_3/' $OUTPUT/f64_to_ui32_rd.tv -sed -ie 's/$/_4_1_3/' $OUTPUT/f64_to_ui32_rnm.tv -echo "Editing f128_to_ui32 test vectors" -sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_ui32_rne.tv -sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_ui32_rz.tv -sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_ui32_ru.tv -sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_ui32_rd.tv -sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_ui32_rnm.tv -echo "Editing f16_to_ui64 test vectors" -sed -ie 's/$/_0_2_7/' $OUTPUT/f16_to_ui64_rne.tv -sed -ie 's/$/_1_2_7/' $OUTPUT/f16_to_ui64_rz.tv -sed -ie 's/$/_3_2_7/' $OUTPUT/f16_to_ui64_ru.tv -sed -ie 's/$/_2_2_7/' $OUTPUT/f16_to_ui64_rd.tv -sed -ie 's/$/_4_2_7/' $OUTPUT/f16_to_ui64_rnm.tv -echo "Editing f32_to_ui64 test vectors" -sed -ie 's/$/_0_0_7/' $OUTPUT/f32_to_ui64_rne.tv -sed -ie 's/$/_1_0_7/' $OUTPUT/f32_to_ui64_rz.tv -sed -ie 's/$/_3_0_7/' $OUTPUT/f32_to_ui64_ru.tv -sed -ie 's/$/_2_0_7/' $OUTPUT/f32_to_ui64_rd.tv -sed -ie 's/$/_4_0_7/' $OUTPUT/f32_to_ui64_rnm.tv -echo "Editing f64_to_ui64 test vectors" -sed -ie 's/$/_0_1_7/' $OUTPUT/f64_to_ui64_rne.tv -sed -ie 's/$/_1_1_7/' $OUTPUT/f64_to_ui64_rz.tv -sed -ie 's/$/_3_1_7/' $OUTPUT/f64_to_ui64_ru.tv -sed -ie 's/$/_2_1_7/' $OUTPUT/f64_to_ui64_rd.tv -sed -ie 's/$/_4_1_7/' $OUTPUT/f64_to_ui64_rnm.tv -echo "Editing f128_to_ui64 test vectors" -sed -ie 's/$/_0_3_7/' $OUTPUT/f128_to_ui64_rne.tv -sed -ie 's/$/_1_3_7/' $OUTPUT/f128_to_ui64_rz.tv -sed -ie 's/$/_3_3_7/' $OUTPUT/f128_to_ui64_ru.tv -sed -ie 's/$/_2_3_7/' $OUTPUT/f128_to_ui64_rd.tv -sed -ie 's/$/_4_3_7/' $OUTPUT/f128_to_ui64_rnm.tv -echo "Editing f16_to_i32 test vectors" -sed -ie 's/$/_0_2_1/' $OUTPUT/f16_to_i32_rne.tv -sed -ie 's/$/_1_2_1/' $OUTPUT/f16_to_i32_rz.tv -sed -ie 's/$/_3_2_1/' $OUTPUT/f16_to_i32_ru.tv -sed -ie 's/$/_2_2_1/' $OUTPUT/f16_to_i32_rd.tv -sed -ie 's/$/_4_2_1/' $OUTPUT/f16_to_i32_rnm.tv -echo "Editing f32_to_i32 test vectors" -sed -ie 's/$/_0_0_1/' $OUTPUT/f32_to_i32_rne.tv -sed -ie 's/$/_1_0_1/' $OUTPUT/f32_to_i32_rz.tv -sed -ie 's/$/_3_0_1/' $OUTPUT/f32_to_i32_ru.tv -sed -ie 's/$/_2_0_1/' $OUTPUT/f32_to_i32_rd.tv -sed -ie 's/$/_4_0_1/' $OUTPUT/f32_to_i32_rnm.tv -echo "Editing f64_to_i32 test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_i32_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_i32_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_i32_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_i32_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_i32_rnm.tv -echo "Editing f128_to_i32 test vectors" -sed -ie 's/$/_0_3_1/' $OUTPUT/f128_to_i32_rne.tv -sed -ie 's/$/_1_3_1/' $OUTPUT/f128_to_i32_rz.tv -sed -ie 's/$/_3_3_1/' $OUTPUT/f128_to_i32_ru.tv -sed -ie 's/$/_2_3_1/' $OUTPUT/f128_to_i32_rd.tv -sed -ie 's/$/_4_3_1/' $OUTPUT/f128_to_i32_rnm.tv -echo "Editing f16_to_i64 test vectors" -sed -ie 's/$/_0_2_5/' $OUTPUT/f16_to_i64_rne.tv -sed -ie 's/$/_1_2_5/' $OUTPUT/f16_to_i64_rz.tv -sed -ie 's/$/_3_2_5/' $OUTPUT/f16_to_i64_ru.tv -sed -ie 's/$/_2_2_5/' $OUTPUT/f16_to_i64_rd.tv -sed -ie 's/$/_4_2_5/' $OUTPUT/f16_to_i64_rnm.tv -echo "Editing f32_to_i64 test vectors" -sed -ie 's/$/_0_0_5/' $OUTPUT/f32_to_i64_rne.tv -sed -ie 's/$/_1_0_5/' $OUTPUT/f32_to_i64_rz.tv -sed -ie 's/$/_3_0_5/' $OUTPUT/f32_to_i64_ru.tv -sed -ie 's/$/_2_0_5/' $OUTPUT/f32_to_i64_rd.tv -sed -ie 's/$/_4_0_5/' $OUTPUT/f32_to_i64_rnm.tv -echo "Editing f64_to_i64 test vectors" -sed -ie 's/$/_0_1_5/' $OUTPUT/f64_to_i64_rne.tv -sed -ie 's/$/_1_1_5/' $OUTPUT/f64_to_i64_rz.tv -sed -ie 's/$/_3_1_5/' $OUTPUT/f64_to_i64_ru.tv -sed -ie 's/$/_2_1_5/' $OUTPUT/f64_to_i64_rd.tv -sed -ie 's/$/_4_1_5/' $OUTPUT/f64_to_i64_rnm.tv -echo "Editing f128_to_i64 test vectors" -sed -ie 's/$/_0_3_5/' $OUTPUT/f128_to_i64_rne.tv -sed -ie 's/$/_1_3_5/' $OUTPUT/f128_to_i64_rz.tv -sed -ie 's/$/_3_3_5/' $OUTPUT/f128_to_i64_ru.tv -sed -ie 's/$/_2_3_5/' $OUTPUT/f128_to_i64_rd.tv -sed -ie 's/$/_4_3_5/' $OUTPUT/f128_to_i64_rnm.tv -echo "Editing f16_to_f32 test vectors" -sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f32_rne.tv -sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f32_rz.tv -sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f32_ru.tv -sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f32_rd.tv -sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f32_rnm.tv -echo "Editing f16_to_f64 test vectors" -sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f64_rne.tv -sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f64_rz.tv -sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f64_ru.tv -sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f64_rd.tv -sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f64_rnm.tv -echo "Editing f16_to_f128 test vectors" -sed -ie 's/$/_0_2_2/' $OUTPUT/f16_to_f128_rne.tv -sed -ie 's/$/_1_2_2/' $OUTPUT/f16_to_f128_rz.tv -sed -ie 's/$/_3_2_2/' $OUTPUT/f16_to_f128_ru.tv -sed -ie 's/$/_2_2_2/' $OUTPUT/f16_to_f128_rd.tv -sed -ie 's/$/_4_2_2/' $OUTPUT/f16_to_f128_rnm.tv -echo "Editing f32_to_f16 test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f16_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f16_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f16_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f16_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f16_rnm.tv -echo "Editing f32_to_f64 test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f64_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f64_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f64_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f64_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f64_rnm.tv -echo "Editing f32_to_f128 test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/f32_to_f128_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/f32_to_f128_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/f32_to_f128_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/f32_to_f128_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/f32_to_f128_rnm.tv -echo "Editing f64_to_f16 test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f16_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f16_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f16_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f16_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f16_rnm.tv -echo "Editing f64_to_f32 test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f32_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f32_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f32_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f32_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f32_rnm.tv -echo "Editing f64_to_f128 test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_to_f128_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_to_f128_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_to_f128_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_to_f128_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_to_f128_rnm.tv -echo "Editing f128_to_f16 test vectors" -sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f16_rne.tv -sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f16_rz.tv -sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f16_ru.tv -sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f16_rd.tv -sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f16_rnm.tv -echo "Editing f128_to_f32 test vectors" -sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f32_rne.tv -sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f32_rz.tv -sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f32_ru.tv -sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f32_rd.tv -sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f32_rnm.tv -echo "Editing f128_to_f64 test vectors" -sed -ie 's/$/_0_3_3/' $OUTPUT/f128_to_f64_rne.tv -sed -ie 's/$/_1_3_3/' $OUTPUT/f128_to_f64_rz.tv -sed -ie 's/$/_3_3_3/' $OUTPUT/f128_to_f64_ru.tv -sed -ie 's/$/_2_3_3/' $OUTPUT/f128_to_f64_rd.tv -sed -ie 's/$/_4_3_3/' $OUTPUT/f128_to_f64_rnm.tv -echo "Editing f16_add test vectors" -sed -ie 's/$/_0_2_6/' $OUTPUT/f16_add_rne.tv -sed -ie 's/$/_1_2_6/' $OUTPUT/f16_add_rz.tv -sed -ie 's/$/_3_2_6/' $OUTPUT/f16_add_ru.tv -sed -ie 's/$/_2_2_6/' $OUTPUT/f16_add_rd.tv -sed -ie 's/$/_4_2_6/' $OUTPUT/f16_add_rnm.tv -echo "Editing f32_add test vectors" -sed -ie 's/$/_0_0_6/' $OUTPUT/f32_add_rne.tv -sed -ie 's/$/_1_0_6/' $OUTPUT/f32_add_rz.tv -sed -ie 's/$/_3_0_6/' $OUTPUT/f32_add_ru.tv -sed -ie 's/$/_2_0_6/' $OUTPUT/f32_add_rd.tv -sed -ie 's/$/_4_0_6/' $OUTPUT/f32_add_rnm.tv -echo "Editing f64_add test vectors" -sed -ie 's/$/_0_1_6/' $OUTPUT/f64_add_rne.tv -sed -ie 's/$/_1_1_6/' $OUTPUT/f64_add_rz.tv -sed -ie 's/$/_3_1_6/' $OUTPUT/f64_add_ru.tv -sed -ie 's/$/_2_1_6/' $OUTPUT/f64_add_rd.tv -sed -ie 's/$/_4_1_6/' $OUTPUT/f64_add_rnm.tv -echo "Editing f128_add test vectors" -sed -ie 's/$/_0_3_6/' $OUTPUT/f128_add_rne.tv -sed -ie 's/$/_1_3_6/' $OUTPUT/f128_add_rz.tv -sed -ie 's/$/_3_3_6/' $OUTPUT/f128_add_ru.tv -sed -ie 's/$/_2_3_6/' $OUTPUT/f128_add_rd.tv -sed -ie 's/$/_4_3_6/' $OUTPUT/f128_add_rnm.tv -echo "Editing f16_sub test vectors" -sed -ie 's/$/_0_2_7/' $OUTPUT/f16_sub_rne.tv -sed -ie 's/$/_1_2_7/' $OUTPUT/f16_sub_rz.tv -sed -ie 's/$/_3_2_7/' $OUTPUT/f16_sub_ru.tv -sed -ie 's/$/_2_2_7/' $OUTPUT/f16_sub_rd.tv -sed -ie 's/$/_4_2_7/' $OUTPUT/f16_sub_rnm.tv -echo "Editing f32_sub test vectors" -sed -ie 's/$/_0_0_7/' $OUTPUT/f32_sub_rne.tv -sed -ie 's/$/_1_0_7/' $OUTPUT/f32_sub_rz.tv -sed -ie 's/$/_3_0_7/' $OUTPUT/f32_sub_ru.tv -sed -ie 's/$/_2_0_7/' $OUTPUT/f32_sub_rd.tv -sed -ie 's/$/_4_0_7/' $OUTPUT/f32_sub_rnm.tv -echo "Editing f64_sub test vectors" -sed -ie 's/$/_0_1_7/' $OUTPUT/f64_sub_rne.tv -sed -ie 's/$/_1_1_7/' $OUTPUT/f64_sub_rz.tv -sed -ie 's/$/_3_1_7/' $OUTPUT/f64_sub_ru.tv -sed -ie 's/$/_2_1_7/' $OUTPUT/f64_sub_rd.tv -sed -ie 's/$/_4_1_7/' $OUTPUT/f64_sub_rnm.tv -echo "Editing f128_sub test vectors" -sed -ie 's/$/_0_3_7/' $OUTPUT/f128_sub_rne.tv -sed -ie 's/$/_1_3_7/' $OUTPUT/f128_sub_rz.tv -sed -ie 's/$/_3_3_7/' $OUTPUT/f128_sub_ru.tv -sed -ie 's/$/_2_3_7/' $OUTPUT/f128_sub_rd.tv -sed -ie 's/$/_4_3_7/' $OUTPUT/f128_sub_rnm.tv -echo "Editing f16_mul test vectors" -sed -ie 's/$/_0_2_4/' $OUTPUT/f16_mul_rne.tv -sed -ie 's/$/_1_2_4/' $OUTPUT/f16_mul_rz.tv -sed -ie 's/$/_3_2_4/' $OUTPUT/f16_mul_ru.tv -sed -ie 's/$/_2_2_4/' $OUTPUT/f16_mul_rd.tv -sed -ie 's/$/_4_2_4/' $OUTPUT/f16_mul_rnm.tv -echo "Editing f32_mul test vectors" -sed -ie 's/$/_0_0_4/' $OUTPUT/f32_mul_rne.tv -sed -ie 's/$/_1_0_4/' $OUTPUT/f32_mul_rz.tv -sed -ie 's/$/_3_0_4/' $OUTPUT/f32_mul_ru.tv -sed -ie 's/$/_2_0_4/' $OUTPUT/f32_mul_rd.tv -sed -ie 's/$/_4_0_4/' $OUTPUT/f32_mul_rnm.tv -echo "Editing f64_mul test vectors" -sed -ie 's/$/_0_1_4/' $OUTPUT/f64_mul_rne.tv -sed -ie 's/$/_1_1_4/' $OUTPUT/f64_mul_rz.tv -sed -ie 's/$/_3_1_4/' $OUTPUT/f64_mul_ru.tv -sed -ie 's/$/_2_1_4/' $OUTPUT/f64_mul_rd.tv -sed -ie 's/$/_4_1_4/' $OUTPUT/f64_mul_rnm.tv -echo "Editing f128_mul test vectors" -sed -ie 's/$/_0_3_4/' $OUTPUT/f128_mul_rne.tv -sed -ie 's/$/_1_3_4/' $OUTPUT/f128_mul_rz.tv -sed -ie 's/$/_3_3_4/' $OUTPUT/f128_mul_ru.tv -sed -ie 's/$/_2_3_4/' $OUTPUT/f128_mul_rd.tv -sed -ie 's/$/_4_3_4/' $OUTPUT/f128_mul_rnm.tv -echo "Editing f16_div test vectors" -sed -ie 's/$/_0_2_0/' $OUTPUT/f16_div_rne.tv -sed -ie 's/$/_1_2_0/' $OUTPUT/f16_div_rz.tv -sed -ie 's/$/_3_2_0/' $OUTPUT/f16_div_ru.tv -sed -ie 's/$/_2_2_0/' $OUTPUT/f16_div_rd.tv -sed -ie 's/$/_4_2_0/' $OUTPUT/f16_div_rnm.tv -echo "Editing f32_div test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/f32_div_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/f32_div_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/f32_div_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/f32_div_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/f32_div_rnm.tv -echo "Editing f64_div test vectors" -sed -ie 's/$/_0_1_0/' $OUTPUT/f64_div_rne.tv -sed -ie 's/$/_1_1_0/' $OUTPUT/f64_div_rz.tv -sed -ie 's/$/_3_1_0/' $OUTPUT/f64_div_ru.tv -sed -ie 's/$/_2_1_0/' $OUTPUT/f64_div_rd.tv -sed -ie 's/$/_4_1_0/' $OUTPUT/f64_div_rnm.tv -echo "Editing f128_div test vectors" -sed -ie 's/$/_0_3_0/' $OUTPUT/f128_div_rne.tv -sed -ie 's/$/_1_3_0/' $OUTPUT/f128_div_rz.tv -sed -ie 's/$/_3_3_0/' $OUTPUT/f128_div_ru.tv -sed -ie 's/$/_2_3_0/' $OUTPUT/f128_div_rd.tv -sed -ie 's/$/_4_3_0/' $OUTPUT/f128_div_rnm.tv -echo "Editing f16_sqrt test vectors" -sed -ie 's/$/_0_2_1/' $OUTPUT/f16_sqrt_rne.tv -sed -ie 's/$/_1_2_1/' $OUTPUT/f16_sqrt_rz.tv -sed -ie 's/$/_3_2_1/' $OUTPUT/f16_sqrt_ru.tv -sed -ie 's/$/_2_2_1/' $OUTPUT/f16_sqrt_rd.tv -sed -ie 's/$/_4_2_1/' $OUTPUT/f16_sqrt_rnm.tv -echo "Editing f32_sqrt test vectors" -sed -ie 's/$/_0_0_1/' $OUTPUT/f32_sqrt_rne.tv -sed -ie 's/$/_1_0_1/' $OUTPUT/f32_sqrt_rz.tv -sed -ie 's/$/_3_0_1/' $OUTPUT/f32_sqrt_ru.tv -sed -ie 's/$/_2_0_1/' $OUTPUT/f32_sqrt_rd.tv -sed -ie 's/$/_4_0_1/' $OUTPUT/f32_sqrt_rnm.tv -echo "Editing f64_sqrt test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_sqrt_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_sqrt_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_sqrt_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_sqrt_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_sqrt_rnm.tv -echo "Editing f128_sqrt test vectors" -sed -ie 's/$/_0_3_1/' $OUTPUT/f128_sqrt_rne.tv -sed -ie 's/$/_1_3_1/' $OUTPUT/f128_sqrt_rz.tv -sed -ie 's/$/_3_3_1/' $OUTPUT/f128_sqrt_ru.tv -sed -ie 's/$/_2_3_1/' $OUTPUT/f128_sqrt_rd.tv -sed -ie 's/$/_4_3_1/' $OUTPUT/f128_sqrt_rnm.tv -echo "Editing f16_eq test vectors" -sed -ie 's/$/_0_2_2/' $OUTPUT/f16_eq_rne.tv -sed -ie 's/$/_1_2_2/' $OUTPUT/f16_eq_rz.tv -sed -ie 's/$/_3_2_2/' $OUTPUT/f16_eq_ru.tv -sed -ie 's/$/_2_2_2/' $OUTPUT/f16_eq_rd.tv -sed -ie 's/$/_4_2_2/' $OUTPUT/f16_eq_rnm.tv -echo "Editing f32_eq test vectors" -sed -ie 's/$/_0_0_2/' $OUTPUT/f32_eq_rne.tv -sed -ie 's/$/_1_0_2/' $OUTPUT/f32_eq_rz.tv -sed -ie 's/$/_3_0_2/' $OUTPUT/f32_eq_ru.tv -sed -ie 's/$/_2_0_2/' $OUTPUT/f32_eq_rd.tv -sed -ie 's/$/_4_0_2/' $OUTPUT/f32_eq_rnm.tv -echo "Editing f64_eq test vectors" -sed -ie 's/$/_0_1_2/' $OUTPUT/f64_eq_rne.tv -sed -ie 's/$/_1_1_2/' $OUTPUT/f64_eq_rz.tv -sed -ie 's/$/_3_1_2/' $OUTPUT/f64_eq_ru.tv -sed -ie 's/$/_2_1_2/' $OUTPUT/f64_eq_rd.tv -sed -ie 's/$/_4_1_2/' $OUTPUT/f64_eq_rnm.tv -echo "Editing f128_eq test vectors" -sed -ie 's/$/_0_3_2/' $OUTPUT/f128_eq_rne.tv -sed -ie 's/$/_1_3_2/' $OUTPUT/f128_eq_rz.tv -sed -ie 's/$/_3_3_2/' $OUTPUT/f128_eq_ru.tv -sed -ie 's/$/_2_3_2/' $OUTPUT/f128_eq_rd.tv -sed -ie 's/$/_4_3_2/' $OUTPUT/f128_eq_rnm.tv -echo "Editing f16_le test vectors" -sed -ie 's/$/_0_2_3/' $OUTPUT/f16_le_rne.tv -sed -ie 's/$/_1_2_3/' $OUTPUT/f16_le_rz.tv -sed -ie 's/$/_3_2_3/' $OUTPUT/f16_le_ru.tv -sed -ie 's/$/_2_2_3/' $OUTPUT/f16_le_rd.tv -sed -ie 's/$/_4_2_3/' $OUTPUT/f16_le_rnm.tv -echo "Editing f32_le test vectors" -sed -ie 's/$/_0_0_3/' $OUTPUT/f32_le_rne.tv -sed -ie 's/$/_1_0_3/' $OUTPUT/f32_le_rz.tv -sed -ie 's/$/_3_0_3/' $OUTPUT/f32_le_ru.tv -sed -ie 's/$/_2_0_3/' $OUTPUT/f32_le_rd.tv -sed -ie 's/$/_4_0_3/' $OUTPUT/f32_le_rnm.tv -echo "Editing f64_le test vectors" -sed -ie 's/$/_0_1_3/' $OUTPUT/f64_le_rne.tv -sed -ie 's/$/_1_1_3/' $OUTPUT/f64_le_rz.tv -sed -ie 's/$/_3_1_3/' $OUTPUT/f64_le_ru.tv -sed -ie 's/$/_2_1_3/' $OUTPUT/f64_le_rd.tv -sed -ie 's/$/_4_1_3/' $OUTPUT/f64_le_rnm.tv -echo "Editing f128_le test vectors" -sed -ie 's/$/_0_3_3/' $OUTPUT/f128_le_rne.tv -sed -ie 's/$/_1_3_3/' $OUTPUT/f128_le_rz.tv -sed -ie 's/$/_3_3_3/' $OUTPUT/f128_le_ru.tv -sed -ie 's/$/_2_3_3/' $OUTPUT/f128_le_rd.tv -sed -ie 's/$/_4_3_3/' $OUTPUT/f128_le_rnm.tv -echo "Editing f16_lt test vectors" -sed -ie 's/$/_0_2_1/' $OUTPUT/f16_lt_rne.tv -sed -ie 's/$/_1_2_1/' $OUTPUT/f16_lt_rz.tv -sed -ie 's/$/_3_2_1/' $OUTPUT/f16_lt_ru.tv -sed -ie 's/$/_2_2_1/' $OUTPUT/f16_lt_rd.tv -sed -ie 's/$/_4_2_1/' $OUTPUT/f16_lt_rnm.tv -echo "Editing f32_lt test vectors" -sed -ie 's/$/_0_0_1/' $OUTPUT/f32_lt_rne.tv -sed -ie 's/$/_1_0_1/' $OUTPUT/f32_lt_rz.tv -sed -ie 's/$/_3_0_1/' $OUTPUT/f32_lt_ru.tv -sed -ie 's/$/_2_0_1/' $OUTPUT/f32_lt_rd.tv -sed -ie 's/$/_4_0_1/' $OUTPUT/f32_lt_rnm.tv -echo "Editing f64_lt test vectors" -sed -ie 's/$/_0_1_1/' $OUTPUT/f64_lt_rne.tv -sed -ie 's/$/_1_1_1/' $OUTPUT/f64_lt_rz.tv -sed -ie 's/$/_3_1_1/' $OUTPUT/f64_lt_ru.tv -sed -ie 's/$/_2_1_1/' $OUTPUT/f64_lt_rd.tv -sed -ie 's/$/_4_1_1/' $OUTPUT/f64_lt_rnm.tv -echo "Editing f128_lt test vectors" -sed -ie 's/$/_0_3_1/' $OUTPUT/f128_lt_rne.tv -sed -ie 's/$/_1_3_1/' $OUTPUT/f128_lt_rz.tv -sed -ie 's/$/_3_3_1/' $OUTPUT/f128_lt_ru.tv -sed -ie 's/$/_2_3_1/' $OUTPUT/f128_lt_rd.tv -sed -ie 's/$/_4_3_1/' $OUTPUT/f128_lt_rnm.tv -echo "Editing f16_mulAdd test vectors" -sed -ie 's/$/_0_2_0/' $OUTPUT/f16_mulAdd_rne.tv -sed -ie 's/$/_1_2_0/' $OUTPUT/f16_mulAdd_rz.tv -sed -ie 's/$/_3_2_0/' $OUTPUT/f16_mulAdd_ru.tv -sed -ie 's/$/_2_2_0/' $OUTPUT/f16_mulAdd_rd.tv -sed -ie 's/$/_4_2_0/' $OUTPUT/f16_mulAdd_rnm.tv -echo "Editing f32_mulAdd test vectors" -sed -ie 's/$/_0_0_0/' $OUTPUT/f32_mulAdd_rne.tv -sed -ie 's/$/_1_0_0/' $OUTPUT/f32_mulAdd_rz.tv -sed -ie 's/$/_3_0_0/' $OUTPUT/f32_mulAdd_ru.tv -sed -ie 's/$/_2_0_0/' $OUTPUT/f32_mulAdd_rd.tv -sed -ie 's/$/_4_0_0/' $OUTPUT/f32_mulAdd_rnm.tv -echo "Editing f64_mulAdd test vectors" -sed -ie 's/$/_0_1_0/' $OUTPUT/f64_mulAdd_rne.tv -sed -ie 's/$/_1_1_0/' $OUTPUT/f64_mulAdd_rz.tv -sed -ie 's/$/_3_1_0/' $OUTPUT/f64_mulAdd_ru.tv -sed -ie 's/$/_2_1_0/' $OUTPUT/f64_mulAdd_rd.tv -sed -ie 's/$/_4_1_0/' $OUTPUT/f64_mulAdd_rnm.tv -echo "Editing f128_mulAdd test vectors" -sed -ie 's/$/_0_3_0/' $OUTPUT/f128_mulAdd_rne.tv -sed -ie 's/$/_1_3_0/' $OUTPUT/f128_mulAdd_rz.tv -sed -ie 's/$/_3_3_0/' $OUTPUT/f128_mulAdd_ru.tv -sed -ie 's/$/_2_3_0/' $OUTPUT/f128_mulAdd_rd.tv -sed -ie 's/$/_4_3_0/' $OUTPUT/f128_mulAdd_rnm.tv -rm vectors/*.tve \ No newline at end of file diff --git a/tests/fp/run_all.sh b/tests/fp/create_all_vectors.sh similarity index 100% rename from tests/fp/run_all.sh rename to tests/fp/create_all_vectors.sh diff --git a/tests/fp/create_vectors.sh b/tests/fp/create_vectors.sh index bac71c608..3ca574fc8 100755 --- a/tests/fp/create_vectors.sh +++ b/tests/fp/create_vectors.sh @@ -2,482 +2,482 @@ BUILD="../../addins/TestFloat-3e/build/Linux-x86_64-GCC" OUTPUT="./vectors" echo "Creating ui32_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv -$BUILD/testfloat_gen -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv -$BUILD/testfloat_gen -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f16 > $OUTPUT/ui32_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f16 > $OUTPUT/ui32_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f16 > $OUTPUT/ui32_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f16 > $OUTPUT/ui32_to_f16_rnm.tv echo "Creating ui32_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv -$BUILD/testfloat_gen -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv -$BUILD/testfloat_gen -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f32 > $OUTPUT/ui32_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f32 > $OUTPUT/ui32_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f32 > $OUTPUT/ui32_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f32 > $OUTPUT/ui32_to_f32_rnm.tv echo "Creating ui32_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv -$BUILD/testfloat_gen -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv -$BUILD/testfloat_gen -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f64 > $OUTPUT/ui32_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f64 > $OUTPUT/ui32_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f64 > $OUTPUT/ui32_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f64 > $OUTPUT/ui32_to_f64_rnm.tv echo "Creating ui32_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv -$BUILD/testfloat_gen -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv -$BUILD/testfloat_gen -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui32_to_f128 > $OUTPUT/ui32_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui32_to_f128 > $OUTPUT/ui32_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui32_to_f128 > $OUTPUT/ui32_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui32_to_f128 > $OUTPUT/ui32_to_f128_rnm.tv echo "Creating ui64_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv -$BUILD/testfloat_gen -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv -$BUILD/testfloat_gen -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f16 > $OUTPUT/ui64_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f16 > $OUTPUT/ui64_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f16 > $OUTPUT/ui64_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f16 > $OUTPUT/ui64_to_f16_rnm.tv echo "Creating ui64_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv -$BUILD/testfloat_gen -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv -$BUILD/testfloat_gen -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f32 > $OUTPUT/ui64_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f32 > $OUTPUT/ui64_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f32 > $OUTPUT/ui64_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f32 > $OUTPUT/ui64_to_f32_rnm.tv echo "Creating ui64_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv -$BUILD/testfloat_gen -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv -$BUILD/testfloat_gen -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f64 > $OUTPUT/ui64_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f64 > $OUTPUT/ui64_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f64 > $OUTPUT/ui64_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f64 > $OUTPUT/ui64_to_f64_rnm.tv echo "Creating ui64_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv -$BUILD/testfloat_gen -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv -$BUILD/testfloat_gen -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even ui64_to_f128 > $OUTPUT/ui64_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax ui64_to_f128 > $OUTPUT/ui64_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin ui64_to_f128 > $OUTPUT/ui64_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag ui64_to_f128 > $OUTPUT/ui64_to_f128_rnm.tv echo "Creating i32_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv -$BUILD/testfloat_gen -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv -$BUILD/testfloat_gen -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f16 > $OUTPUT/i32_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f16 > $OUTPUT/i32_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f16 > $OUTPUT/i32_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f16 > $OUTPUT/i32_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f16 > $OUTPUT/i32_to_f16_rnm.tv echo "Creating i32_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv -$BUILD/testfloat_gen -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv -$BUILD/testfloat_gen -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f32 > $OUTPUT/i32_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f32 > $OUTPUT/i32_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f32 > $OUTPUT/i32_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f32 > $OUTPUT/i32_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f32 > $OUTPUT/i32_to_f32_rnm.tv echo "Creating i32_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv -$BUILD/testfloat_gen -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv -$BUILD/testfloat_gen -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f64 > $OUTPUT/i32_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f64 > $OUTPUT/i32_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f64 > $OUTPUT/i32_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f64 > $OUTPUT/i32_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f64 > $OUTPUT/i32_to_f64_rnm.tv echo "Creating i32_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv -$BUILD/testfloat_gen -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv -$BUILD/testfloat_gen -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i32_to_f128 > $OUTPUT/i32_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i32_to_f128 > $OUTPUT/i32_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i32_to_f128 > $OUTPUT/i32_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i32_to_f128 > $OUTPUT/i32_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i32_to_f128 > $OUTPUT/i32_to_f128_rnm.tv echo "Creating i64_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv -$BUILD/testfloat_gen -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv -$BUILD/testfloat_gen -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f16 > $OUTPUT/i64_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f16 > $OUTPUT/i64_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f16 > $OUTPUT/i64_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f16 > $OUTPUT/i64_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f16 > $OUTPUT/i64_to_f16_rnm.tv echo "Creating i64_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv -$BUILD/testfloat_gen -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv -$BUILD/testfloat_gen -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f32 > $OUTPUT/i64_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f32 > $OUTPUT/i64_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f32 > $OUTPUT/i64_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f32 > $OUTPUT/i64_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f32 > $OUTPUT/i64_to_f32_rnm.tv echo "Creating i64_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv -$BUILD/testfloat_gen -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv -$BUILD/testfloat_gen -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f64 > $OUTPUT/i64_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f64 > $OUTPUT/i64_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f64 > $OUTPUT/i64_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f64 > $OUTPUT/i64_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f64 > $OUTPUT/i64_to_f64_rnm.tv echo "Creating i64_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv -$BUILD/testfloat_gen -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv -$BUILD/testfloat_gen -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even i64_to_f128 > $OUTPUT/i64_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag i64_to_f128 > $OUTPUT/i64_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax i64_to_f128 > $OUTPUT/i64_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin i64_to_f128 > $OUTPUT/i64_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag i64_to_f128 > $OUTPUT/i64_to_f128_rnm.tv echo "Creating f16_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui32 > $OUTPUT/f16_to_ui32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui32 > $OUTPUT/f16_to_ui32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui32 > $OUTPUT/f16_to_ui32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui32 > $OUTPUT/f16_to_ui32_rnm.tv echo "Creating f32_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui32 > $OUTPUT/f32_to_ui32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui32 > $OUTPUT/f32_to_ui32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui32 > $OUTPUT/f32_to_ui32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui32 > $OUTPUT/f32_to_ui32_rnm.tv echo "Creating f64_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui32 > $OUTPUT/f64_to_ui32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui32 > $OUTPUT/f64_to_ui32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui32 > $OUTPUT/f64_to_ui32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui32 > $OUTPUT/f64_to_ui32_rnm.tv echo "Creating f128_to_ui32 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv -$BUILD/testfloat_gen -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv -$BUILD/testfloat_gen -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui32 > $OUTPUT/f128_to_ui32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui32 > $OUTPUT/f128_to_ui32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui32 > $OUTPUT/f128_to_ui32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui32 > $OUTPUT/f128_to_ui32_rnm.tv echo "Creating f16_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_ui64 > $OUTPUT/f16_to_ui64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_ui64 > $OUTPUT/f16_to_ui64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_ui64 > $OUTPUT/f16_to_ui64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_ui64 > $OUTPUT/f16_to_ui64_rnm.tv echo "Creating f32_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_ui64 > $OUTPUT/f32_to_ui64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_ui64 > $OUTPUT/f32_to_ui64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_ui64 > $OUTPUT/f32_to_ui64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_ui64 > $OUTPUT/f32_to_ui64_rnm.tv echo "Creating f64_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_ui64 > $OUTPUT/f64_to_ui64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_ui64 > $OUTPUT/f64_to_ui64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_ui64 > $OUTPUT/f64_to_ui64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_ui64 > $OUTPUT/f64_to_ui64_rnm.tv echo "Creating f128_to_ui64 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv -$BUILD/testfloat_gen -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv -$BUILD/testfloat_gen -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_ui64 > $OUTPUT/f128_to_ui64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_ui64 > $OUTPUT/f128_to_ui64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_ui64 > $OUTPUT/f128_to_ui64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_ui64 > $OUTPUT/f128_to_ui64_rnm.tv echo "Creating f16_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i32 > $OUTPUT/f16_to_i32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i32 > $OUTPUT/f16_to_i32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i32 > $OUTPUT/f16_to_i32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i32 > $OUTPUT/f16_to_i32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i32 > $OUTPUT/f16_to_i32_rnm.tv echo "Creating f32_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i32 > $OUTPUT/f32_to_i32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i32 > $OUTPUT/f32_to_i32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i32 > $OUTPUT/f32_to_i32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i32 > $OUTPUT/f32_to_i32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i32 > $OUTPUT/f32_to_i32_rnm.tv echo "Creating f64_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i32 > $OUTPUT/f64_to_i32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i32 > $OUTPUT/f64_to_i32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i32 > $OUTPUT/f64_to_i32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i32 > $OUTPUT/f64_to_i32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i32 > $OUTPUT/f64_to_i32_rnm.tv echo "Creating f128_to_i32 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv -$BUILD/testfloat_gen -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv -$BUILD/testfloat_gen -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i32 > $OUTPUT/f128_to_i32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i32 > $OUTPUT/f128_to_i32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i32 > $OUTPUT/f128_to_i32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i32 > $OUTPUT/f128_to_i32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i32 > $OUTPUT/f128_to_i32_rnm.tv echo "Creating f16_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f16_to_i64 > $OUTPUT/f16_to_i64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f16_to_i64 > $OUTPUT/f16_to_i64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f16_to_i64 > $OUTPUT/f16_to_i64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f16_to_i64 > $OUTPUT/f16_to_i64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f16_to_i64 > $OUTPUT/f16_to_i64_rnm.tv echo "Creating f32_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f32_to_i64 > $OUTPUT/f32_to_i64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f32_to_i64 > $OUTPUT/f32_to_i64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f32_to_i64 > $OUTPUT/f32_to_i64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f32_to_i64 > $OUTPUT/f32_to_i64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f32_to_i64 > $OUTPUT/f32_to_i64_rnm.tv echo "Creating f64_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f64_to_i64 > $OUTPUT/f64_to_i64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f64_to_i64 > $OUTPUT/f64_to_i64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f64_to_i64 > $OUTPUT/f64_to_i64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f64_to_i64 > $OUTPUT/f64_to_i64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f64_to_i64 > $OUTPUT/f64_to_i64_rnm.tv echo "Creating f128_to_i64 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv -$BUILD/testfloat_gen -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv -$BUILD/testfloat_gen -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_even f128_to_i64 > $OUTPUT/f128_to_i64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rminMag f128_to_i64 > $OUTPUT/f128_to_i64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmax f128_to_i64 > $OUTPUT/f128_to_i64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rmin f128_to_i64 > $OUTPUT/f128_to_i64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -exact -rnear_maxMag f128_to_i64 > $OUTPUT/f128_to_i64_rnm.tv echo "Creating f16_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv -$BUILD/testfloat_gen -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv -$BUILD/testfloat_gen -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f32 > $OUTPUT/f16_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f32 > $OUTPUT/f16_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f32 > $OUTPUT/f16_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f32 > $OUTPUT/f16_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f32 > $OUTPUT/f16_to_f32_rnm.tv echo "Creating f16_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv -$BUILD/testfloat_gen -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv -$BUILD/testfloat_gen -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f64 > $OUTPUT/f16_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f64 > $OUTPUT/f16_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f64 > $OUTPUT/f16_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f64 > $OUTPUT/f16_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f64 > $OUTPUT/f16_to_f64_rnm.tv echo "Creating f16_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv -$BUILD/testfloat_gen -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv -$BUILD/testfloat_gen -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_to_f128 > $OUTPUT/f16_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_to_f128 > $OUTPUT/f16_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_to_f128 > $OUTPUT/f16_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_to_f128 > $OUTPUT/f16_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_to_f128 > $OUTPUT/f16_to_f128_rnm.tv echo "Creating f32_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv -$BUILD/testfloat_gen -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv -$BUILD/testfloat_gen -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f16 > $OUTPUT/f32_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f16 > $OUTPUT/f32_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f16 > $OUTPUT/f32_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f16 > $OUTPUT/f32_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f16 > $OUTPUT/f32_to_f16_rnm.tv echo "Creating f32_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv -$BUILD/testfloat_gen -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv -$BUILD/testfloat_gen -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f64 > $OUTPUT/f32_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f64 > $OUTPUT/f32_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f64 > $OUTPUT/f32_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f64 > $OUTPUT/f32_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f64 > $OUTPUT/f32_to_f64_rnm.tv echo "Creating f32_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv -$BUILD/testfloat_gen -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv -$BUILD/testfloat_gen -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_to_f128 > $OUTPUT/f32_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_to_f128 > $OUTPUT/f32_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_to_f128 > $OUTPUT/f32_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_to_f128 > $OUTPUT/f32_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_to_f128 > $OUTPUT/f32_to_f128_rnm.tv echo "Creating f64_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv -$BUILD/testfloat_gen -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv -$BUILD/testfloat_gen -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f16 > $OUTPUT/f64_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f16 > $OUTPUT/f64_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f16 > $OUTPUT/f64_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f16 > $OUTPUT/f64_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f16 > $OUTPUT/f64_to_f16_rnm.tv echo "Creating f64_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv -$BUILD/testfloat_gen -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv -$BUILD/testfloat_gen -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f32 > $OUTPUT/f64_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f32 > $OUTPUT/f64_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f32 > $OUTPUT/f64_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f32 > $OUTPUT/f64_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f32 > $OUTPUT/f64_to_f32_rnm.tv echo "Creating f64_to_f128 convert vectors" -$BUILD/testfloat_gen -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv -$BUILD/testfloat_gen -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv -$BUILD/testfloat_gen -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv -$BUILD/testfloat_gen -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_to_f128 > $OUTPUT/f64_to_f128_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_to_f128 > $OUTPUT/f64_to_f128_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_to_f128 > $OUTPUT/f64_to_f128_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_to_f128 > $OUTPUT/f64_to_f128_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_to_f128 > $OUTPUT/f64_to_f128_rnm.tv echo "Creating f128_to_f16 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv -$BUILD/testfloat_gen -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv -$BUILD/testfloat_gen -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f16 > $OUTPUT/f128_to_f16_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f16 > $OUTPUT/f128_to_f16_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f16 > $OUTPUT/f128_to_f16_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f16 > $OUTPUT/f128_to_f16_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f16 > $OUTPUT/f128_to_f16_rnm.tv echo "Creating f128_to_f32 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv -$BUILD/testfloat_gen -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv -$BUILD/testfloat_gen -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f32 > $OUTPUT/f128_to_f32_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f32 > $OUTPUT/f128_to_f32_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f32 > $OUTPUT/f128_to_f32_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f32 > $OUTPUT/f128_to_f32_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f32 > $OUTPUT/f128_to_f32_rnm.tv echo "Creating f128_to_f64 convert vectors" -$BUILD/testfloat_gen -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv -$BUILD/testfloat_gen -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv -$BUILD/testfloat_gen -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv -$BUILD/testfloat_gen -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_to_f64 > $OUTPUT/f128_to_f64_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_to_f64 > $OUTPUT/f128_to_f64_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_to_f64 > $OUTPUT/f128_to_f64_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_to_f64 > $OUTPUT/f128_to_f64_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_to_f64 > $OUTPUT/f128_to_f64_rnm.tv echo "Creating f16_add vectors" -$BUILD/testfloat_gen -rnear_even f16_add > $OUTPUT/f16_add_rne.tv -$BUILD/testfloat_gen -rminMag f16_add > $OUTPUT/f16_add_rz.tv -$BUILD/testfloat_gen -rmax f16_add > $OUTPUT/f16_add_ru.tv -$BUILD/testfloat_gen -rmin f16_add > $OUTPUT/f16_add_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_add > $OUTPUT/f16_add_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_add > $OUTPUT/f16_add_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_add > $OUTPUT/f16_add_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_add > $OUTPUT/f16_add_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_add > $OUTPUT/f16_add_rnm.tv echo "Creating f32_add vectors" -$BUILD/testfloat_gen -rnear_even f32_add > $OUTPUT/f32_add_rne.tv -$BUILD/testfloat_gen -rminMag f32_add > $OUTPUT/f32_add_rz.tv -$BUILD/testfloat_gen -rmax f32_add > $OUTPUT/f32_add_ru.tv -$BUILD/testfloat_gen -rmin f32_add > $OUTPUT/f32_add_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_add > $OUTPUT/f32_add_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_add > $OUTPUT/f32_add_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_add > $OUTPUT/f32_add_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_add > $OUTPUT/f32_add_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_add > $OUTPUT/f32_add_rnm.tv echo "Creating f64_add vectors" -$BUILD/testfloat_gen -rnear_even f64_add > $OUTPUT/f64_add_rne.tv -$BUILD/testfloat_gen -rminMag f64_add > $OUTPUT/f64_add_rz.tv -$BUILD/testfloat_gen -rmax f64_add > $OUTPUT/f64_add_ru.tv -$BUILD/testfloat_gen -rmin f64_add > $OUTPUT/f64_add_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_add > $OUTPUT/f64_add_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_add > $OUTPUT/f64_add_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_add > $OUTPUT/f64_add_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_add > $OUTPUT/f64_add_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_add > $OUTPUT/f64_add_rnm.tv echo "Creating f128_add vectors" -$BUILD/testfloat_gen -rnear_even f128_add > $OUTPUT/f128_add_rne.tv -$BUILD/testfloat_gen -rminMag f128_add > $OUTPUT/f128_add_rz.tv -$BUILD/testfloat_gen -rmax f128_add > $OUTPUT/f128_add_ru.tv -$BUILD/testfloat_gen -rmin f128_add > $OUTPUT/f128_add_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_add > $OUTPUT/f128_add_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_add > $OUTPUT/f128_add_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_add > $OUTPUT/f128_add_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_add > $OUTPUT/f128_add_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_add > $OUTPUT/f128_add_rnm.tv echo "Creating f16_sub vectors" -$BUILD/testfloat_gen -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv -$BUILD/testfloat_gen -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv -$BUILD/testfloat_gen -rmax f16_sub > $OUTPUT/f16_sub_ru.tv -$BUILD/testfloat_gen -rmin f16_sub > $OUTPUT/f16_sub_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_sub > $OUTPUT/f16_sub_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_sub > $OUTPUT/f16_sub_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_sub > $OUTPUT/f16_sub_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_sub > $OUTPUT/f16_sub_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_sub > $OUTPUT/f16_sub_rnm.tv echo "Creating f32_sub vectors" -$BUILD/testfloat_gen -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv -$BUILD/testfloat_gen -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv -$BUILD/testfloat_gen -rmax f32_sub > $OUTPUT/f32_sub_ru.tv -$BUILD/testfloat_gen -rmin f32_sub > $OUTPUT/f32_sub_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_sub > $OUTPUT/f32_sub_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_sub > $OUTPUT/f32_sub_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_sub > $OUTPUT/f32_sub_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_sub > $OUTPUT/f32_sub_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_sub > $OUTPUT/f32_sub_rnm.tv echo "Creating f64_sub vectors" -$BUILD/testfloat_gen -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv -$BUILD/testfloat_gen -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv -$BUILD/testfloat_gen -rmax f64_sub > $OUTPUT/f64_sub_ru.tv -$BUILD/testfloat_gen -rmin f64_sub > $OUTPUT/f64_sub_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_sub > $OUTPUT/f64_sub_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_sub > $OUTPUT/f64_sub_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_sub > $OUTPUT/f64_sub_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_sub > $OUTPUT/f64_sub_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_sub > $OUTPUT/f64_sub_rnm.tv echo "Creating f128_sub vectors" -$BUILD/testfloat_gen -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv -$BUILD/testfloat_gen -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv -$BUILD/testfloat_gen -rmax f128_sub > $OUTPUT/f128_sub_ru.tv -$BUILD/testfloat_gen -rmin f128_sub > $OUTPUT/f128_sub_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_sub > $OUTPUT/f128_sub_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_sub > $OUTPUT/f128_sub_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_sub > $OUTPUT/f128_sub_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_sub > $OUTPUT/f128_sub_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_sub > $OUTPUT/f128_sub_rnm.tv echo "Creating f16_mul vectors" -$BUILD/testfloat_gen -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv -$BUILD/testfloat_gen -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv -$BUILD/testfloat_gen -rmax f16_mul > $OUTPUT/f16_mul_ru.tv -$BUILD/testfloat_gen -rmin f16_mul > $OUTPUT/f16_mul_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mul > $OUTPUT/f16_mul_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mul > $OUTPUT/f16_mul_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mul > $OUTPUT/f16_mul_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mul > $OUTPUT/f16_mul_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mul > $OUTPUT/f16_mul_rnm.tv echo "Creating f32_mul vectors" -$BUILD/testfloat_gen -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv -$BUILD/testfloat_gen -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv -$BUILD/testfloat_gen -rmax f32_mul > $OUTPUT/f32_mul_ru.tv -$BUILD/testfloat_gen -rmin f32_mul > $OUTPUT/f32_mul_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mul > $OUTPUT/f32_mul_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mul > $OUTPUT/f32_mul_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mul > $OUTPUT/f32_mul_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mul > $OUTPUT/f32_mul_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mul > $OUTPUT/f32_mul_rnm.tv echo "Creating f64_mul vectors" -$BUILD/testfloat_gen -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv -$BUILD/testfloat_gen -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv -$BUILD/testfloat_gen -rmax f64_mul > $OUTPUT/f64_mul_ru.tv -$BUILD/testfloat_gen -rmin f64_mul > $OUTPUT/f64_mul_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mul > $OUTPUT/f64_mul_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mul > $OUTPUT/f64_mul_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mul > $OUTPUT/f64_mul_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mul > $OUTPUT/f64_mul_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mul > $OUTPUT/f64_mul_rnm.tv echo "Creating f128_mul vectors" -$BUILD/testfloat_gen -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv -$BUILD/testfloat_gen -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv -$BUILD/testfloat_gen -rmax f128_mul > $OUTPUT/f128_mul_ru.tv -$BUILD/testfloat_gen -rmin f128_mul > $OUTPUT/f128_mul_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mul > $OUTPUT/f128_mul_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mul > $OUTPUT/f128_mul_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mul > $OUTPUT/f128_mul_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mul > $OUTPUT/f128_mul_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mul > $OUTPUT/f128_mul_rnm.tv echo "Creating f16_div vectors" -$BUILD/testfloat_gen -rnear_even f16_div > $OUTPUT/f16_div_rne.tv -$BUILD/testfloat_gen -rminMag f16_div > $OUTPUT/f16_div_rz.tv -$BUILD/testfloat_gen -rmax f16_div > $OUTPUT/f16_div_ru.tv -$BUILD/testfloat_gen -rmin f16_div > $OUTPUT/f16_div_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_div > $OUTPUT/f16_div_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_div > $OUTPUT/f16_div_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_div > $OUTPUT/f16_div_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_div > $OUTPUT/f16_div_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_div > $OUTPUT/f16_div_rnm.tv echo "Creating f32_div vectors" -$BUILD/testfloat_gen -rnear_even f32_div > $OUTPUT/f32_div_rne.tv -$BUILD/testfloat_gen -rminMag f32_div > $OUTPUT/f32_div_rz.tv -$BUILD/testfloat_gen -rmax f32_div > $OUTPUT/f32_div_ru.tv -$BUILD/testfloat_gen -rmin f32_div > $OUTPUT/f32_div_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_div > $OUTPUT/f32_div_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_div > $OUTPUT/f32_div_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_div > $OUTPUT/f32_div_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_div > $OUTPUT/f32_div_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_div > $OUTPUT/f32_div_rnm.tv echo "Creating f64_div vectors" -$BUILD/testfloat_gen -rnear_even f64_div > $OUTPUT/f64_div_rne.tv -$BUILD/testfloat_gen -rminMag f64_div > $OUTPUT/f64_div_rz.tv -$BUILD/testfloat_gen -rmax f64_div > $OUTPUT/f64_div_ru.tv -$BUILD/testfloat_gen -rmin f64_div > $OUTPUT/f64_div_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_div > $OUTPUT/f64_div_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_div > $OUTPUT/f64_div_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_div > $OUTPUT/f64_div_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_div > $OUTPUT/f64_div_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_div > $OUTPUT/f64_div_rnm.tv echo "Creating f128_div vectors" -$BUILD/testfloat_gen -rnear_even f128_div > $OUTPUT/f128_div_rne.tv -$BUILD/testfloat_gen -rminMag f128_div > $OUTPUT/f128_div_rz.tv -$BUILD/testfloat_gen -rmax f128_div > $OUTPUT/f128_div_ru.tv -$BUILD/testfloat_gen -rmin f128_div > $OUTPUT/f128_div_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_div > $OUTPUT/f128_div_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_div > $OUTPUT/f128_div_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_div > $OUTPUT/f128_div_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_div > $OUTPUT/f128_div_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_div > $OUTPUT/f128_div_rnm.tv echo "Creating f16_sqrt vectors" -$BUILD/testfloat_gen -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f16_sqrt > $OUTPUT/f16_sqrt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f16_sqrt > $OUTPUT/f16_sqrt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f16_sqrt > $OUTPUT/f16_sqrt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f16_sqrt > $OUTPUT/f16_sqrt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f16_sqrt > $OUTPUT/f16_sqrt_rnm.tv echo "Creating f32_sqrt vectors" -$BUILD/testfloat_gen -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f32_sqrt > $OUTPUT/f32_sqrt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f32_sqrt > $OUTPUT/f32_sqrt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f32_sqrt > $OUTPUT/f32_sqrt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f32_sqrt > $OUTPUT/f32_sqrt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f32_sqrt > $OUTPUT/f32_sqrt_rnm.tv echo "Creating f64_sqrt vectors" -$BUILD/testfloat_gen -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f64_sqrt > $OUTPUT/f64_sqrt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f64_sqrt > $OUTPUT/f64_sqrt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f64_sqrt > $OUTPUT/f64_sqrt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f64_sqrt > $OUTPUT/f64_sqrt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f64_sqrt > $OUTPUT/f64_sqrt_rnm.tv echo "Creating f128_sqrt vectors" -$BUILD/testfloat_gen -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv -$BUILD/testfloat_gen -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv -$BUILD/testfloat_gen -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv -$BUILD/testfloat_gen -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_even f128_sqrt > $OUTPUT/f128_sqrt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rminMag f128_sqrt > $OUTPUT/f128_sqrt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmax f128_sqrt > $OUTPUT/f128_sqrt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rmin f128_sqrt > $OUTPUT/f128_sqrt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 2 -rnear_maxMag f128_sqrt > $OUTPUT/f128_sqrt_rnm.tv echo "Creating f16_eq vectors" -$BUILD/testfloat_gen -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv -$BUILD/testfloat_gen -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv -$BUILD/testfloat_gen -rmax f16_eq > $OUTPUT/f16_eq_ru.tv -$BUILD/testfloat_gen -rmin f16_eq > $OUTPUT/f16_eq_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_eq > $OUTPUT/f16_eq_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_eq > $OUTPUT/f16_eq_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_eq > $OUTPUT/f16_eq_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_eq > $OUTPUT/f16_eq_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_eq > $OUTPUT/f16_eq_rnm.tv echo "Creating f32_eq vectors" -$BUILD/testfloat_gen -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv -$BUILD/testfloat_gen -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv -$BUILD/testfloat_gen -rmax f32_eq > $OUTPUT/f32_eq_ru.tv -$BUILD/testfloat_gen -rmin f32_eq > $OUTPUT/f32_eq_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_eq > $OUTPUT/f32_eq_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_eq > $OUTPUT/f32_eq_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_eq > $OUTPUT/f32_eq_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_eq > $OUTPUT/f32_eq_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_eq > $OUTPUT/f32_eq_rnm.tv echo "Creating f64_eq vectors" -$BUILD/testfloat_gen -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv -$BUILD/testfloat_gen -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv -$BUILD/testfloat_gen -rmax f64_eq > $OUTPUT/f64_eq_ru.tv -$BUILD/testfloat_gen -rmin f64_eq > $OUTPUT/f64_eq_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_eq > $OUTPUT/f64_eq_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_eq > $OUTPUT/f64_eq_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_eq > $OUTPUT/f64_eq_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_eq > $OUTPUT/f64_eq_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_eq > $OUTPUT/f64_eq_rnm.tv echo "Creating f128_eq vectors" -$BUILD/testfloat_gen -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv -$BUILD/testfloat_gen -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv -$BUILD/testfloat_gen -rmax f128_eq > $OUTPUT/f128_eq_ru.tv -$BUILD/testfloat_gen -rmin f128_eq > $OUTPUT/f128_eq_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_eq > $OUTPUT/f128_eq_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_eq > $OUTPUT/f128_eq_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_eq > $OUTPUT/f128_eq_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_eq > $OUTPUT/f128_eq_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_eq > $OUTPUT/f128_eq_rnm.tv echo "Creating f16_le vectors" -$BUILD/testfloat_gen -rnear_even f16_le > $OUTPUT/f16_le_rne.tv -$BUILD/testfloat_gen -rminMag f16_le > $OUTPUT/f16_le_rz.tv -$BUILD/testfloat_gen -rmax f16_le > $OUTPUT/f16_le_ru.tv -$BUILD/testfloat_gen -rmin f16_le > $OUTPUT/f16_le_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_le > $OUTPUT/f16_le_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_le > $OUTPUT/f16_le_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_le > $OUTPUT/f16_le_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_le > $OUTPUT/f16_le_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_le > $OUTPUT/f16_le_rnm.tv echo "Creating f32_le vectors" -$BUILD/testfloat_gen -rnear_even f32_le > $OUTPUT/f32_le_rne.tv -$BUILD/testfloat_gen -rminMag f32_le > $OUTPUT/f32_le_rz.tv -$BUILD/testfloat_gen -rmax f32_le > $OUTPUT/f32_le_ru.tv -$BUILD/testfloat_gen -rmin f32_le > $OUTPUT/f32_le_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_le > $OUTPUT/f32_le_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_le > $OUTPUT/f32_le_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_le > $OUTPUT/f32_le_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_le > $OUTPUT/f32_le_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_le > $OUTPUT/f32_le_rnm.tv echo "Creating f64_le vectors" -$BUILD/testfloat_gen -rnear_even f64_le > $OUTPUT/f64_le_rne.tv -$BUILD/testfloat_gen -rminMag f64_le > $OUTPUT/f64_le_rz.tv -$BUILD/testfloat_gen -rmax f64_le > $OUTPUT/f64_le_ru.tv -$BUILD/testfloat_gen -rmin f64_le > $OUTPUT/f64_le_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_le > $OUTPUT/f64_le_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_le > $OUTPUT/f64_le_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_le > $OUTPUT/f64_le_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_le > $OUTPUT/f64_le_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_le > $OUTPUT/f64_le_rnm.tv echo "Creating f128_le vectors" -$BUILD/testfloat_gen -rnear_even f128_le > $OUTPUT/f128_le_rne.tv -$BUILD/testfloat_gen -rminMag f128_le > $OUTPUT/f128_le_rz.tv -$BUILD/testfloat_gen -rmax f128_le > $OUTPUT/f128_le_ru.tv -$BUILD/testfloat_gen -rmin f128_le > $OUTPUT/f128_le_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_le > $OUTPUT/f128_le_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_le > $OUTPUT/f128_le_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_le > $OUTPUT/f128_le_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_le > $OUTPUT/f128_le_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_le > $OUTPUT/f128_le_rnm.tv echo "Creating f16_lt vectors" -$BUILD/testfloat_gen -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv -$BUILD/testfloat_gen -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv -$BUILD/testfloat_gen -rmax f16_lt > $OUTPUT/f16_lt_ru.tv -$BUILD/testfloat_gen -rmin f16_lt > $OUTPUT/f16_lt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_lt > $OUTPUT/f16_lt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_lt > $OUTPUT/f16_lt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_lt > $OUTPUT/f16_lt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_lt > $OUTPUT/f16_lt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_lt > $OUTPUT/f16_lt_rnm.tv echo "Creating f32_lt vectors" -$BUILD/testfloat_gen -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv -$BUILD/testfloat_gen -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv -$BUILD/testfloat_gen -rmax f32_lt > $OUTPUT/f32_lt_ru.tv -$BUILD/testfloat_gen -rmin f32_lt > $OUTPUT/f32_lt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_lt > $OUTPUT/f32_lt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_lt > $OUTPUT/f32_lt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_lt > $OUTPUT/f32_lt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_lt > $OUTPUT/f32_lt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_lt > $OUTPUT/f32_lt_rnm.tv echo "Creating f64_lt vectors" -$BUILD/testfloat_gen -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv -$BUILD/testfloat_gen -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv -$BUILD/testfloat_gen -rmax f64_lt > $OUTPUT/f64_lt_ru.tv -$BUILD/testfloat_gen -rmin f64_lt > $OUTPUT/f64_lt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_lt > $OUTPUT/f64_lt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_lt > $OUTPUT/f64_lt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_lt > $OUTPUT/f64_lt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_lt > $OUTPUT/f64_lt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_lt > $OUTPUT/f64_lt_rnm.tv echo "Creating f128_lt vectors" -$BUILD/testfloat_gen -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv -$BUILD/testfloat_gen -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv -$BUILD/testfloat_gen -rmax f128_lt > $OUTPUT/f128_lt_ru.tv -$BUILD/testfloat_gen -rmin f128_lt > $OUTPUT/f128_lt_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_lt > $OUTPUT/f128_lt_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_lt > $OUTPUT/f128_lt_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_lt > $OUTPUT/f128_lt_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_lt > $OUTPUT/f128_lt_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_lt > $OUTPUT/f128_lt_rnm.tv echo "Creating f16_mulAdd vectors" -$BUILD/testfloat_gen -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f16_mulAdd > $OUTPUT/f16_mulAdd_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f16_mulAdd > $OUTPUT/f16_mulAdd_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f16_mulAdd > $OUTPUT/f16_mulAdd_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f16_mulAdd > $OUTPUT/f16_mulAdd_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f16_mulAdd > $OUTPUT/f16_mulAdd_rnm.tv echo "Creating f32_mulAdd vectors" -$BUILD/testfloat_gen -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f32_mulAdd > $OUTPUT/f32_mulAdd_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f32_mulAdd > $OUTPUT/f32_mulAdd_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f32_mulAdd > $OUTPUT/f32_mulAdd_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f32_mulAdd > $OUTPUT/f32_mulAdd_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f32_mulAdd > $OUTPUT/f32_mulAdd_rnm.tv echo "Creating f64_mulAdd vectors" -$BUILD/testfloat_gen -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f64_mulAdd > $OUTPUT/f64_mulAdd_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f64_mulAdd > $OUTPUT/f64_mulAdd_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f64_mulAdd > $OUTPUT/f64_mulAdd_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f64_mulAdd > $OUTPUT/f64_mulAdd_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f64_mulAdd > $OUTPUT/f64_mulAdd_rnm.tv echo "Creating f128_mulAdd vectors" -$BUILD/testfloat_gen -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv -$BUILD/testfloat_gen -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv -$BUILD/testfloat_gen -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv -$BUILD/testfloat_gen -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv -$BUILD/testfloat_gen -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_even f128_mulAdd > $OUTPUT/f128_mulAdd_rne.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rminMag f128_mulAdd > $OUTPUT/f128_mulAdd_rz.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmax f128_mulAdd > $OUTPUT/f128_mulAdd_ru.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rmin f128_mulAdd > $OUTPUT/f128_mulAdd_rd.tv +$BUILD/testfloat_gen -tininessafter -level 1 -rnear_maxMag f128_mulAdd > $OUTPUT/f128_mulAdd_rnm.tv diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile new file mode 100644 index 000000000..28906e09b --- /dev/null +++ b/tests/riscof/Makefile @@ -0,0 +1,64 @@ +arch_dir = ../../addins/riscv-arch-test +wally_dir = ../wally-riscv-arch-test +work_dir = ./riscof_work +work = ./work +arch_workdir = $(work)/riscv-arch-test +wally_workdir = $(work)/wally-riscv-arch-test + +current_dir = $(shell pwd) +#XLEN ?= 64 + +all: root fsd_fld_tempfix arch32 wally32 wally32e arch64 wally64 +#all: root fsd_fld_tempfix wally32 + +root: + mkdir -p $(work_dir) + mkdir -p $(work) + mkdir -p $(arch_workdir) + mkdir -p $(wally_workdir) + sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini + sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini + sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini + +fsd_fld_tempfix: + # this is a temporary fix, there's a typo on the rv64i_m/D/src/d_fsd-align-01.S and rv64i_m/D/src/d_fld-align-01.S tests + # https://github.com/riscv-non-isa/riscv-arch-test/issues/266 + find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fld-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {} + find ../../addins/riscv-arch-test/riscv-test-suite -type f -name "*d_fsd-align*.S" | xargs -I{} sed -i 's,regex(\.\*32\.\*),regex(\.\*64\.\*),g' {} + +arch32: + riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser + rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed" + +arch64: + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser + rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" +# Also copy F and D tests to RV64 + rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" + +wally32: + riscof run --work-dir=$(work_dir) --config=config32.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed" + +wally64: + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + rsync -a $(work_dir)/rv64i_m/ $(wally_workdir)/rv64i_m/ || echo "error suppressed" + +wally32e: + riscof run --work-dir=$(work_dir) --config=config32e.ini --suite=$(wally_dir)/riscv-test-suite/ --env=$(wally_dir)/riscv-test-suite/env --no-browser --no-dut-run + rsync -a $(work_dir)/rv32i_m/ $(wally_workdir)/rv32i_m/ || echo "error suppressed" + rsync -a $(work_dir)/rv32e_unratified/ $(wally_workdir)/rv32e_unratified/ || echo "error suppressed" + + +memfile: + find $(work) -type f -name "*.elf" | grep "rv64i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 64 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf" | grep "rv32i_m" | while read f; do riscv64-unknown-elf-elf2hex --bit-width 32 --input "$$f" --output "$$f.memfile"; done + find $(work) -type f -name "*.elf.objdump" | while read f; do extractFunctionRadix.sh $$f; done + +clean: + rm -f config64.ini + rm -f config32.ini + rm -f config32e.ini + rm -rf $(work_dir) + rm -rf $(wally_workdir) + rm -rf $(arch_workdir) diff --git a/tests/riscof/config.ini b/tests/riscof/config.ini new file mode 100644 index 000000000..ae5a2f13b --- /dev/null +++ b/tests/riscof/config.ini @@ -0,0 +1,14 @@ +[RISCOF] +ReferencePlugin=sail_cSim +ReferencePluginPath={0}/sail_cSim +DUTPlugin=spike +DUTPluginPath={0}/spike + +[spike] +pluginpath={0}/spike +ispec={0}/spike/spike_rv{1}_isa.yaml +pspec={0}/spike/spike_platform.yaml +target_run=1 + +[sail_cSim] +pluginpath={0}/sail_cSim diff --git a/tests/riscof/sail_cSim/__init__.py b/tests/riscof/sail_cSim/__init__.py new file mode 100644 index 000000000..0bfb5a62b --- /dev/null +++ b/tests/riscof/sail_cSim/__init__.py @@ -0,0 +1,2 @@ +from pkgutil import extend_path +__path__ = extend_path(__path__, __name__) \ No newline at end of file diff --git a/tests/riscof/sail_cSim/env/link.ld b/tests/riscof/sail_cSim/env/link.ld new file mode 100644 index 000000000..8ad95e049 --- /dev/null +++ b/tests/riscof/sail_cSim/env/link.ld @@ -0,0 +1,18 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .data.string : { *(.data.string)} + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/riscof/sail_cSim/env/model_test.h b/tests/riscof/sail_cSim/env/model_test.h new file mode 100644 index 000000000..be07d625d --- /dev/null +++ b/tests/riscof/sail_cSim/env/model_test.h @@ -0,0 +1,55 @@ +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H + +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t0; \ + j write_tohost; + +#define RVMODEL_BOOT + +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + RVMODEL_DATA_SECTION \ + .align 4;\ + .global begin_signature; begin_signature: + +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4; .global end_signature; end_signature: + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#define RVMODEL_SET_MSW_INT + +#define RVMODEL_CLEAR_MSW_INT + +#define RVMODEL_CLEAR_MTIMER_INT + +#define RVMODEL_CLEAR_MEXT_INT + + +#endif // _COMPLIANCE_MODEL_H diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py new file mode 100644 index 000000000..aa32757ca --- /dev/null +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -0,0 +1,132 @@ +import os +import re +import shutil +import subprocess +import shlex +import logging +import random +import string +from string import Template + +import riscof.utils as utils +from riscof.pluginTemplate import pluginTemplate +import riscof.constants as constants +from riscv_isac.isac import isac + +logger = logging.getLogger() + +class sail_cSim(pluginTemplate): + __model__ = "sail_c_simulator" + __version__ = "0.5.0" + + def __init__(self, *args, **kwargs): + sclass = super().__init__(*args, **kwargs) + + config = kwargs.get('config') + if config is None: + logger.error("Config node for sail_cSim missing.") + raise SystemExit(1) + self.num_jobs = str(config['jobs'] if 'jobs' in config else 1) + self.pluginpath = os.path.abspath(config['pluginpath']) + self.sail_exe = { '32' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV32"), + '64' : os.path.join(config['PATH'] if 'PATH' in config else "","riscv_sim_RV64")} + self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else '' + self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else '' + self.make = config['make'] if 'make' in config else 'make' + logger.debug("SAIL CSim plugin initialised using the following configuration.") + for entry in config: + logger.debug(entry+' : '+config[entry]) + return sclass + + def initialise(self, suite, work_dir, archtest_env): + self.suite = suite + self.work_dir = work_dir + self.objdump_cmd = 'riscv64-unknown-elf-objdump -D {0} > {2};' + self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \ + -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles\ + -T '+self.pluginpath+'/env/link.ld\ + -I '+self.pluginpath+'/env/\ + -I ' + archtest_env + + def build(self, isa_yaml, platform_yaml): + ispec = utils.load_yaml(isa_yaml)['hart0'] + self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') + self.isa = 'rv' + self.xlen + self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) + if "I" in ispec["ISA"]: + self.isa += 'i' + if "M" in ispec["ISA"]: + self.isa += 'm' + if "C" in ispec["ISA"]: + self.isa += 'c' + if "F" in ispec["ISA"]: + self.isa += 'f' + if "D" in ispec["ISA"]: + self.isa += 'd' + objdump = "riscv64-unknown-elf-objdump".format(self.xlen) + if shutil.which(objdump) is None: + logger.error(objdump+": executable not found. Please check environment setup.") + raise SystemExit(1) + compiler = "riscv64-unknown-elf-gcc".format(self.xlen) + if shutil.which(compiler) is None: + logger.error(compiler+": executable not found. Please check environment setup.") + raise SystemExit(1) + if shutil.which(self.sail_exe[self.xlen]) is None: + logger.error(self.sail_exe[self.xlen]+ ": executable not found. Please check environment setup.") + raise SystemExit(1) + if shutil.which(self.make) is None: + logger.error(self.make+": executable not found. Please check environment setup.") + raise SystemExit(1) + + + def runTests(self, testList, cgf_file=None): + if os.path.exists(self.work_dir+ "/Makefile." + self.name[:-1]): + os.remove(self.work_dir+ "/Makefile." + self.name[:-1]) + make = utils.makeUtil(makefilePath=os.path.join(self.work_dir, "Makefile." + self.name[:-1])) + make.makeCommand = self.make + ' -j' + self.num_jobs + for file in testList: + testentry = testList[file] + test = testentry['test_path'] + test_dir = testentry['work_dir'] + test_name = test.rsplit('/',1)[1][:-2] + + elf = 'ref.elf' + + execute = "@cd "+testentry['work_dir']+";" + + cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 1), self.xlen) + ' ' + test + ' -o ' + elf + compile_cmd = cmd + ' -D' + " -D".join(testentry['macros']) + execute+=compile_cmd+";" + + execute += self.objdump_cmd.format(elf, self.xlen, 'ref.elf.objdump') + sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") + + # Check if the tests can be run on SAIL + if ('NO_SAIL=True' in testentry['macros']): + # if the tests can't run on SAIL we copy the reference output to the src directory + reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) + execute += 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying + else: + execute += self.sail_exe[self.xlen] + ' -z268435455 -i --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name) + + cov_str = ' ' + for label in testentry['coverage_labels']: + cov_str+=' -l '+label + + if cgf_file is not None: + coverage_cmd = 'riscv_isac --verbose info coverage -d \ + -t {0}.log --parser-name c_sail -o coverage.rpt \ + --sig-label begin_signature end_signature \ + --test-label rvtest_code_begin rvtest_code_end \ + -e ref.elf -c {1} -x{2} {3};'.format(\ + test_name, ' -c '.join(cgf_file), self.xlen, cov_str) + else: + coverage_cmd = '' + + + execute+=coverage_cmd + + make.add_target(execute) +# make.execute_all(self.work_dir) +# DH 7/26/22 increase timeout so sim will finish on slow machines + make.execute_all(self.work_dir, timeout = 1800) diff --git a/tests/riscof/spike/env/link.ld b/tests/riscof/spike/env/link.ld new file mode 100644 index 000000000..8ad95e049 --- /dev/null +++ b/tests/riscof/spike/env/link.ld @@ -0,0 +1,18 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(rvtest_entry_point) + +SECTIONS +{ + . = 0x80000000; + .text.init : { *(.text.init) } + . = ALIGN(0x1000); + .tohost : { *(.tohost) } + . = ALIGN(0x1000); + .text : { *(.text) } + . = ALIGN(0x1000); + .data : { *(.data) } + .data.string : { *(.data.string)} + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/riscof/spike/env/model_test.h b/tests/riscof/spike/env/model_test.h new file mode 100644 index 000000000..3890c4985 --- /dev/null +++ b/tests/riscof/spike/env/model_test.h @@ -0,0 +1,60 @@ +#ifndef _COMPLIANCE_MODEL_H +#define _COMPLIANCE_MODEL_H +#define RVMODEL_DATA_SECTION \ + .pushsection .tohost,"aw",@progbits; \ + .align 8; .global tohost; tohost: .dword 0; \ + .align 8; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 8; .global begin_regstate; begin_regstate: \ + .word 128; \ + .align 8; .global end_regstate; end_regstate: \ + .word 4; + +//RV_COMPLIANCE_HALT +#define RVMODEL_HALT \ + li x1, 1; \ + write_tohost: \ + sw x1, tohost, t0; \ + j write_tohost; + +#define RVMODEL_BOOT + +//RV_COMPLIANCE_DATA_BEGIN +#define RVMODEL_DATA_BEGIN \ + RVMODEL_DATA_SECTION \ + .align 4;\ + .global begin_signature; begin_signature: + +//RV_COMPLIANCE_DATA_END +#define RVMODEL_DATA_END \ + .align 4;\ + .global end_signature; end_signature: + +//RVTEST_IO_INIT +#define RVMODEL_IO_INIT +//RVTEST_IO_WRITE_STR +#define RVMODEL_IO_WRITE_STR(_R, _STR) +//RVTEST_IO_CHECK +#define RVMODEL_IO_CHECK() +//RVTEST_IO_ASSERT_GPR_EQ +#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I) +//RVTEST_IO_ASSERT_SFPR_EQ +#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I) +//RVTEST_IO_ASSERT_DFPR_EQ +#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I) + +#define RVMODEL_SET_MSW_INT \ + li t1, 1; \ + li t2, 0x2000000; \ + sw t1, 0(t2); + +#define RVMODEL_CLEAR_MSW_INT \ + li t2, 0x2000000; \ + sw x0, 0(t2); + +#define RVMODEL_CLEAR_MTIMER_INT + +#define RVMODEL_CLEAR_MEXT_INT + + +#endif // _COMPLIANCE_MODEL_H diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py new file mode 100644 index 000000000..d7d65c0b3 --- /dev/null +++ b/tests/riscof/spike/riscof_spike.py @@ -0,0 +1,261 @@ +import os +import re +import shutil +import subprocess +import shlex +import logging +import random +import string +from string import Template +import sys + +import riscof.utils as utils +import riscof.constants as constants +from riscof.pluginTemplate import pluginTemplate + +logger = logging.getLogger() + +class spike(pluginTemplate): + __model__ = "spike" + + #TODO: please update the below to indicate family, version, etc of your DUT. + __version__ = "XXX" + + def __init__(self, *args, **kwargs): + sclass = super().__init__(*args, **kwargs) + + config = kwargs.get('config') + + # If the config node for this DUT is missing or empty. Raise an error. At minimum we need + # the paths to the ispec and pspec files + if config is None: + print("Please enter input file paths in configuration.") + raise SystemExit(1) + + # In case of an RTL based DUT, this would be point to the final binary executable of your + # test-bench produced by a simulator (like verilator, vcs, incisive, etc). In case of an iss or + # emulator, this variable could point to where the iss binary is located. If 'PATH variable + # is missing in the config.ini we can hardcode the alternate here. + self.dut_exe = os.path.join(config['PATH'] if 'PATH' in config else "","spike") + + # Number of parallel jobs that can be spawned off by RISCOF + # for various actions performed in later functions, specifically to run the tests in + # parallel on the DUT executable. Can also be used in the build function if required. + self.num_jobs = str(config['jobs'] if 'jobs' in config else 1) + + # Path to the directory where this python file is located. Collect it from the config.ini + self.pluginpath=os.path.abspath(config['pluginpath']) + + # Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose + # to hardcode these here itself instead of picking it from the config.ini file. + self.isa_spec = os.path.abspath(config['ispec']) + self.platform_spec = os.path.abspath(config['pspec']) + + #We capture if the user would like the run the tests on the target or + #not. If you are interested in just compiling the tests and not running + #them on the target, then following variable should be set to False + if 'target_run' in config and config['target_run']=='0': + self.target_run = False + else: + self.target_run = True + + # Return the parameters set above back to RISCOF for further processing. + return sclass + + def initialise(self, suite, work_dir, archtest_env): + + # capture the working directory. Any artifacts that the DUT creates should be placed in this + # directory. Other artifacts from the framework and the Reference plugin will also be placed + # here itself. + self.work_dir = work_dir + + # capture the architectural test-suite directory. + self.suite_dir = suite + + # Note the march is not hardwired here, because it will change for each + # test. Similarly the output elf name and compile macros will be assigned later in the + # runTests function + self.compile_cmd = 'riscv64-unknown-elf-gcc -march={0} \ + -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g\ + -T '+self.pluginpath+'/env/link.ld\ + -I '+self.pluginpath+'/env/\ + -I ' + archtest_env + ' {2} -o {3} {4}' + + # add more utility snippets here + + def build(self, isa_yaml, platform_yaml): + + # load the isa yaml as a dictionary in python. + ispec = utils.load_yaml(isa_yaml)['hart0'] + + # capture the XLEN value by picking the max value in 'supported_xlen' field of isa yaml. This + # will be useful in setting integer value in the compiler string (if not already hardcoded); + self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32') + + # for spike start building the '--isa' argument. the self.isa is dutnmae specific and may not be + # useful for all DUTs + self.isa = 'rv' + self.xlen + if "I" in ispec["ISA"]: + self.isa += 'i' + if "M" in ispec["ISA"]: + self.isa += 'm' + if "F" in ispec["ISA"]: + self.isa += 'f' + if "D" in ispec["ISA"]: + self.isa += 'd' + if "C" in ispec["ISA"]: + self.isa += 'c' + + #TODO: The following assumes you are using the riscv-gcc toolchain. If + # not please change appropriately + self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 ')) + + def runTests(self, testList): + + # Delete Makefile if it already exists. + if os.path.exists(self.work_dir+ "/Makefile." + self.name[:-1]): + os.remove(self.work_dir+ "/Makefile." + self.name[:-1]) + # create an instance the makeUtil class that we will use to create targets. + make = utils.makeUtil(makefilePath=os.path.join(self.work_dir, "Makefile." + self.name[:-1])) + + # set the make command that will be used. The num_jobs parameter was set in the __init__ + # function earlier + make.makeCommand = 'make -j' + self.num_jobs + + # we will iterate over each entry in the testList. Each entry node will be refered to by the + # variable testname. + for testname in testList: + + # for each testname we get all its fields (as described by the testList format) + testentry = testList[testname] + + # we capture the path to the assembly file of this test + test = testentry['test_path'] + + # capture the directory where the artifacts of this test will be dumped/created. RISCOF is + # going to look into this directory for the signature files + test_dir = testentry['work_dir'] + + # name of the elf file after compilation of the test + elf = 'my.elf' + + # name of the signature file as per requirement of RISCOF. RISCOF expects the signature to + # be named as DUT-.signature. The below variable creates an absolute path of + # signature file. + sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") + + # for each test there are specific compile macros that need to be enabled. The macros in + # the testList node only contain the macros/values. For the gcc toolchain we need to + # prefix with "-D". The following does precisely that. + compile_macros= ' -D' + " -D".join(testentry['macros']) + + # substitute all variables in the compile command that we created in the initialize + # function + cmd = self.compile_cmd.format(testentry['isa'].lower().replace('zicsr', ' ', 2), self.xlen, test, elf, compile_macros) + + # if the user wants to disable running the tests and only compile the tests, then + # the "else" clause is executed below assigning the sim command to simple no action + # echo statement. + if self.target_run: + # set up the simulation command. Template is for spike. Please change. + if ('NO_SAIL=True' in testentry['macros']): + # if the tests can't run on SAIL we copy the reference output to the src directory + reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test)) + simcmd = 'cut -c-{0:g} {1} > {2}'.format(8, reference_output, sig_file) #use cut to remove comments when copying + else: + simcmd = self.dut_exe + ' --isa={0} +signature={1} +signature-granularity=4 {2}'.format(self.isa, sig_file, elf) + else: + simcmd = 'echo "NO RUN"' + + # concatenate all commands that need to be executed within a make-target. + execute = '@cd {0}; {1}; {2};'.format(testentry['work_dir'], cmd, simcmd) + + # create a target. The makeutil will create a target with the name "TARGET" where num + # starts from 0 and increments automatically for each new target that is added + make.add_target(execute) + + # if you would like to exit the framework once the makefile generation is complete uncomment the + # following line. Note this will prevent any signature checking or report generation. + #raise SystemExit + + # once the make-targets are done and the makefile has been created, run all the targets in + # parallel using the make command set above. + #make.execute_all(self.work_dir) + # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines + make.execute_all(self.work_dir, timeout = 1800) + + + # if target runs are not required then we simply exit as this point after running all + # the makefile targets. + if not self.target_run: + raise SystemExit(0) + +#The following is an alternate template that can be used instead of the above. +#The following template only uses shell commands to compile and run the tests. + +# def runTests(self, testList): +# +# # we will iterate over each entry in the testList. Each entry node will be referred to by the +# # variable testname. +# for testname in testList: +# +# logger.debug('Running Test: {0} on DUT'.format(testname)) +# # for each testname we get all its fields (as described by the testList format) +# testentry = testList[testname] +# +# # we capture the path to the assembly file of this test +# test = testentry['test_path'] +# +# # capture the directory where the artifacts of this test will be dumped/created. +# test_dir = testentry['work_dir'] +# +# # name of the elf file after compilation of the test +# elf = 'my.elf' +# +# # name of the signature file as per requirement of RISCOF. RISCOF expects the signature to +# # be named as DUT-.signature. The below variable creates an absolute path of +# # signature file. +# sig_file = os.path.join(test_dir, self.name[:-1] + ".signature") +# +# # for each test there are specific compile macros that need to be enabled. The macros in +# # the testList node only contain the macros/values. For the gcc toolchain we need to +# # prefix with "-D". The following does precisely that. +# compile_macros= ' -D' + " -D".join(testentry['macros']) +# +# # collect the march string required for the compiler +# marchstr = testentry['isa'].lower() +# +# # substitute all variables in the compile command that we created in the initialize +# # function +# cmd = self.compile_cmd.format(marchstr, self.xlen, test, elf, compile_macros) +# +# # just a simple logger statement that shows up on the terminal +# logger.debug('Compiling test: ' + test) +# +# # the following command spawns a process to run the compile command. Note here, we are +# # changing the directory for this command to that pointed by test_dir. If you would like +# # the artifacts to be dumped else where change the test_dir variable to the path of your +# # choice. +# utils.shellCommand(cmd).run(cwd=test_dir) +# +# # for debug purposes if you would like stop the DUT plugin after compilation, you can +# # comment out the lines below and raise a SystemExit +# +# if self.target_run: +# # build the command for running the elf on the DUT. In this case we use spike and indicate +# # the isa arg that we parsed in the build stage, elf filename and signature filename. +# # Template is for spike. Please change for your DUT +# execute = self.dut_exe + ' --isa={0} +signature={1} +signature-granularity=4 {2}'.format(self.isa, sig_file, elf) +# logger.debug('Executing on Spike ' + execute) +# +# # launch the execute command. Change the test_dir if required. +# utils.shellCommand(execute).run(cwd=test_dir) +# +# # post-processing steps can be added here in the template below +# #postprocess = 'mv {0} temp.sig'.format(sig_file)' +# #utils.shellCommand(postprocess).run(cwd=test_dir) +# +# # if target runs are not required then we simply exit as this point after running all +# # the makefile targets. +# if not self.target_run: +# raise SystemExit diff --git a/tests/riscof/spike/spike_platform.yaml b/tests/riscof/spike/spike_platform.yaml new file mode 100644 index 000000000..8e1a3d8e3 --- /dev/null +++ b/tests/riscof/spike/spike_platform.yaml @@ -0,0 +1,10 @@ +mtime: + implemented: true + address: 0xbff8 +mtimecmp: + implemented: true + address: 0x4000 +nmi: + label: nmi_vector +reset: + label: reset_vector diff --git a/tests/riscof/spike/spike_rv32e_isa.yaml b/tests/riscof/spike/spike_rv32e_isa.yaml new file mode 100644 index 000000000..7ae54347a --- /dev/null +++ b/tests/riscof/spike/spike_rv32e_isa.yaml @@ -0,0 +1,29 @@ +hart_ids: [0] +hart0: + ISA: RV32EMFCZicsr_Zifencei + physical_addr_sz: 32 + User_Spec_Version: '2.3' + supported_xlen: [32] + misa: + reset-val: 0x40001034 + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x1] + wr_illegal: + - Unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x0001034, 0x0000000] + wr_illegal: + - Unchanged + diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml new file mode 100644 index 000000000..04a5da180 --- /dev/null +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -0,0 +1,28 @@ +hart_ids: [0] +hart0: + ISA: RV32IMAFDCZicsr_Zifencei + physical_addr_sz: 32 + User_Spec_Version: '2.3' + supported_xlen: [32] + misa: + reset-val: 0x4000112D + rv32: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x1] + wr_illegal: + - Unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x000112D, 0x0000000] + wr_illegal: + - Unchanged \ No newline at end of file diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml new file mode 100644 index 000000000..d3dad15c4 --- /dev/null +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -0,0 +1,31 @@ +hart_ids: [0] +hart0: + ISA: RV64IMAFDCSUZicsr_Zifencei + physical_addr_sz: 56 + User_Spec_Version: '2.3' + supported_xlen: [64] + misa: + reset-val: 0x800000000014112D + rv32: + accessible: false + rv64: + accessible: true + mxl: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - mxl[1:0] in [0x2] + wr_illegal: + - Unchanged + extensions: + implemented: true + type: + warl: + dependency_fields: [] + legal: + - extensions[25:0] bitmask [0x014112D, 0x0000000] + wr_illegal: + - Unchanged + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h index 286a64744..4ae101822 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/env/arch_test.h @@ -11,7 +11,7 @@ // #define rvtest_gpr_save // #endif -#define TEST_CASE_1 +// #define TEST_CASE_1 //----------------------------------------------------------------------- // RV Arch Test Macros @@ -95,14 +95,14 @@ #endif #endif -#if XLEN==64 - #if FLEN==32 - #define SREG sw - #define LREG lW - #define REGWIDTH 4 - #define MASK 0xFFFFFFFF - #endif -#endif +// #if XLEN==64 +// #if FLEN==32 +// #define SREG sw +// #define LREG lW +// #define REGWIDTH 4 +// #define MASK 0xFFFFFFFF +// #endif +// #endif #define MMODE_SIG 3 #define RLENG (REGWIDTH<<3) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld.reference_output new file mode 100644 index 000000000..ab5658348 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/references/WALLY-fld.reference_output @@ -0,0 +1,3 @@ +00000000 +40000000 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S new file mode 100644 index 000000000..79b1c963e --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S @@ -0,0 +1,81 @@ +/////////////////////////////////////////// +// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S +// David_Harris@hmc.edu & Katherine Parry +// Created 2022-07-07 16:55:21.991349// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "model_test.h" +#include "arch_test.h" + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_FP_ENABLE() +RVTEST_VALBASEUPD(x7,test_fp) +RVTEST_SIGBASE( x6, wally_signature) +RVTEST_ISA("RV32IFD") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*F.*D.*);def TEST_CASE_1=True;",WALLY-fld) +inst_0: + li x1,2 + fcvt.d.w f3, x1 + la x16, rvtest_data + fsd f3,0(x16) + fld f4,0(x16) + fsd f4,0(x6) + + #endif + +.EQU NUMTESTS,3 + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0x98765432 +.word 0x55555555 +test_fp: +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN + + +wally_signature: + .fill NUMTESTS*(XLEN/32),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine + +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef + +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*(XLEN/32),4,0xdeadbeef + +#endif + +RVMODEL_DATA_END +// ../../wally-riscv-arch-test/riscv-test-suite/rv32i_m/D/src/WALLY-fld.S +// David_Harris@hmc.edu & Katherine Parry diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S index 98916a7c0..9b6561514 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-ADD.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.392776// +// Created 2022-06-17 22:58:09.906970// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -27,6 +28,7 @@ RVMODEL_BOOT RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) # Testcase 0: rs1:x28(0x00000000), rs2:x13(0x00000000), result rd:x25(0x00000000) li x28, MASK_XLEN(0x00000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S index c65543d05..10e5bc509 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLT.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393471// +// Created 2022-06-17 22:58:09.909889// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt) + # Testcase 0: rs1:x11(0x00000000), rs2:x8(0x00000000), result rd:x24(0x00000000) li x11, MASK_XLEN(0x00000000) li x8, MASK_XLEN(0x00000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S index f91493d31..aa080daf9 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SLTU.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393741// +// Created 2022-06-17 22:58:09.911056// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu) + # Testcase 0: rs1:x20(0x00000000), rs2:x26(0x00000000), result rd:x13(0x00000000) li x20, MASK_XLEN(0x00000000) li x26, MASK_XLEN(0x00000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S index e4653f209..b7f5fa299 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-SUB.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.393180// +// Created 2022-06-17 22:58:09.908718// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -26,6 +27,8 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub) + RVTEST_SIGBASE( x6, wally_signature) # Testcase 0: rs1:x3(0x00000000), rs2:x29(0x00000000), result rd:x28(0x00000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S index d531f14d0..ea658637d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-XOR.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394013// +// Created 2022-06-17 22:58:09.913218// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor) + # Testcase 0: rs1:x14(0x00000000), rs2:x19(0x00000000), result rd:x9(0x00000000) li x14, MASK_XLEN(0x00000000) li x19, MASK_XLEN(0x00000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index 3b530f755..23806cf67 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -36,6 +36,9 @@ rv32i_sc_tests = \ WALLY-misa-01 \ WALLY-amo \ WALLY-lrsc \ + WALLY-status-mie-01 \ + WALLY-trap-sret-01 \ + target_tests_nosim = \ WALLY-pma \ @@ -43,15 +46,18 @@ target_tests_nosim = \ WALLY-stvec-01 \ WALLY-mie-01 \ WALLY-sie-01 \ - WALLY-status-mie-01 \ - WALLY-status-sie-01 \ - WALLY-trap-sret-01 \ WALLY-trap-01 \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ - WALLY-status-tw-01 \ WALLY-wfi-01 \ WALLY-status-fp-enabled-01 \ + WALLY-status-sie-01 \ + WALLY-status-tw-01 \ + WALLY-gpio-01 \ + WALLY-clint-01 \ + WALLY-plic-01 \ + WALLY-uart-01 \ + rv32i_tests = $(addsuffix .elf, $(rv32i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-clint-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-clint-01.reference_output new file mode 100644 index 000000000..013ef4604 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-clint-01.reference_output @@ -0,0 +1,9 @@ +00000000 # msip zero on reset +00000000 # mip is zero +00000008 # mip msip bit is set +00000000 # mip msip bit is reset +00000000 # mip mtip bit is reset +FFFFFFFF # mtimecmp is same as written value +A5A5A5A5 # mtimecmph is same as written value +00000000 # mip mtip is zero +00000080 # mip mtip is set diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output new file mode 100644 index 000000000..509d4e9e1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-gpio-01.reference_output @@ -0,0 +1,41 @@ +00000000 # reset to zero tests: input_val +00000000 # input_en +00000000 # output_en +00000000 # output_val +00000000 # rise_ie +00000000 # fall_ie +00000000 # low_ie +00000000 # high_ie +00000000 # rise_ip +00000000 # fall_ip +00000000 # high_ip +ffffffff # low_ip +00000000 # out_xor +A5A5A5A5 # test output pins +5A5AFFFF +00000000 # test input enables +5A5A0000 +A55A0000 # test XOR +A55A0000 # Test interrupt pending bits: high_ip +5AA5FFFF # low_ip +00000000 # rise_ip +00000000 # fall_ip +A4AA0000 # input_val +A5FA0000 # high_ip +5BF5FFFF # low_ip +00A00000 # rise_ip +01500000 # fall_ip +00000000 # MEIP +00000000 # Test interrupts can be enabled without being triggered: MIP = 0 +00000000 # MIP = 0 +00000000 # MIP = 0 +00000000 # MIP = 0 +00000800 # Test interrupts can be enabled and triggered: MEIP set from high_ie +00000000 # MEIP = 0 +00000800 # MEIP set from low_ie +00000000 # MEIP = 0 +00000800 # MEIP set from rise_ie +00000000 # MEIP = 0 +00000800 # MEIP set from fall_ie +00000000 # MEIP = 0 + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output new file mode 100644 index 000000000..6d3b051b1 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-01.reference_output @@ -0,0 +1,249 @@ +00000000 # read empty MIP (1.0.0) +00000008 # check GPIO interrupt pending on intPending0 +00000000 # Claim gives no interrupt due to zero priority +00000008 # interrupt still pending due to no claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.0.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000000 # read empty MIP (1.0.2) +00000000 # check GPIO interrupt pending on intPending0 +00000000 # claim gives no interrupt due to no intPending +00000000 # no interrupts pending after clear +00000000 # still no interrupts after clear +00000000 # read empty MIP (1.1.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # interrupt still pending due to no claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.1.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.2.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.2.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.3.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.3.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.4.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.4.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.5.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.5.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.6.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set due to PLIC priority (1.6.1) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000000 # read empty MIP (1.7.0) +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim gives 3 for ID of GPIO +00000000 # check no interrupts pending after claim +00000000 # check no interrupts pending +00000800 # MEIP set (2.0) +00000408 # gpio and uart pending +00000003 # claim gpio +00000400 # gpio no longer pending +00000000 # no interrupts pending +00000800 # MEIP set (2.1) +00000408 # gpio and uart pending +00000003 # claim gpio +00000400 # gpio no longer pending +00000000 # no interrupts pending +00000800 # MEIP set (2.2) +00000408 # gpio and uart pending +0000000A # claim uart +00000008 # uart no longer pending +00000000 # no interrupts pending +00000800 # MEIP set (2.3) +00000408 # gpio and uart pending +0000000A # claim uart +00000008 # uart no longer pending +00000000 # no interrupts pending +00000000 # MEIP empty (2.4) +00000408 # gpio and uart pending +0000000A # claim none +00000008 # gpio and uart still pending +00000000 # no interrupts pending +00000A00 # MEIP and SEIP set (3.0) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000200 # SEIP set (3.1) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000200 # SEIP set (3.2) +00000408 # check GPIO and UART interrupt pending on intPending0 +0000000A # claim UART +00000008 # GPIO interrupt pending after UART claimcomp +00000000 # check no interrupts pending +00000000 # read empty MIP (3.3) +00000408 # check GPIO and UART interrupt pending on intPending0 +0000000A # claim UART +00000008 # check UART interrupt pending cleared after claim +00000000 # check no interrupts pending +00000A00 # MEIP and SEIP set (4.0) +00000400 # UART interrupt pending +0000000A # claim UART +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000200 # SEIP set (4.1) +00000400 # UART interrupt pending +00000000 # nothing in claim register +00000400 # UART interrupt pending +00000000 # check no interrupts pending +00000A00 # MEIP and SEIP set (4.2) +00000400 # UART interrupt pending +0000000A # claim UART +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000800 # MEIP set (4.3) +00000400 # UART interrupt pending +0000000A # claim UART +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000800 # MEIP set (4.4) +00000400 # UART interrupt pending +0000000A # claim UART +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000200 # SEIP set (4.5) +00000400 # UART interrupt pending +00000000 # nothing in claim register +00000400 # UART interrupt pending +00000000 # check no interrupts pending +00000000 # All disabled (4.6) +00000400 # UART interrupt pending +00000000 # nothing in claim register +00000400 # UART interrupt pending +00000000 # check no interrupts pending +00000200 # SEIP set (5.0) +00000008 # GPIO interrupt pending +00000000 # nothing in claim register +00000008 # GPIO interrupt pending +00000000 # check no interrupts pending +00000A00 # MEIP and SEIP set (5.1) +00000008 # GPIO interrupt pending +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000800 # MEIP set (5.2) +00000008 # GPIO interrupt pending +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000A00 # MEIP and SEIP set (5.3) +00000008 # GPIO interrupt pending +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000800 # MEIP set (5.4) +00000008 # GPIO interrupt pending +00000003 # claim gives 3 for ID of GPIO +00000000 # check no interrupts pending +00000000 # check no interrupts pending +00000200 # SEIP set (5.5) +00000008 # GPIO interrupt pending +00000000 # nothing in claim register +00000008 # GPIO interrupt pending +00000000 # check no interrupts pending +00000000 # read empty MIP (5.6) +00000008 # GPIO interrupt pending +00000000 # nothing in claim register +00000008 # GPIO interrupt pending +00000000 # check no interrupts pending +0000000b # written due to goto_s_mode +00000200 # read sip (7.0) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000200 # read sip (7.1) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000200 # read sip (7.2) +00000408 # check GPIO and UART interrupt pending on intPending0 +0000000A # claim UART +00000008 # GPIO interrupt pending after UART claimcomp +00000000 # check no interrupts pending +00000200 # read sip (7.3) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000000 # read sip (7.4) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 # nothing in claim register +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 # check no interrupts pending +00000200 # read sip (7.5) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000003 # claim gives 3 for ID of GPIO +00000400 # check GPIO interrupt pending cleared after claim +00000000 # check no interrupts pending +00000000 # read sip (7.6) +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 # nothing in claim register +00000408 # check GPIO and UART interrupt pending on intPending0 +00000000 # check no interrupts pending +00000009 # output from ecall in supervisor mode +00000800 # MEIP set (8.0) +00000408 # check GPIO and UART interrupt pending on intPending0 +0000000A # claim UART +00000008 # GPIO interrupt pending after UART claimcomp +00000003 # claim gives 3 for ID of GPIO +00000000 # read empty MIP # no interrupts, meip is low +00000000 # check no interrupts pending +00000800 # MEIP set +00000008 # GPIO interrupt pending after complete +00000003 # claim gives 3 for ID of GPIO +00000000 # read empty MIP # meip is zeroed +00000000 # check no interrupts pending +00000800 # MEIP set +00000400 # check GPIO interrupt pending cleared after claim +00000800 # MEIP set +00000408 # check GPIO and UART interrupt pending on intPending0 +0000000A # claim UART diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output new file mode 100644 index 000000000..007e6b892 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-plic-s-01.reference_output @@ -0,0 +1,45 @@ +0000000b # ecall for change to supervisor mode + +00000200 # 1.1: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000200 # 1.2: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000000 # 1.3: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000000 # No claim +00000008 # Interrupt unclaimed and still pending +00000000 # No interrupts pending + +00000000 # 1.4: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000000 # No claim +00000008 # Interrupt unclaimed and still pending +00000000 # No interrupts pending + +00000000 # 1.5: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context even though it is masked by priority +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000200 # 1.6: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Claim GPIO in supervisor context +00000000 # No interrupts pending +00000000 # No interrupts pending + +00000000 # 1.7: read SIP with supervisor interrupt +00000008 # check GPIO interrupt pending on intPending0 +00000003 # Glaim GPIO in supervisor conxtex even though it is masked by priority +00000000 # No interrupts pending +00000000 # No interrupts pending + + diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output index a9cdc3633..15626485b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma.reference_output @@ -1018,3 +1018,7 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output index 18d33c0d3..bb0290716 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output @@ -1013,3 +1013,12 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output index ba197a523..e6297f1e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-sie-01.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output index f37485d3a..f41585309 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-status-tw-01.reference_output @@ -1013,3 +1013,12 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index 23bdf7233..2877f4a8e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -6,16 +6,16 @@ 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -80000168 # mtval of breakpoint instruction adress +8000015c # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000171 # mtval of misaligned address +80000165 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -80000189 # mtval of address with misaligned store instr +8000017d # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) @@ -62,16 +62,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # mtval of faulting instruction (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000003 # mcause from Breakpoint -80000168 # mtval of breakpoint instruction adress +8000015c # mtval of breakpoint instruction adress 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000004 # mcause from load address misaligned -80000171 # mtval of misaligned address +80000165 # mtval of misaligned address 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000005 # mcause from load access 00000000 # mtval of accessed adress (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000006 # mcause from store misaligned -80000189 # mtval of address with misaligned store instr +8000017d # mtval of address with misaligned store instr 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000007 # mcause from store access 00000000 # mtval of accessed address (0x0) @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 896467ecd..089aeba9d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +8000015c # stval of breakpoint instruction adress 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000171 # stval of misaligned address +80000165 # stval of misaligned address 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -80000189 # stval of address with misaligned store instr +8000017d # stval of address with misaligned store instr 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -64,16 +64,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +8000015c # stval of breakpoint instruction adress 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000171 # stval of misaligned address +80000165 # stval of misaligned address 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -80000189 # stval of address with misaligned store instr +8000017d # stval of address with misaligned store instr 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 85e666b54..22699f42f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -9,16 +9,16 @@ 00000000 # stval of faulting instruction (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +8000015c # stval of breakpoint instruction adress 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000004 # scause from load address misaligned -80000171 # stval of misaligned address +80000165 # stval of misaligned address 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000006 # scause from store misaligned -80000189 # stval of address with misaligned store instr +8000017d # stval of address with misaligned store instr 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -57,16 +57,16 @@ fffff7ff # medeleg after attempted write of all 1's (only some bits are writeabl 00000000 # stval of faulting instruction (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000003 # scause from Breakpoint -80000168 # stval of breakpoint instruction adress +8000015c # stval of breakpoint instruction adress 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000004 # scause from load address misaligned -80000171 # stval of misaligned address +80000165 # stval of misaligned address 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000005 # scause from load access 00000000 # stval of accessed adress (0x0) 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000006 # scause from store misaligned -80000189 # stval of address with misaligned store instr +8000017d # stval of address with misaligned store instr 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000007 # scause from store access 00000000 # stval of accessed address (0x0) @@ -1016,3 +1016,9 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output new file mode 100644 index 000000000..7b4c916c7 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-uart-01.reference_output @@ -0,0 +1,75 @@ +00000000 # Reset tests +00000001 # 00000000 *** commented because LCR should reset to zero but resets to 3 due to the FPGA +00000000 +00000060 +00000000 +00000060 # read-write test +00000020 # transmitter register empty but shift register not +00000101 # transmitter is not empty when done transmitting 5 bits +00000000 +00000060 +00000101 # Multi-bit transmission: 5 bits +00000015 +00000101 # Transmit 6 bits +0000002A +00000101 # Transmit 7 bits +0000007F +00000101 # Transmit 8 bits +ffffff80 +00000101 # Odd parity +00000079 +00000101 # Even parity +0000006A +00000101 # Extra stop bit +0000005B +00000002 # Transmission interrupt tests +00000401 # Interrupt generated by finished transmission +00000004 +00000006 # IIR return LSR intr and LSR has an overflow error +00000063 +00000004 +00000001 +00000001 # MODEM interrupt tests +00000000 +00000011 +00000001 +00000000 # DSR Test +00000032 +00000001 +00000000 # RI Test +00000034 +00000001 +00000000 # DCD Test +ffffffB8 +00000001 +ffffffC2 # FIFO interrupt +0000C101 +00000000 +ffffffC1 +0000C401 +ffffffA5 +ffffffC1 +00000001 +00000002 +00000061 +00000003 +00000060 +0000C101 +ffffffC1 +00000060 +ffffffC1 # FIFO filling/overrun test +0000C401 # Threshold = 1 +ffffffC1 # Threshold = 4 +0000C101 +0000C401 +ffffffC1 # Threshold = 8 +0000C101 +0000C401 +ffffffC1 # Threshold = 14 +0000C101 +0000C401 +0000C101 +00000061 # FIFO has data, no overrun +00000006 # wait for interrupt +ffffffA3 # FIFO overrun error +0000000b # ecall from test termination diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index a72ae385a..7146e8334 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -26,7 +26,7 @@ .macro INIT_TESTS -RVTEST_ISA("RV32I") +// RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point @@ -152,7 +152,15 @@ cause_s_soft_interrupt: csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. ret +cause_s_soft_from_m_interrupt: + li t3, 0x2 + csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + cause_m_ext_interrupt: + // these interrupts involve a time loop waiting for the interrupt to go off. + // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 + li a3, 0x40 // ========== Configure PLIC ========== // m priority threshold = 0 li t3, 0xC200000 @@ -189,6 +197,9 @@ m_ext_loop: ret cause_s_ext_interrupt_GPIO: + // these interrupts involve a time loop waiting for the interrupt to go off. + // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 + li a3, 0x40 // ========== Configure PLIC ========== // s priority threshold = 0 li t3, 0xC201000 @@ -827,6 +838,28 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a addi a6, a6, 4 .endm +// Place this macro in peripheral tests to setup all the PLIC registers to generate external interrupts +.macro SETUP_PLIC + # Setup PLIC with a series of register writes + + .equ PLIC_INTPRI_GPIO, 0x0C00000C # GPIO is interrupt 3 + .equ PLIC_INTPRI_UART, 0x0C000028 # UART is interrupt 10 + .equ PLIC_INTPENDING0, 0x0C001000 # intPending0 register + .equ PLIC_INTEN00, 0x0C002000 # interrupt enables for context 0 (machine mode) sources 31:1 + .equ PLIC_INTEN10, 0x0C002080 # interrupt enables for context 1 (supervisor mode) sources 31:1 + .equ PLIC_THRESH0, 0x0C200000 # Priority threshold for context 0 (machine mode) + .equ PLIC_CLAIM0, 0x0C200004 # Claim/Complete register for context 0 + .equ PLIC_THRESH1, 0x0C201000 # Priority threshold for context 1 (supervisor mode) + .equ PLIC_CLAIM1, 0x0C201004 # Claim/Complete register for context 1 + + .4byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts + .4byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts + .4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority + .4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority + .4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode + .4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode +.endm + .macro END_TESTS // invokes one final ecall to return to machine mode then terminates this program, so the output is // 0x8: termination called from U mode @@ -937,6 +970,128 @@ read08_test: addi a6, a6, 4 j test_loop // go to next test case +read04_test: + // address to read in t3, expected 8 bit value in t4 (unused, but there for your perusal). + li t2, 0xBAD // bad value that will be overwritten on good reads. + lb t2, 0(t3) + andi t2, t2, 15 // mask lower 4 bits + sw t2, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop // go to next test case + +readmip_test: // read the MIP into the signature + csrr t2, mip + sw t2, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop // go to next test case + +readsip_test: // read the MIP into the signature + csrr t2, sip + sw t2, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop // go to next test case + +claim_m_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002000 + li t3, 0x0C200004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +claim_s_plic_interrupts: // clears one non-pending PLIC interrupt + li t2, 0x0C00000C // GPIO priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C000028 // UART priority + li t3, 7 + lw t4, 0(t2) + sw t3, 0(t2) + sw t4, -4(sp) + addi sp, sp, -4 + li t2, 0x0C002080 + li t3, 0x0C201004 + li t4, 0xFFF + lw t6, 0(t2) // save current enable status + sw t4, 0(t2) // enable all relevant interrupts on PLIC + lw t5, 0(t3) // make PLIC claim + sw t5, 0(t3) // complete claim made + sw t6, 0(t2) // restore saved enable status + li t2, 0x0C00000C // GPIO priority + li t3, 0x0C000028 // UART priority + lw t4, 4(sp) // load stored GPIO and UART priority + lw t5, 0(sp) + addi sp, sp, 8 // restore stack pointer + sw t4, 0(t2) + sw t5, 0(t3) + j test_loop + +uart_lsr_intr_wait: // waits for interrupts to be ready + li t2, 0x10000002 // IIR + li t4, 0x6 +uart_lsr_intr_loop: + lb t3, 0(t2) + andi t3, t3, 0x7 + bne t3, t4, uart_lsr_intr_loop +uart_save_iir_status: + sw t3, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop + +uart_data_wait: + li t2, 0x10000005 // LSR + li t3, 0x10000002 // IIR + li a4, 0x61 +uart_read_LSR_IIR: + lb t4, 0(t3) // save IIR before reading LSR mgith clear it + lb t5, 0(t2) // read LSR + andi t6, t5, 0x61 // wait until all transmissions are done and data is ready + bne a4, t6, uart_read_LSR_IIR + +uart_data_ready: + li t2, 0 + sw t2, 0(t1) // clear entry deadbeef from memory + andi t5, t5, 0x9F // mask THRE and TEMT from signature + sb t4, 1(t1) // IIR + sb t5, 0(t1) // LSR + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop + +uart_clearmodemintr: + li t2, 0x10000006 + lb t2, 0(t2) + j test_loop + goto_s_mode: // return to address in t3, li a0, 3 // Trap handler behavior (go to supervisor mode) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S index 4d4d3fee9..8a1906585 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-amo.S @@ -24,7 +24,8 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") +RVTEST_ISA("RV32IAF") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",amo) .section .text.init .globl rvtest_entry_point diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S new file mode 100644 index 000000000..7aac05823 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-clint-01.S @@ -0,0 +1,95 @@ +/////////////////////////////////////////// +// +// WALLY-gpio +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",clint) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.4byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.4byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define CLINT registers =========== + +.equ CLINT, 0x02000000 +.equ msip, (CLINT+0x00) +.equ mtimecmp, (CLINT+0x4000) # doesn't necessarily reset to zero +.equ mtimecmph,(CLINT+0x4004) +.equ mtime, (CLINT+0xBFF8) # resets to zero but cannot be easily tested +.equ mtimeh, (CLINT+0xBFFC) + +# =========== Verify verifiable registers reset to zero =========== + +.4byte msip, 0x00000000, read32_test # msip reset to zero + +# =========== msip tests =========== + +.4byte msip, 0xFFFFFFFE, write32_test # write to invalid bits of msip +.4byte 0x0, 0x00000000, readmip_test # msip bit should be zero +.4byte msip, 0x00000001, write32_test # set msip to one +.4byte 0x0, 0x00000008, readmip_test # msip bit is set +.4byte msip, 0x00000000, write32_test # set msip to zero +.4byte 0x0, 0x00000000, readmip_test # msip bit is released + +# =========== mtime write tests =========== + +.4byte mtime, 0x00000000, write32_test # test we can write to mtime +.4byte mtimeh, 0x00000000, write32_test # test we can write to mtimeh +.4byte 0x0,0x00000000, readmip_test # mtip bit should be zero + +# =========== mtimecmp tests =========== + +.4byte mtimecmp, 0xFFFFFFFF, write32_test # verify mtimecmp is writable +.4byte mtimecmph, 0xA5A5A5A5, write32_test # verify mtimecmph is writable +.4byte mtimecmp, 0xFFFFFFFF, read32_test # read back value written to mtimecmp +.4byte mtimecmph, 0xA5A5A5A5, read32_test # read back value written to mtimecmph +.4byte mtime, 0xFFFFFFFF, write32_test # write to mtime +.4byte 0x0, 0x00000000, readmip_test # mtip should still be zero +.4byte mtimeh, 0xA5A5A5A6, write32_test # cause mtip to go high by making mtime > mtimecmp +.4byte 0x0, 0x00000080, readmip_test # mtip should be set + +.4byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S index 1df8fa249..a43531cc7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-s) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S index b7d3a78f3..ace47a806 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",csr-permission-u) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S new file mode 100644 index 000000000..21ff79d10 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-gpio-01.S @@ -0,0 +1,164 @@ +/////////////////////////////////////////// +// +// WALLY-gpio +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",gpio) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.4byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.4byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Verify all registers reset to zero =========== + +.4byte input_val, 0x00000000, read32_test # input_val reset to zero +.4byte input_en, 0x00000000, read32_test # input_en reset to zero +.4byte output_en, 0x00000000, read32_test # output_en reset to zero +.4byte output_val, 0x00000000, read32_test # output_val reset to zero +.4byte rise_ie, 0x00000000, read32_test # rise_ie reset to zero +.4byte fall_ie, 0x00000000, read32_test # fall_ie reset to zero +.4byte high_ie, 0x00000000, read32_test # high_ie reset to zero +.4byte low_ie, 0x00000000, read32_test # low_ie reset to zero +.4byte rise_ip, 0x00000000, read32_test # rise_ip reset to zero +.4byte fall_ip, 0x00000000, read32_test # fall_ip reset to zero +.4byte high_ip, 0x00000000, read32_test # high_ip reset to zero +.4byte low_ip, 0xffffffff, read32_test # low_ip reset to ones since all zeroes +.4byte out_xor, 0x00000000, read32_test # out_xor reset to zero + +# =========== Test output and input pins =========== + +.4byte output_en, 0xFFFFFFFF, write32_test # enable all output pins +.4byte output_val, 0xA5A5A5A5, write32_test # write alternating pattern to output pins +.4byte input_en, 0xFFFFFFFF, write32_test # enable all input pins +.4byte input_val, 0xA5A5A5A5, read32_test # read pattern from output pins +.4byte output_val, 0x5A5AFFFF, write32_test # write different pattern to output pins +.4byte input_val, 0x5A5AFFFF, read32_test # read different pattern from output pins + +# =========== Test input enables =========== +.4byte input_en, 0x00000000, write32_test # disable all input pins +.4byte input_val, 0x00000000, read32_test # read 0 since input pins are disabled +.4byte input_en, 0xFFFF0000, write32_test # enable a few input pins +.4byte input_val, 0x5A5A0000, read32_test # read part of pattern set above. + + +# =========== Test XOR functionality =========== +.4byte out_xor, 0xFF00FF00, write32_test # invert certain pin values +.4byte input_val, 0xA55A0000, read32_test # read inverted pins and verify input enable is working + +# =========== Test Interrupt Pending bits =========== + +SETUP_PLIC + +.4byte low_ip, 0xFFFFFFFF, write32_test # clear pending low interrupts +.4byte high_ip, 0xFFFFFFFF, write32_test # clear pending high interrupts +.4byte rise_ip, 0xFFFFFFFF, write32_test # clear pending rise interrupts +.4byte fall_ip, 0xFFFFFFFF, write32_test # clear pending fall interrupts +.4byte high_ip, 0xA55A0000, read32_test # check pending high interrupts +.4byte low_ip, 0x5AA5FFFF, read32_test # check pending low interrupts +.4byte rise_ip, 0x00000000, read32_test # check pending rise interrupts +.4byte fall_ip, 0x00000000, read32_test # check pending fall interrupts +.4byte output_val, 0x5BAA000F, write32_test # change output pattern to check rise/fall interrupts +.4byte input_val, 0xA4AA0000, read32_test # check new output matches expected output +.4byte high_ip, 0xA5FA0000, read32_test # high interrupt pending +.4byte low_ip, 0x5BF5FFFF, read32_test # low interrupt pending should be opposite high for enabled pins +.4byte rise_ip, 0x00A00000, read32_test # check for changed bits (rising) +.4byte fall_ip, 0x01500000, read32_test # check for changed bits (falling) +.4byte 0x0, 0x00000000, readmip_test # Check no external interrupt has been generated + +# =========== Test interrupts can be enabled without being triggered =========== + +.4byte high_ie, 0x00010000, write32_test # enable high interrupt on bit 16, no pending interrupt +.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.4byte low_ie, 0x00020000, write32_test # enable low interrupt on bit 17, no pending interrupt +.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.4byte rise_ie, 0x00010000, write32_test # enable rise interrupt on bit 16, no pending interrupt +.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending +.4byte fall_ie, 0x00010000, write32_test # enable fall interrupt on bit 16, no pending interrupt +.4byte 0x0, 0x00000000, readmip_test # No external interrupt should be pending + +# =========== Test interrupts can be enabled and triggered =========== + +.4byte high_ie, 0x00020000, write32_test # enable high interrupt on bit 17, which is pending +.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.4byte high_ie, 0x00000000, write32_test # disable high interrupt on bit 17 +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.4byte 0x0, 0x00000000, readmip_test # MEIP should be released +.4byte low_ie, 0x00010000, write32_test # enable low interrupt on bit 16, which is pending +.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.4byte low_ie, 0x00000000, write32_test # disable low interrupt on bit 16 +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.4byte 0x0, 0x00000000, readmip_test # MEIP should be released +.4byte rise_ie, 0x00200000, write32_test # enable rise interrupt on bit 21, which is pending +.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.4byte rise_ie, 0x00000000, write32_test # disable rise interrupt on bit 21, which is pending +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.4byte 0x0, 0x00000000, readmip_test # MEIP should be released +.4byte fall_ie, 0x01000000, write32_test # enable high interrupt on bit 24, which is pending +.4byte 0x0, 0x00000800, readmip_test # MEIP should be raised +.4byte fall_ie, 0x00000000, write32_test # disable high interrupt on bit 24, which is pending +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear PLIC pending interrupts +.4byte 0x0, 0x00000000, readmip_test # MEIP should be released + +.4byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S index 4078920bd..2ea73ed35 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-lrsc.S @@ -24,7 +24,8 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") +RVTEST_ISA("RV32IA") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",lrsc) .section .text.init .globl rvtest_entry_point diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S index c48450759..6c91f64fc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mie-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mie) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S index 56bbe5b7c..3a4626b64 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",minfo) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S index e1476eaf7..888011ba6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",misa) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S index df11154dc..3bdd03ad2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mmu-sv32.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",mmu) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S index 5c0f70b2d..e2865be3e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",mtvec) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S new file mode 100644 index 000000000..b5a70625a --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-01.S @@ -0,0 +1,954 @@ +/////////////////////////////////////////// +// +// WALLY-plic +// +// Author: Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.4byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.4byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Define UART registers =========== + +.equ UART, 0x10000000 +.equ UART_IER, (UART+0x01) +.equ UART_MCR, (UART+0x04) +.equ UART_MSR, (UART+0x06) + +# =========== Initialize UART and GPIO =========== + +# GPIO Initialization +.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.4byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.4byte PLIC_INTPRI_GPIO, 0x00000000, write32_test # set GPIO priority to zero +.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to zero +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max + +# =========== Machine-Mode Priority Testing (1.T.X) =========== + +# Test 1.0.0: GPIO int lacks priority (0 = 0) +.4byte PLIC_THRESH0, 0x00000000, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +#.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.1: GPIO int has priority (1 > 0) +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.0.2: meip and c/c clear without interrupt pending +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # expect no interrupt pending +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.0: GPIO lacks priority (1 = 1) +.4byte PLIC_THRESH0, 0x00000001, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.1.1: GPIO int has priority (2 > 1) +.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.0: GPIO int lacks priority (2 = 2) +.4byte PLIC_THRESH0, 0x00000002, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.2.1: GPIO int has priority (3 > 2) +.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.0: GPIO int lacks priority (3 = 3) +.4byte PLIC_THRESH0, 0x00000003, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.3.1: GPIO int has priority (4 > 3) +.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.0: GPIO int lacks priority (4 = 4) +.4byte PLIC_THRESH0, 0x00000004, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.4.1: GPIO int has priority (5 > 4) +.4byte PLIC_INTPRI_GPIO, 0x00000005, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.0: GPIO int lacks priority (5 = 5) +.4byte PLIC_THRESH0, 0x00000005, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.5.1: GPIO int has priority (6 > 5) +.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.0: GPIO int lacks priority (6 = 6) +.4byte PLIC_THRESH0, 0x00000006, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.6.1: GPIO int has priority (7 > 6) +.4byte PLIC_INTPRI_GPIO, 0x00000007, write32_test # let GPIO cause interrupts +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# Test 1.7.0: GPIO int lacks priority (7 = 7) +.4byte PLIC_THRESH0, 0x00000007, write32_test # change threshold +.4byte output_val, 0x00000001, write32_test # set GPIO rise_ip high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # expect interrupt pending on bit 3 +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending was cleared +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim from earlier +.4byte 0x0, 0x00000000, claim_m_plic_interrupts # clear interrupt one +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupt pending + +# =========== UART vs GPIO priority (2.X) =========== + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000007, write32_test # set s-mode threshold to max +# UART Initialization +.4byte UART_IER, 0x08, write08_test # enable modem status interrupts from CTS +.4byte UART_MCR, 0x10, write08_test # enable loopback mode, RTS = 0 +.4byte UART_MSR, 0x00, write08_test # disable UART interrupt + +# Test 2.0: GPIO Priority = UART Priority + +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.1: GPIO Priority > UART Priority + +.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.2: GPIO Priority < UART Priority + +.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.3: GPIO Priority < UART Priority + +.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for UART +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 2.4: Interrupts don't have enough priority + +.4byte PLIC_INTPRI_GPIO, 0x00000004, write32_test # GPIOPriority = 4 +.4byte PLIC_INTPRI_UART, 0x00000005, write32_test # UARTPriority = 5 +.4byte PLIC_THRESH0, 0x00000006, write32_test # set m-mode threshold to 6 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== SEIP tests (3.X) =========== + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 + +# Test 3.0: Cause machine and supervisor interrupts + +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UARTPriority = 1 +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000A00, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.1: Suppress machine mode interrupts + +.4byte PLIC_INTPRI_GPIO, 0x00000003, write32_test # GPIOPriority = 3 +.4byte PLIC_INTPRI_UART, 0x00000002, write32_test # UARTPriority = 2 +.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.2: Cause SEIP with UART first + +.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIOPriority = 6 +.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UARTPriority = 7 +.4byte PLIC_THRESH0, 0x00000007, write32_test # set m-mode threshold to 7 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 3.3: Low SEIP due to insufficient priority + +.4byte PLIC_INTPRI_GPIO, 0x00000002, write32_test # GPIOPriority = 2 +.4byte PLIC_INTPRI_UART, 0x00000003, write32_test # UARTPriority = 3 +.4byte PLIC_THRESH0, 0x00000004, write32_test # set m-mode threshold to 4 +.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== UART interrupt enable tests (4.X) =========== + +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 4.0: GPIO m-mode disabled + +.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000A00, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.1: UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.2: GPIO s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000A00, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.3: UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.4: GPIO and UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.5: GPIO and UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 4.6: GPIO and UART fully disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== GPIO interrupt enable tests (5.X) =========== + +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 5.0: GPIO m-mode disabled + +.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.1: UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000A00, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.2: GPIO s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.3: UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000A00, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.4: GPIO and UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.5: GPIO and UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 5.6: GPIO and UART fully disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM0, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO and UART +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM0, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_m_plic_interrupts # clear interrupt two +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== S-mode enable tests (7.X) =========== + +.4byte 0x0, 0x0, goto_s_mode # go to s-mode. 0xb written to output +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIO Priority = 1 +.4byte PLIC_INTPRI_UART, 0x00000001, write32_test # UART Priority = 1 + +# Test 7.0: GPIO m-mode disabled + +.4byte PLIC_INTEN00, 0x00000400, write32_test # disable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.1: UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000008, write32_test # disable UART m-mode interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.2: GPIO s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000400, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x0000000A, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x0000000A, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.3: UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.4: GPIO and UART s-mode disabled + +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000000, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.5: GPIO and UART m-mode disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000408, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000200, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Test 7.6: GPIO and UART fully disabled + +.4byte PLIC_INTEN00, 0x00000000, write32_test # disable GPIO interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000000, readsip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending for GPIO and UART +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte UART_MSR, 0x00000000, write08_test # clear UART interrupt +.4byte PLIC_CLAIM1, 0x00000000, write32_test # complete claim made earlier +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt one +.4byte 0x0, 0x00000000, claim_s_plic_interrupts # clear interrupt two +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# =========== Special claim tests (8) =========== + +.4byte 0x0, 0x0, goto_m_mode # write 0x9 to output + +.4byte PLIC_INTPRI_GPIO, 0x00000006, write32_test # GPIO Priority = 6 +.4byte PLIC_INTPRI_UART, 0x00000007, write32_test # UART Priority = 7 +.4byte PLIC_INTEN00, 0x00000408, write32_test # enable all m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable all s-mode interrupts +.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 + +# Test 8 + +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte UART_MSR, 0x0F, write08_test # cause UART interrupt +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # read interrupt pending +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # UART interrupt cleared +.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO +.4byte 0x0, 0x00000000, readmip_test # no interrupts, meip is low +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO +.4byte 0x0, 0x00000800, readmip_test # GPIO interrupt sets MEIP +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # GPIO bit is set +.4byte PLIC_CLAIM0, 0x00000003, read32_test # claim GPIO again +.4byte 0x0, 0x00000000, readmip_test # meip is zeroed +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # both interrupts claimed +.4byte PLIC_CLAIM0, 0x0000000A, write32_test # complete UART claim +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000400, read32_test # UART pending +.4byte PLIC_CLAIM0, 0x00000003, write32_test # complete GPIO claim +.4byte 0x0, 0x00000800, readmip_test # read mip +.4byte PLIC_INTPENDING0, 0x00000408, read32_test # GPIO and UART pending +.4byte PLIC_CLAIM0, 0x0000000A, read32_test # claim UART + +.4byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S new file mode 100644 index 000000000..68dcf82b6 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-plic-s-01.S @@ -0,0 +1,230 @@ +/////////////////////////////////////////// +// +// WALLY-plic-s +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// Test PLIC supervisor context interrupts and claim/complete +// +// Created 2022-07-29 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",plic-s) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.4byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.4byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== Define PLIC registers =========== + +.equ PLIC, 0x0C000000 +.equ PLIC_INTPRI_GPIO, (PLIC+0x00000C) # GPIO is interrupt 3 +.equ PLIC_INTPRI_UART, (PLIC+0x000028) # UART is interrupt 10 +.equ PLIC_INTPENDING0, (PLIC+0x001000) # intPending0 register +.equ PLIC_INTPENDING1, (PLIC+0x001004) # intPending0 register +.equ PLIC_INTEN00, (PLIC+0x002000) # interrupt enables for context 0 (machine mode) sources 31:1 +.equ PLIC_INTEN10, (PLIC+0x002080) # interrupt enables for context 1 (supervisor mode) sources 31:1 +.equ PLIC_THRESH0, (PLIC+0x200000) # Priority threshold for context 0 (machine mode) +.equ PLIC_CLAIM0, (PLIC+0x200004) # Claim/Complete register for context 0 +.equ PLIC_THRESH1, (PLIC+0x201000) # Priority threshold for context 1 (supervisor mode) +.equ PLIC_CLAIM1, (PLIC+0x201004) # Claim/Complete register for context 1 + +# =========== Define GPIO registers =========== + +.equ GPIO, 0x10060000 +.equ input_val, (GPIO+0x00) +.equ input_en, (GPIO+0x04) +.equ output_en, (GPIO+0x08) +.equ output_val, (GPIO+0x0C) +.equ rise_ie, (GPIO+0x18) +.equ rise_ip, (GPIO+0x1C) +.equ fall_ie, (GPIO+0x20) +.equ fall_ip, (GPIO+0x24) +.equ high_ie, (GPIO+0x28) +.equ high_ip, (GPIO+0x2C) +.equ low_ie, (GPIO+0x30) +.equ low_ip, (GPIO+0x34) +.equ iof_en, (GPIO+0x38) +.equ iof_sel, (GPIO+0x3C) +.equ out_xor, (GPIO+0x40) + +# =========== Initialize GPIO =========== + +# GPIO Initialization +.4byte input_en, 0x00000001, write32_test # enable bit 0 of input_en +.4byte output_en, 0x00000001, write32_test # enable bit 0 of output_en +.4byte output_val, 0x00000000, write32_test # make sure output_val is 0 +.4byte rise_ie, 0x00000001, write32_test # enable rise interrupts + +# =========== Initialize relevant PLIC registers =========== + +.4byte PLIC_INTPRI_UART, 0x00000000, write32_test # set UART priority to 0 to never interrupt + +# =========== Enter Supervisor Mode =========== + +.4byte 0x0, 0x0, goto_s_mode # Enter supervisor mode + +# =========== Test interrupt enables and priorities =========== + +# Case 1.1: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.2: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.3: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.4: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000000, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000000, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000000, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.5: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000000, write32_test # set m-mode threshold to 0 +.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.6: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.4byte PLIC_THRESH1, 0x00000000, write32_test # set s-mode threshold to 0 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000200, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# Case 1.7: +.4byte PLIC_INTPRI_GPIO, 0x00000001, write32_test # GPIOPriority = 1 +.4byte PLIC_INTEN00, 0x00000008, write32_test # enable GPIO m-mode interrupts +.4byte PLIC_INTEN10, 0x00000008, write32_test # enable GPIO s-mode interrupts +.4byte PLIC_THRESH0, 0x00000005, write32_test # set m-mode threshold to 5 +.4byte PLIC_THRESH1, 0x00000005, write32_test # set s-mode threshold to 5 +.4byte output_val, 0x00000001, write32_test # cause rise_ip to go high +.4byte 0x0, 0x00000000, readsip_test # read sip +.4byte PLIC_INTPENDING0, 0x00000008, read32_test # interrupt pending for GPIO +.4byte PLIC_CLAIM1, 0x00000003, read32_test # read claim register +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # interrupt pending cleared for GPIO +.4byte output_val, 0x00000000, write32_test # clear output_val +.4byte rise_ip, 0x00000001, write32_test # clear GPIO interrupt +.4byte PLIC_CLAIM1, 0x00000003, write32_test # complete claim made earlier +.4byte 0x0, 0x0, claim_s_plic_interrupts # clear interrupt from PLIC +.4byte PLIC_INTPENDING0, 0x00000000, read32_test # no interrupts pending + +# All done + +.4byte 0x0, 0x0, terminate_test # terminate tests diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S index 1b65a56f9..3000ddcde 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pma.S @@ -36,6 +36,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pma) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S index dde8c80fc..0f93d4086 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-pmp.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",pmp) + INIT_TESTS TRAP_HANDLER m @@ -54,6 +57,8 @@ test_cases: # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below +.4byte 0x80100300, 0xFEEDBEEF, write32_test + # write pmpaddr regs # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | .4byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S index c3af8142e..64c0567cb 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sie-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",sie) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses @@ -43,7 +46,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR. jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out. jal cause_s_soft_interrupt -li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. +# li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S index 748d84e01..5152e8b1a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S @@ -23,8 +23,15 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32IAF") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*A.*F.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled) + INIT_TESTS +// Set the FS bits to 01, This makes sure SAILs mstatus matches wally in the signature +li x29, 0x00002000 +csrw mstatus, x29 + TRAP_HANDLER m // Misa.F is already 1 in this config, making floating point enabled diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S index 5330afde8..1fc792a98 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-mie-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;",status-mie) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S index 740e1b04e..81e230273 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-sie-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",status-sie) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S index 61c8fc60c..15155fb76 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-status-tw-01.S @@ -24,6 +24,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;", status-tw) + INIT_TESTS TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S index 03dd7756f..e42ffb6dc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",stvec) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S index 71f690deb..9385e3547 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses @@ -48,7 +51,7 @@ GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_s_soft_interrupt +jal cause_s_soft_from_m_interrupt jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt @@ -70,14 +73,11 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_s_soft_from_m_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt -li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO -li a3, 0x40 jal cause_m_ext_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 82787516b..4b1e2afa4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def NO_SAIL=True;",trap-s) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S index 635b09ab9..e0f81a2c0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-sret-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret) + INIT_TESTS TRAP_HANDLER m, EXT_SIGNATURE=1 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S index 90d4fd396..df812db64 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",trap-u) + INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S new file mode 100644 index 000000000..deba11c29 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S @@ -0,0 +1,248 @@ +/////////////////////////////////////////// +// +// WALLY-uart +// +// Author: David_Harris@hmc.edu and Nicholas Lucio +// +// Created 2022-06-16 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",uart) + +INIT_TESTS + +TRAP_HANDLER m + +j run_test_loop // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +END_TESTS + +TEST_STACK_AND_DATA + +.align 2 + +.equ UART, 0x10000000 +.equ UART_RBR, (UART) +.equ UART_THR, (UART) +.equ UART_IER, (UART+0x01) +.equ UART_IIR, (UART+0x02) +.equ UART_FCR, (UART+0x02) +.equ UART_LCR, (UART+0x03) +.equ UART_MCR, (UART+0x04) +.equ UART_LSR, (UART+0x05) +.equ UART_MSR, (UART+0x06) +.equ UART_Scr, (UART+0x07) + +test_cases: +# --------------------------------------------------------------------------------------------- +# Test Contents +# +# Here is where the actual tests are held, or rather, what the actual tests do. +# each entry consists of 3 values that will be read in as follows: +# +# '.4byte [x28 Value], [x29 Value], [x30 value]' +# or +# '.4byte [address], [value], [test type]' +# +# The encoding for x30 test type values can be found in the test handler in the framework file +# +# --------------------------------------------------------------------------------------------- + +# =========== UART resets to correct values on master reset =========== + +.4byte UART_IER, 0x00, read08_test +.4byte UART_IIR, 0x01, read08_test # IIR resets to 1 +# .4byte UART_LCR, 0x00, read08_test *** commented out because LCR should reset to zero but resets to 3 to help Linux boot +.4byte UART_MCR, 0x00, read08_test +.4byte UART_LSR, 0x60, read08_test # LSR resets with transmit status bits set +.4byte UART_MSR, 0x00, read04_test + +# =========== Basic read-write =========== + +.4byte UART_LCR, 0x00, write08_test # set LCR to initial value +.4byte UART_MCR, 0x10, write08_test # put UART into loopback for MSR test +.4byte UART_LSR, 0x60, read08_test +.4byte UART_THR, 0x00, write08_test # write value to UART +.4byte UART_LSR, 0x00, read08_test # data not ready and transmitter is not empty +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and LSR +.4byte UART_RBR, 0x00, read08_test # read written value +.4byte UART_LSR, 0x60, read08_test # read LSR + +# =========== Different size read-write =========== + +# Transmit 5 bits + +.4byte UART_LCR, 0x00, write08_test # set LCR to transmit 5 bits +.4byte UART_THR, 0x55, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x15, read08_test # read written value without bits 5-7 + +# Transmit 6 bits + +.4byte UART_LCR, 0x01, write08_test # set LCR to transmit six bits +.4byte UART_THR, 0xAA, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x2A, read08_test # read written value without bits 6 & 7 + +# Transmit 7 bits + +.4byte UART_LCR, 0x02, write08_test # set LCR to transmit seven bits +.4byte UART_THR, 0xFF, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x7F, read08_test # read written value without bit 7 + +# Transmit 8 bits + +.4byte UART_LCR, 0x03, write08_test # set LCR to transmit eight bits +.4byte UART_THR, 0x80, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x80, read08_test # read full written value + sign extension + +# Check function with odd parity + +.4byte UART_LCR, 0x0B, write08_test # set LCR to transmit 8 bits + odd partiy +.4byte UART_THR, 0x79, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x79, read08_test # read full written value + +# Check function with even parity + +.4byte UART_LCR, 0x1B, write08_test # set LCR to transmit 8 bits + even parity +.4byte UART_THR, 0x6A, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x6A, read08_test # read full written value + +# Check function with extra stop bit + +.4byte UART_LCR, 0x07, write08_test # set LCR to transmit 8 bits + extra stop +.4byte UART_THR, 0x5B, write08_test # write value to UART +.4byte 0x0, 0x0101, uart_data_wait # wait for data to become ready then output IIR and then LSR +.4byte UART_RBR, 0x5B, read08_test # read full written value +.4byte UART_LCR, 0x03, write08_test # set LCR to transmit 8 bits + no extra stop bit + +# =========== Transmit-related interrupts =========== + +.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.4byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt +.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter +.4byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt +.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer +.4byte UART_IIR, 0x04, read08_test # data interrupt should still be high +.4byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error. +.4byte UART_LSR, 0x23, read08_test # read overrun error from LSR +.4byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared +.4byte UART_RBR, 0x01, read08_test # read previous value from UART + +# =========== MODEM interrupts =========== + +.4byte UART_MSR, 0x00, write08_test # clear MSR +.4byte UART_IER, 0x08, write08_test # enable MODEM Status interrupts +.4byte UART_IIR, 0x01, read08_test # no interrupts pending +.4byte UART_MCR, 0x12, write08_test # Cause DCTS interrupt +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0x11, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # interrupt cleared by reading MSR +.4byte UART_MCR, 0x13, write08_test # Set DSR high +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0x32, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x17, write08_test # Set RIb low and keep CTS and DSR +.4byte UART_MCR, 0x13, write08_test # Set RIb high and keep CTS and DSR +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0x34, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x1B, write08_test # Set DCD high and keep CTS and DSR +.4byte UART_IIR, 0x00, read08_test # MODEM interrupt +.4byte UART_MSR, 0xb8, read08_test # Read MSR to clear interrupt +.4byte UART_IIR, 0x01, read08_test # Interrupt cleared by reading MSR +.4byte UART_MCR, 0x10, write08_test # Clear MCR +.4byte UART_MSR, 0x00, write08_test # Clear MSR + +# =========== FIFO interrupts =========== + +.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.4byte UART_FCR, 0x41, write08_test # Set FIFO threshold to 4 and enable FIFO mode +.4byte UART_IIR, 0xC2, read08_test # Enabling FIFO sets top two bits of IIR +.4byte UART_THR, 0x00, write08_test # write 0 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # no interrupts pending (transmitter interrupt squashed by early read) +.4byte UART_RBR, 0x00, read08_test # read 0 from buffer register +.4byte UART_THR, 0xA5, write08_test # Write A5 to transmit register +.4byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.4byte UART_IIR, 0xC1, read08_test # no interrupts pending +.4byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.4byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to data ready +.4byte UART_RBR, 0xA5, read08_test # Read A5 from buffer register +.4byte UART_IIR, 0xC2, read08_test # Data ready interrupt cleared +.4byte UART_RBR, 0x01, read08_test # Read 1 from buffer register +.4byte UART_RBR, 0x02, read08_test # Read 2 from buffer register +.4byte UART_LSR, 0x61, read08_test # Data ready, 1 item left in FIFO +.4byte UART_RBR, 0x03, read08_test # Read 3 from buffer register +.4byte UART_LSR, 0x60, read08_test # No data ready, FIFO is empty +.4byte UART_THR, 0xFF, write08_test # Write FF to transmit register +.4byte UART_THR, 0xFE, write08_test # Write FE to transmit register +.4byte 0x0, 0xC101, uart_data_wait # Interrupt due to data ready +.4byte UART_FCR, 0xC7, write08_test # Clear all bytes in FIFO +.4byte UART_FCR, 0xC1, read08_test # Check that FCR clears bits 1 and 2 when written to 1 +.4byte UART_LSR, 0x60, read08_test # No data ready, FIFO cleared by writing to FCR + +# =========== FIFO receiver/overrun =========== + +.4byte UART_FCR, 0x01, write08_test # Set FIFO trigger threshold to 1 and enable FIFO mode +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger level +.4byte UART_THR, 0x00, write08_test # Write 0 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0x41, write08_test # Set FIFO trigger threshold to 4 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.4byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0x81, write08_test # Set FIFO trigger threshold to 8 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x04, write08_test # Write 4 to transmit register +.4byte UART_THR, 0x05, write08_test # Write 5 to transmit register +.4byte UART_THR, 0x06, write08_test # Write 6 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x07, write08_test # Write 7 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0xC1, write08_test # Set FIFO trigger threshold to 14 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x08, write08_test # Write 8 to transmit register +.4byte UART_THR, 0x09, write08_test # Write 9 to transmit register +.4byte UART_THR, 0x0A, write08_test # Write 10 to transmit register +.4byte UART_THR, 0x0B, write08_test # Write 11 to transmit register +.4byte UART_THR, 0x0C, write08_test # Write 12 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x0D, write08_test # Write 13 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_THR, 0x0E, write08_test # Write 14 to transmit register +.4byte UART_THR, 0x0F, write08_test # Write 15 to transmit register +.4byte 0x0, 0xC101, uart_data_wait +.4byte UART_LSR, 0x61, read08_test # FIFO contains data, no overrun error +.4byte UART_THR, 0x10, write08_test # Write 16 to transmit register, filling RX shift register +.4byte UART_THR, 0x11, write08_test # Write 17 to transmit register, destroying contents held in shift register +.4byte 0x0, 0x06, uart_lsr_intr_wait # Wait for LSR interrupt ID +.4byte UART_LSR, 0xA3, read08_test # Read overrun error from LSR + +.4byte 0x0, 0x0, terminate_test \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S index 7f2c5f46a..720d83956 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-wfi-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-32.h" +RVTEST_ISA("RV32I") +RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True;def TEST_CASE_1=True;def NO_SAIL=True;",wfi) + INIT_TESTS TRAP_HANDLER m, EXT_SIGNATURE=1 // turn on recording mtval and status bits on traps @@ -33,7 +36,9 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // Code copied from test library to cause m time interrupt, with time loop replaced with wfi. -li x28, 0x40 // Desired offset from the present time +/* Note: the following line might cause problems in the future. If more than 0x50 cycles are needed before the wfi + instruction begins, then the program might fall into a loop and run forever*/ +li x28, 0x50 // Desired offset from the present time mv a3, x28 // copy value in to know to stop waiting for interrupt after this many cycles la x29, 0x02004000 // MTIMECMP register in CLINT la x30, 0x0200BFF8 // MTIME register in CLINT diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S index ac596d0f8..ed51aca50 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394307// +// Created 2022-06-17 22:58:09.914370// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add) + # Testcase 0: rs1:x20(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x3(0x0000000000000000) li x20, MASK_XLEN(0x0000000000000000) li x22, MASK_XLEN(0x0000000000000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S index 8a94d265f..134bfe2aa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLT.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394785// +// Created 2022-06-17 22:58:09.916813// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",slt) + # Testcase 0: rs1:x18(0x0000000000000000), rs2:x9(0x0000000000000000), result rd:x5(0x0000000000000000) li x18, MASK_XLEN(0x0000000000000000) li x9, MASK_XLEN(0x0000000000000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S index d55aec980..d3671a1e5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SLTU.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.395005// +// Created 2022-06-17 22:58:09.917963// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sltu) + # Testcase 0: rs1:x22(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x2(0x0000000000000000) li x22, MASK_XLEN(0x0000000000000000) li x23, MASK_XLEN(0x0000000000000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S index 00ca2aaef..bd71d8ba0 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-SUB.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.394545// +// Created 2022-06-17 22:58:09.915580// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sub) + # Testcase 0: rs1:x4(0x0000000000000000), rs2:x23(0x0000000000000000), result rd:x13(0x0000000000000000) li x4, MASK_XLEN(0x0000000000000000) li x23, MASK_XLEN(0x0000000000000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S index f4bc6aa9f..b91ba798f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S @@ -1,7 +1,7 @@ /////////////////////////////////////////// // ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-XOR.S // David_Harris@hmc.edu & Katherine Parry -// Created 2022-01-27 08:08:42.395231// +// Created 2022-06-17 22:58:09.919138// // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // // Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation @@ -19,6 +19,7 @@ #include "model_test.h" #include "arch_test.h" +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -28,6 +29,8 @@ RVTEST_CODE_BEGIN RVTEST_SIGBASE( x6, wally_signature) +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xor) + # Testcase 0: rs1:x27(0x0000000000000000), rs2:x22(0x0000000000000000), result rd:x17(0x0000000000000000) li x27, MASK_XLEN(0x0000000000000000) li x22, MASK_XLEN(0x0000000000000000) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag index c81f1537a..319c5d930 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag @@ -38,6 +38,10 @@ rv64i_sc_tests = \ WALLY-amo \ WALLY-lrsc \ WALLY-trap-sret-01 \ + WALLY-status-mie-01 \ + WALLY-status-sie-01 \ + WALLY-status-tw-01 \ + # Don't simulate these because they rely on SoC features that Spike does not offer. target_tests_nosim = \ @@ -47,14 +51,13 @@ target_tests_nosim = \ WALLY-stvec-01 \ WALLY-mie-01 \ WALLY-sie-01 \ - WALLY-status-mie-01 \ - WALLY-status-sie-01 \ WALLY-trap-01 \ WALLY-trap-s-01 \ WALLY-trap-u-01 \ - WALLY-status-tw-01 \ - WALLY-wfi-01 \ WALLY-status-fp-enabled-01 \ + WALLY-wfi-01 \ + +# unclear why status-fp-enabled and wfi aren't simulating ok rv64i_tests = $(addsuffix .elf, $(rv64i_sc_tests)) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output index 5503d02b5..93e18c06d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output @@ -1021,4 +1021,4 @@ deadbeef deadbeef deadbeef deadbeef -deadbeef \ No newline at end of file +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output index 7b23883c6..fd88590e3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-periph.reference_output @@ -254,12 +254,12 @@ FFFFEE00 FFFFEE00 00000000 00000000 -02BEEF10 +02BEEF10 # Something here is failing 0000000B 80000000 00000003 000000FF -FFFFFFFF +00000000 000000FF 00000000 00000000 @@ -270,20 +270,20 @@ FFFFFFFF FFFFFF00 00000000 00000000 -02BEEF11 +02BEEF11 # this might be wrong 0000000B 80000000 -00000003 -000000CC -CCCCCCCC -00000000 -00000000 -00000033 -00000000 -000000FF -000000CC -FFFFFF33 -FFFFFF33 +00000003 +00000033 # input +00000000 # output +00000000 # rise ip +00000000 # serviced rise ip +000000CC # fall ip +00000000 +000000FF # high ip +00000033 # why is this 0x33? +FFFFFFCC # low ip +FFFFFFCC # serviced low ip 00000000 00000000 03BEEF12 @@ -454,9 +454,9 @@ FFFFFF33 00080000 00080000 00000000 +00000000 # is it this one that's failing? 00000000 -00000000 -00080000 +00080000 # failing 00080000 FFFFFFFF FFF7FFFF @@ -478,7 +478,7 @@ FFFFFFFF FFFFFFFE 00000000 00000000 -04BEEF1E +04BEEF1E # this might also be wrong 00000009 80000000 0000000A diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output index 440bee2aa..f6434b676 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pma.reference_output @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output index 936435099..fe33b6398 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output @@ -1018,3 +1018,7 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 7e6231e75..d77998a66 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -14,13 +14,13 @@ 00000000 00000003 # mcause from Breakpoint 00000000 -80000400 # mtval of breakpoint instruction adress (0x80000400) +800003f4 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -80000409 # mtval of misaligned address (0x80000409) +800003fd # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -32,7 +32,7 @@ 00000000 00000006 # mcause from store misaligned 00000000 -80000421 # mtval of address with misaligned store instr (0x80000421) +80000415 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -126,13 +126,13 @@ ffffffff 00000000 00000003 # mcause from Breakpoint 00000000 -80000400 # mtval of breakpoint instruction adress (0x80000400) +800003f4 # mtval of breakpoint instruction adress (0x80000400) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 00000004 # mcause from load address misaligned 00000000 -80000409 # mtval of misaligned address (0x80000409) +800003fd # mtval of misaligned address (0x80000409) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -144,7 +144,7 @@ ffffffff 00000000 00000006 # mcause from store misaligned 00000000 -80000421 # mtval of address with misaligned store instr (0x80000421) +80000415 # mtval of address with misaligned store instr (0x80000421) 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index 791ebf777..fe559dfb7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -80000400 # stval of breakpoint instruction adress (0x80000400) +800003f4 # stval of breakpoint instruction adress (0x80000400) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -80000409 # stval of misaligned address (0x80000409) +800003fd # stval of misaligned address (0x80000409) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000421 # stval of address with misaligned store instr (0x80000421) +80000415 # stval of address with misaligned store instr (0x80000421) 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -130,13 +130,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -80000400 # stval of breakpoint instruction adress (0x80000400) +800003f4 # stval of breakpoint instruction adress (0x80000400) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -80000409 # stval of misaligned address (0x80000409) +800003fd # stval of misaligned address (0x80000409) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -148,7 +148,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000421 # stval of address with misaligned store instr (0x80000421) +80000415 # stval of address with misaligned store instr (0x80000421) 00000000 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -1000,3 +1000,25 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index c42c74f2d..39f874ef7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -20,13 +20,13 @@ 00000000 00000003 # scause from Breakpoint 00000000 -80000400 # stval of breakpoint instruction adress (0x80000400) +800003f4 # stval of breakpoint instruction adress (0x80000400) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -80000409 # stval of misaligned address (0x80000409) +800003fd # stval of misaligned address (0x80000409) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -38,7 +38,7 @@ 00000000 00000006 # scause from store misaligned 00000000 -80000421 # stval of address with misaligned store instr (0x80000421) +80000415 # stval of address with misaligned store instr (0x80000421) 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 @@ -116,13 +116,13 @@ ffffffff 00000000 00000003 # scause from Breakpoint 00000000 -80000400 # stval of breakpoint instruction adress (0x80000400) +800003f4 # stval of breakpoint instruction adress (0x80000400) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 00000004 # scause from load address misaligned 00000000 -80000409 # stval of misaligned address (0x80000409) +800003fd # stval of misaligned address (0x80000409) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -134,7 +134,7 @@ ffffffff 00000000 00000006 # scause from store misaligned 00000000 -80000421 # stval of address with misaligned store instr (0x80000421) +80000415 # stval of address with misaligned store instr (0x80000421) 00000000 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0 00000000 @@ -1010,3 +1010,15 @@ deadbeef deadbeef deadbeef deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index c24952b42..60872449e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -26,7 +26,7 @@ .macro INIT_TESTS -RVTEST_ISA("RV64I") +// RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point @@ -156,6 +156,7 @@ cause_s_soft_interrupt: cause_m_ext_interrupt: // ========== Configure PLIC ========== + li a3, 0x40 // m priority threshold = 0 li t3, 0xC200000 li t4, 0 @@ -192,6 +193,7 @@ m_ext_loop: cause_s_ext_interrupt_GPIO: // ========== Configure PLIC ========== + li a3, 0x40 // s priority threshold = 0 li t3, 0xC201000 li t4, 0 @@ -857,6 +859,28 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a addi a6, a6, 8 .endm +// Place this macro in peripheral tests to setup all the PLIC registers to generate external interrupts +.macro SETUP_PLIC + # Setup PLIC with a series of register writes + + .equ PLIC_INTPRI_GPIO, 0x0C00000C # GPIO is interrupt 3 + .equ PLIC_INTPRI_UART, 0x0C000028 # UART is interrupt 10 + .equ PLIC_INTPENDING0, 0x0C001000 # intPending0 register + .equ PLIC_INTEN00, 0x0C002000 # interrupt enables for context 0 (machine mode) sources 31:1 + .equ PLIC_INTEN10, 0x0C002080 # interrupt enables for context 1 (supervisor mode) sources 31:1 + .equ PLIC_THRESH0, 0x0C200000 # Priority threshold for context 0 (machine mode) + .equ PLIC_CLAIM0, 0x0C200004 # Claim/Complete register for context 0 + .equ PLIC_THRESH1, 0x0C201000 # Priority threshold for context 1 (supervisor mode) + .equ PLIC_CLAIM1, 0x0C201004 # Claim/Complete register for context 1 + + .4byte PLIC_THRESH0, 0, write32_test # Set PLIC machine mode interrupt threshold to 0 to accept all interrupts + .4byte PLIC_THRESH1, 7, write32_test # Set PLIC supervisor mode interrupt threshold to 7 to accept no interrupts + .4byte PLIC_INTPRI_GPIO, 7, write32_test # Set GPIO to high priority + .4byte PLIC_INTPRI_UART, 7, write32_test # Set UART to high priority + .4byte PLIC_INTEN00, 0xFFFFFFFF, write32_test # Enable all interrupt sources for machine mode + .4byte PLIC_INTEN10, 0x00000000, write32_test # Disable all interrupt sources for supervisor mode +.endm + .macro END_TESTS // invokes one final ecall to return to machine mode then terminates this program, so the output is // 0x8: termination called from U mode @@ -984,6 +1008,20 @@ read08_test: addi a6, a6, 8 j test_loop // go to next test case +readmip_test: // read the MIP into the signature + csrr t2, mip + sw t2, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop // go to next test case + +readsip_test: // read the MIP into the signature + csrr t2, sip + sw t2, 0(t1) + addi t1, t1, 4 + addi a6, a6, 4 + j test_loop // go to next test case + goto_s_mode: // return to address in t3, li a0, 3 // Trap handler behavior (go to supervisor mode) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S index b12297902..1d246a54b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-amo.S @@ -24,7 +24,8 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") +RVTEST_ISA("RV64IAF") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True;",amo) .section .text.init .globl rvtest_entry_point diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S index 9b24b6efe..2ff2e99f2 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S index 904e15dbd..848186a98 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S @@ -23,6 +23,9 @@ #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u) + INIT_TESTS TRAP_HANDLER m diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S index b38331a09..3cf332f6b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-lrsc.S @@ -24,7 +24,8 @@ #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64I") +RVTEST_ISA("RV64IAF") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.A*.F*.*);def TEST_CASE_1=True",lrsc) .section .text.init .globl rvtest_entry_point diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S index 84bcabc4f..664e8ce08 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mie-01.S @@ -22,7 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" - +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",mie) INIT_TESTS CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index bdfe4b316..5f4ae446a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S index 6aafa0098..9dc0b5c43 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S index de6202c74..2a54d4868 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",mmu-sv39) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S index 5de627acf..fafaa242a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",sv48) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S index 543857560..b192d229c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",mtvec) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S index c44d7a681..c4e5a96e6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-periph.S @@ -24,6 +24,8 @@ #include "arch_test.h" RVTEST_ISA("RV64I") +// this test is blocked, it won't build or run. To unblock it remove the check ISA:=regex(BLOCKED); +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True",periph) .section .text.init .globl rvtest_entry_point @@ -271,7 +273,7 @@ main_code: ##### sw t1, 0x04(t0) # raise all output_en sw t1, 0x08(t0) - # raise all input_en + # raise all rise_en sw t1, 0x18(t0) # ========== Execute Test ========== # set MEIE @@ -616,6 +618,9 @@ Intr02BEEF11: sw t1, 0x08(t0) # set initial output state sw x0, 0x0C(t0) + # clear XOR + li t1, 0x00000000 + sw t1, 0x40(t0) # clear all pending interrupts li t1, 0xFFFFFFFF sw t1, 0x1C(t0) @@ -843,7 +848,7 @@ Intr03BEEF1A: sw t1, 0x04(t0) # raise all output_en sw t1, 0x08(t0) - # raise all input_en + # raise all rise_en sw t1, 0x18(t0) # ========== Execute Test ========== # set MEIE and SEIE diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S index 6d93cd8b6..3048c1ebc 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pma.S @@ -35,6 +35,8 @@ #define PLIC_RANGE 0x03FFFFFF #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pma) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S index 7c826ae8f..fc3864d38 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",pmp) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S index cc681af28..28df4374c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-sie-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",sie) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S index 6a3b53bea..1d7cb6bec 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S @@ -22,9 +22,15 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64IAF") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled) INIT_TESTS +// Set the FS bits to 01, This makes sure SAILs mstatus matches wally in the signature +li x29, 0x00002000 +csrw mstatus, x29 + TRAP_HANDLER m // Misa.F is already 1 in this config, making floating point enabled diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S index c554bbf7a..6fc868984 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-mie-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",status-mie) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S index a35e85b46..e9a9e443b 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-sie-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-sie) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S index b84b5103b..184b022ed 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-tw-01.S @@ -23,6 +23,8 @@ #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-tw) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 100834e36..4a4bdb768 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True; def NO_SAIL=True;",stvec) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index e3372a062..41d9cd072 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap) INIT_TESTS @@ -77,7 +79,6 @@ jal cause_m_time_interrupt li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO -li a3, 0x40 jal cause_m_ext_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index 147ad893c..cfe02f3a6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-s) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S index 653eacac6..78692fd1c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-sret) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S index bc07738c9..e10e5d988 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",trap-u) INIT_TESTS diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S index cd057c4db..c67d3c24a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-wfi-01.S @@ -22,6 +22,8 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" +RVTEST_ISA("RV64I") +RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",wfi) INIT_TESTS