From 8b1dc81d345b8130d3a9399f9cb0a0e6cc6939b1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 23 Oct 2021 12:00:32 -0700 Subject: [PATCH] more lsu/ifu lint cleanup --- wally-pipelined/src/cache/dcache.sv | 10 ++-------- wally-pipelined/src/cache/icache.sv | 3 +-- wally-pipelined/src/ifu/ifu.sv | 19 +++++++------------ wally-pipelined/src/lsu/lsu.sv | 10 ++-------- .../src/wally/wallypipelinedhart.sv | 9 ++++----- wally-pipelined/testbench/testbench.sv | 2 +- 6 files changed, 17 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 733f469f3..a61a5accc 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -28,10 +28,7 @@ module dcache (input logic clk, input logic reset, - input logic StallM, input logic StallWtoDCache, - input logic FlushM, - input logic FlushW, // cpu side input logic [1:0] MemRWM, @@ -113,13 +110,12 @@ module dcache logic SRAMWordWriteEnableM; logic SRAMBlockWriteEnableM; logic [NUMWAYS-1:0] SRAMBlockWayWriteEnableM; - logic SRAMWriteEnable; + //logic SRAMWriteEnable; logic [NUMWAYS-1:0] SRAMWayWriteEnable; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; - logic [BLOCKLEN-1:0] VictimReadDataBlockM; logic VictimDirty; logic SelUncached; logic [2**LOGWPL-1:0] MemPAdrDecodedW; @@ -144,9 +140,7 @@ module dcache logic SelFlush; logic VDWriteEnable; - logic AnyCPUReqM; logic FetchCountFlag; - logic PreCntEn; logic CntEn; logic CntReset; logic SelEvict; @@ -349,7 +343,7 @@ module dcache else assign DCtoAHBSizeM = CacheableM | SelFlush ? 3'b011 : Funct3M; endgenerate; - assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; + //assign SRAMWriteEnable = SRAMBlockWriteEnableM | SRAMWordWriteEnableM; // controller diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 1e55e0daf..0f6843585 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -29,8 +29,7 @@ module icache ( // Basic pipeline stuff input logic clk, reset, - input logic StallF, StallD, - input logic FlushD, + input logic StallF, input logic [`PA_BITS-1:0] PCNextF, input logic [`PA_BITS-1:0] PCPF, // Data read in from the ebu unit diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 7a23800be..bdbf096da 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -37,8 +37,6 @@ module ifu ( output logic [`PA_BITS-1:0] InstrPAdrF, output logic InstrReadF, output logic ICacheStallF, - // Decode - output logic [`XLEN-1:0] PCD, // Execute output logic [`XLEN-1:0] PCLinkE, input logic PCSrcE, @@ -49,7 +47,7 @@ module ifu ( input logic RetM, TrapM, input logic [`XLEN-1:0] PrivilegedNextPCM, input logic InvalidateICacheM, - output logic [31:0] InstrD, InstrE, InstrM, InstrW, + output logic [31:0] InstrD, InstrM, output logic [`XLEN-1:0] PCM, output logic [4:0] InstrClassM, output logic BPPredDirWrongM, @@ -89,10 +87,13 @@ module ifu ( logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; logic PrivilegedChangePCM; logic IllegalCompInstrD; - logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD, PCLinkM, PCPF; + logic [`XLEN-1:0] PCPlus2or4F, PCW, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; logic CompressedF; logic [31:0] InstrRawD, FinalInstrRawF; + logic [31:0] InstrE; + logic [`XLEN-1:0] PCD; + localparam [31:0] nop = 32'h00000013; // instruction for NOP logic reset_q; // *** look at this later. @@ -100,14 +101,13 @@ module ifu ( logic [`PA_BITS-1:0] PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`XLEN+1:0] PCFExt; - logic ITLBHitF; generate if (`XLEN==32) begin - assign PCPF = PCPFmmu[31:0]; + //assign PCPF = PCPFmmu[31:0]; assign PCNextFPhys = {{(`PA_BITS-`XLEN){1'b0}}, PCNextF}; end else begin - assign PCPF = {8'b0, PCPFmmu}; + //assign PCPF = {8'b0, PCPFmmu}; assign PCNextFPhys = PCNextF[`PA_BITS-1:0]; end endgenerate @@ -270,10 +270,8 @@ module ifu ( flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE); flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM); - // flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); - // flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later flopenrc #(5) InstrClassRegE(.clk(clk), .reset(reset), @@ -302,8 +300,5 @@ module ifu ( // *** redo this flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD); flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE); - // flopenr #(`XLEN) PCPMReg(clk, reset, ~StallM, PCLinkE, PCLinkM); - // /flopenr #(`XLEN) PCPWReg(clk, reset, ~StallW, PCLinkM, PCLinkW); - endmodule diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 09d76cb65..5c8f1261d 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -94,7 +94,6 @@ module lsu ); logic DTLBPageFaultM; - logic DTLBHitM; logic [`PA_BITS-1:0] MemPAdrM; // from mmu to dcache @@ -122,7 +121,7 @@ module lsu logic CommittedMfromDCache; logic PendingInterruptMtoDCache; - logic FlushWtoDCache; +// logic FlushWtoDCache; logic WalkerPageFaultM; logic AnyCPUReqM; @@ -198,20 +197,18 @@ module lsu .TLBFlush(DTLBFlushM), .PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM), - //.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM), .ExecuteAccessF(1'b0), //.AtomicAccessM(AtomicMaskedM[1]), .AtomicAccessM(1'b0), .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]), - //.SquashBusAccess(), .DisableTranslation(DisableTranslation), .InstrAccessFaultF(), .Cacheable(CacheableM), .Idempotent(), .AtomicAllowed(), - .*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist? + .*); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist? assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED; @@ -241,10 +238,7 @@ module lsu dcache dcache(.clk(clk), .reset(reset), - .StallM(StallM), .StallWtoDCache(StallWtoDCache), - .FlushM(FlushM), - .FlushW(FlushWtoDCache), .MemRWM(MemRWMtoDCache), .Funct3M(Funct3MtoDCache), .Funct7M(Funct7M), diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 1a4c826ea..980166d95 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -63,15 +63,14 @@ module wallypipelinedhart ( logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; // logic [31:0] InstrF; - logic [31:0] InstrD, InstrE, InstrM, InstrW; - logic [`XLEN-1:0] PCF, PCD, PCE, PCM, PCLinkE; + logic [31:0] InstrD, InstrM; + logic [`XLEN-1:0] PCF, PCE, PCM, PCLinkE; logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; logic [1:0] MemRWM; logic InstrValidM; logic InstrMisalignedFaultM; - logic DataMisalignedM; logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD; logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM; logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM; @@ -86,7 +85,7 @@ module wallypipelinedhart ( logic SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; - logic [4:0] RdE, RdM, RdW; + logic [4:0] RdM, RdW; logic FStallD; logic FWriteIntE, FWriteIntM, FWriteIntW; logic [`XLEN-1:0] FWriteDataE; @@ -178,7 +177,7 @@ module wallypipelinedhart ( .DCacheMiss, .DCacheAccess, .SquashSCW(SquashSCW), - .DataMisalignedM(DataMisalignedM), + //.DataMisalignedM(DataMisalignedM), .MemAdrE(MemAdrE), .MemAdrM(MemAdrM), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv index 5999f5d9c..79945d2f1 100644 --- a/wally-pipelined/testbench/testbench.sv +++ b/wally-pipelined/testbench/testbench.sv @@ -174,7 +174,7 @@ logic [3:0] dummy; instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.icache.FinalInstrRawF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + dut.hart.ifu.InstrM, InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests