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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

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David Harris 2022-12-01 16:27:36 -08:00
commit 8afc054e74
3 changed files with 3 additions and 8 deletions
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7
pipelined/src/cache/cache.sv vendored
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@ -81,8 +81,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
logic SetValid;
logic [NUMWAYS-1:0] VictimWay;
logic [NUMWAYS-1:0] VictimDirtyWay;
logic CacheHitDirty;
logic [NUMWAYS-1:0] HitDirtyWay;
logic VictimDirty;
logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
logic [TAGLEN-1:0] VictimTag;
@ -130,14 +128,13 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, DCACHE)
CacheWays[NUMWAYS-1:0](.clk, .reset, .ce, .CAdr, .PAdr, .LineWriteData, .LineByteMask,
.SetValidWay, .ClearValidWay, .SetDirtyWay, .ClearDirtyWay, .SelEvict, .VictimWay,
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .InvalidateCache, .HitDirtyWay);
.FlushWay, .SelFlush, .ReadDataLineWay, .HitWay, .ValidWay, .VictimDirtyWay, .VictimTagWay, .FlushStage, .InvalidateCache);
if(NUMWAYS > 1) begin:vict
cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
.clk, .reset, .ce, .HitWay, .ValidWay, .VictimWay, .CAdr, .LRUWriteEn(LRUWriteEn & ~FlushStage),
.SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache);
end else assign VictimWay = 1'b1; // one hot.
assign CacheHit = | HitWay;
assign CacheHitDirty = | HitDirtyWay;
assign VictimDirty = | VictimDirtyWay;
// ReadDataLineWay is a 2d array of cache line len by number of ways.
// Need to OR together each way in a bitwise manner.
@ -213,7 +210,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
/////////////////////////////////////////////////////////////////////////////////////////////
cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck,
.FlushStage, .CacheRW, .CacheAtomic, .CPUBusy,
.CacheHit, .CacheHitDirty, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
.CacheMiss, .CacheAccess, .SelAdr,
.ClearValid, .ClearDirty, .SetDirty,
.SetValid, .SelEvict, .SelFlush,

1
pipelined/src/cache/cachefsm.sv vendored
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@ -45,7 +45,6 @@ module cachefsm
input logic CacheBusAck,
// dcache internals
input logic CacheHit,
input logic CacheHitDirty,
input logic VictimDirty,
input logic FlushAdrFlag,
input logic FlushWayFlag,

3
pipelined/src/cache/cacheway.sv vendored
View File

@ -54,7 +54,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
output logic [LINELEN-1:0] ReadDataLineWay,
output logic HitWay,
output logic ValidWay,
output logic VictimDirtyWay, HitDirtyWay,
output logic VictimDirtyWay,
output logic [TAGLEN-1:0] VictimTagWay);
localparam integer WORDSPERLINE = LINELEN/`XLEN;
@ -96,7 +96,6 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux
assign VictimDirtyWay = SelTag & Dirty & ValidWay;
assign HitDirtyWay = Dirty & HitWay;
assign HitWay = ValidWay & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]);
/////////////////////////////////////////////////////////////////////////////////////////////