From 8ad920fcb35fa03facc08e4f428290a75b7d0766 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 25 Apr 2022 19:17:29 +0000 Subject: [PATCH] fixed initial value, timing on fs bits changing after floating point instruction --- pipelined/src/privileged/csrsr.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv index 3d29cd903..088d1e95b 100644 --- a/pipelined/src/privileged/csrsr.sv +++ b/pipelined/src/privileged/csrsr.sv @@ -111,7 +111,7 @@ module csrsr ( STATUS_MXR_INT <= #1 0; STATUS_SUM_INT <= #1 0; STATUS_MPRV_INT <= #1 0; // Per Priv 3.3 - STATUS_FS_INT <= #1 0; + STATUS_FS_INT <= #1 `F_SUPPORTED ? 2'b01 : 2'b00; STATUS_MPP <= #1 0; //`M_MODE; STATUS_SPP <= #1 0; //1'b1; STATUS_MPIE <= #1 0; //1; @@ -119,7 +119,7 @@ module csrsr ( STATUS_MIE <= #1 0; // Per Priv 3.3 STATUS_SIE <= #1 0; //`S_SUPPORTED; end else if (~StallW) begin - if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #12'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else; + if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #1 2'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else; if (TrapM) begin // Update interrupt enables per Privileged Spec p. 21