Config cleanup and renamed BPRED_ENABLED to BPRED_SUPPORTED

This commit is contained in:
David Harris 2023-01-28 18:17:42 -08:00
parent c73fe4041e
commit 8a96dcf0ae
13 changed files with 21 additions and 21 deletions

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@ -128,7 +128,7 @@
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -71,7 +71,7 @@
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 16
// Address space // Address space
`define RESET_VECTOR 64'h0000000000001000 `define RESET_VECTOR 64'h0000000000001000
@ -139,7 +139,7 @@
`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt" `define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt" `define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 1
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define TESTSBP 1 `define TESTSBP 1
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -69,7 +69,7 @@
// Integer Divider Configuration // Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4 // IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 1 `define IDIV_BITSPERCYCLE 1
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0 `define PMP_ENTRIES 0
@ -132,7 +132,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 0 `define BPRED_SUPPORTED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -68,7 +68,7 @@
// Integer Divider Configuration // Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4 // IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4 `define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 16 `define PMP_ENTRIES 16
@ -131,7 +131,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -69,10 +69,10 @@
// Integer Divider Configuration // Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4 // IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4 `define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 0
// Address space // Address space
`define RESET_VECTOR 32'h80000000 `define RESET_VECTOR 32'h80000000
@ -132,7 +132,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -68,7 +68,7 @@
// Integer Divider Configuration // Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4 // IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4 `define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0 `define PMP_ENTRIES 0
@ -131,7 +131,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -72,7 +72,7 @@
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 1
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 64 `define PMP_ENTRIES 16
// Address space // Address space
`define RESET_VECTOR 64'h0000000080000000 `define RESET_VECTOR 64'h0000000080000000
@ -134,7 +134,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 1
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -134,7 +134,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 1 `define BPRED_SUPPORTED 1
//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 `define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 //`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2

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@ -69,7 +69,7 @@
// Integer Divider Configuration // Integer Divider Configuration
// IDIV_BITSPERCYCLE must be 1, 2, or 4 // IDIV_BITSPERCYCLE must be 1, 2, or 4
`define IDIV_BITSPERCYCLE 4 `define IDIV_BITSPERCYCLE 4
`define IDIV_ON_FPU 1 `define IDIV_ON_FPU 0
// Legal number of PMP entries are 0, 16, or 64 // Legal number of PMP entries are 0, 16, or 64
`define PMP_ENTRIES 0 `define PMP_ENTRIES 0
@ -134,7 +134,7 @@
`define PLIC_GPIO_ID 3 `define PLIC_GPIO_ID 3
`define PLIC_UART_ID 10 `define PLIC_UART_ID 10
`define BPRED_ENABLED 0 `define BPRED_SUPPORTED 0
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
`define TESTSBP 0 `define TESTSBP 0
`define BPRED_SIZE 10 `define BPRED_SIZE 10

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@ -322,7 +322,7 @@ module ifu (
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
// Branch and Jump Predictor // Branch and Jump Predictor
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
if (`BPRED_ENABLED) begin : bpred if (`BPRED_SUPPORTED) begin : bpred
bpred bpred(.clk, .reset, bpred bpred(.clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushD, .FlushE, .FlushM, .FlushW, .FlushD, .FlushE, .FlushM, .FlushW,

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@ -99,7 +99,7 @@ package cvw;
// parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32; // parameter PLIC_NUM_SRC_LT_32 = `PLIC_NUM_SRC_LT_32;
parameter PLIC_GPIO_ID = `PLIC_GPIO_ID; parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
parameter PLIC_UART_ID = `PLIC_UART_ID; parameter PLIC_UART_ID = `PLIC_UART_ID;
parameter BPRED_ENABLED = `BPRED_ENABLED; parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
parameter BPTYPE = `BPTYPE; parameter BPTYPE = `BPTYPE;
parameter TESTSBP = `TESTSBP; parameter TESTSBP = `TESTSBP;
parameter BPRED_SIZE = `BPRED_SIZE; parameter BPRED_SIZE = `BPRED_SIZE;

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@ -465,7 +465,7 @@ logic [3:0] dummy;
.done(DCacheFlushDone)); .done(DCacheFlushDone));
// initialize the branch predictor // initialize the branch predictor
if (`BPRED_ENABLED == 1) if (`BPRED_SUPPORTED == 1)
begin begin
genvar adrindex; genvar adrindex;

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@ -219,7 +219,7 @@ module testbench;
.done(DCacheFlushDone)); .done(DCacheFlushDone));
// initialize the branch predictor // initialize the branch predictor
if (`BPRED_ENABLED == 1) if (`BPRED_SUPPORTED == 1)
begin begin
genvar adrindex; genvar adrindex;