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updated module instation of LSU on wallypiplinedhard

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This commit is contained in:
Noah Limpert 2021-11-24 22:09:39 -08:00
parent de8e2008d2
commit 8a64510ee4
1 changed files with 30 additions and 53 deletions
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83
wally-pipelined/src/wally/wallypipelinedhart.sv
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@ -233,67 +233,44 @@ module wallypipelinedhart (
); // integer execution unit: integer register file, datapath and controller ); // integer execution unit: integer register file, datapath and controller
lsu lsu(.clk(clk), lsu lsu(
.reset(reset), .clk, .reset, .StallM, .FlushM, .StallW,
.StallM(StallM), .FlushW,
.FlushM(FlushM),
.StallW(StallW),
.FlushW(FlushW),
// CPU interface // CPU interface
.MemRWM(MemRWM), .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]),
.Funct3M(Funct3M), .AtomicM, .ExceptionM, .PendingInterruptM,
.Funct7M(InstrM[31:25]), .CommittedM, .DCacheMiss, .DCacheAccess,
.AtomicM(AtomicM), .SquashSCW,
.ExceptionM(ExceptionM),
.PendingInterruptM(PendingInterruptM),
.CommittedM(CommittedM),
.DCacheMiss,
.DCacheAccess,
.SquashSCW(SquashSCW),
//.DataMisalignedM(DataMisalignedM), //.DataMisalignedM(DataMisalignedM),
.MemAdrE(MemAdrE), .MemAdrE, .MemAdrM, .WriteDataM,
.MemAdrM(MemAdrM), .ReadDataM, .FlushDCacheM,
.WriteDataM(WriteDataM),
.ReadDataM(ReadDataM),
.FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.DCtoAHBPAdrM(DCtoAHBPAdrM), .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
.DCtoAHBReadM(DCtoAHBReadM), .DCfromAHBReadData, .DCtoAHBWriteData, .DCtoAHBSizeM,
.DCtoAHBWriteM(DCtoAHBWriteM),
.DCfromAHBAck(DCfromAHBAck),
.DCfromAHBReadData(DCfromAHBReadData),
.DCtoAHBWriteData(DCtoAHBWriteData),
.DCtoAHBSizeM(DCtoAHBSizeM),
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
.PrivilegeModeW(PrivilegeModeW), // connects to csr .PrivilegeModeW, // connects to csr
.PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr .PMPCFG_ARRAY_REGW, // connects to csr
.PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr .PMPADDR_ARRAY_REGW, // connects to csr
// hptw keep i/o // hptw keep i/o
.SATP_REGW(SATP_REGW), // from csr .SATP_REGW, // from csr
.STATUS_MXR(STATUS_MXR), // from csr .STATUS_MXR, // from csr
.STATUS_SUM(STATUS_SUM), // from csr .STATUS_SUM, // from csr
.STATUS_MPRV(STATUS_MPRV), // from csr .STATUS_MPRV, // from csr
.STATUS_MPP(STATUS_MPP), // from csr .STATUS_MPP, // from csr
.DTLBFlushM(DTLBFlushM), // connects to privilege .DTLBFlushM, // connects to privilege
.DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege .DTLBLoadPageFaultM, // connects to privilege
.DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege .DTLBStorePageFaultM, // connects to privilege
.LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege .LoadMisalignedFaultM, // connects to privilege
.LoadAccessFaultM(LoadAccessFaultM), // connects to privilege .LoadAccessFaultM, // connects to privilege
.StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege .StoreMisalignedFaultM, // connects to privilege
.StoreAccessFaultM(StoreAccessFaultM), // connects to privilege .StoreAccessFaultM, // connects to privilege
.PCF(PCF), .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF,
.ITLBMissF(ITLBMissF), .WalkerInstrPageFaultF, .WalkerLoadPageFaultM,
.PTE(PTE), .WalkerStorePageFaultM,
.PageType, .LSUStall); // change to LSUStall
.ITLBWriteF(ITLBWriteF),
.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
.WalkerStorePageFaultM(WalkerStorePageFaultM),
.LSUStall(LSUStall)); // change to LSUStall