diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv
index ad6b980d3..242d596f8 100644
--- a/wally-pipelined/src/cache/cacheway.sv
+++ b/wally-pipelined/src/cache/cacheway.sv
@@ -34,7 +34,7 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
input logic [$clog2(NUMLINES)-1:0] WAdr,
input logic [`PA_BITS-1:0] PAdr,
input logic WriteEnable,
- input logic VDWriteEnable,
+ input logic VDWriteEnable,
input logic [BLOCKLEN/`XLEN-1:0] WriteWordEnable,
input logic TagWriteEnable,
input logic [BLOCKLEN-1:0] WriteData,
@@ -54,7 +54,8 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
output logic [TAGLEN-1:0] VictimTagWay
);
- logic [NUMLINES-1:0] ValidBits, DirtyBits;
+ logic [NUMLINES-1:0] ValidBits;
+ logic [NUMLINES-1:0] DirtyBits;
logic [BLOCKLEN-1:0] ReadDataBlockWay;
logic [TAGLEN-1:0] ReadTag;
logic Valid;
@@ -117,21 +118,18 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26,
generate
if(DIRTY_BITS) begin
+
always_ff @(posedge clk, posedge reset) begin
if (reset)
DirtyBits <= {NUMLINES{1'b0}};
else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1;
else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0;
end
- end
- endgenerate
- // Since this is always updated on a clock edge we cannot include reset.
- generate
- if(DIRTY_BITS) begin
always_ff @(posedge clk) begin
Dirty <= DirtyBits[RAdr];
end
+
end else begin
assign Dirty = 1'b0;
end
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index a61a5accc..bf943169c 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -70,14 +70,9 @@ module dcache
output logic [2:0] DCtoAHBSizeM
);
-/* localparam integer BLOCKLEN = 256;
- localparam integer NUMLINES = 64;
- localparam integer NUMWAYS = 4;
- localparam integer NUMREPL_BITS = 3;*/
localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS;
localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN;
localparam integer NUMWAYS = `DCACHE_NUMWAYS;
- localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; // *** not used
localparam integer BLOCKBYTELEN = BLOCKLEN/8;
localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN);
@@ -170,7 +165,7 @@ module dcache
.reset,
.RAdr,
.WAdr,
- .PAdr(MemPAdrM[`PA_BITS-1:0]),
+ .PAdr(MemPAdrM),
.WriteEnable(SRAMWayWriteEnable),
.VDWriteEnable,
.WriteWordEnable(SRAMWordEnable),
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index f1c0b29ff..d433f6ed3 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -65,16 +65,12 @@ module icache
localparam LOGWPL = $clog2(WORDSPERLINE);
localparam FetchCountThreshold = WORDSPERLINE - 1;
- localparam BlockByteLength = BLOCKLEN / 8;
-
- localparam OFFSETWIDTH = $clog2(BlockByteLength);
localparam integer PA_WIDTH = `PA_BITS - 2;
localparam integer NUMWAYS = `ICACHE_NUMWAYS;
// Input signals to cache memory
- logic FlushMem;
logic ICacheMemWriteEnable;
logic [BLOCKLEN-1:0] ICacheMemWriteData;
logic [`PA_BITS-1:0] PCTagF;
@@ -91,7 +87,7 @@ module icache
logic FetchCountFlag;
logic CntEn;
- logic [1:0] SelAdr_q;
+ logic [1:1] SelAdr_q;
logic [LOGWPL-1:0] FetchCount, NextFetchCount;
@@ -252,11 +248,11 @@ module icache
// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
// *** read enable may not be necessary.
- flopenr #(2) SelAdrReg(.clk(clk),
+ flopenr #(1) SelAdrReg(.clk(clk),
.reset(reset),
.en(ICacheReadEn),
- .d(SelAdr),
- .q(SelAdr_q));
+ .d(SelAdr[1]),
+ .q(SelAdr_q[1]));
assign PCTagF = SelAdr_q[1] ? PCPSpillF : PCPF;
@@ -281,29 +277,25 @@ module icache
assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
- icachefsm #(.BLOCKLEN(BLOCKLEN))
- controller(.clk,
- .reset,
- .StallF,
- .ICacheReadEn,
- .ICacheMemWriteEnable,
- .ICacheStallF,
- .ITLBMissF,
- .ITLBWriteF,
- .WalkerInstrPageFaultF,
- .InstrAckF,
- .InstrReadF,
- .hit,
- .FetchCountFlag,
- .spill,
- .spillSave,
- .CntEn,
- .CntReset,
- .SelAdr,
- .LRUWriteEn
- );
+ icachefsm controller(.clk,
+ .reset,
+ .StallF,
+ .ICacheReadEn,
+ .ICacheMemWriteEnable,
+ .ICacheStallF,
+ .ITLBMissF,
+ .ITLBWriteF,
+ .WalkerInstrPageFaultF,
+ .InstrAckF,
+ .InstrReadF,
+ .hit,
+ .FetchCountFlag,
+ .spill,
+ .spillSave,
+ .CntEn,
+ .CntReset,
+ .SelAdr,
+ .LRUWriteEn);
- // For now, assume no writes to executable memory
- assign FlushMem = 1'b0;
endmodule
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 1d5ad0cd3..82590747d 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -25,9 +25,8 @@
`include "wally-config.vh"
-module icachefsm #(parameter BLOCKLEN = 256)
- (
- // Inputs from pipeline
+module icachefsm
+ (// Inputs from pipeline
input logic clk, reset,
input logic StallF,
@@ -115,8 +114,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
statetype CurrState, NextState;
logic PreCntEn;
- logic UnalignedSelect;
- logic SavePC; // unused right now *** consider deleting
// the FSM is always runing, do not stall.
always_ff @(posedge clk, posedge reset)
@@ -125,7 +122,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
// Next state logic
always_comb begin
- UnalignedSelect = 1'b0;
CntReset = 1'b0;
PreCntEn = 1'b0;
//InstrReadF = 1'b0;
@@ -133,7 +129,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
spillSave = 1'b0;
SelAdr = 2'b00;
ICacheReadEn = 1'b0;
- SavePC = 1'b0;
ICacheStallF = 1'b1;
LRUWriteEn = 1'b0;
case (CurrState)
@@ -143,7 +138,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
if (ITLBMissF) begin
NextState = STATE_TLB_MISS;
end else if (hit & ~spill) begin
- SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
@@ -176,7 +170,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
// branch 1, hit spill and 2, miss spill hit
STATE_HIT_SPILL: begin
SelAdr = 2'b10;
- UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1;
if (hit) begin
NextState = STATE_HIT_SPILL_FINAL;
@@ -202,15 +195,12 @@ module icachefsm #(parameter BLOCKLEN = 256)
end
STATE_HIT_SPILL_MERGE: begin
SelAdr = 2'b10;
- UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1;
NextState = STATE_HIT_SPILL_FINAL;
end
STATE_HIT_SPILL_FINAL: begin
ICacheReadEn = 1'b1;
SelAdr = 2'b00;
- UnalignedSelect = 1'b1;
- SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
@@ -280,7 +270,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
end
STATE_MISS_SPILL_2: begin
SelAdr = 2'b10;
- UnalignedSelect = 1'b1;
spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_2_START;
@@ -292,8 +281,6 @@ module icachefsm #(parameter BLOCKLEN = 256)
end else begin
ICacheReadEn = 1'b1;
SelAdr = 2'b00;
- UnalignedSelect = 1'b1;
- SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
@@ -321,15 +308,12 @@ module icachefsm #(parameter BLOCKLEN = 256)
end
STATE_MISS_SPILL_MERGE: begin
SelAdr = 2'b10;
- UnalignedSelect = 1'b1;
ICacheReadEn = 1'b1;
NextState = STATE_MISS_SPILL_FINAL;
end
STATE_MISS_SPILL_FINAL: begin
ICacheReadEn = 1'b1;
SelAdr = 2'b00;
- UnalignedSelect = 1'b1;
- SavePC = 1'b1;
ICacheStallF = 1'b0;
LRUWriteEn = 1'b1;
if(StallF) begin
diff --git a/wally-pipelined/src/ifu/BTBPredictor.sv b/wally-pipelined/src/ifu/BTBPredictor.sv
index 4b54c0bb7..07a39c162 100644
--- a/wally-pipelined/src/ifu/BTBPredictor.sv
+++ b/wally-pipelined/src/ifu/BTBPredictor.sv
@@ -33,7 +33,7 @@ module BTBPredictor
)
(input logic clk,
input logic reset,
- input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic StallF, StallE,
input logic [`XLEN-1:0] LookUpPC,
output logic [`XLEN-1:0] TargetPC,
output logic [4:0] InstrClass,
@@ -77,18 +77,7 @@ module BTBPredictor
end
assign Valid = ValidBits[LookUpPCIndexQ];
-/* -----\/----- EXCLUDED -----\/-----
- regfile2p1r1w #(10, 1) validMem(.clk(clk),
- .reset(reset),
- .RA1(LookUpPCIndexQ),
- .RD1(Valid),
- .REN1(1'b1),
- .WA1(UpdatePCIndexQ),
- .WD1(1'b1),
- .WEN1(UpdateEN));
- -----/\----- EXCLUDED -----/\----- */
-
flopenr #(1) UpdateENReg(.clk(clk),
.reset(reset),
.en(~StallF),
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 688c8377f..c0fd17fc8 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -30,8 +30,8 @@
module bpred
(input logic clk, reset,
- input logic StallF, StallD, StallE, StallM, StallW,
- input logic FlushF, FlushD, FlushE, FlushM, FlushW,
+ input logic StallF, StallD, StallE,
+ input logic FlushF, FlushD, FlushE,
// Fetch stage
// the prediction
input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list
@@ -67,8 +67,6 @@ module bpred
logic PredictionPCWrongE;
logic PredictionInstrClassWrongE;
- logic [`XLEN-1:0] CorrectPCE;
-
// Part 1 branch direction prediction
@@ -171,10 +169,6 @@ module bpred
.UpdateInvalid(PredictionInstrClassWrongE),
.UpdateInstrClass(InstrClassE));
- // need to forward when updating to the same address as reading.
- //assign CorrectPCE = PCSrcE ? PCTargetE : PCLinkE;
- //assign TargetPC = (PCE == PCNextF) ? CorrectPCE : BTBPredPCF;
-
// Part 3 RAS
// *** need to add the logic to restore RAS on flushes. We will use incr for this.
RASPredictor RASPredictor(.clk(clk),
diff --git a/wally-pipelined/src/ifu/globalHistoryPredictor.sv b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
index 16964bd87..9f0680ad0 100644
--- a/wally-pipelined/src/ifu/globalHistoryPredictor.sv
+++ b/wally-pipelined/src/ifu/globalHistoryPredictor.sv
@@ -32,7 +32,7 @@ module globalHistoryPredictor
)
(input logic clk,
input logic reset,
- input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF,
output logic [1:0] BPPredF,
// update
diff --git a/wally-pipelined/src/ifu/gsharePredictor.sv b/wally-pipelined/src/ifu/gsharePredictor.sv
index 36e54d4bb..6da754176 100644
--- a/wally-pipelined/src/ifu/gsharePredictor.sv
+++ b/wally-pipelined/src/ifu/gsharePredictor.sv
@@ -32,7 +32,7 @@ module gsharePredictor
)
(input logic clk,
input logic reset,
- input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic StallF, StallE,
input logic [`XLEN-1:0] PCNextF,
output logic [1:0] BPPredF,
// update
diff --git a/wally-pipelined/src/ifu/localHistoryPredictor.sv b/wally-pipelined/src/ifu/localHistoryPredictor.sv
index 6c5c94783..b951704a0 100644
--- a/wally-pipelined/src/ifu/localHistoryPredictor.sv
+++ b/wally-pipelined/src/ifu/localHistoryPredictor.sv
@@ -33,7 +33,7 @@ module localHistoryPredictor
)
(input logic clk,
input logic reset,
- input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
+ input logic StallF, StallE, FlushF,
input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction,
// update
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 1b9604884..1a97d6b33 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -157,7 +157,6 @@ module lsu
// arbiter between IEU and hptw
lsuArb arbiter(.clk(clk),
- .reset(reset),
// HPTW connection
.SelPTW(SelPTW),
.HPTWRead(HPTWRead),
@@ -168,7 +167,7 @@ module lsu
.Funct3M(Funct3M),
.AtomicM(AtomicM),
.MemAdrM(MemAdrM),
- .MemAdrE(MemAdrE),
+ .MemAdrE(MemAdrE[11:0]),
.CommittedM(CommittedM),
.PendingInterruptM(PendingInterruptM),
.StallW(StallW),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index 0ed4cc304..c0647c2b6 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -27,7 +27,7 @@
`include "wally-config.vh"
module lsuArb
- (input logic clk, reset,
+ (input logic clk,
// from page table walker
input logic SelPTW,
@@ -40,7 +40,7 @@ module lsuArb
input logic [2:0] Funct3M,
input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrM,
- input logic [`XLEN-1:0] MemAdrE,
+ input logic [11:0] MemAdrE,
input logic StallW,
input logic PendingInterruptM,
// to CPU