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https://github.com/openhwgroup/cvw
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More Icache clean up.
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parent
2f7cb82c72
commit
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2
wally-pipelined/src/cache/icache.sv
vendored
2
wally-pipelined/src/cache/icache.sv
vendored
@ -48,7 +48,6 @@ module icache
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// High if the icache is requesting a stall
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// High if the icache is requesting a stall
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output logic ICacheStallF,
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output logic ICacheStallF,
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input logic CacheableF,
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input logic CacheableF,
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input logic ITLBMissF,
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input logic InvalidateICacheM,
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input logic InvalidateICacheM,
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// The raw (not decompressed) instruction that was requested
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// The raw (not decompressed) instruction that was requested
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@ -159,7 +158,6 @@ module icache
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.CPUBusy,
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.CPUBusy,
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.ICacheMemWriteEnable,
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.ICacheMemWriteEnable,
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.ICacheStallF,
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.ICacheStallF,
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.ITLBMissF,
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.IgnoreRequest,
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.IgnoreRequest,
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.ICacheBusAck,
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.ICacheBusAck,
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.ICacheFetchLine,
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.ICacheFetchLine,
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8
wally-pipelined/src/cache/icachefsm.sv
vendored
8
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -31,9 +31,6 @@ module icachefsm
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input logic CPUBusy,
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input logic CPUBusy,
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// inputs from mmu
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input logic ITLBMissF,
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input logic IgnoreRequest,
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input logic IgnoreRequest,
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input logic CacheableF,
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input logic CacheableF,
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@ -89,11 +86,6 @@ module icachefsm
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if(IgnoreRequest) begin
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if(IgnoreRequest) begin
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SelAdr = 1'b1;
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SelAdr = 1'b1;
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NextState = STATE_READY;
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NextState = STATE_READY;
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end else
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if(ITLBMissF) begin
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NextState = STATE_READY;
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SelAdr = 1'b1;
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ICacheStallF = 1'b0;
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end
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end
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else if (CacheableF & hit) begin
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else if (CacheableF & hit) begin
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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@ -247,7 +247,7 @@ module ifu (
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generate
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generate
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if(`MEM_ICACHE) begin : icache
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if(`MEM_ICACHE) begin : icache
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icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
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icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
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.ICacheBusAdr, .ICacheStallF, .ITLBMissF, .FinalInstrRawF,
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.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF,
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.ICacheFetchLine,
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.ICacheFetchLine,
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.CacheableF,
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.CacheableF,
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.PCNextF(PCNextFMux),
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.PCNextF(PCNextFMux),
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