Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Removed old signals.

Browse Source
This commit is contained in:
Ross Thompson 2022-08-31 09:50:39 -05:00
parent 5409501ca6
commit 89f13370e2
4 changed files with 13 additions and 74 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
pipelined/src/cache/AHBBuscachefsm.sv vendored
View File

@ -74,15 +74,14 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
logic [LOGWPL-1:0] NextWordCount; logic [LOGWPL-1:0] NextWordCount;
logic WordCountFlag; logic WordCountFlag;
logic [2:0] LocalBurstType; logic [2:0] LocalBurstType;
logic CntReset; logic WordCntReset;
logic [1:0] RWDelay, CacheRWDelay; logic [1:0] RWDelay, CacheRWDelay;
assign CntReset = BusNextState == STATE_READY;
// Used to send address for address stage of AHB. // Used to send address for address stage of AHB.
flopenr #(LOGWPL) flopenr #(LOGWPL)
WordCountReg(.clk(HCLK), WordCountReg(.clk(HCLK),
.reset(~HRESETn | CntReset), .reset(~HRESETn | WordCntReset),
.en(WordCntEn), .en(WordCntEn),
.d(NextWordCount), .d(NextWordCount),
.q(WordCount)); .q(WordCount));
@ -90,7 +89,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
// Used to store data from data phase of AHB. // Used to store data from data phase of AHB.
flopenr #(LOGWPL) flopenr #(LOGWPL)
WordCountDelayedReg(.clk(HCLK), WordCountDelayedReg(.clk(HCLK),
.reset(~HRESETn | CntReset), .reset(~HRESETn | WordCntReset),
.en(WordCntEn), .en(WordCntEn),
.d(WordCount), .d(WordCount),
.q(WordCountDelayed)); .q(WordCountDelayed));
@ -99,6 +98,7 @@ module AHBBuscachefsm #(parameter integer WordCountThreshold,
assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access. assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0] ); // Detect when we are waiting on the final access.
assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) | assign WordCntEn = (BusNextState == STATE_CACHE_ACCESS & HREADY) |
(BusNextState == STATE_READY & |CacheRW & HREADY); (BusNextState == STATE_READY & |CacheRW & HREADY);
assign WordCntReset = BusNextState == STATE_READY;
// replace with fsm with two more states. // replace with fsm with two more states.
flopenr #(2) RWReg(HCLK, ~HRESETn, 1'b1, RW, RWDelay); flopenr #(2) RWReg(HCLK, ~HRESETn, 1'b1, RW, RWDelay);

14
pipelined/src/ifu/ifu.sv
View File

@ -37,16 +37,12 @@ module ifu (
input logic FlushF, FlushD, FlushE, FlushM, input logic FlushF, FlushD, FlushE, FlushM,
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
(* mark_debug = "true" *) input logic IFUBusAck,
(* mark_debug = "true" *) input logic IFUBusInit,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR,
(* mark_debug = "true" *) output logic IFUBusRead,
(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic IFUStallF,
(* mark_debug = "true" *) output logic [2:0] IFUHBURST, (* mark_debug = "true" *) output logic [2:0] IFUHBURST,
(* mark_debug = "true" *) output logic [1:0] IFUHTRANS, (* mark_debug = "true" *) output logic [1:0] IFUHTRANS,
(* mark_debug = "true" *) output logic IFUHWRITE, (* mark_debug = "true" *) output logic IFUHWRITE,
(* mark_debug = "true" *) input logic IFUHREADY, (* mark_debug = "true" *) input logic IFUHREADY,
(* mark_debug = "true" *) output logic IFUTransComplete,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
// Execute // Execute
output logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCLinkE,
@ -250,24 +246,16 @@ module ifu (
flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0])); flopen #(`XLEN) fb(.clk, .en(CaptureEn), .d(HRDATA), .q(AllInstrRawF[31:0]));
/* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm(
.clk, .reset, .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}),
.BusAck(IFUBusAck), .BusInit(IFUBusInit), .CPUBusy,
.BusStall, .BusWrite(), .BusRead(IFUBusRead),
.HTRANS(IFUHTRANS), .BusCommitted());
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn, AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(NonIROMMemRWM & ~{ITLBMissF, ITLBMissF}), .CaptureEn,
.BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE)); .BusCommitted(), .CPUBusy, .HREADY(IFUHREADY), .BusStall, .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE));
assign IFUHBURST = 3'b0; assign IFUHBURST = 3'b0;
assign IFUTransComplete = IFUBusAck;
assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0; assign {ICacheFetchLine, ICacheStallF, FinalInstrRawF} = '0;
assign {ICacheMiss, ICacheAccess} = '0; assign {ICacheMiss, ICacheAccess} = '0;
end end
end else begin : nobus // block: bus end else begin : nobus // block: bus
assign {BusStall, IFUBusRead} = '0; assign BusStall = '0;
assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0; assign {ICacheStallF, ICacheMiss, ICacheAccess} = '0;
assign AllInstrRawF = FinalInstrRawF; assign AllInstrRawF = FinalInstrRawF;
end end

15
pipelined/src/lsu/lsu.sv
View File

@ -72,10 +72,6 @@ module lsu (
output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM,
// connect to ahb // connect to ahb
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUHADDR,
(* mark_debug = "true" *) output logic LSUBusRead,
(* mark_debug = "true" *) output logic LSUBusWrite,
(* mark_debug = "true" *) input logic LSUBusAck,
(* mark_debug = "true" *) input logic LSUBusInit,
(* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA,
(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUHWDATA,
(* mark_debug = "true" *) input logic LSUHREADY, (* mark_debug = "true" *) input logic LSUHREADY,
@ -84,7 +80,6 @@ module lsu (
(* mark_debug = "true" *) output logic [2:0] LSUHBURST, (* mark_debug = "true" *) output logic [2:0] LSUHBURST,
(* mark_debug = "true" *) output logic [1:0] LSUHTRANS, (* mark_debug = "true" *) output logic [1:0] LSUHTRANS,
(* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB, (* mark_debug = "true" *) output logic [`XLEN/8-1:0] LSUHWSTRB,
(* mark_debug = "true" *) output logic LSUTransComplete,
// page table walker // page table walker
input logic [`XLEN-1:0] SATP_REGW, // from csr input logic [`XLEN-1:0] SATP_REGW, // from csr
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -278,6 +273,7 @@ module lsu (
flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flop #(`XLEN) wdreg(clk, LSUHWDATA_noDELAY, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// *** bummer need a second byte mask for bus as it is XLEN rather than LLEN. // *** bummer need a second byte mask for bus as it is XLEN rather than LLEN.
// probably can merge by muxing LSUPAdrM's LLEN/8-1 index bit based on HTRANS being != 0.
logic [`XLEN/8-1:0] BusByteMaskM; logic [`XLEN/8-1:0] BusByteMaskM;
swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM)); swbytemask #(`XLEN) busswbytemask(.Size(LSUHSIZE), .Adr(LSUPAdrM[$clog2(`XLEN/8)-1:0]), .ByteMask(BusByteMaskM));
@ -294,21 +290,12 @@ module lsu (
flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flop #(`XLEN) wdreg(clk, LSUWriteDataM, LSUHWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB); flop #(`XLEN/8) HWSTRBReg(clk, ByteMaskM, LSUHWSTRB);
/* -----\/----- EXCLUDED -----\/-----
busfsm #(LOGBWPL) busfsm(
.clk, .reset, .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusAck(LSUBusAck), .BusInit(LSUBusInit), .CPUBusy,
.BusStall, .BusWrite(LSUBusWrite), .BusRead(LSUBusRead),
.HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM));
-----/\----- EXCLUDED -----/\----- */
AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}), AHBBusfsm busfsm(.HCLK(clk), .HRESETn(~reset), .RW(LSURWM & ~{IgnoreRequest, IgnoreRequest}),
.BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS), .BusCommitted(BusCommittedM), .CPUBusy, .BusStall, .CaptureEn, .HREADY(LSUHREADY), .HTRANS(LSUHTRANS),
.HWRITE(LSUHWRITE)); .HWRITE(LSUHWRITE));
assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping assign ReadDataWordMuxM = LittleEndianReadDataWordM; // from byte swapping
assign LSUHBURST = 3'b0; assign LSUHBURST = 3'b0;
assign LSUTransComplete = LSUBusAck;
assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0; assign {DCacheStallM, DCacheCommittedM, DCacheMiss, DCacheAccess} = '0;
end end
end else begin: nobus // block: bus end else begin: nobus // block: bus

50
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -133,19 +133,13 @@ module wallypipelinedcore (
// AHB ifu interface // AHB ifu interface
logic [`PA_BITS-1:0] IFUHADDR; logic [`PA_BITS-1:0] IFUHADDR;
logic IFUBusRead;
logic IFUBusAck, IFUBusInit;
logic [2:0] IFUHBURST; logic [2:0] IFUHBURST;
logic [1:0] IFUHTRANS; logic [1:0] IFUHTRANS;
logic IFUTransComplete;
logic IFUHWRITE; logic IFUHWRITE;
logic IFUHREADY; logic IFUHREADY;
// AHB LSU interface // AHB LSU interface
logic [`PA_BITS-1:0] LSUHADDR; logic [`PA_BITS-1:0] LSUHADDR;
logic LSUBusRead;
logic LSUBusWrite;
logic LSUBusAck, LSUBusInit;
logic [`XLEN-1:0] LSUHWDATA; logic [`XLEN-1:0] LSUHWDATA;
logic [`XLEN/8-1:0] LSUHWSTRB; logic [`XLEN/8-1:0] LSUHWSTRB;
logic LSUHWRITE; logic LSUHWRITE;
@ -161,7 +155,6 @@ module wallypipelinedcore (
logic [2:0] LSUHSIZE; logic [2:0] LSUHSIZE;
logic [2:0] LSUHBURST; logic [2:0] LSUHBURST;
logic [1:0] LSUHTRANS; logic [1:0] LSUHTRANS;
logic LSUTransComplete;
logic DCacheMiss; logic DCacheMiss;
logic DCacheAccess; logic DCacheAccess;
@ -178,8 +171,8 @@ module wallypipelinedcore (
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushF, .FlushD, .FlushE, .FlushM,
// Fetch // Fetch
.HRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUHADDR, .HRDATA, .PCF, .IFUHADDR,
.IFUBusRead, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUTransComplete, .IFUStallF, .IFUHBURST, .IFUHTRANS,
.IFUHREADY, .IFUHWRITE, .IFUHREADY, .IFUHWRITE,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
@ -264,8 +257,8 @@ module wallypipelinedcore (
.IEUAdrE, .IEUAdrM, .WriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
.ReadDataW, .FlushDCacheM, .ReadDataW, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit, .LSUHADDR,
.HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS, .LSUTransComplete, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST, .LSUHTRANS,
.LSUHWRITE, .LSUHREADY, .LSUHWRITE, .LSUHREADY,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
@ -295,43 +288,14 @@ module wallypipelinedcore (
// *** Ross: please make EBU conditional when only supporting internal memories // *** Ross: please make EBU conditional when only supporting internal memories
if(`BUS) begin : ebu if(`BUS) begin : ebu
/* -----\/----- EXCLUDED -----\/-----
ahblite ebu(// IFU connections
.clk, .reset,
.UnsignedLoadM(1'b0), .AtomicMaskedM(2'b00),
.IFUHADDR, .IFUBusRead,
.IFUHBURST,
.IFUHTRANS,
.IFUTransComplete,
.IFUBusAck,
.IFUBusInit,
.IFUHWRITE,
.IFUHREADY,
// Signals from Data Cache
.LSUHADDR, .LSUBusRead, .LSUBusWrite, .LSUHWDATA,
.LSUHSIZE,
.LSUHBURST,
.LSUHTRANS,
.LSUTransComplete,
.LSUBusAck,
.LSUBusInit,
.LSUHWRITE,
.LSUHREADY,
.HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK);
-----/\----- EXCLUDED -----/\----- */
ahbmultimanager ebu(// IFU connections ahbmultimanager ebu(// IFU connections
.clk, .reset, .clk, .reset,
// IFU interface
.IFUHADDR, .IFUHADDR,
.IFUHBURST, .IFUHBURST,
.IFUHTRANS, .IFUHTRANS,
.IFUHREADY, .IFUHREADY,
// LSU interface
// Signals from Data Cache
.LSUHADDR, .LSUHADDR,
.LSUHWDATA, .LSUHWDATA,
.LSUHWSTRB, .LSUHWSTRB,
@ -340,7 +304,7 @@ module wallypipelinedcore (
.LSUHTRANS, .LSUHTRANS,
.LSUHWRITE, .LSUHWRITE,
.LSUHREADY, .LSUHREADY,
// BUS interface
.HREADY, .HRESP, .HCLK, .HRESETn, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK); .HPROT, .HTRANS, .HMASTLOCK);