From 89c74384243a100a15a6e6957f653644baa0e293 Mon Sep 17 00:00:00 2001 From: slmnemo Date: Thu, 19 May 2022 16:21:38 -0700 Subject: [PATCH] parametrized linux testbench's DEBUG_TRACE and added parameters to relevant calls of the linux testbench in wally-pipelined.do --- pipelined/regression/wally-pipelined.do | 4 ++-- pipelined/testbench/testbench-linux.sv | 22 ++++++++++++---------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/pipelined/regression/wally-pipelined.do b/pipelined/regression/wally-pipelined.do index cf116da6d..ad73634dc 100644 --- a/pipelined/regression/wally-pipelined.do +++ b/pipelined/regression/wally-pipelined.do @@ -34,7 +34,7 @@ vlib work if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation @@ -48,7 +48,7 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} { } elseif {$2 eq "buildroot-no-trace"} { vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 # start and run simulation - vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -o testbenchopt + vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_IE_MTIME_CHECKPOINT=1 -G DEBUG_TRACE=1 -o testbenchopt vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829 #-- Run the Simulation diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv index f405af48f..b397ec70c 100644 --- a/pipelined/testbench/testbench-linux.sv +++ b/pipelined/testbench/testbench-linux.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" -`define DEBUG_TRACE 0 +// `define DEBUG_TRACE 0 // *** move this info down below and remove this line if parametrization works // Debug Levels // 0: don't check against QEMU // 1: print disagreements with QEMU, but only halt on PCW disagreements @@ -46,6 +46,7 @@ module testbench; parameter CHECKPOINT = 0; parameter RISCV_DIR = "/opt/riscv"; parameter NO_IE_MTIME_CHECKPOINT = 0; + parameter DEBUG_TRACE = 32; @@ -237,6 +238,7 @@ module testbench; logic clk, reset_ext; logic reset; initial begin reset_ext <= 1; # 22; reset_ext <= 0; end + initial begin $display(DEBUG_TRACE); #1; end // *** remove this once debug trace is parametrized always begin clk <= 1; # 5; clk <= 0; # 5; end // Wally Interface logic [`AHBW-1:0] HRDATAEXT; @@ -482,7 +484,7 @@ module testbench; if (checkInstrM) begin \ // read 1 line of the trace file \ matchCount``STAGE = $fgets(line``STAGE, traceFile``STAGE); \ - if(`DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ + if(DEBUG_TRACE >= 5) $display("Time %t, line %x", $time, line``STAGE); \ // extract PC, Instr \ matchCount``STAGE = $sscanf(line``STAGE, "%x %x %s", ExpectedPC``STAGE, ExpectedInstr``STAGE, text``STAGE); \ if (`"STAGE`"=="M") begin \ @@ -566,14 +568,14 @@ module testbench; `define checkEQ(NAME, VAL, EXPECTED) \ if(VAL != EXPECTED) begin \ $display("%tns, %d instrs: %s %x differs from expected %x", $time, AttemptedInstructionCount, NAME, VAL, EXPECTED); \ - if ((NAME == "PCW") | (`DEBUG_TRACE >= 2)) fault = 1; \ + if ((NAME == "PCW") | (DEBUG_TRACE >= 2)) fault = 1; \ end `define checkCSR(CSR) \ begin \ if (CSR != ExpectedCSRArrayValueW[NumCSRPostWIndex]) begin \ $display("%tns, %d instrs: CSR %s = %016x, does not equal expected value %016x", $time, AttemptedInstructionCount, ExpectedCSRArrayW[NumCSRPostWIndex], CSR, ExpectedCSRArrayValueW[NumCSRPostWIndex]); \ - if(`DEBUG_TRACE >= 3) fault = 1; \ + if(DEBUG_TRACE >= 3) fault = 1; \ end \ end @@ -658,13 +660,13 @@ module testbench; // end sim if ((AttemptedInstructionCount == INSTR_LIMIT) & (INSTR_LIMIT!=0)) $stop; fault = 0; - if (`DEBUG_TRACE >= 1) begin + if (DEBUG_TRACE >= 1) begin `checkEQ("PCW",PCW,ExpectedPCW) //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of // compressed to uncompressed conversion `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW) #2; // delay 2 ns. - if(`DEBUG_TRACE >= 5) begin + if(DEBUG_TRACE >= 5) begin $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW); $display("%tns, %d instrs: RF[%02d] %016x ? expected value: %016x", $time, AttemptedInstructionCount, ExpectedRegAdrW, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW); end @@ -674,13 +676,13 @@ module testbench; `checkEQ(name, dut.core.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW) end if (MemOpW.substr(0,2) == "Mem") begin - if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); + if(DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW); `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW) if(MemOpW == "MemR" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); + if(DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.core.ieu.dp.ReadDataW, ExpectedMemReadDataW); `checkEQ("ReadDataW",dut.core.ieu.dp.ReadDataW,ExpectedMemReadDataW) end else if(MemOpW == "MemW" | MemOpW == "MemRW") begin - if(`DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); + if(DEBUG_TRACE >= 4) $display("\tWriteDataW: %016x ? expected: %016x", WriteDataW, ExpectedMemWriteDataW); `checkEQ("WriteDataW",ExpectedMemWriteDataW,ExpectedMemWriteDataW) end end @@ -720,7 +722,7 @@ module testbench; $display("processed %0d instructions with %0d warnings", AttemptedInstructionCount, warningCount); $stop; end - end // if (`DEBUG_TRACE >= 1) + end // if (DEBUG_TRACE >= 1) end // if (checkInstrW) end // always @ (negedge clk)