From 8993432928a0cdce85281735e926ccb356ef9cb4 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Tue, 12 Nov 2024 23:57:30 -0600 Subject: [PATCH] Resolved issue with questa not liking the TEST +arg as a generate. --- testbench/common/loggers.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index 89fe59ca8..287d02346 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -52,6 +52,7 @@ module loggers import cvw::*; #(parameter cvw_t P, logic StartSampleDelayed, BeginDelayed; logic EndSampleFirst; logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0]; + logic EndSampleDelayed; string HPMCnames[] = '{"Mcycle", "------", @@ -80,6 +81,7 @@ module loggers import cvw::*; #(parameter cvw_t P, "Divide Cycles" }; + always_comb if (TEST == "embench") begin StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger"; @@ -93,13 +95,21 @@ module loggers import cvw::*; #(parameter cvw_t P, end // this code needs to be with embench and coremark but not the else condition +/* -----\/----- EXCLUDED -----\/----- if (TEST == "embench" | TEST == "coremark") begin - logic EndSampleDelayed; - flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; end else begin assign EndSample = DCacheFlushStart & ~DCacheFlushDone; end + -----/\----- EXCLUDED -----/\----- */ + + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + always_comb + if (TEST == "embench" | TEST == "coremark") begin + EndSample = EndSampleFirst & ~ EndSampleDelayed; + end else begin + EndSample = DCacheFlushStart & ~DCacheFlushDone; + end /* if(TEST == "embench") begin