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Converted tvecmux to structural

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This commit is contained in:
David Harris 2022-12-20 16:24:04 -08:00
parent 6152c028db
commit 88ee834c97
2 changed files with 11 additions and 8 deletions
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2
pipelined/regression/lint-wally
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@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
#for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do #for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do
for config in rv64gc; do for config in rv64gc; do
echo "$config linting..." echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes --Wall); then if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings" echo "Exiting after $config lint due to errors or warnings"
exit 1 exit 1
fi fi

17
pipelined/src/privileged/csr.sv
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@ -100,8 +100,9 @@ module csr #(parameter
logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM;
logic MTrapM, STrapM; logic MTrapM, STrapM;
logic [`XLEN-1:0] XEPC_REG; logic [`XLEN-1:0] EPC;
logic RetM; logic RetM;
logic SelMtvec;
logic InstrValidNotFlushedM; logic InstrValidNotFlushedM;
assign InstrValidNotFlushedM = ~StallW & ~FlushW; assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@ -120,7 +121,7 @@ module csr #(parameter
endcase endcase
/////////////////////////////////////////// ///////////////////////////////////////////
// Trap Vectoring // Trap Vectoring & Returns
/////////////////////////////////////////// ///////////////////////////////////////////
// //
// POSSIBLE OPTIMIZATION: // POSSIBLE OPTIMIZATION:
@ -131,9 +132,8 @@ module csr #(parameter
// [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} // [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000}
// However, this is program dependent, so not implemented at this time. // However, this is program dependent, so not implemented at this time.
always_comb assign SelMtvec = (NextPrivilegeModeM == `M_MODE);
if (NextPrivilegeModeM == `S_MODE) TVec = STVEC_REGW; mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvec, TVec);
else TVec = MTVEC_REGW;
if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec
always_comb always_comb
@ -146,9 +146,12 @@ module csr #(parameter
assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; assign TrapVector = {TVec[`XLEN-1:2], 2'b00};
end end
// Trap Returns
// A trap sets the PC to TrapVector
// A return sets the PC to MEPC or SEPC
assign RetM = mretM | sretM; assign RetM = mretM | sretM;
mux2 #(`XLEN) xepcMux(SEPC_REGW, MEPC_REGW, mretM, XEPC_REG); mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC);
mux3 #(`XLEN) pcmux3(PCNext2F, XEPC_REG, TrapVector, {TrapM, RetM}, UnalignedPCNextF); mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVector, {TrapM, RetM}, UnalignedPCNextF);
/////////////////////////////////////////// ///////////////////////////////////////////