From 88d5edaf13f538efd02fdc92bf8e34e98d96de95 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 7 Jan 2022 17:56:40 -0600
Subject: [PATCH] Added advanced Vivado debug scripts.

---
 .../dcache-miss-evict-dirty-deadlock.tsm      | 37 +++++++++++++++++++
 fpga/generator/trigger.tsm                    | 36 ++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
 create mode 100644 fpga/generator/trigger.tsm

diff --git a/fpga/generator/dcache-miss-evict-dirty-deadlock.tsm b/fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
new file mode 100644
index 000000000..e72180b23
--- /dev/null
+++ b/fpga/generator/dcache-miss-evict-dirty-deadlock.tsm
@@ -0,0 +1,37 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState == 32'h00000003) then
+        reset_counter $counter0;
+        goto state_begin_count;
+        #goto state_trigger;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if($counter0 == 16'h0164) then
+        goto state_trigger;
+    elseif(wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState == 32'h00000003) then
+        increment_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_trigger:
+    trigger;
diff --git a/fpga/generator/trigger.tsm b/fpga/generator/trigger.tsm
new file mode 100644
index 000000000..421c0a7a8
--- /dev/null
+++ b/fpga/generator/trigger.tsm
@@ -0,0 +1,36 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
+        reset_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if($counter0 == 16'h0064) then
+        goto state_trigger;
+    elseif(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
+        increment_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_trigger:
+    trigger;